Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Intel ICH6-10, Series 5 and 6 GPIO driver |
| 3 | * |
| 4 | * Copyright (C) 2010 Extreme Engineering Solutions. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | */ |
| 20 | |
| 21 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 22 | |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/pci.h> |
| 25 | #include <linux/gpio.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/mfd/lpc_ich.h> |
| 28 | |
| 29 | #define DRV_NAME "gpio_ich" |
| 30 | |
| 31 | /* |
| 32 | * GPIO register offsets in GPIO I/O space. |
| 33 | * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and |
| 34 | * LVLx registers. Logic in the read/write functions takes a register and |
| 35 | * an absolute bit number and determines the proper register offset and bit |
| 36 | * number in that register. For example, to read the value of GPIO bit 50 |
| 37 | * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)], |
| 38 | * bit 18 (50%32). |
| 39 | */ |
| 40 | enum GPIO_REG { |
| 41 | GPIO_USE_SEL = 0, |
| 42 | GPIO_IO_SEL, |
| 43 | GPIO_LVL, |
Vincent Donnefort | 7f6569f | 2013-06-17 14:03:49 +0200 | [diff] [blame] | 44 | GPO_BLINK |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 45 | }; |
| 46 | |
Vincent Donnefort | 7f6569f | 2013-06-17 14:03:49 +0200 | [diff] [blame] | 47 | static const u8 ichx_regs[4][3] = { |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 48 | {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */ |
| 49 | {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */ |
| 50 | {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */ |
Vincent Donnefort | 7f6569f | 2013-06-17 14:03:49 +0200 | [diff] [blame] | 51 | {0x18, 0x18, 0x18}, /* BLINK offset */ |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 52 | }; |
| 53 | |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 54 | static const u8 ichx_reglen[3] = { |
| 55 | 0x30, 0x10, 0x10, |
| 56 | }; |
| 57 | |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 58 | #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) |
| 59 | #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) |
| 60 | |
| 61 | struct ichx_desc { |
| 62 | /* Max GPIO pins the chipset can have */ |
| 63 | uint ngpio; |
| 64 | |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 65 | /* chipset registers */ |
| 66 | const u8 (*regs)[3]; |
| 67 | const u8 *reglen; |
| 68 | |
Vincent Donnefort | ba7f74f | 2014-02-14 15:01:55 +0100 | [diff] [blame] | 69 | /* GPO_BLINK is available on this chipset */ |
| 70 | bool have_blink; |
| 71 | |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 72 | /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ |
| 73 | bool uses_gpe0; |
| 74 | |
| 75 | /* USE_SEL is bogus on some chipsets, eg 3100 */ |
| 76 | u32 use_sel_ignore[3]; |
| 77 | |
| 78 | /* Some chipsets have quirks, let these use their own request/get */ |
| 79 | int (*request)(struct gpio_chip *chip, unsigned offset); |
| 80 | int (*get)(struct gpio_chip *chip, unsigned offset); |
| 81 | }; |
| 82 | |
| 83 | static struct { |
| 84 | spinlock_t lock; |
| 85 | struct platform_device *dev; |
| 86 | struct gpio_chip chip; |
| 87 | struct resource *gpio_base; /* GPIO IO base */ |
| 88 | struct resource *pm_base; /* Power Mangagment IO base */ |
| 89 | struct ichx_desc *desc; /* Pointer to chipset-specific description */ |
| 90 | u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */ |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 91 | u8 use_gpio; /* Which GPIO groups are usable */ |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 92 | } ichx_priv; |
| 93 | |
| 94 | static int modparam_gpiobase = -1; /* dynamic */ |
| 95 | module_param_named(gpiobase, modparam_gpiobase, int, 0444); |
| 96 | MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, " |
| 97 | "which is the default."); |
| 98 | |
| 99 | static int ichx_write_bit(int reg, unsigned nr, int val, int verify) |
| 100 | { |
| 101 | unsigned long flags; |
| 102 | u32 data, tmp; |
| 103 | int reg_nr = nr / 32; |
| 104 | int bit = nr & 0x1f; |
| 105 | int ret = 0; |
| 106 | |
| 107 | spin_lock_irqsave(&ichx_priv.lock, flags); |
| 108 | |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 109 | data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], |
| 110 | ichx_priv.gpio_base); |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 111 | if (val) |
| 112 | data |= 1 << bit; |
| 113 | else |
| 114 | data &= ~(1 << bit); |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 115 | ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], |
| 116 | ichx_priv.gpio_base); |
| 117 | tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], |
| 118 | ichx_priv.gpio_base); |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 119 | if (verify && data != tmp) |
| 120 | ret = -EPERM; |
| 121 | |
| 122 | spin_unlock_irqrestore(&ichx_priv.lock, flags); |
| 123 | |
| 124 | return ret; |
| 125 | } |
| 126 | |
| 127 | static int ichx_read_bit(int reg, unsigned nr) |
| 128 | { |
| 129 | unsigned long flags; |
| 130 | u32 data; |
| 131 | int reg_nr = nr / 32; |
| 132 | int bit = nr & 0x1f; |
| 133 | |
| 134 | spin_lock_irqsave(&ichx_priv.lock, flags); |
| 135 | |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 136 | data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], |
| 137 | ichx_priv.gpio_base); |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 138 | |
| 139 | spin_unlock_irqrestore(&ichx_priv.lock, flags); |
| 140 | |
| 141 | return data & (1 << bit) ? 1 : 0; |
| 142 | } |
| 143 | |
Mika Westerberg | e97f9b5 | 2013-02-27 17:25:15 +0200 | [diff] [blame] | 144 | static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr) |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 145 | { |
Mika Westerberg | 61d793b | 2013-03-07 10:48:19 +0200 | [diff] [blame] | 146 | return !!(ichx_priv.use_gpio & (1 << (nr / 32))); |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 147 | } |
| 148 | |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 149 | static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) |
| 150 | { |
| 151 | /* |
| 152 | * Try setting pin as an input and verify it worked since many pins |
| 153 | * are output-only. |
| 154 | */ |
| 155 | if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1)) |
| 156 | return -EINVAL; |
| 157 | |
| 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, |
| 162 | int val) |
| 163 | { |
Vincent Donnefort | 7f6569f | 2013-06-17 14:03:49 +0200 | [diff] [blame] | 164 | /* Disable blink hardware which is available for GPIOs from 0 to 31. */ |
Vincent Donnefort | ba7f74f | 2014-02-14 15:01:55 +0100 | [diff] [blame] | 165 | if (nr < 32 && ichx_priv.desc->have_blink) |
Vincent Donnefort | 7f6569f | 2013-06-17 14:03:49 +0200 | [diff] [blame] | 166 | ichx_write_bit(GPO_BLINK, nr, 0, 0); |
| 167 | |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 168 | /* Set GPIO output value. */ |
| 169 | ichx_write_bit(GPIO_LVL, nr, val, 0); |
| 170 | |
| 171 | /* |
| 172 | * Try setting pin as an output and verify it worked since many pins |
| 173 | * are input-only. |
| 174 | */ |
| 175 | if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1)) |
| 176 | return -EINVAL; |
| 177 | |
| 178 | return 0; |
| 179 | } |
| 180 | |
| 181 | static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr) |
| 182 | { |
| 183 | return ichx_read_bit(GPIO_LVL, nr); |
| 184 | } |
| 185 | |
| 186 | static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) |
| 187 | { |
| 188 | unsigned long flags; |
| 189 | u32 data; |
| 190 | |
| 191 | /* |
| 192 | * GPI 0 - 15 need to be read from the power management registers on |
| 193 | * a ICH6/3100 bridge. |
| 194 | */ |
| 195 | if (nr < 16) { |
| 196 | if (!ichx_priv.pm_base) |
| 197 | return -ENXIO; |
| 198 | |
| 199 | spin_lock_irqsave(&ichx_priv.lock, flags); |
| 200 | |
| 201 | /* GPI 0 - 15 are latched, write 1 to clear*/ |
| 202 | ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base); |
| 203 | data = ICHX_READ(0, ichx_priv.pm_base); |
| 204 | |
| 205 | spin_unlock_irqrestore(&ichx_priv.lock, flags); |
| 206 | |
| 207 | return (data >> 16) & (1 << nr) ? 1 : 0; |
| 208 | } else { |
| 209 | return ichx_gpio_get(chip, nr); |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) |
| 214 | { |
Jean Delvare | 25f27db | 2013-03-05 21:22:38 +0100 | [diff] [blame] | 215 | if (!ichx_gpio_check_available(chip, nr)) |
| 216 | return -ENXIO; |
| 217 | |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 218 | /* |
| 219 | * Note we assume the BIOS properly set a bridge's USE value. Some |
| 220 | * chips (eg Intel 3100) have bogus USE values though, so first see if |
| 221 | * the chipset's USE value can be trusted for this specific bit. |
| 222 | * If it can't be trusted, assume that the pin can be used as a GPIO. |
| 223 | */ |
| 224 | if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f))) |
Jean Delvare | 2ab3a74 | 2013-03-05 09:06:58 +0100 | [diff] [blame] | 225 | return 0; |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 226 | |
| 227 | return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; |
| 228 | } |
| 229 | |
| 230 | static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr) |
| 231 | { |
| 232 | /* |
| 233 | * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100 |
| 234 | * bridge as they are controlled by USE register bits 0 and 1. See |
| 235 | * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for |
| 236 | * additional info. |
| 237 | */ |
| 238 | if (nr == 16 || nr == 17) |
| 239 | nr -= 16; |
| 240 | |
| 241 | return ichx_gpio_request(chip, nr); |
| 242 | } |
| 243 | |
| 244 | static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val) |
| 245 | { |
| 246 | ichx_write_bit(GPIO_LVL, nr, val, 0); |
| 247 | } |
| 248 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 249 | static void ichx_gpiolib_setup(struct gpio_chip *chip) |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 250 | { |
| 251 | chip->owner = THIS_MODULE; |
| 252 | chip->label = DRV_NAME; |
| 253 | chip->dev = &ichx_priv.dev->dev; |
| 254 | |
| 255 | /* Allow chip-specific overrides of request()/get() */ |
| 256 | chip->request = ichx_priv.desc->request ? |
| 257 | ichx_priv.desc->request : ichx_gpio_request; |
| 258 | chip->get = ichx_priv.desc->get ? |
| 259 | ichx_priv.desc->get : ichx_gpio_get; |
| 260 | |
| 261 | chip->set = ichx_gpio_set; |
| 262 | chip->direction_input = ichx_gpio_direction_input; |
| 263 | chip->direction_output = ichx_gpio_direction_output; |
| 264 | chip->base = modparam_gpiobase; |
| 265 | chip->ngpio = ichx_priv.desc->ngpio; |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 266 | chip->can_sleep = false; |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 267 | chip->dbg_show = NULL; |
| 268 | } |
| 269 | |
| 270 | /* ICH6-based, 631xesb-based */ |
| 271 | static struct ichx_desc ich6_desc = { |
| 272 | /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */ |
| 273 | .request = ich6_gpio_request, |
| 274 | .get = ich6_gpio_get, |
| 275 | |
| 276 | /* GPIO 0-15 are read in the GPE0_STS PM register */ |
| 277 | .uses_gpe0 = true, |
| 278 | |
| 279 | .ngpio = 50, |
Vincent Donnefort | ba7f74f | 2014-02-14 15:01:55 +0100 | [diff] [blame] | 280 | .have_blink = true, |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 281 | }; |
| 282 | |
| 283 | /* Intel 3100 */ |
| 284 | static struct ichx_desc i3100_desc = { |
| 285 | /* |
| 286 | * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on |
| 287 | * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100 |
| 288 | * Datasheet for more info. |
| 289 | */ |
| 290 | .use_sel_ignore = {0x00130000, 0x00010000, 0x0}, |
| 291 | |
| 292 | /* The 3100 needs fixups for GPIO 0 - 17 */ |
| 293 | .request = ich6_gpio_request, |
| 294 | .get = ich6_gpio_get, |
| 295 | |
| 296 | /* GPIO 0-15 are read in the GPE0_STS PM register */ |
| 297 | .uses_gpe0 = true, |
| 298 | |
| 299 | .ngpio = 50, |
| 300 | }; |
| 301 | |
| 302 | /* ICH7 and ICH8-based */ |
| 303 | static struct ichx_desc ich7_desc = { |
| 304 | .ngpio = 50, |
Vincent Donnefort | ba7f74f | 2014-02-14 15:01:55 +0100 | [diff] [blame] | 305 | .have_blink = true, |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 306 | .regs = ichx_regs, |
| 307 | .reglen = ichx_reglen, |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 308 | }; |
| 309 | |
| 310 | /* ICH9-based */ |
| 311 | static struct ichx_desc ich9_desc = { |
| 312 | .ngpio = 61, |
Vincent Donnefort | ba7f74f | 2014-02-14 15:01:55 +0100 | [diff] [blame] | 313 | .have_blink = true, |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 314 | .regs = ichx_regs, |
| 315 | .reglen = ichx_reglen, |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 316 | }; |
| 317 | |
| 318 | /* ICH10-based - Consumer/corporate versions have different amount of GPIO */ |
| 319 | static struct ichx_desc ich10_cons_desc = { |
| 320 | .ngpio = 61, |
Vincent Donnefort | ba7f74f | 2014-02-14 15:01:55 +0100 | [diff] [blame] | 321 | .have_blink = true, |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 322 | .regs = ichx_regs, |
| 323 | .reglen = ichx_reglen, |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 324 | }; |
| 325 | static struct ichx_desc ich10_corp_desc = { |
| 326 | .ngpio = 72, |
Vincent Donnefort | ba7f74f | 2014-02-14 15:01:55 +0100 | [diff] [blame] | 327 | .have_blink = true, |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 328 | .regs = ichx_regs, |
| 329 | .reglen = ichx_reglen, |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 330 | }; |
| 331 | |
| 332 | /* Intel 5 series, 6 series, 3400 series, and C200 series */ |
| 333 | static struct ichx_desc intel5_desc = { |
| 334 | .ngpio = 76, |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 335 | .regs = ichx_regs, |
| 336 | .reglen = ichx_reglen, |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 337 | }; |
| 338 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 339 | static int ichx_gpio_request_regions(struct resource *res_base, |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 340 | const char *name, u8 use_gpio) |
| 341 | { |
| 342 | int i; |
| 343 | |
| 344 | if (!res_base || !res_base->start || !res_base->end) |
| 345 | return -ENODEV; |
| 346 | |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 347 | for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 348 | if (!(use_gpio & (1 << i))) |
| 349 | continue; |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 350 | if (!request_region( |
| 351 | res_base->start + ichx_priv.desc->regs[0][i], |
| 352 | ichx_priv.desc->reglen[i], name)) |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 353 | goto request_err; |
| 354 | } |
| 355 | return 0; |
| 356 | |
| 357 | request_err: |
| 358 | /* Clean up: release already requested regions, if any */ |
| 359 | for (i--; i >= 0; i--) { |
| 360 | if (!(use_gpio & (1 << i))) |
| 361 | continue; |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 362 | release_region(res_base->start + ichx_priv.desc->regs[0][i], |
| 363 | ichx_priv.desc->reglen[i]); |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 364 | } |
| 365 | return -EBUSY; |
| 366 | } |
| 367 | |
| 368 | static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio) |
| 369 | { |
| 370 | int i; |
| 371 | |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 372 | for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 373 | if (!(use_gpio & (1 << i))) |
| 374 | continue; |
Vincent Donnefort | bb62a35 | 2014-02-14 15:01:56 +0100 | [diff] [blame^] | 375 | release_region(res_base->start + ichx_priv.desc->regs[0][i], |
| 376 | ichx_priv.desc->reglen[i]); |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 377 | } |
| 378 | } |
| 379 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 380 | static int ichx_gpio_probe(struct platform_device *pdev) |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 381 | { |
| 382 | struct resource *res_base, *res_pm; |
| 383 | int err; |
Jingoo Han | e56aee1 | 2013-07-30 17:08:05 +0900 | [diff] [blame] | 384 | struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev); |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 385 | |
| 386 | if (!ich_info) |
| 387 | return -ENODEV; |
| 388 | |
| 389 | ichx_priv.dev = pdev; |
| 390 | |
| 391 | switch (ich_info->gpio_version) { |
| 392 | case ICH_I3100_GPIO: |
| 393 | ichx_priv.desc = &i3100_desc; |
| 394 | break; |
| 395 | case ICH_V5_GPIO: |
| 396 | ichx_priv.desc = &intel5_desc; |
| 397 | break; |
| 398 | case ICH_V6_GPIO: |
| 399 | ichx_priv.desc = &ich6_desc; |
| 400 | break; |
| 401 | case ICH_V7_GPIO: |
| 402 | ichx_priv.desc = &ich7_desc; |
| 403 | break; |
| 404 | case ICH_V9_GPIO: |
| 405 | ichx_priv.desc = &ich9_desc; |
| 406 | break; |
| 407 | case ICH_V10CORP_GPIO: |
| 408 | ichx_priv.desc = &ich10_corp_desc; |
| 409 | break; |
| 410 | case ICH_V10CONS_GPIO: |
| 411 | ichx_priv.desc = &ich10_cons_desc; |
| 412 | break; |
| 413 | default: |
| 414 | return -ENODEV; |
| 415 | } |
| 416 | |
Jean Delvare | d39a948 | 2012-12-16 21:31:40 +0100 | [diff] [blame] | 417 | spin_lock_init(&ichx_priv.lock); |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 418 | res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO); |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 419 | ichx_priv.use_gpio = ich_info->use_gpio; |
| 420 | err = ichx_gpio_request_regions(res_base, pdev->name, |
| 421 | ichx_priv.use_gpio); |
| 422 | if (err) |
| 423 | return err; |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 424 | |
| 425 | ichx_priv.gpio_base = res_base; |
| 426 | |
| 427 | /* |
| 428 | * If necessary, determine the I/O address of ACPI/power management |
| 429 | * registers which are needed to read the the GPE0 register for GPI pins |
| 430 | * 0 - 15 on some chipsets. |
| 431 | */ |
| 432 | if (!ichx_priv.desc->uses_gpe0) |
| 433 | goto init; |
| 434 | |
| 435 | res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0); |
| 436 | if (!res_pm) { |
| 437 | pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n"); |
| 438 | goto init; |
| 439 | } |
| 440 | |
| 441 | if (!request_region(res_pm->start, resource_size(res_pm), |
| 442 | pdev->name)) { |
| 443 | pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n"); |
| 444 | goto init; |
| 445 | } |
| 446 | |
| 447 | ichx_priv.pm_base = res_pm; |
| 448 | |
| 449 | init: |
| 450 | ichx_gpiolib_setup(&ichx_priv.chip); |
| 451 | err = gpiochip_add(&ichx_priv.chip); |
| 452 | if (err) { |
| 453 | pr_err("Failed to register GPIOs\n"); |
| 454 | goto add_err; |
| 455 | } |
| 456 | |
| 457 | pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base, |
| 458 | ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME); |
| 459 | |
| 460 | return 0; |
| 461 | |
| 462 | add_err: |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 463 | ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio); |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 464 | if (ichx_priv.pm_base) |
| 465 | release_region(ichx_priv.pm_base->start, |
| 466 | resource_size(ichx_priv.pm_base)); |
| 467 | return err; |
| 468 | } |
| 469 | |
Bill Pemberton | 206210c | 2012-11-19 13:25:50 -0500 | [diff] [blame] | 470 | static int ichx_gpio_remove(struct platform_device *pdev) |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 471 | { |
| 472 | int err; |
| 473 | |
| 474 | err = gpiochip_remove(&ichx_priv.chip); |
| 475 | if (err) { |
| 476 | dev_err(&pdev->dev, "%s failed, %d\n", |
| 477 | "gpiochip_remove()", err); |
| 478 | return err; |
| 479 | } |
| 480 | |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 481 | ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio); |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 482 | if (ichx_priv.pm_base) |
| 483 | release_region(ichx_priv.pm_base->start, |
| 484 | resource_size(ichx_priv.pm_base)); |
| 485 | |
| 486 | return 0; |
| 487 | } |
| 488 | |
| 489 | static struct platform_driver ichx_gpio_driver = { |
| 490 | .driver = { |
| 491 | .owner = THIS_MODULE, |
| 492 | .name = DRV_NAME, |
| 493 | }, |
| 494 | .probe = ichx_gpio_probe, |
Bill Pemberton | 8283c4f | 2012-11-19 13:20:08 -0500 | [diff] [blame] | 495 | .remove = ichx_gpio_remove, |
Peter Tyser | 6ed9f9c | 2012-04-18 09:48:24 -0500 | [diff] [blame] | 496 | }; |
| 497 | |
| 498 | module_platform_driver(ichx_gpio_driver); |
| 499 | |
| 500 | MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>"); |
| 501 | MODULE_DESCRIPTION("GPIO interface for Intel ICH series"); |
| 502 | MODULE_LICENSE("GPL"); |
| 503 | MODULE_ALIAS("platform:"DRV_NAME); |