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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Toshiba Corporation
7 */
Atsushi Nemoto22b1d702008-07-11 00:31:36 +09008#ifndef __ASM_TXX9_TX3927_H
9#define __ASM_TXX9_TX3927_H
Linus Torvalds1da177e2005-04-16 15:20:36 -070010
Atsushi Nemoto22b1d702008-07-11 00:31:36 +090011#include <asm/txx9/txx927.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012
Atsushi Nemotoe0eb7302008-07-19 01:51:52 +090013#define TX3927_REG_BASE 0xfffe0000UL
Atsushi Nemotof6727fb2008-07-24 00:25:19 +090014#define TX3927_REG_SIZE 0x00010000
Atsushi Nemotoe0eb7302008-07-19 01:51:52 +090015#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
16#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
17#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
18#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
19#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
20#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#define TX3927_NR_TMR 3
Atsushi Nemotoe0eb7302008-07-19 01:51:52 +090022#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#define TX3927_NR_SIO 2
Atsushi Nemotoe0eb7302008-07-19 01:51:52 +090024#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
25#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Linus Torvalds1da177e2005-04-16 15:20:36 -070027struct tx3927_sdramc_reg {
28 volatile unsigned long cr[8];
29 volatile unsigned long tr[3];
30 volatile unsigned long cmd;
31 volatile unsigned long smrs[2];
32};
33
34struct tx3927_romc_reg {
35 volatile unsigned long cr[8];
36};
37
38struct tx3927_dma_reg {
39 struct tx3927_dma_ch_reg {
40 volatile unsigned long cha;
41 volatile unsigned long sar;
42 volatile unsigned long dar;
43 volatile unsigned long cntr;
44 volatile unsigned long sair;
45 volatile unsigned long dair;
46 volatile unsigned long ccr;
47 volatile unsigned long csr;
48 } ch[4];
49 volatile unsigned long dbr[8];
50 volatile unsigned long tdhr;
51 volatile unsigned long mcr;
52 volatile unsigned long unused0;
53};
54
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#include <asm/byteorder.h>
56
57#ifdef __BIG_ENDIAN
Ralf Baechle21a151d2007-10-11 23:46:15 +010058#define endian_def_s2(e1, e2) \
59 volatile unsigned short e1, e2
60#define endian_def_sb2(e1, e2, e3) \
61 volatile unsigned short e1;volatile unsigned char e2, e3
62#define endian_def_b2s(e1, e2, e3) \
63 volatile unsigned char e1, e2;volatile unsigned short e3
64#define endian_def_b4(e1, e2, e3, e4) \
65 volatile unsigned char e1, e2, e3, e4
Linus Torvalds1da177e2005-04-16 15:20:36 -070066#else
Ralf Baechle21a151d2007-10-11 23:46:15 +010067#define endian_def_s2(e1, e2) \
68 volatile unsigned short e2, e1
69#define endian_def_sb2(e1, e2, e3) \
70 volatile unsigned char e3, e2;volatile unsigned short e1
71#define endian_def_b2s(e1, e2, e3) \
72 volatile unsigned short e3;volatile unsigned char e2, e1
73#define endian_def_b4(e1, e2, e3, e4) \
74 volatile unsigned char e4, e3, e2, e1
Linus Torvalds1da177e2005-04-16 15:20:36 -070075#endif
76
77struct tx3927_pcic_reg {
78 endian_def_s2(did, vid);
79 endian_def_s2(pcistat, pcicmd);
80 endian_def_b4(cc, scc, rpli, rid);
81 endian_def_b4(unused0, ht, mlt, cls);
82 volatile unsigned long ioba; /* +10 */
83 volatile unsigned long mba;
84 volatile unsigned long unused1[5];
85 endian_def_s2(svid, ssvid);
86 volatile unsigned long unused2; /* +30 */
87 endian_def_sb2(unused3, unused4, capptr);
88 volatile unsigned long unused5;
89 endian_def_b4(ml, mg, ip, il);
90 volatile unsigned long unused6; /* +40 */
91 volatile unsigned long istat;
92 volatile unsigned long iim;
93 volatile unsigned long rrt;
94 volatile unsigned long unused7[3]; /* +50 */
95 volatile unsigned long ipbmma;
96 volatile unsigned long ipbioma; /* +60 */
97 volatile unsigned long ilbmma;
98 volatile unsigned long ilbioma;
99 volatile unsigned long unused8[9];
100 volatile unsigned long tc; /* +90 */
101 volatile unsigned long tstat;
102 volatile unsigned long tim;
103 volatile unsigned long tccmd;
104 volatile unsigned long pcirrt; /* +a0 */
105 volatile unsigned long pcirrt_cmd;
106 volatile unsigned long pcirrdt;
107 volatile unsigned long unused9[3];
108 volatile unsigned long tlboap;
109 volatile unsigned long tlbiap;
110 volatile unsigned long tlbmma; /* +c0 */
111 volatile unsigned long tlbioma;
112 volatile unsigned long sc_msg;
113 volatile unsigned long sc_be;
114 volatile unsigned long tbl; /* +d0 */
115 volatile unsigned long unused10[3];
116 volatile unsigned long pwmng; /* +e0 */
117 volatile unsigned long pwmngs;
118 volatile unsigned long unused11[6];
119 volatile unsigned long req_trace; /* +100 */
120 volatile unsigned long pbapmc;
121 volatile unsigned long pbapms;
122 volatile unsigned long pbapmim;
123 volatile unsigned long bm; /* +110 */
124 volatile unsigned long cpcibrs;
125 volatile unsigned long cpcibgs;
126 volatile unsigned long pbacs;
127 volatile unsigned long iobas; /* +120 */
128 volatile unsigned long mbas;
129 volatile unsigned long lbc;
130 volatile unsigned long lbstat;
131 volatile unsigned long lbim; /* +130 */
132 volatile unsigned long pcistatim;
133 volatile unsigned long ica;
134 volatile unsigned long icd;
135 volatile unsigned long iiadp; /* +140 */
136 volatile unsigned long iscdp;
137 volatile unsigned long mmas;
138 volatile unsigned long iomas;
139 volatile unsigned long ipciaddr; /* +150 */
140 volatile unsigned long ipcidata;
141 volatile unsigned long ipcibe;
142};
143
144struct tx3927_ccfg_reg {
145 volatile unsigned long ccfg;
146 volatile unsigned long crir;
147 volatile unsigned long pcfg;
148 volatile unsigned long tear;
149 volatile unsigned long pdcr;
150};
151
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152/*
153 * SDRAMC
154 */
155
156/*
157 * ROMC
158 */
159
160/*
161 * DMA
162 */
163/* bits for MCR */
164#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
165#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
166#define TX3927_DMA_MCR_RSFIF 0x00000080
167#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
168#define TX3927_DMA_MCR_LE 0x00000004
169#define TX3927_DMA_MCR_RPRT 0x00000002
170#define TX3927_DMA_MCR_MSTEN 0x00000001
171
172/* bits for CCRn */
173#define TX3927_DMA_CCR_DBINH 0x04000000
174#define TX3927_DMA_CCR_SBINH 0x02000000
175#define TX3927_DMA_CCR_CHRST 0x01000000
176#define TX3927_DMA_CCR_RVBYTE 0x00800000
177#define TX3927_DMA_CCR_ACKPOL 0x00400000
178#define TX3927_DMA_CCR_REQPL 0x00200000
179#define TX3927_DMA_CCR_EGREQ 0x00100000
180#define TX3927_DMA_CCR_CHDN 0x00080000
181#define TX3927_DMA_CCR_DNCTL 0x00060000
182#define TX3927_DMA_CCR_EXTRQ 0x00010000
183#define TX3927_DMA_CCR_INTRQD 0x0000e000
184#define TX3927_DMA_CCR_INTENE 0x00001000
185#define TX3927_DMA_CCR_INTENC 0x00000800
186#define TX3927_DMA_CCR_INTENT 0x00000400
187#define TX3927_DMA_CCR_CHNEN 0x00000200
188#define TX3927_DMA_CCR_XFACT 0x00000100
189#define TX3927_DMA_CCR_SNOP 0x00000080
190#define TX3927_DMA_CCR_DSTINC 0x00000040
191#define TX3927_DMA_CCR_SRCINC 0x00000020
192#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
193#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
194#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
195#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
196#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
197#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
198#define TX3927_DMA_CCR_MEMIO 0x00000002
199#define TX3927_DMA_CCR_ONEAD 0x00000001
200
201/* bits for CSRn */
202#define TX3927_DMA_CSR_CHNACT 0x00000100
203#define TX3927_DMA_CSR_ABCHC 0x00000080
204#define TX3927_DMA_CSR_NCHNC 0x00000040
205#define TX3927_DMA_CSR_NTRNFC 0x00000020
206#define TX3927_DMA_CSR_EXTDN 0x00000010
207#define TX3927_DMA_CSR_CFERR 0x00000008
208#define TX3927_DMA_CSR_CHERR 0x00000004
209#define TX3927_DMA_CSR_DESERR 0x00000002
210#define TX3927_DMA_CSR_SORERR 0x00000001
211
212/*
213 * IRC
214 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215#define TX3927_IR_INT0 0
216#define TX3927_IR_INT1 1
217#define TX3927_IR_INT2 2
218#define TX3927_IR_INT3 3
219#define TX3927_IR_INT4 4
220#define TX3927_IR_INT5 5
221#define TX3927_IR_SIO0 6
222#define TX3927_IR_SIO1 7
223#define TX3927_IR_SIO(ch) (6 + (ch))
224#define TX3927_IR_DMA 8
225#define TX3927_IR_PIO 9
226#define TX3927_IR_PCI 10
Atsushi Nemoto229f7732007-10-25 01:34:09 +0900227#define TX3927_IR_TMR(ch) (13 + (ch))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228#define TX3927_NUM_IR 16
229
230/*
231 * PCIC
232 */
233/* bits for PCICMD */
234/* see PCI_COMMAND_XXX in linux/pci.h */
235
236/* bits for PCISTAT */
237/* see PCI_STATUS_XXX in linux/pci.h */
238#define PCI_STATUS_NEW_CAP 0x0010
239
Atsushi Nemoto455cc252008-07-25 23:01:35 +0900240/* bits for ISTAT/IIM */
241#define TX3927_PCIC_IIM_ALL 0x00001600
242
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243/* bits for TC */
244#define TX3927_PCIC_TC_OF16E 0x00000020
245#define TX3927_PCIC_TC_IF8E 0x00000010
246#define TX3927_PCIC_TC_OF8E 0x00000008
247
Atsushi Nemoto455cc252008-07-25 23:01:35 +0900248/* bits for TSTAT/TIM */
249#define TX3927_PCIC_TIM_ALL 0x0003ffff
250
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251/* bits for IOBA/MBA */
252/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
253
254/* bits for PBAPMC */
255#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
256#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
257#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
258
259/* bits for LBSTAT/LBIM */
260#define TX3927_PCIC_LBIM_ALL 0x0000003e
261
262/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
263#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
264
265/* bits for LBC */
266#define TX3927_PCIC_LBC_IBSE 0x00004000
267#define TX3927_PCIC_LBC_TIBSE 0x00002000
268#define TX3927_PCIC_LBC_TMFBSE 0x00001000
269#define TX3927_PCIC_LBC_HRST 0x00000800
270#define TX3927_PCIC_LBC_SRST 0x00000400
271#define TX3927_PCIC_LBC_EPCAD 0x00000200
272#define TX3927_PCIC_LBC_MSDSE 0x00000100
273#define TX3927_PCIC_LBC_CRR 0x00000080
274#define TX3927_PCIC_LBC_ILMDE 0x00000040
275#define TX3927_PCIC_LBC_ILIDE 0x00000020
276
277#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
278#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
279
280/*
281 * CCFG
282 */
283/* CCFG : Chip Configuration */
284#define TX3927_CCFG_TLBOFF 0x00020000
285#define TX3927_CCFG_BEOW 0x00010000
286#define TX3927_CCFG_WR 0x00008000
287#define TX3927_CCFG_TOE 0x00004000
288#define TX3927_CCFG_PCIXARB 0x00002000
289#define TX3927_CCFG_PCI3 0x00001000
290#define TX3927_CCFG_PSNP 0x00000800
291#define TX3927_CCFG_PPRI 0x00000400
292#define TX3927_CCFG_PLLM 0x00000030
293#define TX3927_CCFG_ENDIAN 0x00000004
294#define TX3927_CCFG_HALT 0x00000002
295#define TX3927_CCFG_ACEHOLD 0x00000001
296
297/* PCFG : Pin Configuration */
298#define TX3927_PCFG_SYSCLKEN 0x08000000
299#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
300#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
301#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
302#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
303#define TX3927_PCFG_SELALL 0x0003ffff
304#define TX3927_PCFG_SELCS 0x00020000
305#define TX3927_PCFG_SELDSF 0x00010000
306#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
307#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
308#define TX3927_PCFG_SELSIO_ALL 0x00003000
309#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
310#define TX3927_PCFG_SELTMR_ALL 0x00000e00
311#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
312#define TX3927_PCFG_SELDONE 0x00000100
313#define TX3927_PCFG_INTDMA_ALL 0x000000f0
314#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
315#define TX3927_PCFG_SELDMA_ALL 0x0000000f
316#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
317
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
319#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
320#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
322#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
Atsushi Nemoto1bd09622008-04-05 00:56:27 +0900324#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325
Atsushi Nemotof6727fb2008-07-24 00:25:19 +0900326#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
327#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
328#define TX3927_ROMC_SIZE(ch) \
329 (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
330
331void tx3927_wdt_init(void);
332void tx3927_setup(void);
333void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
334void tx3927_setup_serial(unsigned int cts_mask);
Atsushi Nemoto89d63fe2008-07-11 00:33:08 +0900335struct pci_controller;
Atsushi Nemotobb72f1f2008-07-24 00:25:21 +0900336void tx3927_pcic_setup(struct pci_controller *channel,
337 unsigned long sdram_size, int extarb);
Atsushi Nemoto455cc252008-07-25 23:01:35 +0900338void tx3927_setup_pcierr_irq(void);
Atsushi Nemotof6727fb2008-07-24 00:25:19 +0900339void tx3927_irq_init(void);
Atsushi Nemoto89d63fe2008-07-11 00:33:08 +0900340
Atsushi Nemoto22b1d702008-07-11 00:31:36 +0900341#endif /* __ASM_TXX9_TX3927_H */