blob: 224ce1dbb1cb9eecb0b9b183783ef7ce30198fd6 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Reding1503ca42014-11-24 17:41:23 +010036static void tegra_atomic_schedule(struct tegra_drm *tegra,
37 struct drm_atomic_state *state)
38{
39 tegra->commit.state = state;
40 schedule_work(&tegra->commit.work);
41}
42
43static void tegra_atomic_complete(struct tegra_drm *tegra,
44 struct drm_atomic_state *state)
45{
46 struct drm_device *drm = tegra->drm;
47
48 /*
49 * Everything below can be run asynchronously without the need to grab
50 * any modeset locks at all under one condition: It must be guaranteed
51 * that the asynchronous work has either been cancelled (if the driver
52 * supports it, which at least requires that the framebuffers get
53 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
54 * before the new state gets committed on the software side with
55 * drm_atomic_helper_swap_state().
56 *
57 * This scheme allows new atomic state updates to be prepared and
58 * checked in parallel to the asynchronous completion of the previous
59 * update. Which is important since compositors need to figure out the
60 * composition of the next frame right after having submitted the
61 * current layout.
62 */
63
Daniel Vetter1af434a2015-02-22 12:24:19 +010064 drm_atomic_helper_commit_modeset_disables(drm, state);
Daniel Vetter1af434a2015-02-22 12:24:19 +010065 drm_atomic_helper_commit_modeset_enables(drm, state);
Liu Ying2b58e982016-08-29 17:12:03 +080066 drm_atomic_helper_commit_planes(drm, state,
67 DRM_PLANE_COMMIT_ACTIVE_ONLY);
Thierry Reding1503ca42014-11-24 17:41:23 +010068
69 drm_atomic_helper_wait_for_vblanks(drm, state);
70
71 drm_atomic_helper_cleanup_planes(drm, state);
Chris Wilson08536952016-10-14 13:18:18 +010072 drm_atomic_state_put(state);
Thierry Reding1503ca42014-11-24 17:41:23 +010073}
74
75static void tegra_atomic_work(struct work_struct *work)
76{
77 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
78 commit.work);
79
80 tegra_atomic_complete(tegra, tegra->commit.state);
81}
82
83static int tegra_atomic_commit(struct drm_device *drm,
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020084 struct drm_atomic_state *state, bool nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +010085{
86 struct tegra_drm *tegra = drm->dev_private;
87 int err;
88
89 err = drm_atomic_helper_prepare_planes(drm, state);
90 if (err)
91 return err;
92
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020093 /* serialize outstanding nonblocking commits */
Thierry Reding1503ca42014-11-24 17:41:23 +010094 mutex_lock(&tegra->commit.lock);
95 flush_work(&tegra->commit.work);
96
97 /*
98 * This is the point of no return - everything below never fails except
99 * when the hw goes bonghits. Which means we can commit the new state on
100 * the software side now.
101 */
102
Maarten Lankhorst424624e2017-07-11 16:33:10 +0200103 err = drm_atomic_helper_swap_state(state, true);
104 if (err) {
105 mutex_unlock(&tegra->commit.lock);
106 drm_atomic_helper_cleanup_planes(drm, state);
107 return err;
108 }
Thierry Reding1503ca42014-11-24 17:41:23 +0100109
Chris Wilson08536952016-10-14 13:18:18 +0100110 drm_atomic_state_get(state);
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +0200111 if (nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +0100112 tegra_atomic_schedule(tegra, state);
113 else
114 tegra_atomic_complete(tegra, state);
115
116 mutex_unlock(&tegra->commit.lock);
117 return 0;
118}
119
Thierry Redingf9914212014-11-26 13:03:57 +0100120static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
121 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +0530122#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +0100123 .output_poll_changed = tegra_fb_output_poll_changed,
124#endif
Thierry Reding07866962014-11-24 17:08:06 +0100125 .atomic_check = drm_atomic_helper_check,
Thierry Reding1503ca42014-11-24 17:41:23 +0100126 .atomic_commit = tegra_atomic_commit,
Thierry Redingf9914212014-11-26 13:03:57 +0100127};
128
Thierry Reding776dc382013-10-14 14:43:22 +0200129static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000130{
Thierry Reding776dc382013-10-14 14:43:22 +0200131 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200132 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000133 int err;
134
Thierry Reding776dc382013-10-14 14:43:22 +0200135 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200136 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200137 return -ENOMEM;
138
Thierry Redingdf06b752014-06-26 21:41:53 +0200139 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200140 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100141 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200142 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100143
Thierry Redingdf06b752014-06-26 21:41:53 +0200144 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300145 if (!tegra->domain) {
146 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200147 goto free;
148 }
149
Thierry Reding4553f732015-01-19 16:15:04 +0100150 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200151 gem_start = geometry->aperture_start;
152 gem_end = geometry->aperture_end - CARVEOUT_SZ;
153 carveout_start = gem_end + 1;
154 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100155
Mikko Perttunenad926012016-12-14 13:16:11 +0200156 order = __ffs(tegra->domain->pgsize_bitmap);
157 init_iova_domain(&tegra->carveout.domain, 1UL << order,
158 carveout_start >> order,
159 carveout_end >> order);
160
161 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
162 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
163
164 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100165 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200166
167 DRM_DEBUG("IOMMU apertures:\n");
168 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
169 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
170 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200171 }
172
Thierry Reding386a2a72013-09-24 13:22:17 +0200173 mutex_init(&tegra->clients_lock);
174 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100175
176 mutex_init(&tegra->commit.lock);
177 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
178
Thierry Reding386a2a72013-09-24 13:22:17 +0200179 drm->dev_private = tegra;
180 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000181
182 drm_mode_config_init(drm);
183
Thierry Redingf9914212014-11-26 13:03:57 +0100184 drm->mode_config.min_width = 0;
185 drm->mode_config.min_height = 0;
186
187 drm->mode_config.max_width = 4096;
188 drm->mode_config.max_height = 4096;
189
Alexandre Courbot5e911442016-11-08 16:50:42 +0900190 drm->mode_config.allow_fb_modifiers = true;
191
Thierry Redingf9914212014-11-26 13:03:57 +0100192 drm->mode_config.funcs = &tegra_drm_mode_funcs;
193
Thierry Redinge2215322014-06-27 17:19:25 +0200194 err = tegra_drm_fb_prepare(drm);
195 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100196 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200197
198 drm_kms_helper_poll_init(drm);
199
Thierry Reding776dc382013-10-14 14:43:22 +0200200 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000201 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100202 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000203
Thierry Reding603f0cc2013-04-22 21:22:14 +0200204 /*
205 * We don't use the drm_irq_install() helpers provided by the DRM
206 * core, so we need to set this manually in order to allow the
207 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
208 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300209 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200210
Thierry Reding42e9ce02015-01-28 14:43:05 +0100211 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100212 drm->max_vblank_count = 0xffffffff;
213
Thierry Reding6e5ff992012-11-28 11:45:47 +0100214 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
215 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100216 goto device;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100217
Thierry Reding31930d42015-07-02 17:04:06 +0200218 drm_mode_config_reset(drm);
219
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000220 err = tegra_drm_fb_init(drm);
221 if (err < 0)
Daniel Vetter00a91212017-05-24 16:52:08 +0200222 goto device;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000223
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000224 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100225
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100226device:
227 host1x_device_exit(device);
228fbdev:
229 drm_kms_helper_poll_fini(drm);
230 tegra_drm_fb_free(drm);
231config:
232 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200233
234 if (tegra->domain) {
235 iommu_domain_free(tegra->domain);
236 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100237 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200238 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200239 }
240free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100241 kfree(tegra);
242 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000243}
244
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200245static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000246{
Thierry Reding776dc382013-10-14 14:43:22 +0200247 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200248 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200249 int err;
250
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000251 drm_kms_helper_poll_fini(drm);
252 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200253 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000254
Thierry Reding776dc382013-10-14 14:43:22 +0200255 err = host1x_device_exit(device);
256 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200257 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200258
Thierry Redingdf06b752014-06-26 21:41:53 +0200259 if (tegra->domain) {
260 iommu_domain_free(tegra->domain);
261 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100262 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200263 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200264 }
265
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100266 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000267}
268
269static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
270{
Thierry Reding08943e62013-09-26 16:08:18 +0200271 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200272
273 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
274 if (!fpriv)
275 return -ENOMEM;
276
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100277 idr_init(&fpriv->contexts);
278 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200279 filp->driver_priv = fpriv;
280
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000281 return 0;
282}
283
Thierry Redingc88c3632013-09-26 16:08:22 +0200284static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200285{
286 context->client->ops->close_channel(context);
287 kfree(context);
288}
289
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000290static void tegra_drm_lastclose(struct drm_device *drm)
291{
Archit Tanejab110ef32015-10-27 13:40:59 +0530292#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200293 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000294
Thierry Reding386a2a72013-09-24 13:22:17 +0200295 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100296#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000297}
298
Thierry Redingc40f0f12013-10-10 11:00:33 +0200299static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100300host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200301{
302 struct drm_gem_object *gem;
303 struct tegra_bo *bo;
304
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100305 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200306 if (!gem)
307 return NULL;
308
Daniel Vettera07cdfe2015-11-23 10:32:48 +0100309 drm_gem_object_unreference_unlocked(gem);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200310
311 bo = to_tegra_bo(gem);
312 return &bo->base;
313}
314
Thierry Reding961e3be2014-06-10 10:25:00 +0200315static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
316 struct drm_tegra_reloc __user *src,
317 struct drm_device *drm,
318 struct drm_file *file)
319{
320 u32 cmdbuf, target;
321 int err;
322
323 err = get_user(cmdbuf, &src->cmdbuf.handle);
324 if (err < 0)
325 return err;
326
327 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
328 if (err < 0)
329 return err;
330
331 err = get_user(target, &src->target.handle);
332 if (err < 0)
333 return err;
334
David Ung31f40f82015-01-20 18:37:35 -0800335 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200336 if (err < 0)
337 return err;
338
339 err = get_user(dest->shift, &src->shift);
340 if (err < 0)
341 return err;
342
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100343 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200344 if (!dest->cmdbuf.bo)
345 return -ENOENT;
346
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100347 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200348 if (!dest->target.bo)
349 return -ENOENT;
350
351 return 0;
352}
353
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300354static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
355 struct drm_tegra_waitchk __user *src,
356 struct drm_file *file)
357{
358 u32 cmdbuf;
359 int err;
360
361 err = get_user(cmdbuf, &src->handle);
362 if (err < 0)
363 return err;
364
365 err = get_user(dest->offset, &src->offset);
366 if (err < 0)
367 return err;
368
369 err = get_user(dest->syncpt_id, &src->syncpt);
370 if (err < 0)
371 return err;
372
373 err = get_user(dest->thresh, &src->thresh);
374 if (err < 0)
375 return err;
376
377 dest->bo = host1x_bo_lookup(file, cmdbuf);
378 if (!dest->bo)
379 return -ENOENT;
380
381 return 0;
382}
383
Thierry Redingc40f0f12013-10-10 11:00:33 +0200384int tegra_drm_submit(struct tegra_drm_context *context,
385 struct drm_tegra_submit *args, struct drm_device *drm,
386 struct drm_file *file)
387{
388 unsigned int num_cmdbufs = args->num_cmdbufs;
389 unsigned int num_relocs = args->num_relocs;
390 unsigned int num_waitchks = args->num_waitchks;
391 struct drm_tegra_cmdbuf __user *cmdbufs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100392 (void __user *)(uintptr_t)args->cmdbufs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200393 struct drm_tegra_reloc __user *relocs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100394 (void __user *)(uintptr_t)args->relocs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200395 struct drm_tegra_waitchk __user *waitchks =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100396 (void __user *)(uintptr_t)args->waitchks;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200397 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300398 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
399 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200400 struct host1x_job *job;
401 int err;
402
403 /* We don't yet support other than one syncpt_incr struct per submit */
404 if (args->num_syncpts != 1)
405 return -EINVAL;
406
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300407 /* We don't yet support waitchks */
408 if (args->num_waitchks != 0)
409 return -EINVAL;
410
Thierry Redingc40f0f12013-10-10 11:00:33 +0200411 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
412 args->num_relocs, args->num_waitchks);
413 if (!job)
414 return -ENOMEM;
415
416 job->num_relocs = args->num_relocs;
417 job->num_waitchk = args->num_waitchks;
418 job->client = (u32)args->context;
419 job->class = context->client->base.class;
420 job->serialize = true;
421
422 while (num_cmdbufs) {
423 struct drm_tegra_cmdbuf cmdbuf;
424 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300425 struct tegra_bo *obj;
426 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200427
Dan Carpenter9a991602013-11-08 13:07:37 +0300428 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
429 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200430 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300431 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200432
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300433 /*
434 * The maximum number of CDMA gather fetches is 16383, a higher
435 * value means the words count is malformed.
436 */
437 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
438 err = -EINVAL;
439 goto fail;
440 }
441
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100442 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200443 if (!bo) {
444 err = -ENOENT;
445 goto fail;
446 }
447
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300448 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
449 obj = host1x_to_tegra_bo(bo);
450
451 /*
452 * Gather buffer base address must be 4-bytes aligned,
453 * unaligned offset is malformed and cause commands stream
454 * corruption on the buffer address relocation.
455 */
456 if (offset & 3 || offset >= obj->gem.size) {
457 err = -EINVAL;
458 goto fail;
459 }
460
Thierry Redingc40f0f12013-10-10 11:00:33 +0200461 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
462 num_cmdbufs--;
463 cmdbufs++;
464 }
465
Thierry Reding961e3be2014-06-10 10:25:00 +0200466 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200467 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300468 struct host1x_reloc *reloc;
469 struct tegra_bo *obj;
470
Thierry Reding961e3be2014-06-10 10:25:00 +0200471 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
472 &relocs[num_relocs], drm,
473 file);
474 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200475 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300476
477 reloc = &job->relocarray[num_relocs];
478 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
479
480 /*
481 * The unaligned cmdbuf offset will cause an unaligned write
482 * during of the relocations patching, corrupting the commands
483 * stream.
484 */
485 if (reloc->cmdbuf.offset & 3 ||
486 reloc->cmdbuf.offset >= obj->gem.size) {
487 err = -EINVAL;
488 goto fail;
489 }
490
491 obj = host1x_to_tegra_bo(reloc->target.bo);
492
493 if (reloc->target.offset >= obj->gem.size) {
494 err = -EINVAL;
495 goto fail;
496 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200497 }
498
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300499 /* copy and resolve waitchks from submit */
500 while (num_waitchks--) {
501 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
502 struct tegra_bo *obj;
503
504 err = host1x_waitchk_copy_from_user(wait,
505 &waitchks[num_waitchks],
506 file);
507 if (err < 0)
508 goto fail;
509
510 obj = host1x_to_tegra_bo(wait->bo);
511
512 /*
513 * The unaligned offset will cause an unaligned write during
514 * of the waitchks patching, corrupting the commands stream.
515 */
516 if (wait->offset & 3 ||
517 wait->offset >= obj->gem.size) {
518 err = -EINVAL;
519 goto fail;
520 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300521 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200522
Dan Carpenter9a991602013-11-08 13:07:37 +0300523 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
524 sizeof(syncpt))) {
525 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200526 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300527 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200528
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300529 /* check whether syncpoint ID is valid */
530 sp = host1x_syncpt_get(host1x, syncpt.id);
531 if (!sp) {
532 err = -ENOENT;
533 goto fail;
534 }
535
Thierry Redingc40f0f12013-10-10 11:00:33 +0200536 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300537 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200538 job->syncpt_incrs = syncpt.incrs;
539 job->syncpt_id = syncpt.id;
540 job->timeout = 10000;
541
542 if (args->timeout && args->timeout < 10000)
543 job->timeout = args->timeout;
544
545 err = host1x_job_pin(job, context->client->base.dev);
546 if (err)
547 goto fail;
548
549 err = host1x_job_submit(job);
550 if (err)
551 goto fail_submit;
552
553 args->fence = job->syncpt_end;
554
555 host1x_job_put(job);
556 return 0;
557
558fail_submit:
559 host1x_job_unpin(job);
560fail:
561 host1x_job_put(job);
562 return err;
563}
564
565
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200566#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200567static int tegra_gem_create(struct drm_device *drm, void *data,
568 struct drm_file *file)
569{
570 struct drm_tegra_gem_create *args = data;
571 struct tegra_bo *bo;
572
Thierry Reding773af772013-10-04 22:34:01 +0200573 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200574 &args->handle);
575 if (IS_ERR(bo))
576 return PTR_ERR(bo);
577
578 return 0;
579}
580
581static int tegra_gem_mmap(struct drm_device *drm, void *data,
582 struct drm_file *file)
583{
584 struct drm_tegra_gem_mmap *args = data;
585 struct drm_gem_object *gem;
586 struct tegra_bo *bo;
587
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100588 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200589 if (!gem)
590 return -EINVAL;
591
592 bo = to_tegra_bo(gem);
593
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200594 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200595
Daniel Vetter11533302015-11-23 10:32:40 +0100596 drm_gem_object_unreference_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200597
598 return 0;
599}
600
601static int tegra_syncpt_read(struct drm_device *drm, void *data,
602 struct drm_file *file)
603{
Thierry Reding776dc382013-10-14 14:43:22 +0200604 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200605 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200606 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200607
Thierry Reding776dc382013-10-14 14:43:22 +0200608 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200609 if (!sp)
610 return -EINVAL;
611
612 args->value = host1x_syncpt_read_min(sp);
613 return 0;
614}
615
616static int tegra_syncpt_incr(struct drm_device *drm, void *data,
617 struct drm_file *file)
618{
Thierry Reding776dc382013-10-14 14:43:22 +0200619 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200620 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200621 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200622
Thierry Reding776dc382013-10-14 14:43:22 +0200623 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200624 if (!sp)
625 return -EINVAL;
626
Arto Merilainenebae30b2013-05-29 13:26:08 +0300627 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200628}
629
630static int tegra_syncpt_wait(struct drm_device *drm, void *data,
631 struct drm_file *file)
632{
Thierry Reding776dc382013-10-14 14:43:22 +0200633 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200634 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200635 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200636
Thierry Reding776dc382013-10-14 14:43:22 +0200637 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200638 if (!sp)
639 return -EINVAL;
640
641 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
642 &args->value);
643}
644
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100645static int tegra_client_open(struct tegra_drm_file *fpriv,
646 struct tegra_drm_client *client,
647 struct tegra_drm_context *context)
648{
649 int err;
650
651 err = client->ops->open_channel(client, context);
652 if (err < 0)
653 return err;
654
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300655 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100656 if (err < 0) {
657 client->ops->close_channel(context);
658 return err;
659 }
660
661 context->client = client;
662 context->id = err;
663
664 return 0;
665}
666
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200667static int tegra_open_channel(struct drm_device *drm, void *data,
668 struct drm_file *file)
669{
Thierry Reding08943e62013-09-26 16:08:18 +0200670 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200671 struct tegra_drm *tegra = drm->dev_private;
672 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200673 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200674 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200675 int err = -ENODEV;
676
677 context = kzalloc(sizeof(*context), GFP_KERNEL);
678 if (!context)
679 return -ENOMEM;
680
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100681 mutex_lock(&fpriv->lock);
682
Thierry Reding776dc382013-10-14 14:43:22 +0200683 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200684 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100685 err = tegra_client_open(fpriv, client, context);
686 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200687 break;
688
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100689 args->context = context->id;
690 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200691 }
692
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100693 if (err < 0)
694 kfree(context);
695
696 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200697 return err;
698}
699
700static int tegra_close_channel(struct drm_device *drm, void *data,
701 struct drm_file *file)
702{
Thierry Reding08943e62013-09-26 16:08:18 +0200703 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200704 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200705 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100706 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200707
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100708 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200709
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300710 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100711 if (!context) {
712 err = -EINVAL;
713 goto unlock;
714 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200715
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100716 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200717 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200718
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100719unlock:
720 mutex_unlock(&fpriv->lock);
721 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200722}
723
724static int tegra_get_syncpt(struct drm_device *drm, void *data,
725 struct drm_file *file)
726{
Thierry Reding08943e62013-09-26 16:08:18 +0200727 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200728 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200729 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200730 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100731 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200732
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100733 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200734
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300735 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100736 if (!context) {
737 err = -ENODEV;
738 goto unlock;
739 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200740
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100741 if (args->index >= context->client->base.num_syncpts) {
742 err = -EINVAL;
743 goto unlock;
744 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200745
Thierry Reding53fa7f72013-09-24 15:35:40 +0200746 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200747 args->id = host1x_syncpt_id(syncpt);
748
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100749unlock:
750 mutex_unlock(&fpriv->lock);
751 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200752}
753
754static int tegra_submit(struct drm_device *drm, void *data,
755 struct drm_file *file)
756{
Thierry Reding08943e62013-09-26 16:08:18 +0200757 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200758 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200759 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100760 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200761
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100762 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200763
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300764 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100765 if (!context) {
766 err = -ENODEV;
767 goto unlock;
768 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200769
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100770 err = context->client->ops->submit(context, args, drm, file);
771
772unlock:
773 mutex_unlock(&fpriv->lock);
774 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200775}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300776
777static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
778 struct drm_file *file)
779{
780 struct tegra_drm_file *fpriv = file->driver_priv;
781 struct drm_tegra_get_syncpt_base *args = data;
782 struct tegra_drm_context *context;
783 struct host1x_syncpt_base *base;
784 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100785 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300786
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100787 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300788
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300789 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100790 if (!context) {
791 err = -ENODEV;
792 goto unlock;
793 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300794
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100795 if (args->syncpt >= context->client->base.num_syncpts) {
796 err = -EINVAL;
797 goto unlock;
798 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300799
800 syncpt = context->client->base.syncpts[args->syncpt];
801
802 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100803 if (!base) {
804 err = -ENXIO;
805 goto unlock;
806 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300807
808 args->id = host1x_syncpt_base_id(base);
809
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100810unlock:
811 mutex_unlock(&fpriv->lock);
812 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300813}
Thierry Reding7678d712014-06-03 14:56:57 +0200814
815static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
816 struct drm_file *file)
817{
818 struct drm_tegra_gem_set_tiling *args = data;
819 enum tegra_bo_tiling_mode mode;
820 struct drm_gem_object *gem;
821 unsigned long value = 0;
822 struct tegra_bo *bo;
823
824 switch (args->mode) {
825 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
826 mode = TEGRA_BO_TILING_MODE_PITCH;
827
828 if (args->value != 0)
829 return -EINVAL;
830
831 break;
832
833 case DRM_TEGRA_GEM_TILING_MODE_TILED:
834 mode = TEGRA_BO_TILING_MODE_TILED;
835
836 if (args->value != 0)
837 return -EINVAL;
838
839 break;
840
841 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
842 mode = TEGRA_BO_TILING_MODE_BLOCK;
843
844 if (args->value > 5)
845 return -EINVAL;
846
847 value = args->value;
848 break;
849
850 default:
851 return -EINVAL;
852 }
853
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100854 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200855 if (!gem)
856 return -ENOENT;
857
858 bo = to_tegra_bo(gem);
859
860 bo->tiling.mode = mode;
861 bo->tiling.value = value;
862
Daniel Vetter11533302015-11-23 10:32:40 +0100863 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200864
865 return 0;
866}
867
868static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
869 struct drm_file *file)
870{
871 struct drm_tegra_gem_get_tiling *args = data;
872 struct drm_gem_object *gem;
873 struct tegra_bo *bo;
874 int err = 0;
875
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100876 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200877 if (!gem)
878 return -ENOENT;
879
880 bo = to_tegra_bo(gem);
881
882 switch (bo->tiling.mode) {
883 case TEGRA_BO_TILING_MODE_PITCH:
884 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
885 args->value = 0;
886 break;
887
888 case TEGRA_BO_TILING_MODE_TILED:
889 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
890 args->value = 0;
891 break;
892
893 case TEGRA_BO_TILING_MODE_BLOCK:
894 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
895 args->value = bo->tiling.value;
896 break;
897
898 default:
899 err = -EINVAL;
900 break;
901 }
902
Daniel Vetter11533302015-11-23 10:32:40 +0100903 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200904
905 return err;
906}
Thierry Reding7b129082014-06-10 12:04:03 +0200907
908static int tegra_gem_set_flags(struct drm_device *drm, void *data,
909 struct drm_file *file)
910{
911 struct drm_tegra_gem_set_flags *args = data;
912 struct drm_gem_object *gem;
913 struct tegra_bo *bo;
914
915 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
916 return -EINVAL;
917
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100918 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200919 if (!gem)
920 return -ENOENT;
921
922 bo = to_tegra_bo(gem);
923 bo->flags = 0;
924
925 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
926 bo->flags |= TEGRA_BO_BOTTOM_UP;
927
Daniel Vetter11533302015-11-23 10:32:40 +0100928 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200929
930 return 0;
931}
932
933static int tegra_gem_get_flags(struct drm_device *drm, void *data,
934 struct drm_file *file)
935{
936 struct drm_tegra_gem_get_flags *args = data;
937 struct drm_gem_object *gem;
938 struct tegra_bo *bo;
939
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100940 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200941 if (!gem)
942 return -ENOENT;
943
944 bo = to_tegra_bo(gem);
945 args->flags = 0;
946
947 if (bo->flags & TEGRA_BO_BOTTOM_UP)
948 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
949
Daniel Vetter11533302015-11-23 10:32:40 +0100950 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200951
952 return 0;
953}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200954#endif
955
Rob Clarkbaa70942013-08-02 13:27:49 -0400956static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200957#ifdef CONFIG_DRM_TEGRA_STAGING
Daniel Vetterf8c47142015-09-08 13:56:30 +0200958 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
959 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
960 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
961 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
962 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
963 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
964 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
965 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
966 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
967 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
968 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
969 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
970 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
971 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200972#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000973};
974
975static const struct file_operations tegra_drm_fops = {
976 .owner = THIS_MODULE,
977 .open = drm_open,
978 .release = drm_release,
979 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200980 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000981 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000982 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000983 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000984 .llseek = noop_llseek,
985};
986
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100987static int tegra_drm_context_cleanup(int id, void *p, void *data)
988{
989 struct tegra_drm_context *context = p;
990
991 tegra_drm_context_free(context);
992
993 return 0;
994}
995
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200996static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100997{
Thierry Reding08943e62013-09-26 16:08:18 +0200998 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100999
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001000 mutex_lock(&fpriv->lock);
1001 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1002 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001003
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001004 idr_destroy(&fpriv->contexts);
1005 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001006 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001007}
1008
Thierry Redinge450fcc2013-02-13 16:13:16 +01001009#ifdef CONFIG_DEBUG_FS
1010static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1011{
1012 struct drm_info_node *node = (struct drm_info_node *)s->private;
1013 struct drm_device *drm = node->minor->dev;
1014 struct drm_framebuffer *fb;
1015
1016 mutex_lock(&drm->mode_config.fb_lock);
1017
1018 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1019 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001020 fb->base.id, fb->width, fb->height,
1021 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001022 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001023 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001024 }
1025
1026 mutex_unlock(&drm->mode_config.fb_lock);
1027
1028 return 0;
1029}
1030
Thierry Reding28c23372015-01-23 09:16:03 +01001031static int tegra_debugfs_iova(struct seq_file *s, void *data)
1032{
1033 struct drm_info_node *node = (struct drm_info_node *)s->private;
1034 struct drm_device *drm = node->minor->dev;
1035 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001036 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001037
Thierry Reding347ad49d2017-03-09 20:04:56 +01001038 mutex_lock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +01001039 drm_mm_print(&tegra->mm, &p);
Thierry Reding347ad49d2017-03-09 20:04:56 +01001040 mutex_unlock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +01001041
1042 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001043}
1044
Thierry Redinge450fcc2013-02-13 16:13:16 +01001045static struct drm_info_list tegra_debugfs_list[] = {
1046 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001047 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001048};
1049
1050static int tegra_debugfs_init(struct drm_minor *minor)
1051{
1052 return drm_debugfs_create_files(tegra_debugfs_list,
1053 ARRAY_SIZE(tegra_debugfs_list),
1054 minor->debugfs_root, minor);
1055}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001056#endif
1057
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001058static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001059 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
1060 DRIVER_ATOMIC,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001061 .load = tegra_drm_load,
1062 .unload = tegra_drm_unload,
1063 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001064 .postclose = tegra_drm_postclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001065 .lastclose = tegra_drm_lastclose,
1066
Thierry Redinge450fcc2013-02-13 16:13:16 +01001067#if defined(CONFIG_DEBUG_FS)
1068 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001069#endif
1070
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001071 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001072 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001073
1074 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1075 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1076 .gem_prime_export = tegra_gem_prime_export,
1077 .gem_prime_import = tegra_gem_prime_import,
1078
Arto Merilainende2ba662013-03-22 16:34:08 +02001079 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001080
1081 .ioctls = tegra_drm_ioctls,
1082 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1083 .fops = &tegra_drm_fops,
1084
1085 .name = DRIVER_NAME,
1086 .desc = DRIVER_DESC,
1087 .date = DRIVER_DATE,
1088 .major = DRIVER_MAJOR,
1089 .minor = DRIVER_MINOR,
1090 .patchlevel = DRIVER_PATCHLEVEL,
1091};
Thierry Reding776dc382013-10-14 14:43:22 +02001092
1093int tegra_drm_register_client(struct tegra_drm *tegra,
1094 struct tegra_drm_client *client)
1095{
1096 mutex_lock(&tegra->clients_lock);
1097 list_add_tail(&client->list, &tegra->clients);
1098 mutex_unlock(&tegra->clients_lock);
1099
1100 return 0;
1101}
1102
1103int tegra_drm_unregister_client(struct tegra_drm *tegra,
1104 struct tegra_drm_client *client)
1105{
1106 mutex_lock(&tegra->clients_lock);
1107 list_del_init(&client->list);
1108 mutex_unlock(&tegra->clients_lock);
1109
1110 return 0;
1111}
1112
Mikko Perttunenad926012016-12-14 13:16:11 +02001113void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
1114 dma_addr_t *dma)
1115{
1116 struct iova *alloc;
1117 void *virt;
1118 gfp_t gfp;
1119 int err;
1120
1121 if (tegra->domain)
1122 size = iova_align(&tegra->carveout.domain, size);
1123 else
1124 size = PAGE_ALIGN(size);
1125
1126 gfp = GFP_KERNEL | __GFP_ZERO;
1127 if (!tegra->domain) {
1128 /*
1129 * Many units only support 32-bit addresses, even on 64-bit
1130 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1131 * virtual address space, force allocations to be in the
1132 * lower 32-bit range.
1133 */
1134 gfp |= GFP_DMA;
1135 }
1136
1137 virt = (void *)__get_free_pages(gfp, get_order(size));
1138 if (!virt)
1139 return ERR_PTR(-ENOMEM);
1140
1141 if (!tegra->domain) {
1142 /*
1143 * If IOMMU is disabled, devices address physical memory
1144 * directly.
1145 */
1146 *dma = virt_to_phys(virt);
1147 return virt;
1148 }
1149
1150 alloc = alloc_iova(&tegra->carveout.domain,
1151 size >> tegra->carveout.shift,
1152 tegra->carveout.limit, true);
1153 if (!alloc) {
1154 err = -EBUSY;
1155 goto free_pages;
1156 }
1157
1158 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1159 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1160 size, IOMMU_READ | IOMMU_WRITE);
1161 if (err < 0)
1162 goto free_iova;
1163
1164 return virt;
1165
1166free_iova:
1167 __free_iova(&tegra->carveout.domain, alloc);
1168free_pages:
1169 free_pages((unsigned long)virt, get_order(size));
1170
1171 return ERR_PTR(err);
1172}
1173
1174void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1175 dma_addr_t dma)
1176{
1177 if (tegra->domain)
1178 size = iova_align(&tegra->carveout.domain, size);
1179 else
1180 size = PAGE_ALIGN(size);
1181
1182 if (tegra->domain) {
1183 iommu_unmap(tegra->domain, dma, size);
1184 free_iova(&tegra->carveout.domain,
1185 iova_pfn(&tegra->carveout.domain, dma));
1186 }
1187
1188 free_pages((unsigned long)virt, get_order(size));
1189}
1190
Thierry Reding9910f5c2014-05-22 09:57:15 +02001191static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001192{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001193 struct drm_driver *driver = &tegra_drm_driver;
1194 struct drm_device *drm;
1195 int err;
1196
1197 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001198 if (IS_ERR(drm))
1199 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001200
Thierry Reding9910f5c2014-05-22 09:57:15 +02001201 dev_set_drvdata(&dev->dev, drm);
1202
1203 err = drm_dev_register(drm, 0);
1204 if (err < 0)
1205 goto unref;
1206
Thierry Reding9910f5c2014-05-22 09:57:15 +02001207 return 0;
1208
1209unref:
1210 drm_dev_unref(drm);
1211 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001212}
1213
Thierry Reding9910f5c2014-05-22 09:57:15 +02001214static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001215{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001216 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1217
1218 drm_dev_unregister(drm);
1219 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001220
1221 return 0;
1222}
1223
Thierry Reding359ae682014-12-18 17:15:25 +01001224#ifdef CONFIG_PM_SLEEP
1225static int host1x_drm_suspend(struct device *dev)
1226{
1227 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001228 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001229
1230 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001231 tegra_drm_fb_suspend(drm);
1232
1233 tegra->state = drm_atomic_helper_suspend(drm);
1234 if (IS_ERR(tegra->state)) {
1235 tegra_drm_fb_resume(drm);
1236 drm_kms_helper_poll_enable(drm);
1237 return PTR_ERR(tegra->state);
1238 }
Thierry Reding359ae682014-12-18 17:15:25 +01001239
1240 return 0;
1241}
1242
1243static int host1x_drm_resume(struct device *dev)
1244{
1245 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001246 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001247
Thierry Reding986c58d2015-08-11 13:11:49 +02001248 drm_atomic_helper_resume(drm, tegra->state);
1249 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001250 drm_kms_helper_poll_enable(drm);
1251
1252 return 0;
1253}
1254#endif
1255
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001256static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1257 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001258
Thierry Reding776dc382013-10-14 14:43:22 +02001259static const struct of_device_id host1x_drm_subdevs[] = {
1260 { .compatible = "nvidia,tegra20-dc", },
1261 { .compatible = "nvidia,tegra20-hdmi", },
1262 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001263 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001264 { .compatible = "nvidia,tegra30-dc", },
1265 { .compatible = "nvidia,tegra30-hdmi", },
1266 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001267 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001268 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001269 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001270 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001271 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001272 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001273 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001274 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001275 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001276 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001277 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001278 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001279 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001280 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001281 { .compatible = "nvidia,tegra210-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001282 { /* sentinel */ }
1283};
1284
1285static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001286 .driver = {
1287 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001288 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001289 },
Thierry Reding776dc382013-10-14 14:43:22 +02001290 .probe = host1x_drm_probe,
1291 .remove = host1x_drm_remove,
1292 .subdevs = host1x_drm_subdevs,
1293};
1294
Thierry Reding473112e2015-09-10 16:07:14 +02001295static struct platform_driver * const drivers[] = {
1296 &tegra_dc_driver,
1297 &tegra_hdmi_driver,
1298 &tegra_dsi_driver,
1299 &tegra_dpaux_driver,
1300 &tegra_sor_driver,
1301 &tegra_gr2d_driver,
1302 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001303 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001304};
1305
Thierry Reding776dc382013-10-14 14:43:22 +02001306static int __init host1x_drm_init(void)
1307{
1308 int err;
1309
1310 err = host1x_driver_register(&host1x_drm_driver);
1311 if (err < 0)
1312 return err;
1313
Thierry Reding473112e2015-09-10 16:07:14 +02001314 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001315 if (err < 0)
1316 goto unregister_host1x;
1317
Thierry Reding776dc382013-10-14 14:43:22 +02001318 return 0;
1319
Thierry Reding776dc382013-10-14 14:43:22 +02001320unregister_host1x:
1321 host1x_driver_unregister(&host1x_drm_driver);
1322 return err;
1323}
1324module_init(host1x_drm_init);
1325
1326static void __exit host1x_drm_exit(void)
1327{
Thierry Reding473112e2015-09-10 16:07:14 +02001328 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001329 host1x_driver_unregister(&host1x_drm_driver);
1330}
1331module_exit(host1x_drm_exit);
1332
1333MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1334MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1335MODULE_LICENSE("GPL v2");