Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 29 | #include "radeon.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/radeon_drm.h> |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 31 | #include "radeon_asic.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 32 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 33 | #include <linux/vga_switcheroo.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 36 | /** |
| 37 | * radeon_driver_unload_kms - Main unload function for KMS. |
| 38 | * |
| 39 | * @dev: drm dev pointer |
| 40 | * |
| 41 | * This is the main unload function for KMS (all asics). |
| 42 | * It calls radeon_modeset_fini() to tear down the |
| 43 | * displays, and radeon_device_fini() to tear down |
| 44 | * the rest of the device (CP, writeback, etc.). |
| 45 | * Returns 0 on success. |
| 46 | */ |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 47 | int radeon_driver_unload_kms(struct drm_device *dev) |
| 48 | { |
| 49 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 50 | |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 51 | if (rdev == NULL) |
| 52 | return 0; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 53 | |
Alex Deucher | 0cd9cb7 | 2013-04-12 19:15:52 -0400 | [diff] [blame] | 54 | if (rdev->rmmio == NULL) |
| 55 | goto done_free; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 56 | |
| 57 | pm_runtime_get_sync(dev->dev); |
| 58 | |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 59 | radeon_acpi_fini(rdev); |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 60 | |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 61 | radeon_modeset_fini(rdev); |
| 62 | radeon_device_fini(rdev); |
Alex Deucher | 0cd9cb7 | 2013-04-12 19:15:52 -0400 | [diff] [blame] | 63 | |
| 64 | done_free: |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 65 | kfree(rdev); |
| 66 | dev->dev_private = NULL; |
| 67 | return 0; |
| 68 | } |
| 69 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 70 | /** |
| 71 | * radeon_driver_load_kms - Main load function for KMS. |
| 72 | * |
| 73 | * @dev: drm dev pointer |
| 74 | * @flags: device flags |
| 75 | * |
| 76 | * This is the main load function for KMS (all asics). |
| 77 | * It calls radeon_device_init() to set up the non-display |
| 78 | * parts of the chip (asic init, CP, writeback, etc.), and |
| 79 | * radeon_modeset_init() to set up the display parts |
| 80 | * (crtcs, encoders, hotplug detect, etc.). |
| 81 | * Returns 0 on success, error on failure. |
| 82 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 83 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
| 84 | { |
| 85 | struct radeon_device *rdev; |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 86 | int r, acpi_status; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 87 | |
| 88 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
| 89 | if (rdev == NULL) { |
| 90 | return -ENOMEM; |
| 91 | } |
| 92 | dev->dev_private = (void *)rdev; |
| 93 | |
| 94 | /* update BUS flag */ |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 95 | if (drm_pci_device_is_agp(dev)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 96 | flags |= RADEON_IS_AGP; |
Jon Mason | 58b6542 | 2011-06-27 16:07:50 +0000 | [diff] [blame] | 97 | } else if (pci_is_pcie(dev->pdev)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 98 | flags |= RADEON_IS_PCIE; |
| 99 | } else { |
| 100 | flags |= RADEON_IS_PCI; |
| 101 | } |
| 102 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 103 | /* radeon_device_init should report only fatal error |
| 104 | * like memory allocation failure or iomapping failure, |
| 105 | * or memory manager initialization failure, it must |
| 106 | * properly initialize the GPU MC controller and permit |
| 107 | * VRAM allocation |
| 108 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
| 110 | if (r) { |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 111 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
| 112 | goto out; |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 113 | } |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 114 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 115 | /* Again modeset_init should fail only on fatal error |
| 116 | * otherwise it should provide enough functionalities |
| 117 | * for shadowfb to run |
| 118 | */ |
| 119 | r = radeon_modeset_init(rdev); |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 120 | if (r) |
| 121 | dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); |
Luca Tettamanti | fda4b25 | 2012-07-30 21:20:35 +0200 | [diff] [blame] | 122 | |
| 123 | /* Call ACPI methods: require modeset init |
| 124 | * but failure is not fatal |
| 125 | */ |
| 126 | if (!r) { |
| 127 | acpi_status = radeon_acpi_init(rdev); |
| 128 | if (acpi_status) |
| 129 | dev_dbg(&dev->pdev->dev, |
| 130 | "Error during ACPI methods call\n"); |
| 131 | } |
| 132 | |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 133 | if (radeon_runtime_pm != 0) { |
| 134 | pm_runtime_use_autosuspend(dev->dev); |
| 135 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); |
| 136 | pm_runtime_set_active(dev->dev); |
| 137 | pm_runtime_allow(dev->dev); |
| 138 | pm_runtime_mark_last_busy(dev->dev); |
| 139 | pm_runtime_put_autosuspend(dev->dev); |
| 140 | } |
| 141 | |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 142 | out: |
| 143 | if (r) |
| 144 | radeon_driver_unload_kms(dev); |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 145 | |
| 146 | |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 147 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 148 | } |
| 149 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 150 | /** |
| 151 | * radeon_set_filp_rights - Set filp right. |
| 152 | * |
| 153 | * @dev: drm dev pointer |
| 154 | * @owner: drm file |
| 155 | * @applier: drm file |
| 156 | * @value: value |
| 157 | * |
| 158 | * Sets the filp rights for the device (all asics). |
| 159 | */ |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 160 | static void radeon_set_filp_rights(struct drm_device *dev, |
| 161 | struct drm_file **owner, |
| 162 | struct drm_file *applier, |
| 163 | uint32_t *value) |
| 164 | { |
| 165 | mutex_lock(&dev->struct_mutex); |
| 166 | if (*value == 1) { |
| 167 | /* wants rights */ |
| 168 | if (!*owner) |
| 169 | *owner = applier; |
| 170 | } else if (*value == 0) { |
| 171 | /* revokes rights */ |
| 172 | if (*owner == applier) |
| 173 | *owner = NULL; |
| 174 | } |
| 175 | *value = *owner == applier ? 1 : 0; |
| 176 | mutex_unlock(&dev->struct_mutex); |
| 177 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 178 | |
| 179 | /* |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 180 | * Userspace get information ioctl |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | */ |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 182 | /** |
| 183 | * radeon_info_ioctl - answer a device specific request. |
| 184 | * |
| 185 | * @rdev: radeon device pointer |
| 186 | * @data: request object |
| 187 | * @filp: drm filp |
| 188 | * |
| 189 | * This function is used to pass device specific parameters to the userspace |
| 190 | * drivers. Examples include: pci device id, pipeline parms, tiling params, |
| 191 | * etc. (all asics). |
| 192 | * Returns 0 on success, -EINVAL on failure. |
| 193 | */ |
Rashika Kheria | 5520345 | 2014-01-06 20:53:07 +0530 | [diff] [blame] | 194 | static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 195 | { |
| 196 | struct radeon_device *rdev = dev->dev_private; |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 197 | struct drm_radeon_info *info = data; |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 198 | struct radeon_mode_info *minfo = &rdev->mode_info; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 199 | uint32_t *value, value_tmp, *value_ptr, value_size; |
| 200 | uint64_t value64; |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 201 | struct drm_crtc *crtc; |
| 202 | int i, found; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 203 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 204 | value_ptr = (uint32_t *)((unsigned long)info->value); |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 205 | value = &value_tmp; |
| 206 | value_size = sizeof(uint32_t); |
Dr. David Alan Gilbert | d8ab355 | 2010-08-02 09:43:52 +1000 | [diff] [blame] | 207 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 208 | switch (info->request) { |
| 209 | case RADEON_INFO_DEVICE_ID: |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 210 | *value = dev->pdev->device; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 211 | break; |
| 212 | case RADEON_INFO_NUM_GB_PIPES: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 213 | *value = rdev->num_gb_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 214 | break; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 215 | case RADEON_INFO_NUM_Z_PIPES: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 216 | *value = rdev->num_z_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 217 | break; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 218 | case RADEON_INFO_ACCEL_WORKING: |
Alex Deucher | 148a03b | 2010-06-03 19:00:03 -0400 | [diff] [blame] | 219 | /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ |
| 220 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 221 | *value = false; |
Alex Deucher | 148a03b | 2010-06-03 19:00:03 -0400 | [diff] [blame] | 222 | else |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 223 | *value = rdev->accel_working; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 224 | break; |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 225 | case RADEON_INFO_CRTC_FROM_ID: |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 226 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 227 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 228 | return -EFAULT; |
| 229 | } |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 230 | for (i = 0, found = 0; i < rdev->num_crtc; i++) { |
| 231 | crtc = (struct drm_crtc *)minfo->crtcs[i]; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 232 | if (crtc && crtc->base.id == *value) { |
Alex Deucher | 0baf2d8 | 2010-07-21 14:05:35 -0400 | [diff] [blame] | 233 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 234 | *value = radeon_crtc->crtc_id; |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 235 | found = 1; |
| 236 | break; |
| 237 | } |
| 238 | } |
| 239 | if (!found) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 240 | DRM_DEBUG_KMS("unknown crtc id %d\n", *value); |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 241 | return -EINVAL; |
| 242 | } |
| 243 | break; |
Alex Deucher | 148a03b | 2010-06-03 19:00:03 -0400 | [diff] [blame] | 244 | case RADEON_INFO_ACCEL_WORKING2: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 245 | *value = rdev->accel_working; |
Alex Deucher | 148a03b | 2010-06-03 19:00:03 -0400 | [diff] [blame] | 246 | break; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 247 | case RADEON_INFO_TILING_CONFIG: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 248 | if (rdev->family >= CHIP_BONAIRE) |
| 249 | *value = rdev->config.cik.tile_config; |
| 250 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 251 | *value = rdev->config.si.tile_config; |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 252 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 253 | *value = rdev->config.cayman.tile_config; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 254 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 255 | *value = rdev->config.evergreen.tile_config; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 256 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 257 | *value = rdev->config.rv770.tile_config; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 258 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 259 | *value = rdev->config.r600.tile_config; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 260 | else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 261 | DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 262 | return -EINVAL; |
| 263 | } |
Alex Deucher | b824b36 | 2010-08-12 08:25:47 -0400 | [diff] [blame] | 264 | break; |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 265 | case RADEON_INFO_WANT_HYPERZ: |
Marek Olšák | 43861f7 | 2010-08-07 03:36:34 +0200 | [diff] [blame] | 266 | /* The "value" here is both an input and output parameter. |
| 267 | * If the input value is 1, filp requests hyper-z access. |
| 268 | * If the input value is 0, filp revokes its hyper-z access. |
| 269 | * |
| 270 | * When returning, the value is 1 if filp owns hyper-z access, |
| 271 | * 0 otherwise. */ |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 272 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 273 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 274 | return -EFAULT; |
| 275 | } |
| 276 | if (*value >= 2) { |
| 277 | DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); |
Marek Olšák | 43861f7 | 2010-08-07 03:36:34 +0200 | [diff] [blame] | 278 | return -EINVAL; |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 279 | } |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 280 | radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 281 | break; |
| 282 | case RADEON_INFO_WANT_CMASK: |
| 283 | /* The same logic as Hyper-Z. */ |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 284 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 285 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 286 | return -EFAULT; |
| 287 | } |
| 288 | if (*value >= 2) { |
| 289 | DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 290 | return -EINVAL; |
Marek Olšák | 43861f7 | 2010-08-07 03:36:34 +0200 | [diff] [blame] | 291 | } |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 292 | radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 293 | break; |
Alex Deucher | 58bbf01 | 2011-01-24 17:14:26 -0500 | [diff] [blame] | 294 | case RADEON_INFO_CLOCK_CRYSTAL_FREQ: |
| 295 | /* return clock value in KHz */ |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 296 | if (rdev->asic->get_xclk) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 297 | *value = radeon_get_xclk(rdev) * 10; |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 298 | else |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 299 | *value = rdev->clock.spll.reference_freq * 10; |
Alex Deucher | 58bbf01 | 2011-01-24 17:14:26 -0500 | [diff] [blame] | 300 | break; |
Dave Airlie | 486af18 | 2011-03-01 14:32:27 +1000 | [diff] [blame] | 301 | case RADEON_INFO_NUM_BACKENDS: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 302 | if (rdev->family >= CHIP_BONAIRE) |
| 303 | *value = rdev->config.cik.max_backends_per_se * |
| 304 | rdev->config.cik.max_shader_engines; |
| 305 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 306 | *value = rdev->config.si.max_backends_per_se * |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 307 | rdev->config.si.max_shader_engines; |
| 308 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 309 | *value = rdev->config.cayman.max_backends_per_se * |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 310 | rdev->config.cayman.max_shader_engines; |
| 311 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 312 | *value = rdev->config.evergreen.max_backends; |
Dave Airlie | 486af18 | 2011-03-01 14:32:27 +1000 | [diff] [blame] | 313 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 314 | *value = rdev->config.rv770.max_backends; |
Dave Airlie | 486af18 | 2011-03-01 14:32:27 +1000 | [diff] [blame] | 315 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 316 | *value = rdev->config.r600.max_backends; |
Dave Airlie | 486af18 | 2011-03-01 14:32:27 +1000 | [diff] [blame] | 317 | else { |
| 318 | return -EINVAL; |
| 319 | } |
| 320 | break; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 321 | case RADEON_INFO_NUM_TILE_PIPES: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 322 | if (rdev->family >= CHIP_BONAIRE) |
| 323 | *value = rdev->config.cik.max_tile_pipes; |
| 324 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 325 | *value = rdev->config.si.max_tile_pipes; |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 326 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 327 | *value = rdev->config.cayman.max_tile_pipes; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 328 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 329 | *value = rdev->config.evergreen.max_tile_pipes; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 330 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 331 | *value = rdev->config.rv770.max_tile_pipes; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 332 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 333 | *value = rdev->config.r600.max_tile_pipes; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 334 | else { |
| 335 | return -EINVAL; |
| 336 | } |
| 337 | break; |
Alex Deucher | 8aeb96f | 2011-05-03 19:28:02 -0400 | [diff] [blame] | 338 | case RADEON_INFO_FUSION_GART_WORKING: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 339 | *value = 1; |
Alex Deucher | 8aeb96f | 2011-05-03 19:28:02 -0400 | [diff] [blame] | 340 | break; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 341 | case RADEON_INFO_BACKEND_MAP: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 342 | if (rdev->family >= CHIP_BONAIRE) |
Michel Dänzer | 1ddce27 | 2013-11-18 18:25:59 +0900 | [diff] [blame] | 343 | *value = rdev->config.cik.backend_map; |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 344 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 345 | *value = rdev->config.si.backend_map; |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 346 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 347 | *value = rdev->config.cayman.backend_map; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 348 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 349 | *value = rdev->config.evergreen.backend_map; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 350 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 351 | *value = rdev->config.rv770.backend_map; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 352 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 353 | *value = rdev->config.r600.backend_map; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 354 | else { |
| 355 | return -EINVAL; |
| 356 | } |
| 357 | break; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 358 | case RADEON_INFO_VA_START: |
| 359 | /* this is where we report if vm is supported or not */ |
| 360 | if (rdev->family < CHIP_CAYMAN) |
| 361 | return -EINVAL; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 362 | *value = RADEON_VA_RESERVED_SIZE; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 363 | break; |
| 364 | case RADEON_INFO_IB_VM_MAX_SIZE: |
| 365 | /* this is where we report if vm is supported or not */ |
| 366 | if (rdev->family < CHIP_CAYMAN) |
| 367 | return -EINVAL; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 368 | *value = RADEON_IB_VM_MAX_SIZE; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 369 | break; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 370 | case RADEON_INFO_MAX_PIPES: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 371 | if (rdev->family >= CHIP_BONAIRE) |
| 372 | *value = rdev->config.cik.max_cu_per_sh; |
| 373 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 374 | *value = rdev->config.si.max_cu_per_sh; |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 375 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 376 | *value = rdev->config.cayman.max_pipes_per_simd; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 377 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 378 | *value = rdev->config.evergreen.max_pipes; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 379 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 380 | *value = rdev->config.rv770.max_pipes; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 381 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 382 | *value = rdev->config.r600.max_pipes; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 383 | else { |
| 384 | return -EINVAL; |
| 385 | } |
| 386 | break; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 387 | case RADEON_INFO_TIMESTAMP: |
| 388 | if (rdev->family < CHIP_R600) { |
| 389 | DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); |
| 390 | return -EINVAL; |
| 391 | } |
| 392 | value = (uint32_t*)&value64; |
| 393 | value_size = sizeof(uint64_t); |
| 394 | value64 = radeon_get_gpu_clock_counter(rdev); |
| 395 | break; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 396 | case RADEON_INFO_MAX_SE: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 397 | if (rdev->family >= CHIP_BONAIRE) |
| 398 | *value = rdev->config.cik.max_shader_engines; |
| 399 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 400 | *value = rdev->config.si.max_shader_engines; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 401 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 402 | *value = rdev->config.cayman.max_shader_engines; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 403 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 404 | *value = rdev->config.evergreen.num_ses; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 405 | else |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 406 | *value = 1; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 407 | break; |
| 408 | case RADEON_INFO_MAX_SH_PER_SE: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 409 | if (rdev->family >= CHIP_BONAIRE) |
| 410 | *value = rdev->config.cik.max_sh_per_se; |
| 411 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 412 | *value = rdev->config.si.max_sh_per_se; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 413 | else |
| 414 | return -EINVAL; |
| 415 | break; |
Samuel Li | a0a53aa | 2013-04-08 17:25:47 -0400 | [diff] [blame] | 416 | case RADEON_INFO_FASTFB_WORKING: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 417 | *value = rdev->fastfb_working; |
Samuel Li | a0a53aa | 2013-04-08 17:25:47 -0400 | [diff] [blame] | 418 | break; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 419 | case RADEON_INFO_RING_WORKING: |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 420 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 421 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 422 | return -EFAULT; |
| 423 | } |
| 424 | switch (*value) { |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 425 | case RADEON_CS_RING_GFX: |
| 426 | case RADEON_CS_RING_COMPUTE: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 427 | *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 428 | break; |
| 429 | case RADEON_CS_RING_DMA: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 430 | *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; |
| 431 | *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 432 | break; |
| 433 | case RADEON_CS_RING_UVD: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 434 | *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 435 | break; |
Christian König | f7ba8b0 | 2014-01-27 10:16:06 -0700 | [diff] [blame] | 436 | case RADEON_CS_RING_VCE: |
| 437 | *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; |
| 438 | break; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 439 | default: |
| 440 | return -EINVAL; |
| 441 | } |
| 442 | break; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 443 | case RADEON_INFO_SI_TILE_MODE_ARRAY: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 444 | if (rdev->family >= CHIP_BONAIRE) { |
Alex Deucher | 39aee49 | 2013-04-10 13:41:25 -0400 | [diff] [blame] | 445 | value = rdev->config.cik.tile_mode_array; |
| 446 | value_size = sizeof(uint32_t)*32; |
| 447 | } else if (rdev->family >= CHIP_TAHITI) { |
| 448 | value = rdev->config.si.tile_mode_array; |
| 449 | value_size = sizeof(uint32_t)*32; |
| 450 | } else { |
| 451 | DRM_DEBUG_KMS("tile mode array is si+ only!\n"); |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 452 | return -EINVAL; |
| 453 | } |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 454 | break; |
Michel Dänzer | 32f79a8 | 2013-11-18 18:26:00 +0900 | [diff] [blame] | 455 | case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: |
| 456 | if (rdev->family >= CHIP_BONAIRE) { |
| 457 | value = rdev->config.cik.macrotile_mode_array; |
| 458 | value_size = sizeof(uint32_t)*16; |
| 459 | } else { |
| 460 | DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); |
| 461 | return -EINVAL; |
| 462 | } |
| 463 | break; |
Tom Stellard | e5b9e75 | 2013-08-16 17:47:39 -0400 | [diff] [blame] | 464 | case RADEON_INFO_SI_CP_DMA_COMPUTE: |
| 465 | *value = 1; |
| 466 | break; |
Marek Olšák | 439a1cf | 2013-12-22 02:18:01 +0100 | [diff] [blame] | 467 | case RADEON_INFO_SI_BACKEND_ENABLED_MASK: |
| 468 | if (rdev->family >= CHIP_BONAIRE) { |
| 469 | *value = rdev->config.cik.backend_enable_mask; |
| 470 | } else if (rdev->family >= CHIP_TAHITI) { |
| 471 | *value = rdev->config.si.backend_enable_mask; |
| 472 | } else { |
| 473 | DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); |
| 474 | } |
| 475 | break; |
Alex Deucher | f5f1f89 | 2014-01-20 18:20:29 -0500 | [diff] [blame] | 476 | case RADEON_INFO_MAX_SCLK: |
| 477 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && |
| 478 | rdev->pm.dpm_enabled) |
| 479 | *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; |
| 480 | else |
| 481 | *value = rdev->pm.default_sclk * 10; |
| 482 | break; |
Christian König | 98ccc29 | 2014-01-23 09:50:49 -0700 | [diff] [blame] | 483 | case RADEON_INFO_VCE_FW_VERSION: |
| 484 | *value = rdev->vce.fw_version; |
| 485 | break; |
| 486 | case RADEON_INFO_VCE_FB_VERSION: |
| 487 | *value = rdev->vce.fb_version; |
| 488 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 489 | default: |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 490 | DRM_DEBUG_KMS("Invalid request %d\n", info->request); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 491 | return -EINVAL; |
| 492 | } |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 493 | if (copy_to_user(value_ptr, (char*)value, value_size)) { |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 494 | DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 495 | return -EFAULT; |
| 496 | } |
| 497 | return 0; |
| 498 | } |
| 499 | |
| 500 | |
| 501 | /* |
| 502 | * Outdated mess for old drm with Xorg being in charge (void function now). |
| 503 | */ |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 504 | /** |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 505 | * radeon_driver_firstopen_kms - drm callback for last close |
| 506 | * |
| 507 | * @dev: drm dev pointer |
| 508 | * |
| 509 | * Switch vga switcheroo state after last close (all asics). |
| 510 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 511 | void radeon_driver_lastclose_kms(struct drm_device *dev) |
| 512 | { |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 513 | vga_switcheroo_process_delayed_switch(); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 514 | } |
| 515 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 516 | /** |
| 517 | * radeon_driver_open_kms - drm callback for open |
| 518 | * |
| 519 | * @dev: drm dev pointer |
| 520 | * @file_priv: drm file |
| 521 | * |
| 522 | * On device open, init vm on cayman+ (all asics). |
| 523 | * Returns 0 on success, error on failure. |
| 524 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 525 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) |
| 526 | { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 527 | struct radeon_device *rdev = dev->dev_private; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 528 | int r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 529 | |
| 530 | file_priv->driver_priv = NULL; |
| 531 | |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 532 | r = pm_runtime_get_sync(dev->dev); |
| 533 | if (r < 0) |
| 534 | return r; |
| 535 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 536 | /* new gpu have virtual address space support */ |
| 537 | if (rdev->family >= CHIP_CAYMAN) { |
| 538 | struct radeon_fpriv *fpriv; |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 539 | struct radeon_bo_va *bo_va; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 540 | int r; |
| 541 | |
| 542 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 543 | if (unlikely(!fpriv)) { |
| 544 | return -ENOMEM; |
| 545 | } |
| 546 | |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 547 | radeon_vm_init(rdev, &fpriv->vm); |
| 548 | |
| 549 | /* map the ib pool buffer read only into |
| 550 | * virtual address space */ |
| 551 | bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, |
| 552 | rdev->ring_tmp_bo.bo); |
| 553 | r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, |
| 554 | RADEON_VM_PAGE_READABLE | |
| 555 | RADEON_VM_PAGE_SNOOPED); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 556 | if (r) { |
| 557 | radeon_vm_fini(rdev, &fpriv->vm); |
| 558 | kfree(fpriv); |
| 559 | return r; |
| 560 | } |
| 561 | |
| 562 | file_priv->driver_priv = fpriv; |
| 563 | } |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 564 | |
| 565 | pm_runtime_mark_last_busy(dev->dev); |
| 566 | pm_runtime_put_autosuspend(dev->dev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 567 | return 0; |
| 568 | } |
| 569 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 570 | /** |
| 571 | * radeon_driver_postclose_kms - drm callback for post close |
| 572 | * |
| 573 | * @dev: drm dev pointer |
| 574 | * @file_priv: drm file |
| 575 | * |
| 576 | * On device post close, tear down vm on cayman+ (all asics). |
| 577 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 578 | void radeon_driver_postclose_kms(struct drm_device *dev, |
| 579 | struct drm_file *file_priv) |
| 580 | { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 581 | struct radeon_device *rdev = dev->dev_private; |
| 582 | |
| 583 | /* new gpu have virtual address space support */ |
| 584 | if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { |
| 585 | struct radeon_fpriv *fpriv = file_priv->driver_priv; |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 586 | struct radeon_bo_va *bo_va; |
| 587 | int r; |
| 588 | |
| 589 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); |
| 590 | if (!r) { |
| 591 | bo_va = radeon_vm_bo_find(&fpriv->vm, |
| 592 | rdev->ring_tmp_bo.bo); |
| 593 | if (bo_va) |
| 594 | radeon_vm_bo_rmv(rdev, bo_va); |
| 595 | radeon_bo_unreserve(rdev->ring_tmp_bo.bo); |
| 596 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 597 | |
| 598 | radeon_vm_fini(rdev, &fpriv->vm); |
| 599 | kfree(fpriv); |
| 600 | file_priv->driver_priv = NULL; |
| 601 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 602 | } |
| 603 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 604 | /** |
| 605 | * radeon_driver_preclose_kms - drm callback for pre close |
| 606 | * |
| 607 | * @dev: drm dev pointer |
| 608 | * @file_priv: drm file |
| 609 | * |
| 610 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx |
| 611 | * (all asics). |
| 612 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 613 | void radeon_driver_preclose_kms(struct drm_device *dev, |
| 614 | struct drm_file *file_priv) |
| 615 | { |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 616 | struct radeon_device *rdev = dev->dev_private; |
| 617 | if (rdev->hyperz_filp == file_priv) |
| 618 | rdev->hyperz_filp = NULL; |
Marek Olšák | dca0d61 | 2011-01-27 22:46:15 +0100 | [diff] [blame] | 619 | if (rdev->cmask_filp == file_priv) |
| 620 | rdev->cmask_filp = NULL; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 621 | radeon_uvd_free_handles(rdev, file_priv); |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 622 | radeon_vce_free_handles(rdev, file_priv); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 623 | } |
| 624 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 625 | /* |
| 626 | * VBlank related functions. |
| 627 | */ |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 628 | /** |
| 629 | * radeon_get_vblank_counter_kms - get frame count |
| 630 | * |
| 631 | * @dev: drm dev pointer |
| 632 | * @crtc: crtc to get the frame count from |
| 633 | * |
| 634 | * Gets the frame count on the requested crtc (all asics). |
| 635 | * Returns frame count on success, -EINVAL on failure. |
| 636 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 637 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) |
| 638 | { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 639 | struct radeon_device *rdev = dev->dev_private; |
| 640 | |
Dave Airlie | 9c950a4 | 2010-04-23 13:21:58 +1000 | [diff] [blame] | 641 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 642 | DRM_ERROR("Invalid crtc %d\n", crtc); |
| 643 | return -EINVAL; |
| 644 | } |
| 645 | |
| 646 | return radeon_get_vblank_counter(rdev, crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 647 | } |
| 648 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 649 | /** |
| 650 | * radeon_enable_vblank_kms - enable vblank interrupt |
| 651 | * |
| 652 | * @dev: drm dev pointer |
| 653 | * @crtc: crtc to enable vblank interrupt for |
| 654 | * |
| 655 | * Enable the interrupt on the requested crtc (all asics). |
| 656 | * Returns 0 on success, -EINVAL on failure. |
| 657 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 658 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) |
| 659 | { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 660 | struct radeon_device *rdev = dev->dev_private; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 661 | unsigned long irqflags; |
| 662 | int r; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 663 | |
Dave Airlie | 9c950a4 | 2010-04-23 13:21:58 +1000 | [diff] [blame] | 664 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 665 | DRM_ERROR("Invalid crtc %d\n", crtc); |
| 666 | return -EINVAL; |
| 667 | } |
| 668 | |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 669 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 670 | rdev->irq.crtc_vblank_int[crtc] = true; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 671 | r = radeon_irq_set(rdev); |
| 672 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
| 673 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 674 | } |
| 675 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 676 | /** |
| 677 | * radeon_disable_vblank_kms - disable vblank interrupt |
| 678 | * |
| 679 | * @dev: drm dev pointer |
| 680 | * @crtc: crtc to disable vblank interrupt for |
| 681 | * |
| 682 | * Disable the interrupt on the requested crtc (all asics). |
| 683 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 684 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) |
| 685 | { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 686 | struct radeon_device *rdev = dev->dev_private; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 687 | unsigned long irqflags; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 688 | |
Dave Airlie | 9c950a4 | 2010-04-23 13:21:58 +1000 | [diff] [blame] | 689 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 690 | DRM_ERROR("Invalid crtc %d\n", crtc); |
| 691 | return; |
| 692 | } |
| 693 | |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 694 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 695 | rdev->irq.crtc_vblank_int[crtc] = false; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 696 | radeon_irq_set(rdev); |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 697 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 698 | } |
| 699 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 700 | /** |
| 701 | * radeon_get_vblank_timestamp_kms - get vblank timestamp |
| 702 | * |
| 703 | * @dev: drm dev pointer |
| 704 | * @crtc: crtc to get the timestamp for |
| 705 | * @max_error: max error |
| 706 | * @vblank_time: time value |
| 707 | * @flags: flags passed to the driver |
| 708 | * |
| 709 | * Gets the timestamp on the requested crtc based on the |
| 710 | * scanout position. (all asics). |
| 711 | * Returns postive status flags on success, negative error on failure. |
| 712 | */ |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 713 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
| 714 | int *max_error, |
| 715 | struct timeval *vblank_time, |
| 716 | unsigned flags) |
| 717 | { |
| 718 | struct drm_crtc *drmcrtc; |
| 719 | struct radeon_device *rdev = dev->dev_private; |
| 720 | |
| 721 | if (crtc < 0 || crtc >= dev->num_crtcs) { |
| 722 | DRM_ERROR("Invalid crtc %d\n", crtc); |
| 723 | return -EINVAL; |
| 724 | } |
| 725 | |
| 726 | /* Get associated drm_crtc: */ |
| 727 | drmcrtc = &rdev->mode_info.crtcs[crtc]->base; |
| 728 | |
| 729 | /* Helper routine in DRM core does all the work: */ |
| 730 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, |
| 731 | vblank_time, flags, |
Ville Syrjälä | 7da903e | 2013-10-26 17:57:31 +0300 | [diff] [blame] | 732 | drmcrtc, &drmcrtc->hwmode); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 733 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 734 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 735 | #define KMS_INVALID_IOCTL(name) \ |
Rashika Kheria | f6e2e40 | 2014-01-06 21:06:44 +0530 | [diff] [blame] | 736 | static int name(struct drm_device *dev, void *data, struct drm_file \ |
| 737 | *file_priv) \ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 738 | { \ |
| 739 | DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ |
| 740 | return -EINVAL; \ |
| 741 | } |
| 742 | |
| 743 | /* |
| 744 | * All these ioctls are invalid in kms world. |
| 745 | */ |
| 746 | KMS_INVALID_IOCTL(radeon_cp_init_kms) |
| 747 | KMS_INVALID_IOCTL(radeon_cp_start_kms) |
| 748 | KMS_INVALID_IOCTL(radeon_cp_stop_kms) |
| 749 | KMS_INVALID_IOCTL(radeon_cp_reset_kms) |
| 750 | KMS_INVALID_IOCTL(radeon_cp_idle_kms) |
| 751 | KMS_INVALID_IOCTL(radeon_cp_resume_kms) |
| 752 | KMS_INVALID_IOCTL(radeon_engine_reset_kms) |
| 753 | KMS_INVALID_IOCTL(radeon_fullscreen_kms) |
| 754 | KMS_INVALID_IOCTL(radeon_cp_swap_kms) |
| 755 | KMS_INVALID_IOCTL(radeon_cp_clear_kms) |
| 756 | KMS_INVALID_IOCTL(radeon_cp_vertex_kms) |
| 757 | KMS_INVALID_IOCTL(radeon_cp_indices_kms) |
| 758 | KMS_INVALID_IOCTL(radeon_cp_texture_kms) |
| 759 | KMS_INVALID_IOCTL(radeon_cp_stipple_kms) |
| 760 | KMS_INVALID_IOCTL(radeon_cp_indirect_kms) |
| 761 | KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) |
| 762 | KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) |
| 763 | KMS_INVALID_IOCTL(radeon_cp_getparam_kms) |
| 764 | KMS_INVALID_IOCTL(radeon_cp_flip_kms) |
| 765 | KMS_INVALID_IOCTL(radeon_mem_alloc_kms) |
| 766 | KMS_INVALID_IOCTL(radeon_mem_free_kms) |
| 767 | KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) |
| 768 | KMS_INVALID_IOCTL(radeon_irq_emit_kms) |
| 769 | KMS_INVALID_IOCTL(radeon_irq_wait_kms) |
| 770 | KMS_INVALID_IOCTL(radeon_cp_setparam_kms) |
| 771 | KMS_INVALID_IOCTL(radeon_surface_alloc_kms) |
| 772 | KMS_INVALID_IOCTL(radeon_surface_free_kms) |
| 773 | |
| 774 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 775 | const struct drm_ioctl_desc radeon_ioctls_kms[] = { |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 776 | DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 777 | DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 778 | DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 779 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 780 | DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), |
| 781 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), |
| 782 | DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), |
| 783 | DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), |
| 784 | DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), |
| 785 | DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), |
| 786 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), |
| 787 | DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), |
| 788 | DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), |
| 789 | DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), |
| 790 | DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 791 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), |
| 792 | DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), |
| 793 | DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), |
| 794 | DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), |
| 795 | DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), |
| 796 | DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), |
| 797 | DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 798 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), |
| 799 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), |
| 800 | DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), |
| 801 | DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), |
| 802 | DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 803 | /* KMS */ |
Christian König | f33bcab | 2013-08-25 18:29:03 +0200 | [diff] [blame] | 804 | DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 805 | DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 806 | DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 807 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 808 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), |
| 809 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), |
Christian König | f33bcab | 2013-08-25 18:29:03 +0200 | [diff] [blame] | 810 | DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 811 | DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 812 | DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 813 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 814 | DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 815 | DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 816 | DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame^] | 817 | DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 818 | }; |
| 819 | int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); |