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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Terje Bergstromd43f81c2013-03-22 16:34:09 +02003 * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Thierry Reding776dc382013-10-14 14:43:22 +020010#include <linux/host1x.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020011#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020012
Thierry Reding1503ca42014-11-24 17:41:23 +010013#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010014#include <drm/drm_atomic_helper.h>
15
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000016#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020017#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018
19#define DRIVER_NAME "tegra"
20#define DRIVER_DESC "NVIDIA Tegra graphics"
21#define DRIVER_DATE "20120330"
22#define DRIVER_MAJOR 0
23#define DRIVER_MINOR 0
24#define DRIVER_PATCHLEVEL 0
25
Thierry Reding08943e62013-09-26 16:08:18 +020026struct tegra_drm_file {
27 struct list_head contexts;
28};
29
Thierry Reding1503ca42014-11-24 17:41:23 +010030static void tegra_atomic_schedule(struct tegra_drm *tegra,
31 struct drm_atomic_state *state)
32{
33 tegra->commit.state = state;
34 schedule_work(&tegra->commit.work);
35}
36
37static void tegra_atomic_complete(struct tegra_drm *tegra,
38 struct drm_atomic_state *state)
39{
40 struct drm_device *drm = tegra->drm;
41
42 /*
43 * Everything below can be run asynchronously without the need to grab
44 * any modeset locks at all under one condition: It must be guaranteed
45 * that the asynchronous work has either been cancelled (if the driver
46 * supports it, which at least requires that the framebuffers get
47 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
48 * before the new state gets committed on the software side with
49 * drm_atomic_helper_swap_state().
50 *
51 * This scheme allows new atomic state updates to be prepared and
52 * checked in parallel to the asynchronous completion of the previous
53 * update. Which is important since compositors need to figure out the
54 * composition of the next frame right after having submitted the
55 * current layout.
56 */
57
Daniel Vetter1af434a2015-02-22 12:24:19 +010058 drm_atomic_helper_commit_modeset_disables(drm, state);
Daniel Vetter1af434a2015-02-22 12:24:19 +010059 drm_atomic_helper_commit_modeset_enables(drm, state);
Liu Ying2b58e982016-08-29 17:12:03 +080060 drm_atomic_helper_commit_planes(drm, state,
61 DRM_PLANE_COMMIT_ACTIVE_ONLY);
Thierry Reding1503ca42014-11-24 17:41:23 +010062
63 drm_atomic_helper_wait_for_vblanks(drm, state);
64
65 drm_atomic_helper_cleanup_planes(drm, state);
Chris Wilson08536952016-10-14 13:18:18 +010066 drm_atomic_state_put(state);
Thierry Reding1503ca42014-11-24 17:41:23 +010067}
68
69static void tegra_atomic_work(struct work_struct *work)
70{
71 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
72 commit.work);
73
74 tegra_atomic_complete(tegra, tegra->commit.state);
75}
76
77static int tegra_atomic_commit(struct drm_device *drm,
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020078 struct drm_atomic_state *state, bool nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +010079{
80 struct tegra_drm *tegra = drm->dev_private;
81 int err;
82
83 err = drm_atomic_helper_prepare_planes(drm, state);
84 if (err)
85 return err;
86
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020087 /* serialize outstanding nonblocking commits */
Thierry Reding1503ca42014-11-24 17:41:23 +010088 mutex_lock(&tegra->commit.lock);
89 flush_work(&tegra->commit.work);
90
91 /*
92 * This is the point of no return - everything below never fails except
93 * when the hw goes bonghits. Which means we can commit the new state on
94 * the software side now.
95 */
96
Daniel Vetter5e84c262016-06-10 00:06:32 +020097 drm_atomic_helper_swap_state(state, true);
Thierry Reding1503ca42014-11-24 17:41:23 +010098
Chris Wilson08536952016-10-14 13:18:18 +010099 drm_atomic_state_get(state);
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +0200100 if (nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +0100101 tegra_atomic_schedule(tegra, state);
102 else
103 tegra_atomic_complete(tegra, state);
104
105 mutex_unlock(&tegra->commit.lock);
106 return 0;
107}
108
Thierry Redingf9914212014-11-26 13:03:57 +0100109static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
110 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +0530111#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +0100112 .output_poll_changed = tegra_fb_output_poll_changed,
113#endif
Thierry Reding07866962014-11-24 17:08:06 +0100114 .atomic_check = drm_atomic_helper_check,
Thierry Reding1503ca42014-11-24 17:41:23 +0100115 .atomic_commit = tegra_atomic_commit,
Thierry Redingf9914212014-11-26 13:03:57 +0100116};
117
Thierry Reding776dc382013-10-14 14:43:22 +0200118static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000119{
Thierry Reding776dc382013-10-14 14:43:22 +0200120 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200121 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000122 int err;
123
Thierry Reding776dc382013-10-14 14:43:22 +0200124 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200125 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200126 return -ENOMEM;
127
Thierry Redingdf06b752014-06-26 21:41:53 +0200128 if (iommu_present(&platform_bus_type)) {
Thierry Reding4553f732015-01-19 16:15:04 +0100129 struct iommu_domain_geometry *geometry;
130 u64 start, end;
131
Thierry Redingdf06b752014-06-26 21:41:53 +0200132 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300133 if (!tegra->domain) {
134 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200135 goto free;
136 }
137
Thierry Reding4553f732015-01-19 16:15:04 +0100138 geometry = &tegra->domain->geometry;
139 start = geometry->aperture_start;
140 end = geometry->aperture_end;
141
Thierry Redingd2d8c352015-11-23 16:46:30 +0100142 DRM_DEBUG_DRIVER("IOMMU aperture initialized (%#llx-%#llx)\n",
143 start, end);
Thierry Reding4553f732015-01-19 16:15:04 +0100144 drm_mm_init(&tegra->mm, start, end - start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100145 mutex_init(&tegra->mm_lock);
Thierry Redingdf06b752014-06-26 21:41:53 +0200146 }
147
Thierry Reding386a2a72013-09-24 13:22:17 +0200148 mutex_init(&tegra->clients_lock);
149 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100150
151 mutex_init(&tegra->commit.lock);
152 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
153
Thierry Reding386a2a72013-09-24 13:22:17 +0200154 drm->dev_private = tegra;
155 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000156
157 drm_mode_config_init(drm);
158
Thierry Redingf9914212014-11-26 13:03:57 +0100159 drm->mode_config.min_width = 0;
160 drm->mode_config.min_height = 0;
161
162 drm->mode_config.max_width = 4096;
163 drm->mode_config.max_height = 4096;
164
165 drm->mode_config.funcs = &tegra_drm_mode_funcs;
166
Thierry Redinge2215322014-06-27 17:19:25 +0200167 err = tegra_drm_fb_prepare(drm);
168 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100169 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200170
171 drm_kms_helper_poll_init(drm);
172
Thierry Reding776dc382013-10-14 14:43:22 +0200173 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000174 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100175 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000176
Thierry Reding603f0cc2013-04-22 21:22:14 +0200177 /*
178 * We don't use the drm_irq_install() helpers provided by the DRM
179 * core, so we need to set this manually in order to allow the
180 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
181 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300182 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200183
Thierry Reding42e9ce02015-01-28 14:43:05 +0100184 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100185 drm->max_vblank_count = 0xffffffff;
186
Thierry Reding6e5ff992012-11-28 11:45:47 +0100187 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
188 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100189 goto device;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100190
Thierry Reding31930d42015-07-02 17:04:06 +0200191 drm_mode_config_reset(drm);
192
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000193 err = tegra_drm_fb_init(drm);
194 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100195 goto vblank;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000196
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000197 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100198
199vblank:
200 drm_vblank_cleanup(drm);
201device:
202 host1x_device_exit(device);
203fbdev:
204 drm_kms_helper_poll_fini(drm);
205 tegra_drm_fb_free(drm);
206config:
207 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200208
209 if (tegra->domain) {
210 iommu_domain_free(tegra->domain);
211 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100212 mutex_destroy(&tegra->mm_lock);
Thierry Redingdf06b752014-06-26 21:41:53 +0200213 }
214free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100215 kfree(tegra);
216 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000217}
218
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200219static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000220{
Thierry Reding776dc382013-10-14 14:43:22 +0200221 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200222 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200223 int err;
224
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000225 drm_kms_helper_poll_fini(drm);
226 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200227 drm_mode_config_cleanup(drm);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100228 drm_vblank_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000229
Thierry Reding776dc382013-10-14 14:43:22 +0200230 err = host1x_device_exit(device);
231 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200232 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200233
Thierry Redingdf06b752014-06-26 21:41:53 +0200234 if (tegra->domain) {
235 iommu_domain_free(tegra->domain);
236 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100237 mutex_destroy(&tegra->mm_lock);
Thierry Redingdf06b752014-06-26 21:41:53 +0200238 }
239
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100240 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000241}
242
243static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
244{
Thierry Reding08943e62013-09-26 16:08:18 +0200245 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200246
247 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
248 if (!fpriv)
249 return -ENOMEM;
250
251 INIT_LIST_HEAD(&fpriv->contexts);
252 filp->driver_priv = fpriv;
253
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000254 return 0;
255}
256
Thierry Redingc88c3632013-09-26 16:08:22 +0200257static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200258{
259 context->client->ops->close_channel(context);
260 kfree(context);
261}
262
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000263static void tegra_drm_lastclose(struct drm_device *drm)
264{
Archit Tanejab110ef32015-10-27 13:40:59 +0530265#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200266 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000267
Thierry Reding386a2a72013-09-24 13:22:17 +0200268 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100269#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000270}
271
Thierry Redingc40f0f12013-10-10 11:00:33 +0200272static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100273host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200274{
275 struct drm_gem_object *gem;
276 struct tegra_bo *bo;
277
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100278 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200279 if (!gem)
280 return NULL;
281
Daniel Vettera07cdfe2015-11-23 10:32:48 +0100282 drm_gem_object_unreference_unlocked(gem);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200283
284 bo = to_tegra_bo(gem);
285 return &bo->base;
286}
287
Thierry Reding961e3be2014-06-10 10:25:00 +0200288static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
289 struct drm_tegra_reloc __user *src,
290 struct drm_device *drm,
291 struct drm_file *file)
292{
293 u32 cmdbuf, target;
294 int err;
295
296 err = get_user(cmdbuf, &src->cmdbuf.handle);
297 if (err < 0)
298 return err;
299
300 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
301 if (err < 0)
302 return err;
303
304 err = get_user(target, &src->target.handle);
305 if (err < 0)
306 return err;
307
David Ung31f40f82015-01-20 18:37:35 -0800308 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200309 if (err < 0)
310 return err;
311
312 err = get_user(dest->shift, &src->shift);
313 if (err < 0)
314 return err;
315
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100316 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200317 if (!dest->cmdbuf.bo)
318 return -ENOENT;
319
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100320 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200321 if (!dest->target.bo)
322 return -ENOENT;
323
324 return 0;
325}
326
Thierry Redingc40f0f12013-10-10 11:00:33 +0200327int tegra_drm_submit(struct tegra_drm_context *context,
328 struct drm_tegra_submit *args, struct drm_device *drm,
329 struct drm_file *file)
330{
331 unsigned int num_cmdbufs = args->num_cmdbufs;
332 unsigned int num_relocs = args->num_relocs;
333 unsigned int num_waitchks = args->num_waitchks;
334 struct drm_tegra_cmdbuf __user *cmdbufs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100335 (void __user *)(uintptr_t)args->cmdbufs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200336 struct drm_tegra_reloc __user *relocs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100337 (void __user *)(uintptr_t)args->relocs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200338 struct drm_tegra_waitchk __user *waitchks =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100339 (void __user *)(uintptr_t)args->waitchks;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200340 struct drm_tegra_syncpt syncpt;
341 struct host1x_job *job;
342 int err;
343
344 /* We don't yet support other than one syncpt_incr struct per submit */
345 if (args->num_syncpts != 1)
346 return -EINVAL;
347
348 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
349 args->num_relocs, args->num_waitchks);
350 if (!job)
351 return -ENOMEM;
352
353 job->num_relocs = args->num_relocs;
354 job->num_waitchk = args->num_waitchks;
355 job->client = (u32)args->context;
356 job->class = context->client->base.class;
357 job->serialize = true;
358
359 while (num_cmdbufs) {
360 struct drm_tegra_cmdbuf cmdbuf;
361 struct host1x_bo *bo;
362
Dan Carpenter9a991602013-11-08 13:07:37 +0300363 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
364 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200365 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300366 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200367
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100368 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200369 if (!bo) {
370 err = -ENOENT;
371 goto fail;
372 }
373
374 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
375 num_cmdbufs--;
376 cmdbufs++;
377 }
378
Thierry Reding961e3be2014-06-10 10:25:00 +0200379 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200380 while (num_relocs--) {
Thierry Reding961e3be2014-06-10 10:25:00 +0200381 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
382 &relocs[num_relocs], drm,
383 file);
384 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200385 goto fail;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200386 }
387
Dan Carpenter9a991602013-11-08 13:07:37 +0300388 if (copy_from_user(job->waitchk, waitchks,
389 sizeof(*waitchks) * num_waitchks)) {
390 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200391 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300392 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200393
Dan Carpenter9a991602013-11-08 13:07:37 +0300394 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
395 sizeof(syncpt))) {
396 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200397 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300398 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200399
400 job->is_addr_reg = context->client->ops->is_addr_reg;
401 job->syncpt_incrs = syncpt.incrs;
402 job->syncpt_id = syncpt.id;
403 job->timeout = 10000;
404
405 if (args->timeout && args->timeout < 10000)
406 job->timeout = args->timeout;
407
408 err = host1x_job_pin(job, context->client->base.dev);
409 if (err)
410 goto fail;
411
412 err = host1x_job_submit(job);
413 if (err)
414 goto fail_submit;
415
416 args->fence = job->syncpt_end;
417
418 host1x_job_put(job);
419 return 0;
420
421fail_submit:
422 host1x_job_unpin(job);
423fail:
424 host1x_job_put(job);
425 return err;
426}
427
428
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200429#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Redingc88c3632013-09-26 16:08:22 +0200430static struct tegra_drm_context *tegra_drm_get_context(__u64 context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200431{
Thierry Redingc88c3632013-09-26 16:08:22 +0200432 return (struct tegra_drm_context *)(uintptr_t)context;
433}
434
435static bool tegra_drm_file_owns_context(struct tegra_drm_file *file,
436 struct tegra_drm_context *context)
437{
438 struct tegra_drm_context *ctx;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200439
440 list_for_each_entry(ctx, &file->contexts, list)
441 if (ctx == context)
442 return true;
443
444 return false;
445}
446
447static int tegra_gem_create(struct drm_device *drm, void *data,
448 struct drm_file *file)
449{
450 struct drm_tegra_gem_create *args = data;
451 struct tegra_bo *bo;
452
Thierry Reding773af772013-10-04 22:34:01 +0200453 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200454 &args->handle);
455 if (IS_ERR(bo))
456 return PTR_ERR(bo);
457
458 return 0;
459}
460
461static int tegra_gem_mmap(struct drm_device *drm, void *data,
462 struct drm_file *file)
463{
464 struct drm_tegra_gem_mmap *args = data;
465 struct drm_gem_object *gem;
466 struct tegra_bo *bo;
467
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100468 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200469 if (!gem)
470 return -EINVAL;
471
472 bo = to_tegra_bo(gem);
473
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200474 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200475
Daniel Vetter11533302015-11-23 10:32:40 +0100476 drm_gem_object_unreference_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200477
478 return 0;
479}
480
481static int tegra_syncpt_read(struct drm_device *drm, void *data,
482 struct drm_file *file)
483{
Thierry Reding776dc382013-10-14 14:43:22 +0200484 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200485 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200486 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200487
Thierry Reding776dc382013-10-14 14:43:22 +0200488 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200489 if (!sp)
490 return -EINVAL;
491
492 args->value = host1x_syncpt_read_min(sp);
493 return 0;
494}
495
496static int tegra_syncpt_incr(struct drm_device *drm, void *data,
497 struct drm_file *file)
498{
Thierry Reding776dc382013-10-14 14:43:22 +0200499 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200500 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200501 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200502
Thierry Reding776dc382013-10-14 14:43:22 +0200503 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200504 if (!sp)
505 return -EINVAL;
506
Arto Merilainenebae30b2013-05-29 13:26:08 +0300507 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200508}
509
510static int tegra_syncpt_wait(struct drm_device *drm, void *data,
511 struct drm_file *file)
512{
Thierry Reding776dc382013-10-14 14:43:22 +0200513 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200514 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200515 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200516
Thierry Reding776dc382013-10-14 14:43:22 +0200517 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200518 if (!sp)
519 return -EINVAL;
520
521 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
522 &args->value);
523}
524
525static int tegra_open_channel(struct drm_device *drm, void *data,
526 struct drm_file *file)
527{
Thierry Reding08943e62013-09-26 16:08:18 +0200528 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200529 struct tegra_drm *tegra = drm->dev_private;
530 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200531 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200532 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200533 int err = -ENODEV;
534
535 context = kzalloc(sizeof(*context), GFP_KERNEL);
536 if (!context)
537 return -ENOMEM;
538
Thierry Reding776dc382013-10-14 14:43:22 +0200539 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200540 if (client->base.class == args->client) {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200541 err = client->ops->open_channel(client, context);
542 if (err)
543 break;
544
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200545 list_add(&context->list, &fpriv->contexts);
546 args->context = (uintptr_t)context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200547 context->client = client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200548 return 0;
549 }
550
551 kfree(context);
552 return err;
553}
554
555static int tegra_close_channel(struct drm_device *drm, void *data,
556 struct drm_file *file)
557{
Thierry Reding08943e62013-09-26 16:08:18 +0200558 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200559 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200560 struct tegra_drm_context *context;
561
562 context = tegra_drm_get_context(args->context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200563
Thierry Reding08943e62013-09-26 16:08:18 +0200564 if (!tegra_drm_file_owns_context(fpriv, context))
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200565 return -EINVAL;
566
567 list_del(&context->list);
Thierry Redingc88c3632013-09-26 16:08:22 +0200568 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200569
570 return 0;
571}
572
573static int tegra_get_syncpt(struct drm_device *drm, void *data,
574 struct drm_file *file)
575{
Thierry Reding08943e62013-09-26 16:08:18 +0200576 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200577 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200578 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200579 struct host1x_syncpt *syncpt;
580
Thierry Redingc88c3632013-09-26 16:08:22 +0200581 context = tegra_drm_get_context(args->context);
582
Thierry Reding08943e62013-09-26 16:08:18 +0200583 if (!tegra_drm_file_owns_context(fpriv, context))
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200584 return -ENODEV;
585
Thierry Reding53fa7f72013-09-24 15:35:40 +0200586 if (args->index >= context->client->base.num_syncpts)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200587 return -EINVAL;
588
Thierry Reding53fa7f72013-09-24 15:35:40 +0200589 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200590 args->id = host1x_syncpt_id(syncpt);
591
592 return 0;
593}
594
595static int tegra_submit(struct drm_device *drm, void *data,
596 struct drm_file *file)
597{
Thierry Reding08943e62013-09-26 16:08:18 +0200598 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200599 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200600 struct tegra_drm_context *context;
601
602 context = tegra_drm_get_context(args->context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200603
Thierry Reding08943e62013-09-26 16:08:18 +0200604 if (!tegra_drm_file_owns_context(fpriv, context))
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200605 return -ENODEV;
606
607 return context->client->ops->submit(context, args, drm, file);
608}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300609
610static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
611 struct drm_file *file)
612{
613 struct tegra_drm_file *fpriv = file->driver_priv;
614 struct drm_tegra_get_syncpt_base *args = data;
615 struct tegra_drm_context *context;
616 struct host1x_syncpt_base *base;
617 struct host1x_syncpt *syncpt;
618
619 context = tegra_drm_get_context(args->context);
620
621 if (!tegra_drm_file_owns_context(fpriv, context))
622 return -ENODEV;
623
624 if (args->syncpt >= context->client->base.num_syncpts)
625 return -EINVAL;
626
627 syncpt = context->client->base.syncpts[args->syncpt];
628
629 base = host1x_syncpt_get_base(syncpt);
630 if (!base)
631 return -ENXIO;
632
633 args->id = host1x_syncpt_base_id(base);
634
635 return 0;
636}
Thierry Reding7678d712014-06-03 14:56:57 +0200637
638static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
639 struct drm_file *file)
640{
641 struct drm_tegra_gem_set_tiling *args = data;
642 enum tegra_bo_tiling_mode mode;
643 struct drm_gem_object *gem;
644 unsigned long value = 0;
645 struct tegra_bo *bo;
646
647 switch (args->mode) {
648 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
649 mode = TEGRA_BO_TILING_MODE_PITCH;
650
651 if (args->value != 0)
652 return -EINVAL;
653
654 break;
655
656 case DRM_TEGRA_GEM_TILING_MODE_TILED:
657 mode = TEGRA_BO_TILING_MODE_TILED;
658
659 if (args->value != 0)
660 return -EINVAL;
661
662 break;
663
664 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
665 mode = TEGRA_BO_TILING_MODE_BLOCK;
666
667 if (args->value > 5)
668 return -EINVAL;
669
670 value = args->value;
671 break;
672
673 default:
674 return -EINVAL;
675 }
676
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100677 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200678 if (!gem)
679 return -ENOENT;
680
681 bo = to_tegra_bo(gem);
682
683 bo->tiling.mode = mode;
684 bo->tiling.value = value;
685
Daniel Vetter11533302015-11-23 10:32:40 +0100686 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200687
688 return 0;
689}
690
691static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
692 struct drm_file *file)
693{
694 struct drm_tegra_gem_get_tiling *args = data;
695 struct drm_gem_object *gem;
696 struct tegra_bo *bo;
697 int err = 0;
698
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100699 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200700 if (!gem)
701 return -ENOENT;
702
703 bo = to_tegra_bo(gem);
704
705 switch (bo->tiling.mode) {
706 case TEGRA_BO_TILING_MODE_PITCH:
707 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
708 args->value = 0;
709 break;
710
711 case TEGRA_BO_TILING_MODE_TILED:
712 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
713 args->value = 0;
714 break;
715
716 case TEGRA_BO_TILING_MODE_BLOCK:
717 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
718 args->value = bo->tiling.value;
719 break;
720
721 default:
722 err = -EINVAL;
723 break;
724 }
725
Daniel Vetter11533302015-11-23 10:32:40 +0100726 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200727
728 return err;
729}
Thierry Reding7b129082014-06-10 12:04:03 +0200730
731static int tegra_gem_set_flags(struct drm_device *drm, void *data,
732 struct drm_file *file)
733{
734 struct drm_tegra_gem_set_flags *args = data;
735 struct drm_gem_object *gem;
736 struct tegra_bo *bo;
737
738 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
739 return -EINVAL;
740
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100741 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200742 if (!gem)
743 return -ENOENT;
744
745 bo = to_tegra_bo(gem);
746 bo->flags = 0;
747
748 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
749 bo->flags |= TEGRA_BO_BOTTOM_UP;
750
Daniel Vetter11533302015-11-23 10:32:40 +0100751 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200752
753 return 0;
754}
755
756static int tegra_gem_get_flags(struct drm_device *drm, void *data,
757 struct drm_file *file)
758{
759 struct drm_tegra_gem_get_flags *args = data;
760 struct drm_gem_object *gem;
761 struct tegra_bo *bo;
762
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100763 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200764 if (!gem)
765 return -ENOENT;
766
767 bo = to_tegra_bo(gem);
768 args->flags = 0;
769
770 if (bo->flags & TEGRA_BO_BOTTOM_UP)
771 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
772
Daniel Vetter11533302015-11-23 10:32:40 +0100773 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200774
775 return 0;
776}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200777#endif
778
Rob Clarkbaa70942013-08-02 13:27:49 -0400779static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200780#ifdef CONFIG_DRM_TEGRA_STAGING
Daniel Vetterf8c47142015-09-08 13:56:30 +0200781 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
782 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
783 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
784 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
785 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
786 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
787 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
788 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
789 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
790 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
791 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
792 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
793 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
794 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200795#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000796};
797
798static const struct file_operations tegra_drm_fops = {
799 .owner = THIS_MODULE,
800 .open = drm_open,
801 .release = drm_release,
802 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200803 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000804 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000805 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000806 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000807 .llseek = noop_llseek,
808};
809
Thierry Reding88e72712015-09-24 18:35:31 +0200810static u32 tegra_drm_get_vblank_counter(struct drm_device *drm,
811 unsigned int pipe)
Thierry Reding6e5ff992012-11-28 11:45:47 +0100812{
Shawn Guo75bcb052017-01-09 19:25:44 +0800813 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
Thierry Reding42e9ce02015-01-28 14:43:05 +0100814 struct tegra_dc *dc = to_tegra_dc(crtc);
Thierry Redinged7dae52014-12-16 16:03:13 +0100815
816 if (!crtc)
817 return 0;
818
Thierry Reding42e9ce02015-01-28 14:43:05 +0100819 return tegra_dc_get_vblank_counter(dc);
Thierry Reding6e5ff992012-11-28 11:45:47 +0100820}
821
Thierry Reding88e72712015-09-24 18:35:31 +0200822static int tegra_drm_enable_vblank(struct drm_device *drm, unsigned int pipe)
Thierry Reding6e5ff992012-11-28 11:45:47 +0100823{
Shawn Guo75bcb052017-01-09 19:25:44 +0800824 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
Thierry Reding6e5ff992012-11-28 11:45:47 +0100825 struct tegra_dc *dc = to_tegra_dc(crtc);
826
827 if (!crtc)
828 return -ENODEV;
829
830 tegra_dc_enable_vblank(dc);
831
832 return 0;
833}
834
Thierry Reding88e72712015-09-24 18:35:31 +0200835static void tegra_drm_disable_vblank(struct drm_device *drm, unsigned int pipe)
Thierry Reding6e5ff992012-11-28 11:45:47 +0100836{
Shawn Guo75bcb052017-01-09 19:25:44 +0800837 struct drm_crtc *crtc = drm_crtc_from_index(drm, pipe);
Thierry Reding6e5ff992012-11-28 11:45:47 +0100838 struct tegra_dc *dc = to_tegra_dc(crtc);
839
840 if (crtc)
841 tegra_dc_disable_vblank(dc);
842}
843
Thierry Reding3c03c462012-11-28 12:00:18 +0100844static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file)
845{
Thierry Reding08943e62013-09-26 16:08:18 +0200846 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Redingc88c3632013-09-26 16:08:22 +0200847 struct tegra_drm_context *context, *tmp;
Thierry Reding3c03c462012-11-28 12:00:18 +0100848
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200849 list_for_each_entry_safe(context, tmp, &fpriv->contexts, list)
Thierry Redingc88c3632013-09-26 16:08:22 +0200850 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200851
852 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100853}
854
Thierry Redinge450fcc2013-02-13 16:13:16 +0100855#ifdef CONFIG_DEBUG_FS
856static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
857{
858 struct drm_info_node *node = (struct drm_info_node *)s->private;
859 struct drm_device *drm = node->minor->dev;
860 struct drm_framebuffer *fb;
861
862 mutex_lock(&drm->mode_config.fb_lock);
863
864 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
865 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200866 fb->base.id, fb->width, fb->height,
867 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200868 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000869 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100870 }
871
872 mutex_unlock(&drm->mode_config.fb_lock);
873
874 return 0;
875}
876
Thierry Reding28c23372015-01-23 09:16:03 +0100877static int tegra_debugfs_iova(struct seq_file *s, void *data)
878{
879 struct drm_info_node *node = (struct drm_info_node *)s->private;
880 struct drm_device *drm = node->minor->dev;
881 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100882 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100883
Thierry Reding347ad49d2017-03-09 20:04:56 +0100884 mutex_lock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +0100885 drm_mm_print(&tegra->mm, &p);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100886 mutex_unlock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +0100887
888 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100889}
890
Thierry Redinge450fcc2013-02-13 16:13:16 +0100891static struct drm_info_list tegra_debugfs_list[] = {
892 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +0100893 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +0100894};
895
896static int tegra_debugfs_init(struct drm_minor *minor)
897{
898 return drm_debugfs_create_files(tegra_debugfs_list,
899 ARRAY_SIZE(tegra_debugfs_list),
900 minor->debugfs_root, minor);
901}
Thierry Redinge450fcc2013-02-13 16:13:16 +0100902#endif
903
Thierry Reding9b57f5f2013-11-08 13:17:14 +0100904static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +0200905 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
906 DRIVER_ATOMIC,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000907 .load = tegra_drm_load,
908 .unload = tegra_drm_unload,
909 .open = tegra_drm_open,
Thierry Reding3c03c462012-11-28 12:00:18 +0100910 .preclose = tegra_drm_preclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000911 .lastclose = tegra_drm_lastclose,
912
Thierry Reding6e5ff992012-11-28 11:45:47 +0100913 .get_vblank_counter = tegra_drm_get_vblank_counter,
914 .enable_vblank = tegra_drm_enable_vblank,
915 .disable_vblank = tegra_drm_disable_vblank,
916
Thierry Redinge450fcc2013-02-13 16:13:16 +0100917#if defined(CONFIG_DEBUG_FS)
918 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +0100919#endif
920
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +0200921 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +0200922 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +0100923
924 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
925 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
926 .gem_prime_export = tegra_gem_prime_export,
927 .gem_prime_import = tegra_gem_prime_import,
928
Arto Merilainende2ba662013-03-22 16:34:08 +0200929 .dumb_create = tegra_bo_dumb_create,
930 .dumb_map_offset = tegra_bo_dumb_map_offset,
Daniel Vetter43387b32013-07-16 09:12:04 +0200931 .dumb_destroy = drm_gem_dumb_destroy,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000932
933 .ioctls = tegra_drm_ioctls,
934 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
935 .fops = &tegra_drm_fops,
936
937 .name = DRIVER_NAME,
938 .desc = DRIVER_DESC,
939 .date = DRIVER_DATE,
940 .major = DRIVER_MAJOR,
941 .minor = DRIVER_MINOR,
942 .patchlevel = DRIVER_PATCHLEVEL,
943};
Thierry Reding776dc382013-10-14 14:43:22 +0200944
945int tegra_drm_register_client(struct tegra_drm *tegra,
946 struct tegra_drm_client *client)
947{
948 mutex_lock(&tegra->clients_lock);
949 list_add_tail(&client->list, &tegra->clients);
950 mutex_unlock(&tegra->clients_lock);
951
952 return 0;
953}
954
955int tegra_drm_unregister_client(struct tegra_drm *tegra,
956 struct tegra_drm_client *client)
957{
958 mutex_lock(&tegra->clients_lock);
959 list_del_init(&client->list);
960 mutex_unlock(&tegra->clients_lock);
961
962 return 0;
963}
964
Thierry Reding9910f5c2014-05-22 09:57:15 +0200965static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +0200966{
Thierry Reding9910f5c2014-05-22 09:57:15 +0200967 struct drm_driver *driver = &tegra_drm_driver;
968 struct drm_device *drm;
969 int err;
970
971 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +0200972 if (IS_ERR(drm))
973 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +0200974
Thierry Reding9910f5c2014-05-22 09:57:15 +0200975 dev_set_drvdata(&dev->dev, drm);
976
977 err = drm_dev_register(drm, 0);
978 if (err < 0)
979 goto unref;
980
Thierry Reding9910f5c2014-05-22 09:57:15 +0200981 return 0;
982
983unref:
984 drm_dev_unref(drm);
985 return err;
Thierry Reding776dc382013-10-14 14:43:22 +0200986}
987
Thierry Reding9910f5c2014-05-22 09:57:15 +0200988static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +0200989{
Thierry Reding9910f5c2014-05-22 09:57:15 +0200990 struct drm_device *drm = dev_get_drvdata(&dev->dev);
991
992 drm_dev_unregister(drm);
993 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +0200994
995 return 0;
996}
997
Thierry Reding359ae682014-12-18 17:15:25 +0100998#ifdef CONFIG_PM_SLEEP
999static int host1x_drm_suspend(struct device *dev)
1000{
1001 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001002 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001003
1004 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001005 tegra_drm_fb_suspend(drm);
1006
1007 tegra->state = drm_atomic_helper_suspend(drm);
1008 if (IS_ERR(tegra->state)) {
1009 tegra_drm_fb_resume(drm);
1010 drm_kms_helper_poll_enable(drm);
1011 return PTR_ERR(tegra->state);
1012 }
Thierry Reding359ae682014-12-18 17:15:25 +01001013
1014 return 0;
1015}
1016
1017static int host1x_drm_resume(struct device *dev)
1018{
1019 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001020 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001021
Thierry Reding986c58d2015-08-11 13:11:49 +02001022 drm_atomic_helper_resume(drm, tegra->state);
1023 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001024 drm_kms_helper_poll_enable(drm);
1025
1026 return 0;
1027}
1028#endif
1029
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001030static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1031 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001032
Thierry Reding776dc382013-10-14 14:43:22 +02001033static const struct of_device_id host1x_drm_subdevs[] = {
1034 { .compatible = "nvidia,tegra20-dc", },
1035 { .compatible = "nvidia,tegra20-hdmi", },
1036 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001037 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001038 { .compatible = "nvidia,tegra30-dc", },
1039 { .compatible = "nvidia,tegra30-hdmi", },
1040 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001041 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001042 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001043 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001044 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001045 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001046 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001047 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001048 { .compatible = "nvidia,tegra124-dsi", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001049 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001050 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001051 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001052 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001053 { .compatible = "nvidia,tegra210-sor1", },
Thierry Reding776dc382013-10-14 14:43:22 +02001054 { /* sentinel */ }
1055};
1056
1057static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001058 .driver = {
1059 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001060 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001061 },
Thierry Reding776dc382013-10-14 14:43:22 +02001062 .probe = host1x_drm_probe,
1063 .remove = host1x_drm_remove,
1064 .subdevs = host1x_drm_subdevs,
1065};
1066
Thierry Reding473112e2015-09-10 16:07:14 +02001067static struct platform_driver * const drivers[] = {
1068 &tegra_dc_driver,
1069 &tegra_hdmi_driver,
1070 &tegra_dsi_driver,
1071 &tegra_dpaux_driver,
1072 &tegra_sor_driver,
1073 &tegra_gr2d_driver,
1074 &tegra_gr3d_driver,
1075};
1076
Thierry Reding776dc382013-10-14 14:43:22 +02001077static int __init host1x_drm_init(void)
1078{
1079 int err;
1080
1081 err = host1x_driver_register(&host1x_drm_driver);
1082 if (err < 0)
1083 return err;
1084
Thierry Reding473112e2015-09-10 16:07:14 +02001085 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001086 if (err < 0)
1087 goto unregister_host1x;
1088
Thierry Reding776dc382013-10-14 14:43:22 +02001089 return 0;
1090
Thierry Reding776dc382013-10-14 14:43:22 +02001091unregister_host1x:
1092 host1x_driver_unregister(&host1x_drm_driver);
1093 return err;
1094}
1095module_init(host1x_drm_init);
1096
1097static void __exit host1x_drm_exit(void)
1098{
Thierry Reding473112e2015-09-10 16:07:14 +02001099 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001100 host1x_driver_unregister(&host1x_drm_driver);
1101}
1102module_exit(host1x_drm_exit);
1103
1104MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1105MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1106MODULE_LICENSE("GPL v2");