blob: ea5616036bf6de255d1b6c8fc761af1c20cb004e [file] [log] [blame]
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26#include <linux/firmware.h>
27#include "drmP.h"
28#include "amdgpu.h"
29#include "amdgpu_psp.h"
30#include "amdgpu_ucode.h"
31#include "soc15_common.h"
32#include "psp_v3_1.h"
33
34static void psp_set_funcs(struct amdgpu_device *adev);
35
36static int psp_early_init(void *handle)
37{
38 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
39
40 psp_set_funcs(adev);
41
42 return 0;
43}
44
45static int psp_sw_init(void *handle)
46{
47 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
48 struct psp_context *psp = &adev->psp;
49 int ret;
50
51 switch (adev->asic_type) {
52 case CHIP_VEGA10:
53 psp->init_microcode = psp_v3_1_init_microcode;
54 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
55 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
56 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
57 psp->ring_init = psp_v3_1_ring_init;
58 psp->cmd_submit = psp_v3_1_cmd_submit;
59 psp->compare_sram_data = psp_v3_1_compare_sram_data;
60 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 psp->adev = adev;
67
68 ret = psp_init_microcode(psp);
69 if (ret) {
70 DRM_ERROR("Failed to load psp firmware!\n");
71 return ret;
72 }
73
74 return 0;
75}
76
77static int psp_sw_fini(void *handle)
78{
79 return 0;
80}
81
82int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
83 uint32_t reg_val, uint32_t mask, bool check_changed)
84{
85 uint32_t val;
86 int i;
87 struct amdgpu_device *adev = psp->adev;
88
89 val = RREG32(reg_index);
90
91 for (i = 0; i < adev->usec_timeout; i++) {
92 if (check_changed) {
93 if (val != reg_val)
94 return 0;
95 } else {
96 if ((val & mask) == reg_val)
97 return 0;
98 }
99 udelay(1);
100 }
101
102 return -ETIME;
103}
104
105static int
106psp_cmd_submit_buf(struct psp_context *psp,
107 struct amdgpu_firmware_info *ucode,
108 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
109 int index)
110{
111 int ret;
112 struct amdgpu_bo *cmd_buf_bo;
113 uint64_t cmd_buf_mc_addr;
114 struct psp_gfx_cmd_resp *cmd_buf_mem;
115 struct amdgpu_device *adev = psp->adev;
116
117 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
118 AMDGPU_GEM_DOMAIN_VRAM,
119 &cmd_buf_bo, &cmd_buf_mc_addr,
120 (void **)&cmd_buf_mem);
121 if (ret)
122 return ret;
123
124 memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
125
126 memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
127
128 ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
129 fence_mc_addr, index);
130
131 while (*((unsigned int *)psp->fence_buf) != index) {
132 msleep(1);
kbuild test robotca7f65c2017-03-31 18:15:10 +0800133 }
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500134
135 amdgpu_bo_free_kernel(&cmd_buf_bo,
136 &cmd_buf_mc_addr,
137 (void **)&cmd_buf_mem);
138
139 return ret;
140}
141
142static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
143 uint64_t tmr_mc, uint32_t size)
144{
145 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
146 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
147 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
148 cmd->cmd.cmd_setup_tmr.buf_size = size;
149}
150
151/* Set up Trusted Memory Region */
152static int psp_tmr_init(struct psp_context *psp)
153{
154 int ret;
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500155
156 /*
157 * Allocate 3M memory aligned to 1M from Frame Buffer (local
158 * physical).
159 *
160 * Note: this memory need be reserved till the driver
161 * uninitializes.
162 */
163 ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
164 AMDGPU_GEM_DOMAIN_VRAM,
165 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
Huang Rui6f2b1fc2017-03-21 16:18:11 +0800166
167 return ret;
168}
169
170static int psp_tmr_load(struct psp_context *psp)
171{
172 int ret;
173 struct psp_gfx_cmd_resp *cmd;
174
175 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
176 if (!cmd)
177 return -ENOMEM;
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500178
179 psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
180
181 ret = psp_cmd_submit_buf(psp, NULL, cmd,
182 psp->fence_buf_mc_addr, 1);
183 if (ret)
Huang Rui6f2b1fc2017-03-21 16:18:11 +0800184 goto failed;
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500185
186 kfree(cmd);
187
188 return 0;
189
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500190failed:
191 kfree(cmd);
192 return ret;
193}
194
195static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
196 uint64_t asd_mc, uint64_t asd_mc_shared,
197 uint32_t size, uint32_t shared_size)
198{
199 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
200 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
201 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
202 cmd->cmd.cmd_load_ta.app_len = size;
203
204 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
205 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
206 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
207}
208
Huang Ruif5cfef92017-03-21 18:02:04 +0800209static int psp_asd_init(struct psp_context *psp)
210{
211 int ret;
212
213 /*
214 * Allocate 16k memory aligned to 4k from Frame Buffer (local
215 * physical) for shared ASD <-> Driver
216 */
217 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
218 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
219 &psp->asd_shared_bo,
220 &psp->asd_shared_mc_addr,
221 &psp->asd_shared_buf);
222
223 return ret;
224}
225
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500226static int psp_asd_load(struct psp_context *psp)
227{
228 int ret;
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500229 struct psp_gfx_cmd_resp *cmd;
230
231 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
232 if (!cmd)
233 return -ENOMEM;
234
Huang Rui2b0c3ae2017-03-22 10:16:05 +0800235 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
236 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500237
Huang Ruif5cfef92017-03-21 18:02:04 +0800238 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500239 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
240
241 ret = psp_cmd_submit_buf(psp, NULL, cmd,
242 psp->fence_buf_mc_addr, 2);
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500243
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500244 kfree(cmd);
245
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500246 return ret;
247}
248
249static int psp_load_fw(struct amdgpu_device *adev)
250{
251 int ret;
252 struct psp_gfx_cmd_resp *cmd;
253 int i;
254 struct amdgpu_firmware_info *ucode;
255 struct psp_context *psp = &adev->psp;
256
257 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
258 if (!cmd)
259 return -ENOMEM;
260
Huang Rui53a5cf52017-03-21 16:51:00 +0800261 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
262 AMDGPU_GEM_DOMAIN_GTT,
263 &psp->fw_pri_bo,
264 &psp->fw_pri_mc_addr,
265 &psp->fw_pri_buf);
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500266 if (ret)
267 goto failed;
268
Huang Rui53a5cf52017-03-21 16:51:00 +0800269 ret = psp_bootloader_load_sysdrv(psp);
270 if (ret)
271 goto failed_mem1;
272
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500273 ret = psp_bootloader_load_sos(psp);
274 if (ret)
Huang Rui53a5cf52017-03-21 16:51:00 +0800275 goto failed_mem1;
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500276
277 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
278 if (ret)
Huang Rui53a5cf52017-03-21 16:51:00 +0800279 goto failed_mem1;
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500280
281 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
282 AMDGPU_GEM_DOMAIN_VRAM,
283 &psp->fence_buf_bo,
284 &psp->fence_buf_mc_addr,
285 &psp->fence_buf);
286 if (ret)
Huang Rui53a5cf52017-03-21 16:51:00 +0800287 goto failed_mem1;
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500288
289 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
290
291 ret = psp_tmr_init(psp);
292 if (ret)
293 goto failed_mem;
294
Huang Rui6f2b1fc2017-03-21 16:18:11 +0800295 ret = psp_tmr_load(psp);
296 if (ret)
297 goto failed_mem;
298
Huang Ruif5cfef92017-03-21 18:02:04 +0800299 ret = psp_asd_init(psp);
300 if (ret)
301 goto failed_mem;
302
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500303 ret = psp_asd_load(psp);
304 if (ret)
305 goto failed_mem;
306
307 for (i = 0; i < adev->firmware.max_ucodes; i++) {
308 ucode = &adev->firmware.ucode[i];
309 if (!ucode->fw)
310 continue;
311
312 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
313 psp_smu_reload_quirk(psp))
314 continue;
315
316 ret = psp_prep_cmd_buf(ucode, cmd);
317 if (ret)
318 goto failed_mem;
319
320 ret = psp_cmd_submit_buf(psp, ucode, cmd,
321 psp->fence_buf_mc_addr, i + 3);
322 if (ret)
323 goto failed_mem;
324
325#if 0
326 /* check if firmware loaded sucessfully */
327 if (!amdgpu_psp_check_fw_loading_status(adev, i))
328 return -EINVAL;
329#endif
330 }
331
332 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
333 &psp->fence_buf_mc_addr, &psp->fence_buf);
334 kfree(cmd);
335
336 return 0;
337
338failed_mem:
339 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
340 &psp->fence_buf_mc_addr, &psp->fence_buf);
Huang Rui53a5cf52017-03-21 16:51:00 +0800341failed_mem1:
342 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
343 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500344failed:
345 kfree(cmd);
346 return ret;
347}
348
349static int psp_hw_init(void *handle)
350{
351 int ret;
352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353
354
355 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
356 return 0;
357
358 mutex_lock(&adev->firmware.mutex);
359 /*
360 * This sequence is just used on hw_init only once, no need on
361 * resume.
362 */
363 ret = amdgpu_ucode_init_bo(adev);
364 if (ret)
365 goto failed;
366
367 ret = psp_load_fw(adev);
368 if (ret) {
369 DRM_ERROR("PSP firmware loading failed\n");
370 goto failed;
371 }
372
373 mutex_unlock(&adev->firmware.mutex);
374 return 0;
375
376failed:
377 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
378 mutex_unlock(&adev->firmware.mutex);
379 return -EINVAL;
380}
381
382static int psp_hw_fini(void *handle)
383{
384 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
385 struct psp_context *psp = &adev->psp;
386
387 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
388 amdgpu_ucode_fini_bo(adev);
389
390 if (psp->tmr_buf)
391 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
392
Huang Rui53a5cf52017-03-21 16:51:00 +0800393 if (psp->fw_pri_buf)
394 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
395 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
396
Huang Rui0e5ca0d2017-03-03 18:37:23 -0500397 return 0;
398}
399
400static int psp_suspend(void *handle)
401{
402 return 0;
403}
404
405static int psp_resume(void *handle)
406{
407 int ret;
408 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
409
410 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
411 return 0;
412
413 mutex_lock(&adev->firmware.mutex);
414
415 ret = psp_load_fw(adev);
416 if (ret)
417 DRM_ERROR("PSP resume failed\n");
418
419 mutex_unlock(&adev->firmware.mutex);
420
421 return ret;
422}
423
424static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
425 enum AMDGPU_UCODE_ID ucode_type)
426{
427 struct amdgpu_firmware_info *ucode = NULL;
428
429 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
430 DRM_INFO("firmware is not loaded by PSP\n");
431 return true;
432 }
433
434 if (!adev->firmware.fw_size)
435 return false;
436
437 ucode = &adev->firmware.ucode[ucode_type];
438 if (!ucode->fw || !ucode->ucode_size)
439 return false;
440
441 return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
442}
443
444static int psp_set_clockgating_state(void *handle,
445 enum amd_clockgating_state state)
446{
447 return 0;
448}
449
450static int psp_set_powergating_state(void *handle,
451 enum amd_powergating_state state)
452{
453 return 0;
454}
455
456const struct amd_ip_funcs psp_ip_funcs = {
457 .name = "psp",
458 .early_init = psp_early_init,
459 .late_init = NULL,
460 .sw_init = psp_sw_init,
461 .sw_fini = psp_sw_fini,
462 .hw_init = psp_hw_init,
463 .hw_fini = psp_hw_fini,
464 .suspend = psp_suspend,
465 .resume = psp_resume,
466 .is_idle = NULL,
467 .wait_for_idle = NULL,
468 .soft_reset = NULL,
469 .set_clockgating_state = psp_set_clockgating_state,
470 .set_powergating_state = psp_set_powergating_state,
471};
472
473static const struct amdgpu_psp_funcs psp_funcs = {
474 .check_fw_loading_status = psp_check_fw_loading_status,
475};
476
477static void psp_set_funcs(struct amdgpu_device *adev)
478{
479 if (NULL == adev->firmware.funcs)
480 adev->firmware.funcs = &psp_funcs;
481}
482
483const struct amdgpu_ip_block_version psp_v3_1_ip_block =
484{
485 .type = AMD_IP_BLOCK_TYPE_PSP,
486 .major = 3,
487 .minor = 1,
488 .rev = 0,
489 .funcs = &psp_ip_funcs,
490};