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Patrick Boettcher4de27302006-04-17 13:22:15 -03001/*
2 * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
3 *
4 * Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
Patrick Boettcher4de27302006-04-17 13:22:15 -030016 */
17
18#ifndef MT2060_PRIV_H
19#define MT2060_PRIV_H
20
21// Uncomment the #define below to enable spurs checking. The results where quite unconvincing.
22// #define MT2060_SPURCHECK
23
24/* This driver is based on the information available in the datasheet of the
25 "Comtech SDVBT-3K6M" tuner ( K1000737843.pdf ) which features the MT2060 register map :
26
27 I2C Address : 0x60
28
29 Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults )
30 --------------------------------------------------------------------------------
31 00 | [ PART ] | [ REV ] | R = 0x63
32 01 | [ LNABAND ] | [ NUM1(5:2) ] | RW = 0x3F
33 02 | [ DIV1 ] | RW = 0x74
34 03 | FM1CA | FM1SS | [ NUM1(1:0) ] | [ NUM2(3:0) ] | RW = 0x00
35 04 | NUM2(11:4) ] | RW = 0x08
36 05 | [ DIV2 ] |NUM2(12)| RW = 0x93
37 06 | L1LK | [ TAD1 ] | L2LK | [ TAD2 ] | R
38 07 | [ FMF ] | R
39 08 | ? | FMCAL | ? | ? | ? | ? | ? | TEMP | R
40 09 | 0 | 0 | [ FMGC ] | 0 | GP02 | GP01 | 0 | RW = 0x20
41 0A | ??
42 0B | 0 | 0 | 1 | 1 | 0 | 0 | [ VGAG ] | RW = 0x30
43 0C | V1CSE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RW = 0xFF
44 0D | 1 | 0 | [ V1CS ] | RW = 0xB0
45 0E | ??
46 0F | ??
47 10 | ??
48 11 | [ LOTO ] | 0 | 0 | 1 | 0 | RW = 0x42
49
50 PART : Part code : 6 for MT2060
51 REV : Revision code : 3 for current revision
52 LNABAND : Input frequency range : ( See code for details )
53 NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details )
54 FM1CA : Calibration Start Bit
55 FM1SS : Calibration Single Step bit
56 L1LK : LO1 Lock Detect
57 TAD1 : Tune Line ADC ( ? )
58 L2LK : LO2 Lock Detect
59 TAD2 : Tune Line ADC ( ? )
60 FMF : Estimated first IF Center frequency Offset ( ? )
61 FM1CAL : Calibration done bit
62 TEMP : On chip temperature sensor
63 FMCG : Mixer 1 Cap Gain ( ? )
64 GP01 / GP02 : Programmable digital outputs. Unconnected pins ?
65 V1CSE : LO1 VCO Automatic Capacitor Select Enable ( ? )
66 V1CS : LO1 Capacitor Selection Value ( ? )
67 LOTO : LO Timeout ( ? )
68 VGAG : Tuner Output gain
69*/
70
71#define I2C_ADDRESS 0x60
72
73#define REG_PART_REV 0
74#define REG_LO1C1 1
75#define REG_LO1C2 2
76#define REG_LO2C1 3
77#define REG_LO2C2 4
78#define REG_LO2C3 5
79#define REG_LO_STATUS 6
80#define REG_FM_FREQ 7
81#define REG_MISC_STAT 8
82#define REG_MISC_CTRL 9
83#define REG_RESERVED_A 0x0A
84#define REG_VGAG 0x0B
85#define REG_LO1B1 0x0C
86#define REG_LO1B2 0x0D
87#define REG_LOTO 0x11
88
89#define PART_REV 0x63 // The current driver works only with PART=6 and REV=3 chips
90
Olivier DANET46f73f92006-08-08 15:48:10 -030091struct mt2060_priv {
92 struct mt2060_config *cfg;
93 struct i2c_adapter *i2c;
Antti Palosaari59e8b7a2015-07-26 18:45:05 -030094 struct i2c_client *client;
95 struct mt2060_config config;
Olivier DANET46f73f92006-08-08 15:48:10 -030096
Antti Palosaari433c4862015-07-26 17:30:07 -030097 u8 i2c_max_regs;
Olivier DANET46f73f92006-08-08 15:48:10 -030098 u32 frequency;
Olivier DANET46f73f92006-08-08 15:48:10 -030099 u16 if1_freq;
100 u8 fmfreq;
Antti Palosaarie11415c2016-12-09 15:11:09 -0200101
102 /*
103 * Use REG_MISC_CTRL register for sleep. That drops sleep power usage
104 * about 0.9W (huge!). Register bit meanings are unknown, so let it be
105 * disabled by default to avoid possible regression. Convert driver to
106 * i2c model in order to enable it.
107 */
108 bool sleep;
Olivier DANET46f73f92006-08-08 15:48:10 -0300109};
110
Patrick Boettcher4de27302006-04-17 13:22:15 -0300111#endif