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David Gibsonf88df142007-04-30 16:30:56 +10001#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
2#define _ASM_POWERPC_PGTABLE_PPC32_H
3
David Gibsond1953c82007-05-08 12:46:49 +10004#include <asm-generic/pgtable-nopmd.h>
David Gibsonf88df142007-04-30 16:30:56 +10005
6#ifndef __ASSEMBLY__
7#include <linux/sched.h>
8#include <linux/threads.h>
David Gibsonf88df142007-04-30 16:30:56 +10009#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
David Gibsonf88df142007-04-30 16:30:56 +100010
11extern unsigned long va_to_phys(unsigned long address);
12extern pte_t *va_to_pte(unsigned long address);
13extern unsigned long ioremap_bot, ioremap_base;
Benjamin Herrenschmidtb98ac05d2007-10-31 16:42:19 +110014
15#ifdef CONFIG_44x
16extern int icache_44x_need_flush;
17#endif
18
David Gibsonf88df142007-04-30 16:30:56 +100019#endif /* __ASSEMBLY__ */
20
21/*
22 * The PowerPC MMU uses a hash table containing PTEs, together with
23 * a set of 16 segment registers (on 32-bit implementations), to define
24 * the virtual to physical address mapping.
25 *
26 * We use the hash table as an extended TLB, i.e. a cache of currently
27 * active mappings. We maintain a two-level page table tree, much
28 * like that used by the i386, for the sake of the Linux memory
29 * management code. Low-level assembler code in hashtable.S
30 * (procedure hash_page) is responsible for extracting ptes from the
31 * tree and putting them into the hash table when necessary, and
32 * updating the accessed and modified bits in the page table tree.
33 */
34
35/*
36 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
37 * We also use the two level tables, but we can put the real bits in them
38 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
39 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
40 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
41 * based upon user/super access. The TLB does not have accessed nor write
42 * protect. We assume that if the TLB get loaded with an entry it is
43 * accessed, and overload the changed bit for write protect. We use
44 * two bits in the software pte that are supposed to be set to zero in
45 * the TLB entry (24 and 25) for these indicators. Although the level 1
46 * descriptor contains the guarded and writethrough/copyback bits, we can
47 * set these at the page level since they get copied from the Mx_TWC
48 * register when the TLB entry is loaded. We will use bit 27 for guard, since
49 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
50 * These will get masked from the level 2 descriptor at TLB load time, and
51 * copied to the MD_TWC before it gets loaded.
52 * Large page sizes added. We currently support two sizes, 4K and 8M.
53 * This also allows a TLB hander optimization because we can directly
54 * load the PMD into MD_TWC. The 8M pages are only used for kernel
55 * mapping of well known areas. The PMD (PGD) entries contain control
56 * flags in addition to the address, so care must be taken that the
57 * software no longer assumes these are only pointers.
58 */
59
60/*
61 * At present, all PowerPC 400-class processors share a similar TLB
62 * architecture. The instruction and data sides share a unified,
63 * 64-entry, fully-associative TLB which is maintained totally under
64 * software control. In addition, the instruction side has a
65 * hardware-managed, 4-entry, fully-associative TLB which serves as a
66 * first level to the shared TLB. These two TLBs are known as the UTLB
67 * and ITLB, respectively (see "mmu.h" for definitions).
68 */
69
70/*
71 * The normal case is that PTEs are 32-bits and we have a 1-page
72 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
73 *
74 * For any >32-bit physical address platform, we can use the following
75 * two level page table layout where the pgdir is 8KB and the MS 13 bits
76 * are an index to the second level table. The combined pgdir/pmd first
77 * level has 2048 entries and the second level has 512 64-bit PTE entries.
78 * -Matt
79 */
David Gibsonf88df142007-04-30 16:30:56 +100080/* PGDIR_SHIFT determines what a top-level page table entry can map */
David Gibsond1953c82007-05-08 12:46:49 +100081#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
David Gibsonf88df142007-04-30 16:30:56 +100082#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
83#define PGDIR_MASK (~(PGDIR_SIZE-1))
84
85/*
86 * entries per page directory level: our page-table tree is two-level, so
87 * we don't really have any PMD directory.
88 */
Kumar Galabee86f12007-12-06 13:11:04 -060089#ifndef __ASSEMBLY__
90#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
91#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
92#endif /* __ASSEMBLY__ */
93
David Gibsonf88df142007-04-30 16:30:56 +100094#define PTRS_PER_PTE (1 << PTE_SHIFT)
95#define PTRS_PER_PMD 1
96#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
97
98#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
99#define FIRST_USER_ADDRESS 0
100
David Gibsonf88df142007-04-30 16:30:56 +1000101#define pte_ERROR(e) \
David Gibson0aeafb02007-05-04 16:47:51 +1000102 printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
103 (unsigned long long)pte_val(e))
David Gibsonf88df142007-04-30 16:30:56 +1000104#define pgd_ERROR(e) \
105 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
106
107/*
108 * Just any arbitrary offset to the start of the vmalloc VM area: the
109 * current 64MB value just means that there will be a 64MB "hole" after the
110 * physical memory until the kernel virtual memory starts. That means that
111 * any out-of-bounds memory accesses will hopefully be caught.
112 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
113 * area for the same reason. ;)
114 *
115 * We no longer map larger than phys RAM with the BATs so we don't have
116 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
117 * about clashes between our early calls to ioremap() that start growing down
118 * from ioremap_base being run into the VM area allocations (growing upwards
119 * from VMALLOC_START). For this reason we have ioremap_bot to check when
120 * we actually run into our mappings setup in the early boot with the VM
121 * system. This really does become a problem for machines with good amounts
122 * of RAM. -- Cort
123 */
124#define VMALLOC_OFFSET (0x1000000) /* 16M */
125#ifdef PPC_PIN_SIZE
126#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
127#else
128#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
129#endif
130#define VMALLOC_END ioremap_bot
131
132/*
133 * Bits in a linux-style PTE. These match the bits in the
134 * (hardware-defined) PowerPC PTE as closely as possible.
135 */
136
137#if defined(CONFIG_40x)
138
139/* There are several potential gotchas here. The 40x hardware TLBLO
140 field looks like this:
141
142 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
143 RPN..................... 0 0 EX WR ZSEL....... W I M G
144
145 Where possible we make the Linux PTE bits match up with this
146
147 - bits 20 and 21 must be cleared, because we use 4k pages (40x can
148 support down to 1k pages), this is done in the TLBMiss exception
149 handler.
150 - We use only zones 0 (for kernel pages) and 1 (for user pages)
151 of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
152 miss handler. Bit 27 is PAGE_USER, thus selecting the correct
153 zone.
154 - PRESENT *must* be in the bottom two bits because swap cache
155 entries use the top 30 bits. Because 40x doesn't support SMP
156 anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
157 is cleared in the TLB miss handler before the TLB entry is loaded.
158 - All other bits of the PTE are loaded into TLBLO without
159 modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
160 software PTE bits. We actually use use bits 21, 24, 25, and
161 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
162 PRESENT.
163*/
164
165/* Definitions for 40x embedded chips. */
166#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
167#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
168#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
169#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
170#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
171#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
172#define _PAGE_RW 0x040 /* software: Writes permitted */
173#define _PAGE_DIRTY 0x080 /* software: dirty page */
174#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
175#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
176#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
177
178#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
179#define _PMD_BAD 0x802
180#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
181#define _PMD_SIZE_4M 0x0c0
182#define _PMD_SIZE_16M 0x0e0
183#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
184
185#elif defined(CONFIG_44x)
186/*
187 * Definitions for PPC440
188 *
189 * Because of the 3 word TLB entries to support 36-bit addressing,
190 * the attribute are difficult to map in such a fashion that they
191 * are easily loaded during exception processing. I decided to
192 * organize the entry so the ERPN is the only portion in the
193 * upper word of the PTE and the attribute bits below are packed
194 * in as sensibly as they can be in the area below a 4KB page size
195 * oriented RPN. This at least makes it easy to load the RPN and
196 * ERPN fields in the TLB. -Matt
197 *
198 * Note that these bits preclude future use of a page size
199 * less than 4KB.
200 *
201 *
202 * PPC 440 core has following TLB attribute fields;
203 *
204 * TLB1:
205 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
206 * RPN................................. - - - - - - ERPN.......
207 *
208 * TLB2:
209 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
210 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
211 *
Stefan Roesea96df492008-05-05 16:53:19 +1000212 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
213 * TLB2 storage attibute fields. Those are:
214 *
215 * TLB2:
216 * 0...10 11 12 13 14 15 16...31
217 * no change WL1 IL1I IL1D IL2I IL2D no change
218 *
David Gibsonf88df142007-04-30 16:30:56 +1000219 * There are some constrains and options, to decide mapping software bits
220 * into TLB entry.
221 *
222 * - PRESENT *must* be in the bottom three bits because swap cache
223 * entries use the top 29 bits for TLB2.
224 *
225 * - FILE *must* be in the bottom three bits because swap cache
226 * entries use the top 29 bits for TLB2.
227 *
228 * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
229 * doesn't support SMP. So we can use this as software bit, like
230 * DIRTY.
231 *
232 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
233 * for memory protection related functions (see PTE structure in
234 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
235 * above bits. Note that the bit values are CPU specific, not architecture
236 * specific.
237 *
238 * The kernel PTE entry holds an arch-dependent swp_entry structure under
239 * certain situations. In other words, in such situations some portion of
240 * the PTE bits are used as a swp_entry. In the PPC implementation, the
241 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
242 * hold protection values. That means the three protection bits are
243 * reserved for both PTE and SWAP entry at the most significant three
244 * LSBs.
245 *
246 * There are three protection bits available for SWAP entry:
247 * _PAGE_PRESENT
248 * _PAGE_FILE
249 * _PAGE_HASHPTE (if HW has)
250 *
251 * So those three bits have to be inside of 0-2nd LSB of PTE.
252 *
253 */
254
255#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
256#define _PAGE_RW 0x00000002 /* S: Write permission */
257#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
258#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
259#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */
260#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */
261#define _PAGE_USER 0x00000040 /* S: User page */
262#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
263#define _PAGE_GUARDED 0x00000100 /* H: G bit */
264#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */
265#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
266#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
267
268/* TODO: Add large page lowmem mapping support */
269#define _PMD_PRESENT 0
270#define _PMD_PRESENT_MASK (PAGE_MASK)
271#define _PMD_BAD (~PAGE_MASK)
272
273/* ERPN in a PTE never gets cleared, ignore it */
274#define _PTE_NONE_MASK 0xffffffff00000000ULL
275
276#elif defined(CONFIG_FSL_BOOKE)
277/*
278 MMU Assist Register 3:
279
280 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
281 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
282
283 - PRESENT *must* be in the bottom three bits because swap cache
284 entries use the top 29 bits.
285
286 - FILE *must* be in the bottom three bits because swap cache
287 entries use the top 29 bits.
288*/
289
290/* Definitions for FSL Book-E Cores */
291#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
292#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
293#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
294#define _PAGE_ACCESSED 0x00004 /* S: Page referenced */
295#define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */
296#define _PAGE_RW 0x00010 /* S: Write permission */
297#define _PAGE_HWEXEC 0x00020 /* H: UX permission */
298
299#define _PAGE_ENDIAN 0x00040 /* H: E bit */
300#define _PAGE_GUARDED 0x00080 /* H: G bit */
301#define _PAGE_COHERENT 0x00100 /* H: M bit */
302#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
303#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
304
305#ifdef CONFIG_PTE_64BIT
306#define _PAGE_DIRTY 0x08000 /* S: Page dirty */
307
308/* ERPN in a PTE never gets cleared, ignore it */
309#define _PTE_NONE_MASK 0xffffffffffff0000ULL
310#else
311#define _PAGE_DIRTY 0x00800 /* S: Page dirty */
312#endif
313
314#define _PMD_PRESENT 0
315#define _PMD_PRESENT_MASK (PAGE_MASK)
316#define _PMD_BAD (~PAGE_MASK)
317
318#elif defined(CONFIG_8xx)
319/* Definitions for 8xx embedded chips. */
320#define _PAGE_PRESENT 0x0001 /* Page is valid */
321#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
322#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
323#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
324
325/* These five software bits must be masked out when the entry is loaded
326 * into the TLB.
327 */
328#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
329#define _PAGE_GUARDED 0x0010 /* software: guarded access */
330#define _PAGE_DIRTY 0x0020 /* software: page changed */
331#define _PAGE_RW 0x0040 /* software: user write access allowed */
332#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
333
334/* Setting any bits in the nibble with the follow two controls will
335 * require a TLB exception handler change. It is assumed unused bits
336 * are always zero.
337 */
338#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
339#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
340
341#define _PMD_PRESENT 0x0001
342#define _PMD_BAD 0x0ff0
343#define _PMD_PAGE_MASK 0x000c
344#define _PMD_PAGE_8M 0x000c
345
David Gibsonf88df142007-04-30 16:30:56 +1000346#define _PTE_NONE_MASK _PAGE_ACCESSED
347
348#else /* CONFIG_6xx */
349/* Definitions for 60x, 740/750, etc. */
350#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
351#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
352#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
353#define _PAGE_USER 0x004 /* usermode access allowed */
354#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
355#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
356#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
357#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
358#define _PAGE_DIRTY 0x080 /* C: page changed */
359#define _PAGE_ACCESSED 0x100 /* R: page referenced */
360#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
361#define _PAGE_RW 0x400 /* software: user write access allowed */
362
363#define _PTE_NONE_MASK _PAGE_HASHPTE
364
365#define _PMD_PRESENT 0
366#define _PMD_PRESENT_MASK (PAGE_MASK)
367#define _PMD_BAD (~PAGE_MASK)
368#endif
369
370/*
371 * Some bits are only used on some cpu families...
372 */
373#ifndef _PAGE_HASHPTE
374#define _PAGE_HASHPTE 0
375#endif
376#ifndef _PTE_NONE_MASK
377#define _PTE_NONE_MASK 0
378#endif
379#ifndef _PAGE_SHARED
380#define _PAGE_SHARED 0
381#endif
382#ifndef _PAGE_HWWRITE
383#define _PAGE_HWWRITE 0
384#endif
385#ifndef _PAGE_HWEXEC
386#define _PAGE_HWEXEC 0
387#endif
388#ifndef _PAGE_EXEC
389#define _PAGE_EXEC 0
390#endif
391#ifndef _PMD_PRESENT_MASK
392#define _PMD_PRESENT_MASK _PMD_PRESENT
393#endif
394#ifndef _PMD_SIZE
395#define _PMD_SIZE 0
396#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
397#endif
398
399#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
400
401/*
402 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
403 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
404 * to have it in the Linux PTE, and in fact the bit could be reused for
405 * another purpose. -- paulus.
406 */
407
408#ifdef CONFIG_44x
409#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
410#else
411#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
412#endif
413#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
414#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
415
416#ifdef CONFIG_PPC_STD_MMU
417/* On standard PPC MMU, no user access implies kernel read/write access,
418 * so to write-protect kernel memory we must turn on user access */
419#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
420#else
421#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
422#endif
423
424#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
425#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
426
Ionut Nicu221ac322008-03-06 03:12:54 +1100427#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
428 defined(CONFIG_KPROBES)
David Gibsonf88df142007-04-30 16:30:56 +1000429/* We want the debuggers to be able to set breakpoints anywhere, so
430 * don't write protect the kernel text */
431#define _PAGE_RAM_TEXT _PAGE_RAM
432#else
433#define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
434#endif
435
436#define PAGE_NONE __pgprot(_PAGE_BASE)
437#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
438#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
439#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
440#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
441#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
442#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
443
444#define PAGE_KERNEL __pgprot(_PAGE_RAM)
445#define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO)
446
447/*
448 * The PowerPC can only do execute protection on a segment (256MB) basis,
449 * not on a page basis. So we consider execute permission the same as read.
450 * Also, write permissions imply read permissions.
451 * This is the closest we can get..
452 */
453#define __P000 PAGE_NONE
454#define __P001 PAGE_READONLY_X
455#define __P010 PAGE_COPY
456#define __P011 PAGE_COPY_X
457#define __P100 PAGE_READONLY
458#define __P101 PAGE_READONLY_X
459#define __P110 PAGE_COPY
460#define __P111 PAGE_COPY_X
461
462#define __S000 PAGE_NONE
463#define __S001 PAGE_READONLY_X
464#define __S010 PAGE_SHARED
465#define __S011 PAGE_SHARED_X
466#define __S100 PAGE_READONLY
467#define __S101 PAGE_READONLY_X
468#define __S110 PAGE_SHARED
469#define __S111 PAGE_SHARED_X
470
471#ifndef __ASSEMBLY__
472/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
473 * kernel without large page PMD support */
474extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
475
476/*
477 * Conversions between PTE values and page frame numbers.
478 */
479
480/* in some case we want to additionaly adjust where the pfn is in the pte to
481 * allow room for more flags */
482#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
483#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
484#else
485#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
486#endif
487
488#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
489#define pte_page(x) pfn_to_page(pte_pfn(x))
490
491#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
492 pgprot_val(prot))
493#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
David Gibsonf88df142007-04-30 16:30:56 +1000494#endif /* __ASSEMBLY__ */
495
496#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
497#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
498#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
499
500#define pmd_none(pmd) (!pmd_val(pmd))
501#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
502#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
503#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
504
505#ifndef __ASSEMBLY__
506/*
David Gibsonf88df142007-04-30 16:30:56 +1000507 * The following only work if pte_present() is true.
508 * Undefined behaviour if not..
509 */
David Gibsonf88df142007-04-30 16:30:56 +1000510static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
David Gibsonf88df142007-04-30 16:30:56 +1000511static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
512static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
513static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
Nick Piggin7e675132008-04-28 02:13:00 -0700514static inline int pte_special(pte_t pte) { return 0; }
David Gibsonf88df142007-04-30 16:30:56 +1000515
516static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
517static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
518
David Gibsonf88df142007-04-30 16:30:56 +1000519static inline pte_t pte_wrprotect(pte_t pte) {
520 pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
David Gibsonf88df142007-04-30 16:30:56 +1000521static inline pte_t pte_mkclean(pte_t pte) {
522 pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
523static inline pte_t pte_mkold(pte_t pte) {
524 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
525
David Gibsonf88df142007-04-30 16:30:56 +1000526static inline pte_t pte_mkwrite(pte_t pte) {
527 pte_val(pte) |= _PAGE_RW; return pte; }
528static inline pte_t pte_mkdirty(pte_t pte) {
529 pte_val(pte) |= _PAGE_DIRTY; return pte; }
530static inline pte_t pte_mkyoung(pte_t pte) {
531 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
Nick Piggin7e675132008-04-28 02:13:00 -0700532static inline pte_t pte_mkspecial(pte_t pte) {
533 return pte; }
David Gibsonf88df142007-04-30 16:30:56 +1000534
535static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
536{
537 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
538 return pte;
539}
540
541/*
542 * When flushing the tlb entry for a page, we also need to flush the hash
543 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
544 */
545extern int flush_hash_pages(unsigned context, unsigned long va,
546 unsigned long pmdval, int count);
547
548/* Add an HPTE to the hash table */
549extern void add_hash_page(unsigned context, unsigned long va,
550 unsigned long pmdval);
551
552/*
553 * Atomic PTE updates.
554 *
555 * pte_update clears and sets bit atomically, and returns
556 * the old pte value. In the 64-bit PTE case we lock around the
557 * low PTE word since we expect ALL flag bits to be there
558 */
559#ifndef CONFIG_PTE_64BIT
560static inline unsigned long pte_update(pte_t *p, unsigned long clr,
561 unsigned long set)
562{
563 unsigned long old, tmp;
564
565 __asm__ __volatile__("\
5661: lwarx %0,0,%3\n\
567 andc %1,%0,%4\n\
568 or %1,%1,%5\n"
569 PPC405_ERR77(0,%3)
570" stwcx. %1,0,%3\n\
571 bne- 1b"
572 : "=&r" (old), "=&r" (tmp), "=m" (*p)
573 : "r" (p), "r" (clr), "r" (set), "m" (*p)
574 : "cc" );
Benjamin Herrenschmidtb98ac05d2007-10-31 16:42:19 +1100575#ifdef CONFIG_44x
576 if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
577 icache_44x_need_flush = 1;
578#endif
David Gibsonf88df142007-04-30 16:30:56 +1000579 return old;
580}
581#else
582static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
583 unsigned long set)
584{
585 unsigned long long old;
586 unsigned long tmp;
587
588 __asm__ __volatile__("\
5891: lwarx %L0,0,%4\n\
590 lwzx %0,0,%3\n\
591 andc %1,%L0,%5\n\
592 or %1,%1,%6\n"
593 PPC405_ERR77(0,%3)
594" stwcx. %1,0,%4\n\
595 bne- 1b"
596 : "=&r" (old), "=&r" (tmp), "=m" (*p)
597 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
598 : "cc" );
Benjamin Herrenschmidtb98ac05d2007-10-31 16:42:19 +1100599#ifdef CONFIG_44x
600 if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
601 icache_44x_need_flush = 1;
602#endif
David Gibsonf88df142007-04-30 16:30:56 +1000603 return old;
604}
605#endif
606
607/*
608 * set_pte stores a linux PTE into the linux page table.
609 * On machines which use an MMU hash table we avoid changing the
610 * _PAGE_HASHPTE bit.
611 */
612static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
613 pte_t *ptep, pte_t pte)
614{
615#if _PAGE_HASHPTE != 0
616 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
617#else
618 *ptep = pte;
619#endif
620}
621
622/*
623 * 2.6 calles this without flushing the TLB entry, this is wrong
624 * for our hash-based implementation, we fix that up here
625 */
626#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
627static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
628{
629 unsigned long old;
630 old = pte_update(ptep, _PAGE_ACCESSED, 0);
631#if _PAGE_HASHPTE != 0
632 if (old & _PAGE_HASHPTE) {
633 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
634 flush_hash_pages(context, addr, ptephys, 1);
635 }
636#endif
637 return (old & _PAGE_ACCESSED) != 0;
638}
639#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
640 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
641
David Gibsonf88df142007-04-30 16:30:56 +1000642#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
643static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
644 pte_t *ptep)
645{
646 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
647}
648
649#define __HAVE_ARCH_PTEP_SET_WRPROTECT
650static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
651 pte_t *ptep)
652{
653 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
654}
655
656#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
657static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
658{
659 unsigned long bits = pte_val(entry) &
660 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
661 pte_update(ptep, 0, bits);
662}
663
664#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
Benjamin Herrenschmidt8dab5242007-06-16 10:16:12 -0700665({ \
666 int __changed = !pte_same(*(__ptep), __entry); \
667 if (__changed) { \
668 __ptep_set_access_flags(__ptep, __entry, __dirty); \
669 flush_tlb_page_nohash(__vma, __address); \
670 } \
671 __changed; \
672})
David Gibsonf88df142007-04-30 16:30:56 +1000673
674/*
675 * Macro to mark a page protection value as "uncacheable".
676 */
677#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
678
679struct file;
680extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
681 unsigned long size, pgprot_t vma_prot);
682#define __HAVE_PHYS_MEM_ACCESS_PROT
683
684#define __HAVE_ARCH_PTE_SAME
685#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
686
687/*
688 * Note that on Book E processors, the pmd contains the kernel virtual
689 * (lowmem) address of the pte page. The physical address is less useful
690 * because everything runs with translation enabled (even the TLB miss
691 * handler). On everything else the pmd contains the physical address
692 * of the pte page. -- paulus
693 */
694#ifndef CONFIG_BOOKE
695#define pmd_page_vaddr(pmd) \
696 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
697#define pmd_page(pmd) \
698 (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
699#else
700#define pmd_page_vaddr(pmd) \
701 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
702#define pmd_page(pmd) \
Kumar Galaaf892e02008-04-16 05:52:30 +1000703 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
David Gibsonf88df142007-04-30 16:30:56 +1000704#endif
705
706/* to find an entry in a kernel page-table-directory */
707#define pgd_offset_k(address) pgd_offset(&init_mm, address)
708
709/* to find an entry in a page-table-directory */
710#define pgd_index(address) ((address) >> PGDIR_SHIFT)
711#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
712
David Gibsonf88df142007-04-30 16:30:56 +1000713/* Find an entry in the third-level page table.. */
714#define pte_index(address) \
715 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
716#define pte_offset_kernel(dir, addr) \
717 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
718#define pte_offset_map(dir, addr) \
719 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
720#define pte_offset_map_nested(dir, addr) \
721 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
722
723#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
724#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
725
David Gibsonf88df142007-04-30 16:30:56 +1000726/*
727 * Encode and decode a swap entry.
728 * Note that the bits we use in a PTE for representing a swap entry
729 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
730 *_PAGE_HASHPTE bit (if used). -- paulus
731 */
732#define __swp_type(entry) ((entry).val & 0x1f)
733#define __swp_offset(entry) ((entry).val >> 5)
734#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
735#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
736#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
737
738/* Encode and decode a nonlinear file mapping entry */
739#define PTE_FILE_MAX_BITS 29
740#define pte_to_pgoff(pte) (pte_val(pte) >> 3)
741#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
742
David Gibsonf88df142007-04-30 16:30:56 +1000743/*
744 * No page table caches to initialise
745 */
746#define pgtable_cache_init() do { } while (0)
747
748extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
749 pmd_t **pmdp);
750
751#endif /* !__ASSEMBLY__ */
752
753#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */