blob: 1b1dd80897f75d09e13acbf2102f1c19c020dcc7 [file] [log] [blame]
Alexander Shishkine443b332012-05-11 17:25:46 +03001/*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
Peter Chen58ce8492014-05-23 08:12:47 +080026 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
Alexander Shishkine443b332012-05-11 17:25:46 +030027 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
Alexander Shishkine443b332012-05-11 17:25:46 +030045 * - Suspend & Remote Wakeup
46 */
47#include <linux/delay.h>
48#include <linux/device.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030049#include <linux/dma-mapping.h>
Antoine Tenart1e5e2d32014-10-30 18:41:19 +010050#include <linux/phy/phy.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030051#include <linux/platform_device.h>
52#include <linux/module.h>
Richard Zhaofe6e1252012-07-07 22:56:42 +080053#include <linux/idr.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030054#include <linux/interrupt.h>
55#include <linux/io.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030056#include <linux/kernel.h>
57#include <linux/slab.h>
58#include <linux/pm_runtime.h>
59#include <linux/usb/ch9.h>
60#include <linux/usb/gadget.h>
61#include <linux/usb/otg.h>
62#include <linux/usb/chipidea.h>
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +030063#include <linux/usb/of.h>
Michael Grzeschik4f6743d2014-02-19 13:41:43 +080064#include <linux/of.h>
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +030065#include <linux/phy.h>
Peter Chen1542d9c2013-08-14 12:44:03 +030066#include <linux/regulator/consumer.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030067
68#include "ci.h"
69#include "udc.h"
70#include "bits.h"
Alexander Shishkineb70e5a2012-05-11 17:25:54 +030071#include "host.h"
Alexander Shishkine443b332012-05-11 17:25:46 +030072#include "debug.h"
Peter Chenc10b4f02013-08-14 12:44:06 +030073#include "otg.h"
Li Jun4dcf7202014-04-23 15:56:50 +080074#include "otg_fsm.h"
Alexander Shishkine443b332012-05-11 17:25:46 +030075
Alexander Shishkin5f36e232012-05-11 17:25:47 +030076/* Controller register map */
Marc Kleine-Budde987e7bc2014-01-06 10:10:39 +080077static const u8 ci_regs_nolpm[] = {
78 [CAP_CAPLENGTH] = 0x00U,
79 [CAP_HCCPARAMS] = 0x08U,
80 [CAP_DCCPARAMS] = 0x24U,
81 [CAP_TESTMODE] = 0x38U,
82 [OP_USBCMD] = 0x00U,
83 [OP_USBSTS] = 0x04U,
84 [OP_USBINTR] = 0x08U,
85 [OP_DEVICEADDR] = 0x14U,
86 [OP_ENDPTLISTADDR] = 0x18U,
Peter Chen28362672015-06-18 11:51:53 +080087 [OP_TTCTRL] = 0x1CU,
Marc Kleine-Budde987e7bc2014-01-06 10:10:39 +080088 [OP_PORTSC] = 0x44U,
89 [OP_DEVLC] = 0x84U,
90 [OP_OTGSC] = 0x64U,
91 [OP_USBMODE] = 0x68U,
92 [OP_ENDPTSETUPSTAT] = 0x6CU,
93 [OP_ENDPTPRIME] = 0x70U,
94 [OP_ENDPTFLUSH] = 0x74U,
95 [OP_ENDPTSTAT] = 0x78U,
96 [OP_ENDPTCOMPLETE] = 0x7CU,
97 [OP_ENDPTCTRL] = 0x80U,
Alexander Shishkine443b332012-05-11 17:25:46 +030098};
99
Marc Kleine-Budde987e7bc2014-01-06 10:10:39 +0800100static const u8 ci_regs_lpm[] = {
101 [CAP_CAPLENGTH] = 0x00U,
102 [CAP_HCCPARAMS] = 0x08U,
103 [CAP_DCCPARAMS] = 0x24U,
104 [CAP_TESTMODE] = 0xFCU,
105 [OP_USBCMD] = 0x00U,
106 [OP_USBSTS] = 0x04U,
107 [OP_USBINTR] = 0x08U,
108 [OP_DEVICEADDR] = 0x14U,
109 [OP_ENDPTLISTADDR] = 0x18U,
Peter Chen28362672015-06-18 11:51:53 +0800110 [OP_TTCTRL] = 0x1CU,
Marc Kleine-Budde987e7bc2014-01-06 10:10:39 +0800111 [OP_PORTSC] = 0x44U,
112 [OP_DEVLC] = 0x84U,
113 [OP_OTGSC] = 0xC4U,
114 [OP_USBMODE] = 0xC8U,
115 [OP_ENDPTSETUPSTAT] = 0xD8U,
116 [OP_ENDPTPRIME] = 0xDCU,
117 [OP_ENDPTFLUSH] = 0xE0U,
118 [OP_ENDPTSTAT] = 0xE4U,
119 [OP_ENDPTCOMPLETE] = 0xE8U,
120 [OP_ENDPTCTRL] = 0xECU,
Alexander Shishkine443b332012-05-11 17:25:46 +0300121};
122
Alexander Shishkin8e229782013-06-24 14:46:36 +0300123static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
Alexander Shishkine443b332012-05-11 17:25:46 +0300124{
125 int i;
126
Alexander Shishkine443b332012-05-11 17:25:46 +0300127 for (i = 0; i < OP_ENDPTCTRL; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300128 ci->hw_bank.regmap[i] =
129 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
Alexander Shishkine443b332012-05-11 17:25:46 +0300130 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
131
132 for (; i <= OP_LAST; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300133 ci->hw_bank.regmap[i] = ci->hw_bank.op +
Alexander Shishkine443b332012-05-11 17:25:46 +0300134 4 * (i - OP_ENDPTCTRL) +
135 (is_lpm
136 ? ci_regs_lpm[OP_ENDPTCTRL]
137 : ci_regs_nolpm[OP_ENDPTCTRL]);
138
139 return 0;
140}
141
Peter Chencb271f32015-02-11 12:44:55 +0800142static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
143{
144 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
145 enum ci_revision rev = CI_REVISION_UNKNOWN;
146
147 if (ver == 0x2) {
148 rev = hw_read_id_reg(ci, ID_ID, REVISION)
149 >> __ffs(REVISION);
150 rev += CI_REVISION_20;
151 } else if (ver == 0x0) {
152 rev = CI_REVISION_1X;
153 }
154
155 return rev;
156}
157
Alexander Shishkine443b332012-05-11 17:25:46 +0300158/**
Li Jun36304b02014-04-23 15:56:39 +0800159 * hw_read_intr_enable: returns interrupt enable register
160 *
Peter Chen19353882014-09-22 08:14:17 +0800161 * @ci: the controller
162 *
Li Jun36304b02014-04-23 15:56:39 +0800163 * This function returns register data
164 */
165u32 hw_read_intr_enable(struct ci_hdrc *ci)
166{
167 return hw_read(ci, OP_USBINTR, ~0);
168}
169
170/**
171 * hw_read_intr_status: returns interrupt status register
172 *
Peter Chen19353882014-09-22 08:14:17 +0800173 * @ci: the controller
174 *
Li Jun36304b02014-04-23 15:56:39 +0800175 * This function returns register data
176 */
177u32 hw_read_intr_status(struct ci_hdrc *ci)
178{
179 return hw_read(ci, OP_USBSTS, ~0);
180}
181
182/**
Alexander Shishkine443b332012-05-11 17:25:46 +0300183 * hw_port_test_set: writes port test mode (execute without interruption)
184 * @mode: new value
185 *
186 * This function returns an error code
187 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300188int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
Alexander Shishkine443b332012-05-11 17:25:46 +0300189{
190 const u8 TEST_MODE_MAX = 7;
191
192 if (mode > TEST_MODE_MAX)
193 return -EINVAL;
194
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200195 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
Alexander Shishkine443b332012-05-11 17:25:46 +0300196 return 0;
197}
198
199/**
200 * hw_port_test_get: reads port test mode value
201 *
Peter Chen19353882014-09-22 08:14:17 +0800202 * @ci: the controller
203 *
Alexander Shishkine443b332012-05-11 17:25:46 +0300204 * This function returns port test mode value
205 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300206u8 hw_port_test_get(struct ci_hdrc *ci)
Alexander Shishkine443b332012-05-11 17:25:46 +0300207{
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200208 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
Alexander Shishkine443b332012-05-11 17:25:46 +0300209}
210
Peter Chenb82613c2014-11-26 13:44:28 +0800211static void hw_wait_phy_stable(void)
212{
213 /*
214 * The phy needs some delay to output the stable status from low
215 * power mode. And for OTGSC, the status inputs are debounced
216 * using a 1 ms time constant, so, delay 2ms for controller to get
217 * the stable status, like vbus and id when the phy leaves low power.
218 */
219 usleep_range(2000, 2500);
220}
221
Peter Chen864cf942013-09-24 12:47:55 +0800222/* The PHY enters/leaves low power mode */
223static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
224{
225 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
226 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
227
Peter Chen6d037db2014-11-26 13:44:27 +0800228 if (enable && !lpm)
Peter Chen864cf942013-09-24 12:47:55 +0800229 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
230 PORTSC_PHCD(ci->hw_bank.lpm));
Peter Chen6d037db2014-11-26 13:44:27 +0800231 else if (!enable && lpm)
Peter Chen864cf942013-09-24 12:47:55 +0800232 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
233 0);
Peter Chen864cf942013-09-24 12:47:55 +0800234}
235
Alexander Shishkin8e229782013-06-24 14:46:36 +0300236static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
Alexander Shishkine443b332012-05-11 17:25:46 +0300237{
238 u32 reg;
239
240 /* bank is a module variable */
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300241 ci->hw_bank.abs = base;
Alexander Shishkine443b332012-05-11 17:25:46 +0300242
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300243 ci->hw_bank.cap = ci->hw_bank.abs;
Richard Zhao77c44002012-06-29 17:48:53 +0800244 ci->hw_bank.cap += ci->platdata->capoffset;
Svetoslav Neykov938d3232013-03-30 12:54:03 +0200245 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
Alexander Shishkine443b332012-05-11 17:25:46 +0300246
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300247 hw_alloc_regmap(ci, false);
248 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200249 __ffs(HCCPARAMS_LEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300250 ci->hw_bank.lpm = reg;
Chris Ruehlaeb2c122013-12-06 16:35:12 +0800251 if (reg)
252 hw_alloc_regmap(ci, !!reg);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300253 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
254 ci->hw_bank.size += OP_LAST;
255 ci->hw_bank.size /= sizeof(u32);
Alexander Shishkine443b332012-05-11 17:25:46 +0300256
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300257 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200258 __ffs(DCCPARAMS_DEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300259 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
Alexander Shishkine443b332012-05-11 17:25:46 +0300260
Richard Zhao09c94e62012-05-15 21:58:18 +0800261 if (ci->hw_ep_max > ENDPT_MAX)
Alexander Shishkine443b332012-05-11 17:25:46 +0300262 return -ENODEV;
263
Peter Chen864cf942013-09-24 12:47:55 +0800264 ci_hdrc_enter_lpm(ci, false);
265
Peter Chenc344b512013-08-14 12:44:09 +0300266 /* Disable all interrupts bits */
267 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
268
269 /* Clear all interrupts status bits*/
270 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
271
Peter Chencb271f32015-02-11 12:44:55 +0800272 ci->rev = ci_get_revision(ci);
273
274 dev_dbg(ci->dev,
275 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
276 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
Alexander Shishkine443b332012-05-11 17:25:46 +0300277
278 /* setup lock mode ? */
279
280 /* ENDPTSETUPSTAT is '0' by default */
281
282 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
283
284 return 0;
285}
286
Alexander Shishkin8e229782013-06-24 14:46:36 +0300287static void hw_phymode_configure(struct ci_hdrc *ci)
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300288{
Chris Ruehl3b5d3e62014-01-10 13:51:29 +0800289 u32 portsc, lpm, sts = 0;
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300290
291 switch (ci->platdata->phy_mode) {
292 case USBPHY_INTERFACE_MODE_UTMI:
293 portsc = PORTSC_PTS(PTS_UTMI);
294 lpm = DEVLC_PTS(PTS_UTMI);
295 break;
296 case USBPHY_INTERFACE_MODE_UTMIW:
297 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
298 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
299 break;
300 case USBPHY_INTERFACE_MODE_ULPI:
301 portsc = PORTSC_PTS(PTS_ULPI);
302 lpm = DEVLC_PTS(PTS_ULPI);
303 break;
304 case USBPHY_INTERFACE_MODE_SERIAL:
305 portsc = PORTSC_PTS(PTS_SERIAL);
306 lpm = DEVLC_PTS(PTS_SERIAL);
307 sts = 1;
308 break;
309 case USBPHY_INTERFACE_MODE_HSIC:
310 portsc = PORTSC_PTS(PTS_HSIC);
311 lpm = DEVLC_PTS(PTS_HSIC);
312 break;
313 default:
314 return;
315 }
316
317 if (ci->hw_bank.lpm) {
318 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
Chris Ruehl3b5d3e62014-01-10 13:51:29 +0800319 if (sts)
320 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300321 } else {
322 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
Chris Ruehl3b5d3e62014-01-10 13:51:29 +0800323 if (sts)
324 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300325 }
326}
327
Alexander Shishkine443b332012-05-11 17:25:46 +0300328/**
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100329 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
330 * interfaces
331 * @ci: the controller
332 *
333 * This function returns an error code if the phy failed to init
334 */
335static int _ci_usb_phy_init(struct ci_hdrc *ci)
336{
337 int ret;
338
339 if (ci->phy) {
340 ret = phy_init(ci->phy);
341 if (ret)
342 return ret;
343
344 ret = phy_power_on(ci->phy);
345 if (ret) {
346 phy_exit(ci->phy);
347 return ret;
348 }
349 } else {
350 ret = usb_phy_init(ci->usb_phy);
351 }
352
353 return ret;
354}
355
356/**
357 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
358 * interfaces
359 * @ci: the controller
360 */
361static void ci_usb_phy_exit(struct ci_hdrc *ci)
362{
363 if (ci->phy) {
364 phy_power_off(ci->phy);
365 phy_exit(ci->phy);
366 } else {
367 usb_phy_shutdown(ci->usb_phy);
368 }
369}
370
371/**
Peter Chend03cccf2014-04-23 15:56:37 +0800372 * ci_usb_phy_init: initialize phy according to different phy type
373 * @ci: the controller
Peter Chen19353882014-09-22 08:14:17 +0800374 *
Peter Chend03cccf2014-04-23 15:56:37 +0800375 * This function returns an error code if usb_phy_init has failed
376 */
377static int ci_usb_phy_init(struct ci_hdrc *ci)
378{
379 int ret;
380
381 switch (ci->platdata->phy_mode) {
382 case USBPHY_INTERFACE_MODE_UTMI:
383 case USBPHY_INTERFACE_MODE_UTMIW:
384 case USBPHY_INTERFACE_MODE_HSIC:
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100385 ret = _ci_usb_phy_init(ci);
Peter Chenb82613c2014-11-26 13:44:28 +0800386 if (!ret)
387 hw_wait_phy_stable();
388 else
Peter Chend03cccf2014-04-23 15:56:37 +0800389 return ret;
390 hw_phymode_configure(ci);
391 break;
392 case USBPHY_INTERFACE_MODE_ULPI:
393 case USBPHY_INTERFACE_MODE_SERIAL:
394 hw_phymode_configure(ci);
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100395 ret = _ci_usb_phy_init(ci);
Peter Chend03cccf2014-04-23 15:56:37 +0800396 if (ret)
397 return ret;
398 break;
399 default:
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100400 ret = _ci_usb_phy_init(ci);
Peter Chenb82613c2014-11-26 13:44:28 +0800401 if (!ret)
402 hw_wait_phy_stable();
Peter Chend03cccf2014-04-23 15:56:37 +0800403 }
404
405 return ret;
406}
407
Peter Chenbf9c85e2015-03-17 10:40:50 +0800408
409/**
410 * ci_platform_configure: do controller configure
411 * @ci: the controller
412 *
413 */
414void ci_platform_configure(struct ci_hdrc *ci)
415{
416 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
417 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
418
419 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
420 if (ci->hw_bank.lpm)
421 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
422 else
423 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
424 }
425
426 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
427 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
428}
429
Peter Chend03cccf2014-04-23 15:56:37 +0800430/**
Peter Chencdd278f2014-11-26 13:44:32 +0800431 * hw_controller_reset: do controller reset
Alexander Shishkine443b332012-05-11 17:25:46 +0300432 * @ci: the controller
433 *
434 * This function returns an error code
435 */
Peter Chencdd278f2014-11-26 13:44:32 +0800436static int hw_controller_reset(struct ci_hdrc *ci)
437{
438 int count = 0;
439
440 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
441 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
442 udelay(10);
443 if (count++ > 1000)
444 return -ETIMEDOUT;
445 }
446
447 return 0;
448}
449
450/**
451 * hw_device_reset: resets chip (execute without interruption)
452 * @ci: the controller
453 *
454 * This function returns an error code
455 */
Peter Chen5b157302014-11-26 13:44:33 +0800456int hw_device_reset(struct ci_hdrc *ci)
Alexander Shishkine443b332012-05-11 17:25:46 +0300457{
Peter Chencdd278f2014-11-26 13:44:32 +0800458 int ret;
459
Alexander Shishkine443b332012-05-11 17:25:46 +0300460 /* should flush & stop before reset */
461 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
462 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
463
Peter Chencdd278f2014-11-26 13:44:32 +0800464 ret = hw_controller_reset(ci);
465 if (ret) {
466 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
467 return ret;
468 }
Alexander Shishkine443b332012-05-11 17:25:46 +0300469
Richard Zhao77c44002012-06-29 17:48:53 +0800470 if (ci->platdata->notify_event)
471 ci->platdata->notify_event(ci,
Alexander Shishkin8e229782013-06-24 14:46:36 +0300472 CI_HDRC_CONTROLLER_RESET_EVENT);
Alexander Shishkine443b332012-05-11 17:25:46 +0300473
Alexander Shishkine443b332012-05-11 17:25:46 +0300474 /* USBMODE should be configured step by step */
475 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
Peter Chen5b157302014-11-26 13:44:33 +0800476 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
Alexander Shishkine443b332012-05-11 17:25:46 +0300477 /* HW >= 2.3 */
478 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
479
Peter Chen5b157302014-11-26 13:44:33 +0800480 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
481 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
Alexander Shishkine443b332012-05-11 17:25:46 +0300482 pr_err("lpm = %i", ci->hw_bank.lpm);
483 return -ENODEV;
484 }
485
Peter Chenbf9c85e2015-03-17 10:40:50 +0800486 ci_platform_configure(ci);
487
Alexander Shishkine443b332012-05-11 17:25:46 +0300488 return 0;
489}
490
Peter Chen22fa8442013-08-14 12:44:12 +0300491/**
492 * hw_wait_reg: wait the register value
493 *
494 * Sometimes, it needs to wait register value before going on.
495 * Eg, when switch to device mode, the vbus value should be lower
496 * than OTGSC_BSV before connects to host.
497 *
498 * @ci: the controller
499 * @reg: register index
500 * @mask: mast bit
501 * @value: the bit value to wait
502 * @timeout_ms: timeout in millisecond
503 *
504 * This function returns an error code if timeout
505 */
506int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
507 u32 value, unsigned int timeout_ms)
508{
509 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
510
511 while (hw_read(ci, reg, mask) != value) {
512 if (time_after(jiffies, elapse)) {
513 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
514 mask, reg);
515 return -ETIMEDOUT;
516 }
517 msleep(20);
518 }
519
520 return 0;
521}
522
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300523static irqreturn_t ci_irq(int irq, void *data)
524{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300525 struct ci_hdrc *ci = data;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300526 irqreturn_t ret = IRQ_NONE;
Richard Zhaob183c192012-09-12 14:58:11 +0300527 u32 otgsc = 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300528
Peter Chen1f874ed2015-02-11 12:44:45 +0800529 if (ci->in_lpm) {
530 disable_irq_nosync(irq);
531 ci->wakeup_int = true;
532 pm_runtime_get(ci->dev);
533 return IRQ_HANDLED;
534 }
535
Li Jun4dcf7202014-04-23 15:56:50 +0800536 if (ci->is_otg) {
Li Jun0c33bf72014-04-23 15:56:38 +0800537 otgsc = hw_read_otgsc(ci, ~0);
Li Jun4dcf7202014-04-23 15:56:50 +0800538 if (ci_otg_is_fsm_mode(ci)) {
539 ret = ci_otg_fsm_irq(ci);
540 if (ret == IRQ_HANDLED)
541 return ret;
542 }
543 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300544
Peter Chena107f8c2013-08-14 12:44:11 +0300545 /*
546 * Handle id change interrupt, it indicates device/host function
547 * switch.
548 */
549 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
550 ci->id_event = true;
Li Jun0c33bf72014-04-23 15:56:38 +0800551 /* Clear ID change irq status */
552 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
Peter Chenbe6b0c12014-05-23 08:12:49 +0800553 ci_otg_queue_work(ci);
Peter Chena107f8c2013-08-14 12:44:11 +0300554 return IRQ_HANDLED;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300555 }
556
Peter Chena107f8c2013-08-14 12:44:11 +0300557 /*
558 * Handle vbus change interrupt, it indicates device connection
559 * and disconnection events.
560 */
561 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
562 ci->b_sess_valid_event = true;
Li Jun0c33bf72014-04-23 15:56:38 +0800563 /* Clear BSV irq */
564 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
Peter Chenbe6b0c12014-05-23 08:12:49 +0800565 ci_otg_queue_work(ci);
Peter Chena107f8c2013-08-14 12:44:11 +0300566 return IRQ_HANDLED;
567 }
568
569 /* Handle device/host interrupt */
570 if (ci->role != CI_ROLE_END)
571 ret = ci_role(ci)->irq(ci);
572
Richard Zhaob183c192012-09-12 14:58:11 +0300573 return ret;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300574}
575
Peter Chen1542d9c2013-08-14 12:44:03 +0300576static int ci_get_platdata(struct device *dev,
577 struct ci_hdrc_platform_data *platdata)
578{
Peter Chenc22600c2013-09-17 12:37:22 +0800579 if (!platdata->phy_mode)
580 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
581
582 if (!platdata->dr_mode)
583 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
584
585 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
586 platdata->dr_mode = USB_DR_MODE_OTG;
587
Peter Chenc2ec3a72013-10-30 09:19:29 +0800588 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
589 /* Get the vbus regulator */
590 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
591 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
592 return -EPROBE_DEFER;
593 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
Mickael Maison66294672014-11-26 13:44:38 +0800594 /* no vbus regulator is needed */
Peter Chenc2ec3a72013-10-30 09:19:29 +0800595 platdata->reg_vbus = NULL;
596 } else if (IS_ERR(platdata->reg_vbus)) {
597 dev_err(dev, "Getting regulator error: %ld\n",
598 PTR_ERR(platdata->reg_vbus));
599 return PTR_ERR(platdata->reg_vbus);
600 }
Peter Chenf6a9ff02014-08-19 09:51:56 +0800601 /* Get TPL support */
602 if (!platdata->tpl_support)
603 platdata->tpl_support =
604 of_usb_host_tpl_support(dev->of_node);
Peter Chenc2ec3a72013-10-30 09:19:29 +0800605 }
606
Michael Grzeschik4f6743d2014-02-19 13:41:43 +0800607 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
608 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
609
Peter Chen1542d9c2013-08-14 12:44:03 +0300610 return 0;
611}
612
Richard Zhaofe6e1252012-07-07 22:56:42 +0800613static DEFINE_IDA(ci_ida);
614
Alexander Shishkin8e229782013-06-24 14:46:36 +0300615struct platform_device *ci_hdrc_add_device(struct device *dev,
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800616 struct resource *res, int nres,
Alexander Shishkin8e229782013-06-24 14:46:36 +0300617 struct ci_hdrc_platform_data *platdata)
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800618{
619 struct platform_device *pdev;
Richard Zhaofe6e1252012-07-07 22:56:42 +0800620 int id, ret;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800621
Peter Chen1542d9c2013-08-14 12:44:03 +0300622 ret = ci_get_platdata(dev, platdata);
623 if (ret)
624 return ERR_PTR(ret);
625
Richard Zhaofe6e1252012-07-07 22:56:42 +0800626 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
627 if (id < 0)
628 return ERR_PTR(id);
629
630 pdev = platform_device_alloc("ci_hdrc", id);
631 if (!pdev) {
632 ret = -ENOMEM;
633 goto put_id;
634 }
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800635
636 pdev->dev.parent = dev;
637 pdev->dev.dma_mask = dev->dma_mask;
638 pdev->dev.dma_parms = dev->dma_parms;
639 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
640
641 ret = platform_device_add_resources(pdev, res, nres);
642 if (ret)
643 goto err;
644
645 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
646 if (ret)
647 goto err;
648
649 ret = platform_device_add(pdev);
650 if (ret)
651 goto err;
652
653 return pdev;
654
655err:
656 platform_device_put(pdev);
Richard Zhaofe6e1252012-07-07 22:56:42 +0800657put_id:
658 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800659 return ERR_PTR(ret);
660}
Alexander Shishkin8e229782013-06-24 14:46:36 +0300661EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800662
Alexander Shishkin8e229782013-06-24 14:46:36 +0300663void ci_hdrc_remove_device(struct platform_device *pdev)
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800664{
Lothar Waßmann98c35532012-11-22 10:11:25 +0100665 int id = pdev->id;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800666 platform_device_unregister(pdev);
Lothar Waßmann98c35532012-11-22 10:11:25 +0100667 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800668}
Alexander Shishkin8e229782013-06-24 14:46:36 +0300669EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800670
Peter Chen3f124d22013-08-14 12:44:07 +0300671static inline void ci_role_destroy(struct ci_hdrc *ci)
672{
673 ci_hdrc_gadget_destroy(ci);
674 ci_hdrc_host_destroy(ci);
Peter Chencbec6bd2013-08-14 12:44:10 +0300675 if (ci->is_otg)
676 ci_hdrc_otg_destroy(ci);
Peter Chen3f124d22013-08-14 12:44:07 +0300677}
678
Peter Chen577b2322013-08-14 12:44:08 +0300679static void ci_get_otg_capable(struct ci_hdrc *ci)
680{
681 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
682 ci->is_otg = false;
683 else
684 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
685 DCCPARAMS_DC | DCCPARAMS_HC)
686 == (DCCPARAMS_DC | DCCPARAMS_HC));
Peter Chen2e37cfd2015-02-11 12:44:51 +0800687 if (ci->is_otg) {
Peter Chen577b2322013-08-14 12:44:08 +0300688 dev_dbg(ci->dev, "It is OTG capable controller\n");
Peter Chen2e37cfd2015-02-11 12:44:51 +0800689 /* Disable and clear all OTG irq */
690 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
691 OTGSC_INT_STATUS_BITS);
692 }
Peter Chen577b2322013-08-14 12:44:08 +0300693}
694
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500695static int ci_hdrc_probe(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300696{
697 struct device *dev = &pdev->dev;
Alexander Shishkin8e229782013-06-24 14:46:36 +0300698 struct ci_hdrc *ci;
Alexander Shishkine443b332012-05-11 17:25:46 +0300699 struct resource *res;
700 void __iomem *base;
701 int ret;
Sascha Hauer691962d2013-06-13 17:59:57 +0300702 enum usb_dr_mode dr_mode;
Alexander Shishkine443b332012-05-11 17:25:46 +0300703
Jingoo Hanfad56742014-02-19 13:41:42 +0800704 if (!dev_get_platdata(dev)) {
Alexander Shishkine443b332012-05-11 17:25:46 +0300705 dev_err(dev, "platform data missing\n");
706 return -ENODEV;
707 }
708
709 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Felipe Balbi19290812013-03-30 02:46:27 +0200710 base = devm_ioremap_resource(dev, res);
711 if (IS_ERR(base))
712 return PTR_ERR(base);
Alexander Shishkine443b332012-05-11 17:25:46 +0300713
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300714 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
Fabio Estevamd0f99242014-11-26 13:44:23 +0800715 if (!ci)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300716 return -ENOMEM;
Alexander Shishkine443b332012-05-11 17:25:46 +0300717
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300718 ci->dev = dev;
Jingoo Hanfad56742014-02-19 13:41:42 +0800719 ci->platdata = dev_get_platdata(dev);
Peter Chened8f8312014-01-10 13:51:27 +0800720 ci->imx28_write_fix = !!(ci->platdata->flags &
721 CI_HDRC_IMX28_WRITE_FIX);
Peter Chen1f874ed2015-02-11 12:44:45 +0800722 ci->supports_runtime_pm = !!(ci->platdata->flags &
723 CI_HDRC_SUPPORTS_RUNTIME_PM);
Alexander Shishkine443b332012-05-11 17:25:46 +0300724
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300725 ret = hw_device_init(ci, base);
726 if (ret < 0) {
727 dev_err(dev, "can't initialize hardware\n");
728 return -ENODEV;
729 }
730
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100731 if (ci->platdata->phy) {
732 ci->phy = ci->platdata->phy;
733 } else if (ci->platdata->usb_phy) {
Antoine Tenartef44cb42014-10-30 18:41:16 +0100734 ci->usb_phy = ci->platdata->usb_phy;
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100735 } else {
Antoine Tenart21a5b572014-11-26 13:44:35 +0800736 ci->phy = devm_phy_get(dev->parent, "usb-phy");
737 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
Peter Chenc859aa652014-02-19 13:41:40 +0800738
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100739 /* if both generic PHY and USB PHY layers aren't enabled */
740 if (PTR_ERR(ci->phy) == -ENOSYS &&
741 PTR_ERR(ci->usb_phy) == -ENXIO)
742 return -ENXIO;
Peter Chenc859aa652014-02-19 13:41:40 +0800743
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100744 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
745 return -EPROBE_DEFER;
746
747 if (IS_ERR(ci->phy))
748 ci->phy = NULL;
749 else if (IS_ERR(ci->usb_phy))
750 ci->usb_phy = NULL;
Peter Chenc859aa652014-02-19 13:41:40 +0800751 }
752
Peter Chend03cccf2014-04-23 15:56:37 +0800753 ret = ci_usb_phy_init(ci);
Peter Chen74475ed2013-09-24 12:47:53 +0800754 if (ret) {
755 dev_err(dev, "unable to init phy: %d\n", ret);
756 return ret;
757 }
758
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300759 ci->hw_bank.phys = res->start;
760
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300761 ci->irq = platform_get_irq(pdev, 0);
762 if (ci->irq < 0) {
763 dev_err(dev, "missing IRQ\n");
Fabio Estevam42d18212014-02-19 13:41:44 +0800764 ret = ci->irq;
Peter Chenc859aa652014-02-19 13:41:40 +0800765 goto deinit_phy;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300766 }
767
Peter Chen577b2322013-08-14 12:44:08 +0300768 ci_get_otg_capable(ci);
769
Sascha Hauer691962d2013-06-13 17:59:57 +0300770 dr_mode = ci->platdata->dr_mode;
771 /* initialize role(s) before the interrupt is requested */
772 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
773 ret = ci_hdrc_host_init(ci);
774 if (ret)
775 dev_info(dev, "doesn't support host\n");
776 }
777
778 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
779 ret = ci_hdrc_gadget_init(ci);
780 if (ret)
781 dev_info(dev, "doesn't support gadget\n");
782 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300783
784 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
785 dev_err(dev, "no supported roles\n");
Peter Chen74475ed2013-09-24 12:47:53 +0800786 ret = -ENODEV;
Peter Chenc859aa652014-02-19 13:41:40 +0800787 goto deinit_phy;
Peter Chencbec6bd2013-08-14 12:44:10 +0300788 }
789
Peter Chen27c62c22014-09-22 08:14:16 +0800790 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
Peter Chencbec6bd2013-08-14 12:44:10 +0300791 ret = ci_hdrc_otg_init(ci);
792 if (ret) {
793 dev_err(dev, "init otg fails, ret = %d\n", ret);
794 goto stop;
795 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300796 }
797
798 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
Peter Chen577b2322013-08-14 12:44:08 +0300799 if (ci->is_otg) {
Peter Chen577b2322013-08-14 12:44:08 +0300800 ci->role = ci_otg_role(ci);
Li Jun0c33bf72014-04-23 15:56:38 +0800801 /* Enable ID change irq */
802 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
Peter Chen577b2322013-08-14 12:44:08 +0300803 } else {
804 /*
805 * If the controller is not OTG capable, but support
806 * role switch, the defalt role is gadget, and the
807 * user can switch it through debugfs.
808 */
809 ci->role = CI_ROLE_GADGET;
810 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300811 } else {
812 ci->role = ci->roles[CI_ROLE_HOST]
813 ? CI_ROLE_HOST
814 : CI_ROLE_GADGET;
815 }
816
Li Jun4dcf7202014-04-23 15:56:50 +0800817 if (!ci_otg_is_fsm_mode(ci)) {
Li Jun961ea492015-02-11 12:45:03 +0800818 /* only update vbus status for peripheral */
819 if (ci->role == CI_ROLE_GADGET)
820 ci_handle_vbus_change(ci);
821
Li Jun4dcf7202014-04-23 15:56:50 +0800822 ret = ci_role_start(ci, ci->role);
823 if (ret) {
824 dev_err(dev, "can't start %s role\n",
825 ci_role(ci)->name);
826 goto stop;
827 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300828 }
829
Peter Chen24c498d2014-12-24 11:33:17 +0800830 platform_set_drvdata(pdev, ci);
Peter Chen4c503dd2014-11-26 13:44:22 +0800831 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
832 ci->platdata->name, ci);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300833 if (ret)
834 goto stop;
835
Peter Chen1f874ed2015-02-11 12:44:45 +0800836 if (ci->supports_runtime_pm) {
837 pm_runtime_set_active(&pdev->dev);
838 pm_runtime_enable(&pdev->dev);
839 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
840 pm_runtime_mark_last_busy(ci->dev);
841 pm_runtime_use_autosuspend(&pdev->dev);
842 }
843
Li Jun4dcf7202014-04-23 15:56:50 +0800844 if (ci_otg_is_fsm_mode(ci))
845 ci_hdrc_otg_fsm_start(ci);
846
Peter Chenf8efa762015-02-11 12:44:48 +0800847 device_set_wakeup_capable(&pdev->dev, true);
848
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200849 ret = dbg_create_files(ci);
850 if (!ret)
851 return 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300852
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300853stop:
Peter Chen3f124d22013-08-14 12:44:07 +0300854 ci_role_destroy(ci);
Peter Chenc859aa652014-02-19 13:41:40 +0800855deinit_phy:
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100856 ci_usb_phy_exit(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300857
858 return ret;
859}
860
Bill Pembertonfb4e98a2012-11-19 13:26:20 -0500861static int ci_hdrc_remove(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300862{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300863 struct ci_hdrc *ci = platform_get_drvdata(pdev);
Alexander Shishkine443b332012-05-11 17:25:46 +0300864
Peter Chen1f874ed2015-02-11 12:44:45 +0800865 if (ci->supports_runtime_pm) {
866 pm_runtime_get_sync(&pdev->dev);
867 pm_runtime_disable(&pdev->dev);
868 pm_runtime_put_noidle(&pdev->dev);
869 }
870
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200871 dbg_remove_files(ci);
Peter Chen3f124d22013-08-14 12:44:07 +0300872 ci_role_destroy(ci);
Peter Chen864cf942013-09-24 12:47:55 +0800873 ci_hdrc_enter_lpm(ci, true);
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100874 ci_usb_phy_exit(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300875
876 return 0;
877}
878
Peter Chen1f874ed2015-02-11 12:44:45 +0800879#ifdef CONFIG_PM
Li Jun961ea492015-02-11 12:45:03 +0800880/* Prepare wakeup by SRP before suspend */
881static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
882{
883 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
884 !hw_read_otgsc(ci, OTGSC_ID)) {
885 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
886 PORTSC_PP);
887 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
888 PORTSC_WKCN);
889 }
890}
891
892/* Handle SRP when wakeup by data pulse */
893static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
894{
895 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
896 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
897 if (!hw_read_otgsc(ci, OTGSC_ID)) {
898 ci->fsm.a_srp_det = 1;
899 ci->fsm.a_bus_drop = 0;
900 } else {
901 ci->fsm.id = 1;
902 }
903 ci_otg_queue_work(ci);
904 }
905}
906
Peter Chen80769322014-11-26 13:44:29 +0800907static void ci_controller_suspend(struct ci_hdrc *ci)
908{
Peter Chen1f874ed2015-02-11 12:44:45 +0800909 disable_irq(ci->irq);
Peter Chen80769322014-11-26 13:44:29 +0800910 ci_hdrc_enter_lpm(ci, true);
Peter Chen1f874ed2015-02-11 12:44:45 +0800911 usb_phy_set_suspend(ci->usb_phy, 1);
912 ci->in_lpm = true;
913 enable_irq(ci->irq);
Peter Chen80769322014-11-26 13:44:29 +0800914}
915
916static int ci_controller_resume(struct device *dev)
917{
918 struct ci_hdrc *ci = dev_get_drvdata(dev);
919
920 dev_dbg(dev, "at %s\n", __func__);
921
Peter Chen1f874ed2015-02-11 12:44:45 +0800922 if (!ci->in_lpm) {
923 WARN_ON(1);
924 return 0;
925 }
Peter Chen80769322014-11-26 13:44:29 +0800926
Peter Chen1f874ed2015-02-11 12:44:45 +0800927 ci_hdrc_enter_lpm(ci, false);
Peter Chen80769322014-11-26 13:44:29 +0800928 if (ci->usb_phy) {
929 usb_phy_set_suspend(ci->usb_phy, 0);
930 usb_phy_set_wakeup(ci->usb_phy, false);
931 hw_wait_phy_stable();
932 }
933
Peter Chen1f874ed2015-02-11 12:44:45 +0800934 ci->in_lpm = false;
935 if (ci->wakeup_int) {
936 ci->wakeup_int = false;
937 pm_runtime_mark_last_busy(ci->dev);
938 pm_runtime_put_autosuspend(ci->dev);
939 enable_irq(ci->irq);
Li Jun961ea492015-02-11 12:45:03 +0800940 if (ci_otg_is_fsm_mode(ci))
941 ci_otg_fsm_wakeup_by_srp(ci);
Peter Chen1f874ed2015-02-11 12:44:45 +0800942 }
943
Peter Chen80769322014-11-26 13:44:29 +0800944 return 0;
945}
946
Peter Chen1f874ed2015-02-11 12:44:45 +0800947#ifdef CONFIG_PM_SLEEP
Peter Chen80769322014-11-26 13:44:29 +0800948static int ci_suspend(struct device *dev)
949{
950 struct ci_hdrc *ci = dev_get_drvdata(dev);
951
952 if (ci->wq)
953 flush_workqueue(ci->wq);
Peter Chen1f874ed2015-02-11 12:44:45 +0800954 /*
955 * Controller needs to be active during suspend, otherwise the core
956 * may run resume when the parent is at suspend if other driver's
957 * suspend fails, it occurs before parent's suspend has not started,
958 * but the core suspend has finished.
959 */
960 if (ci->in_lpm)
961 pm_runtime_resume(dev);
962
963 if (ci->in_lpm) {
964 WARN_ON(1);
965 return 0;
966 }
Peter Chen80769322014-11-26 13:44:29 +0800967
Peter Chenf8efa762015-02-11 12:44:48 +0800968 if (device_may_wakeup(dev)) {
Li Jun961ea492015-02-11 12:45:03 +0800969 if (ci_otg_is_fsm_mode(ci))
970 ci_otg_fsm_suspend_for_srp(ci);
971
Peter Chenf8efa762015-02-11 12:44:48 +0800972 usb_phy_set_wakeup(ci->usb_phy, true);
973 enable_irq_wake(ci->irq);
974 }
975
Peter Chen80769322014-11-26 13:44:29 +0800976 ci_controller_suspend(ci);
977
978 return 0;
979}
980
981static int ci_resume(struct device *dev)
982{
Peter Chen1f874ed2015-02-11 12:44:45 +0800983 struct ci_hdrc *ci = dev_get_drvdata(dev);
984 int ret;
985
Peter Chenf8efa762015-02-11 12:44:48 +0800986 if (device_may_wakeup(dev))
987 disable_irq_wake(ci->irq);
988
Peter Chen1f874ed2015-02-11 12:44:45 +0800989 ret = ci_controller_resume(dev);
990 if (ret)
991 return ret;
992
993 if (ci->supports_runtime_pm) {
994 pm_runtime_disable(dev);
995 pm_runtime_set_active(dev);
996 pm_runtime_enable(dev);
997 }
998
999 return ret;
Peter Chen80769322014-11-26 13:44:29 +08001000}
1001#endif /* CONFIG_PM_SLEEP */
1002
Peter Chen1f874ed2015-02-11 12:44:45 +08001003static int ci_runtime_suspend(struct device *dev)
1004{
1005 struct ci_hdrc *ci = dev_get_drvdata(dev);
1006
1007 dev_dbg(dev, "at %s\n", __func__);
1008
1009 if (ci->in_lpm) {
1010 WARN_ON(1);
1011 return 0;
1012 }
1013
Li Jun961ea492015-02-11 12:45:03 +08001014 if (ci_otg_is_fsm_mode(ci))
1015 ci_otg_fsm_suspend_for_srp(ci);
1016
Peter Chen1f874ed2015-02-11 12:44:45 +08001017 usb_phy_set_wakeup(ci->usb_phy, true);
1018 ci_controller_suspend(ci);
1019
1020 return 0;
1021}
1022
1023static int ci_runtime_resume(struct device *dev)
1024{
1025 return ci_controller_resume(dev);
1026}
1027
1028#endif /* CONFIG_PM */
Peter Chen80769322014-11-26 13:44:29 +08001029static const struct dev_pm_ops ci_pm_ops = {
1030 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
Peter Chen1f874ed2015-02-11 12:44:45 +08001031 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
Peter Chen80769322014-11-26 13:44:29 +08001032};
Peter Chen1f874ed2015-02-11 12:44:45 +08001033
Alexander Shishkin5f36e232012-05-11 17:25:47 +03001034static struct platform_driver ci_hdrc_driver = {
1035 .probe = ci_hdrc_probe,
Bill Pemberton76904172012-11-19 13:21:08 -05001036 .remove = ci_hdrc_remove,
Alexander Shishkine443b332012-05-11 17:25:46 +03001037 .driver = {
Alexander Shishkin5f36e232012-05-11 17:25:47 +03001038 .name = "ci_hdrc",
Peter Chen80769322014-11-26 13:44:29 +08001039 .pm = &ci_pm_ops,
Alexander Shishkine443b332012-05-11 17:25:46 +03001040 },
1041};
1042
Peter Chen2f01a332015-07-21 09:51:29 +08001043static int __init ci_hdrc_platform_register(void)
1044{
1045 ci_hdrc_host_driver_init();
1046 return platform_driver_register(&ci_hdrc_driver);
1047}
1048module_init(ci_hdrc_platform_register);
1049
1050static void __exit ci_hdrc_platform_unregister(void)
1051{
1052 platform_driver_unregister(&ci_hdrc_driver);
1053}
1054module_exit(ci_hdrc_platform_unregister);
Alexander Shishkine443b332012-05-11 17:25:46 +03001055
Alexander Shishkin5f36e232012-05-11 17:25:47 +03001056MODULE_ALIAS("platform:ci_hdrc");
Alexander Shishkine443b332012-05-11 17:25:46 +03001057MODULE_LICENSE("GPL v2");
1058MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
Alexander Shishkin5f36e232012-05-11 17:25:47 +03001059MODULE_DESCRIPTION("ChipIdea HDRC Driver");