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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/mtd/nandids.c
3 *
4 * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
Thomas Gleixnerbd7bcf52005-06-23 10:38:54 +01005 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/module.h>
12#include <linux/mtd/nand.h>
13/*
14* Chip ID list
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000015*
Linus Torvalds1da177e2005-04-16 15:20:36 -070016* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
17* options
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000018*
Thomas Gleixner7a306012006-05-25 09:50:16 +020019* Pagesize; 0, 256, 512
20* 0 get this information from the extended chip ID
Linus Torvalds1da177e2005-04-16 15:20:36 -070021+ 256 256 Byte page size
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000022* 512 512 Byte page size
Linus Torvalds1da177e2005-04-16 15:20:36 -070023*/
24struct nand_flash_dev nand_flash_ids[] = {
Thomas Gleixner1cf98272007-04-17 18:30:57 +010025
26#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
Thomas Gleixner7a306012006-05-25 09:50:16 +020027 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
28 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
29 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
30 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
31 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
32 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
33 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
34 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
35 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
36 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000037
Thomas Gleixner7a306012006-05-25 09:50:16 +020038 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
39 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
40 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
41 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
Thomas Gleixner1cf98272007-04-17 18:30:57 +010042#endif
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000043
Thomas Gleixner7a306012006-05-25 09:50:16 +020044 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
45 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
46 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
47 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000048
Thomas Gleixner7a306012006-05-25 09:50:16 +020049 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
50 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
51 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
52 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000053
Thomas Gleixner7a306012006-05-25 09:50:16 +020054 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
55 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
56 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
57 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000058
Thomas Gleixner7a306012006-05-25 09:50:16 +020059 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
60 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
61 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
62 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
63 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
64 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
65 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000066
Thomas Gleixner7a306012006-05-25 09:50:16 +020067 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
Thomas Gleixner7a306012006-05-25 09:50:16 +020069 /*
70 * These are the new chips with large page size. The pagesize and the
71 * erasesize is determined from the extended id bytes
72 */
73#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
74#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
75
Brian Norrisc01804e2011-11-02 13:34:43 -070076 /* 512 Megabit */
Thomas Gleixner7a306012006-05-25 09:50:16 +020077 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
Brian Norris13ed7ae2010-08-20 12:36:12 -070078 {"NAND 64MiB 1,8V 8-bit", 0xA0, 0, 64, 0, LP_OPTIONS},
Thomas Gleixner7a306012006-05-25 09:50:16 +020079 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
Brian Norris13ed7ae2010-08-20 12:36:12 -070080 {"NAND 64MiB 3,3V 8-bit", 0xD0, 0, 64, 0, LP_OPTIONS},
Brian Norrisc01804e2011-11-02 13:34:43 -070081 {"NAND 64MiB 3,3V 8-bit", 0xF0, 0, 64, 0, LP_OPTIONS},
Thomas Gleixner7a306012006-05-25 09:50:16 +020082 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
Brian Norris13ed7ae2010-08-20 12:36:12 -070083 {"NAND 64MiB 1,8V 16-bit", 0xB0, 0, 64, 0, LP_OPTIONS16},
Thomas Gleixner7a306012006-05-25 09:50:16 +020084 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
Brian Norris13ed7ae2010-08-20 12:36:12 -070085 {"NAND 64MiB 3,3V 16-bit", 0xC0, 0, 64, 0, LP_OPTIONS16},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000086
Linus Torvalds1da177e2005-04-16 15:20:36 -070087 /* 1 Gigabit */
Thomas Gleixner7a306012006-05-25 09:50:16 +020088 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
89 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
Florian Fainellif6b173c2010-05-07 19:09:13 +020090 {"NAND 128MiB 3,3V 8-bit", 0xD1, 0, 128, 0, LP_OPTIONS},
Thomas Gleixner7a306012006-05-25 09:50:16 +020091 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
92 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
Brian Norris24cc7b82010-06-17 12:35:11 -070093 {"NAND 128MiB 1,8V 16-bit", 0xAD, 0, 128, 0, LP_OPTIONS16},
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
95 /* 2 Gigabit */
Thomas Gleixner7a306012006-05-25 09:50:16 +020096 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
97 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
98 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
99 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 /* 4 Gigabit */
Thomas Gleixner7a306012006-05-25 09:50:16 +0200102 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
103 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
104 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
105 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000106
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 /* 8 Gigabit */
Thomas Gleixner7a306012006-05-25 09:50:16 +0200108 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
109 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
110 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
111 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112
113 /* 16 Gigabit */
Thomas Gleixner7a306012006-05-25 09:50:16 +0200114 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
115 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
116 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
117 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
Brian Norris24cc7b82010-06-17 12:35:11 -0700119 /* 32 Gigabit */
Brian Norris13ed7ae2010-08-20 12:36:12 -0700120 {"NAND 4GiB 1,8V 8-bit", 0xA7, 0, 4096, 0, LP_OPTIONS},
Brian Norris84c4f462010-08-13 10:29:14 -0700121 {"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 4096, 0, LP_OPTIONS},
Brian Norris13ed7ae2010-08-20 12:36:12 -0700122 {"NAND 4GiB 1,8V 16-bit", 0xB7, 0, 4096, 0, LP_OPTIONS16},
123 {"NAND 4GiB 3,3V 16-bit", 0xC7, 0, 4096, 0, LP_OPTIONS16},
124
125 /* 64 Gigabit */
126 {"NAND 8GiB 1,8V 8-bit", 0xAE, 0, 8192, 0, LP_OPTIONS},
127 {"NAND 8GiB 3,3V 8-bit", 0xDE, 0, 8192, 0, LP_OPTIONS},
128 {"NAND 8GiB 1,8V 16-bit", 0xBE, 0, 8192, 0, LP_OPTIONS16},
129 {"NAND 8GiB 3,3V 16-bit", 0xCE, 0, 8192, 0, LP_OPTIONS16},
130
131 /* 128 Gigabit */
132 {"NAND 16GiB 1,8V 8-bit", 0x1A, 0, 16384, 0, LP_OPTIONS},
133 {"NAND 16GiB 3,3V 8-bit", 0x3A, 0, 16384, 0, LP_OPTIONS},
134 {"NAND 16GiB 1,8V 16-bit", 0x2A, 0, 16384, 0, LP_OPTIONS16},
135 {"NAND 16GiB 3,3V 16-bit", 0x4A, 0, 16384, 0, LP_OPTIONS16},
136
137 /* 256 Gigabit */
138 {"NAND 32GiB 1,8V 8-bit", 0x1C, 0, 32768, 0, LP_OPTIONS},
139 {"NAND 32GiB 3,3V 8-bit", 0x3C, 0, 32768, 0, LP_OPTIONS},
140 {"NAND 32GiB 1,8V 16-bit", 0x2C, 0, 32768, 0, LP_OPTIONS16},
141 {"NAND 32GiB 3,3V 16-bit", 0x4C, 0, 32768, 0, LP_OPTIONS16},
142
143 /* 512 Gigabit */
144 {"NAND 64GiB 1,8V 8-bit", 0x1E, 0, 65536, 0, LP_OPTIONS},
145 {"NAND 64GiB 3,3V 8-bit", 0x3E, 0, 65536, 0, LP_OPTIONS},
146 {"NAND 64GiB 1,8V 16-bit", 0x2E, 0, 65536, 0, LP_OPTIONS16},
147 {"NAND 64GiB 3,3V 16-bit", 0x4E, 0, 65536, 0, LP_OPTIONS16},
Brian Norris24cc7b82010-06-17 12:35:11 -0700148
Thomas Gleixner7a306012006-05-25 09:50:16 +0200149 /*
150 * Renesas AND 1 Gigabit. Those chips do not support extended id and
151 * have a strange page/block layout ! The chosen minimum erasesize is
152 * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
153 * planes 1 block = 2 pages, but due to plane arrangement the blocks
154 * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
155 * increase the eraseblock size so we chose a combined one which can be
156 * erased in one go There are more speed improvements for reads and
157 * writes possible, but not implemented now
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158 */
Thomas Gleixner7a306012006-05-25 09:50:16 +0200159 {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000,
160 NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
161 BBT_AUTO_REFRESH
162 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163
164 {NULL,}
165};
166
167/*
168* Manufacturer ID list
169*/
170struct nand_manufacturers nand_manuf_ids[] = {
171 {NAND_MFR_TOSHIBA, "Toshiba"},
172 {NAND_MFR_SAMSUNG, "Samsung"},
173 {NAND_MFR_FUJITSU, "Fujitsu"},
174 {NAND_MFR_NATIONAL, "National"},
175 {NAND_MFR_RENESAS, "Renesas"},
176 {NAND_MFR_STMICRO, "ST Micro"},
David Woodhousee0c7d762006-05-13 18:07:53 +0100177 {NAND_MFR_HYNIX, "Hynix"},
sshahrom@micron.com8c60e542007-03-21 18:48:02 -0700178 {NAND_MFR_MICRON, "Micron"},
Steven J. Hill30eb0db2007-07-18 23:29:46 -0500179 {NAND_MFR_AMD, "AMD"},
Brian Norrisc1257b42011-11-02 13:34:42 -0700180 {NAND_MFR_MACRONIX, "Macronix"},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 {0x0, "Unknown"}
182};
183
David Woodhousee0c7d762006-05-13 18:07:53 +0100184EXPORT_SYMBOL(nand_manuf_ids);
185EXPORT_SYMBOL(nand_flash_ids);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
David Woodhousee0c7d762006-05-13 18:07:53 +0100187MODULE_LICENSE("GPL");
188MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
189MODULE_DESCRIPTION("Nand device & manufacturer IDs");