blob: ae387e5ee6f79435ecd206bfd237b499d7e50b51 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#include <linux/init.h>
2#include <linux/pci.h>
Robert Richterd199a042008-07-02 22:50:26 +02003#include <linux/topology.h>
Robert Richter91ede002008-08-22 20:23:38 +02004#include <linux/cpu.h>
Yinghai Lu27811d82010-02-10 01:20:07 -08005#include <linux/range.h>
6
Jan Beulich24d9b702011-01-10 16:20:23 +00007#include <asm/amd_nb.h>
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +05308#include <asm/pci_x86.h>
Robert Richter3a27dd12008-06-12 20:19:23 +02009
Yinghai Lu871d5f82008-02-19 03:20:09 -080010#include <asm/pci-direct.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011
Yinghai Lu99935a72009-10-04 21:54:24 -070012#include "bus_numa.h"
13
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050014#define AMD_NB_F0_NODE_ID 0x60
15#define AMD_NB_F0_UNIT_ID 0x64
16#define AMD_NB_F1_CONFIG_MAP_REG 0xe0
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050018#define RANGE_NUM 16
19#define AMD_NB_F1_CONFIG_MAP_RANGES 4
20
21struct amd_hostbridge {
Yinghai Lu30a18d62008-02-19 03:21:20 -080022 u32 bus;
23 u32 slot;
Yinghai Lu30a18d62008-02-19 03:21:20 -080024 u32 device;
25};
26
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050027/*
28 * IMPORTANT NOTE:
29 * hb_probes[] and early_root_info_init() is in maintenance mode.
30 * It only supports K8, Fam10h, Fam11h, and Fam15h_00h-0fh .
31 * Future processor will rely on information in ACPI.
32 */
33static struct amd_hostbridge hb_probes[] __initdata = {
34 { 0, 0x18, 0x1100 }, /* K8 */
35 { 0, 0x18, 0x1200 }, /* Family10h */
36 { 0xff, 0, 0x1200 }, /* Family10h */
37 { 0, 0x18, 0x1300 }, /* Family11h */
38 { 0, 0x18, 0x1600 }, /* Family15h */
Yinghai Lu30a18d62008-02-19 03:21:20 -080039};
40
Yinghai Lud28e5ac2012-04-02 18:31:54 -070041static struct pci_root_info __init *find_pci_root_info(int node, int link)
42{
43 struct pci_root_info *info;
44
45 /* find the position */
46 list_for_each_entry(info, &pci_root_infos, list)
47 if (info->node == node && info->link == link)
48 return info;
49
50 return NULL;
51}
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/**
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050054 * early_root_info_init()
Yinghai Lu871d5f82008-02-19 03:20:09 -080055 * called before pcibios_scan_root and pci_scan_bus
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050056 * fills the mp_bus_to_cpumask array based according
57 * to the LDT Bus Number Registers found in the northbridge.
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 */
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050059static int __init early_root_info_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070060{
Yinghai Lu30a18d62008-02-19 03:21:20 -080061 int i;
Yinghai Lu30a18d62008-02-19 03:21:20 -080062 unsigned bus;
Yinghai Lu871d5f82008-02-19 03:20:09 -080063 unsigned slot;
Yinghai Lu35ddd062008-02-19 03:15:08 -080064 int node;
Yinghai Lu30a18d62008-02-19 03:21:20 -080065 int link;
66 int def_node;
67 int def_link;
68 struct pci_root_info *info;
69 u32 reg;
Yinghai Lu97445c32010-02-10 01:20:10 -080070 u64 start;
71 u64 end;
Yinghai Lu27811d82010-02-10 01:20:07 -080072 struct range range[RANGE_NUM];
Yinghai Lu30a18d62008-02-19 03:21:20 -080073 u64 val;
74 u32 address;
Yinghai Lu3e3da002010-02-10 01:20:09 -080075 bool found;
Bjorn Helgaas24d25db2012-01-05 14:27:19 -070076 struct resource fam10h_mmconf_res, *fam10h_mmconf;
77 u64 fam10h_mmconf_start;
78 u64 fam10h_mmconf_end;
Yinghai Lu35ddd062008-02-19 03:15:08 -080079
Yinghai Lu871d5f82008-02-19 03:20:09 -080080 if (!early_pci_allowed())
81 return -1;
82
Yinghai Lu3e3da002010-02-10 01:20:09 -080083 found = false;
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050084 for (i = 0; i < ARRAY_SIZE(hb_probes); i++) {
Yinghai Lu30a18d62008-02-19 03:21:20 -080085 u32 id;
86 u16 device;
87 u16 vendor;
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050089 bus = hb_probes[i].bus;
90 slot = hb_probes[i].slot;
Yinghai Lu30a18d62008-02-19 03:21:20 -080091 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
Yinghai Lu30a18d62008-02-19 03:21:20 -080092 vendor = id & 0xffff;
93 device = (id>>16) & 0xffff;
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -050094
95 if (vendor != PCI_VENDOR_ID_AMD)
96 continue;
97
98 if (hb_probes[i].device == device) {
Yinghai Lu3e3da002010-02-10 01:20:09 -080099 found = true;
Yinghai Lu30a18d62008-02-19 03:21:20 -0800100 break;
101 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 }
103
Yinghai Lu3e3da002010-02-10 01:20:09 -0800104 if (!found)
Yinghai Lu30a18d62008-02-19 03:21:20 -0800105 return 0;
106
Suravee Suthikulpanit94d4bb52014-05-08 11:44:18 -0500107 /*
108 * We should learn topology and routing information from _PXM and
109 * _CRS methods in the ACPI namespace. We extract node numbers
110 * here to work around BIOSes that don't supply _PXM.
111 */
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -0500112 for (i = 0; i < AMD_NB_F1_CONFIG_MAP_RANGES; i++) {
Yinghai Lu30a18d62008-02-19 03:21:20 -0800113 int min_bus;
114 int max_bus;
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -0500115 reg = read_pci_config(bus, slot, 1,
116 AMD_NB_F1_CONFIG_MAP_REG + (i << 2));
Yinghai Lu30a18d62008-02-19 03:21:20 -0800117
118 /* Check if that register is enabled for bus range */
119 if ((reg & 7) != 3)
120 continue;
121
122 min_bus = (reg >> 16) & 0xff;
123 max_bus = (reg >> 24) & 0xff;
124 node = (reg >> 4) & 0x07;
Yinghai Lu30a18d62008-02-19 03:21:20 -0800125 link = (reg >> 8) & 0x03;
126
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700127 info = alloc_pci_root_info(min_bus, max_bus, node, link);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800128 }
129
Suravee Suthikulpanit94d4bb52014-05-08 11:44:18 -0500130 /*
131 * The following code extracts routing information for use on old
132 * systems where Linux doesn't automatically use host bridge _CRS
133 * methods (or when the user specifies "pci=nocrs").
134 *
135 * We only do this through Fam11h, because _CRS should be enough on
136 * newer systems.
137 */
138 if (boot_cpu_data.x86 > 0x11)
139 return 0;
140
Yinghai Lu30a18d62008-02-19 03:21:20 -0800141 /* get the default node and link for left over res */
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -0500142 reg = read_pci_config(bus, slot, 0, AMD_NB_F0_NODE_ID);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800143 def_node = (reg >> 8) & 0x07;
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -0500144 reg = read_pci_config(bus, slot, 0, AMD_NB_F0_UNIT_ID);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800145 def_link = (reg >> 8) & 0x03;
146
147 memset(range, 0, sizeof(range));
Yinghai Lue9a00642010-02-10 01:20:13 -0800148 add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800149 /* io port resource */
150 for (i = 0; i < 4; i++) {
151 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
152 if (!(reg & 3))
153 continue;
154
155 start = reg & 0xfff000;
156 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
157 node = reg & 0x07;
158 link = (reg >> 4) & 0x03;
159 end = (reg & 0xfff000) | 0xfff;
160
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700161 info = find_pci_root_info(node, link);
162 if (!info)
Yinghai Lu30a18d62008-02-19 03:21:20 -0800163 continue; /* not found */
164
Yinghai Lu6e184f22008-03-06 01:15:31 -0800165 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
Yinghai Lu97445c32010-02-10 01:20:10 -0800166 node, link, start, end);
Yinghai Lue8ee6f02008-04-13 01:41:58 -0700167
168 /* kernel only handle 16 bit only */
169 if (end > 0xffff)
170 end = 0xffff;
171 update_res(info, start, end, IORESOURCE_IO, 1);
Yinghai Lue9a00642010-02-10 01:20:13 -0800172 subtract_range(range, RANGE_NUM, start, end + 1);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800173 }
174 /* add left over io port range to def node/link, [0, 0xffff] */
175 /* find the position */
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700176 info = find_pci_root_info(def_node, def_link);
177 if (info) {
Yinghai Lu30a18d62008-02-19 03:21:20 -0800178 for (i = 0; i < RANGE_NUM; i++) {
179 if (!range[i].end)
180 continue;
181
Yinghai Lue9a00642010-02-10 01:20:13 -0800182 update_res(info, range[i].start, range[i].end - 1,
Yinghai Lu30a18d62008-02-19 03:21:20 -0800183 IORESOURCE_IO, 1);
184 }
185 }
186
187 memset(range, 0, sizeof(range));
188 /* 0xfd00000000-0xffffffffff for HT */
Yinghai Lue9a00642010-02-10 01:20:13 -0800189 end = cap_resource((0xfdULL<<32) - 1);
190 end++;
191 add_range(range, RANGE_NUM, 0, 0, end);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800192
193 /* need to take out [0, TOM) for RAM*/
194 address = MSR_K8_TOP_MEM1;
195 rdmsrl(address, val);
Yinghai Lu8004dd92008-05-12 17:40:39 -0700196 end = (val & 0xffffff800000ULL);
Yinghai Lu97445c32010-02-10 01:20:10 -0800197 printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800198 if (end < (1ULL<<32))
Yinghai Lue9a00642010-02-10 01:20:13 -0800199 subtract_range(range, RANGE_NUM, 0, end);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800200
Yinghai Lu6e184f22008-03-06 01:15:31 -0800201 /* get mmconfig */
Bjorn Helgaas24d25db2012-01-05 14:27:19 -0700202 fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
Yinghai Lu6e184f22008-03-06 01:15:31 -0800203 /* need to take out mmconf range */
Bjorn Helgaas24d25db2012-01-05 14:27:19 -0700204 if (fam10h_mmconf) {
205 printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
206 fam10h_mmconf_start = fam10h_mmconf->start;
207 fam10h_mmconf_end = fam10h_mmconf->end;
Yinghai Lue9a00642010-02-10 01:20:13 -0800208 subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
209 fam10h_mmconf_end + 1);
Bjorn Helgaas24d25db2012-01-05 14:27:19 -0700210 } else {
211 fam10h_mmconf_start = 0;
212 fam10h_mmconf_end = 0;
Yinghai Lu6e184f22008-03-06 01:15:31 -0800213 }
214
Yinghai Lu30a18d62008-02-19 03:21:20 -0800215 /* mmio resource */
216 for (i = 0; i < 8; i++) {
217 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
218 if (!(reg & 3))
219 continue;
220
221 start = reg & 0xffffff00; /* 39:16 on 31:8*/
222 start <<= 8;
223 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
224 node = reg & 0x07;
225 link = (reg >> 4) & 0x03;
226 end = (reg & 0xffffff00);
227 end <<= 8;
228 end |= 0xffff;
229
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700230 info = find_pci_root_info(node, link);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800231
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700232 if (!info)
233 continue;
Yinghai Lu6e184f22008-03-06 01:15:31 -0800234
235 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
Yinghai Lu97445c32010-02-10 01:20:10 -0800236 node, link, start, end);
Yinghai Lu6e184f22008-03-06 01:15:31 -0800237 /*
238 * some sick allocation would have range overlap with fam10h
239 * mmconf range, so need to update start and end.
240 */
241 if (fam10h_mmconf_end) {
242 int changed = 0;
243 u64 endx = 0;
244 if (start >= fam10h_mmconf_start &&
245 start <= fam10h_mmconf_end) {
246 start = fam10h_mmconf_end + 1;
247 changed = 1;
248 }
249
250 if (end >= fam10h_mmconf_start &&
251 end <= fam10h_mmconf_end) {
252 end = fam10h_mmconf_start - 1;
253 changed = 1;
254 }
255
256 if (start < fam10h_mmconf_start &&
257 end > fam10h_mmconf_end) {
258 /* we got a hole */
259 endx = fam10h_mmconf_start - 1;
260 update_res(info, start, endx, IORESOURCE_MEM, 0);
Yinghai Lue9a00642010-02-10 01:20:13 -0800261 subtract_range(range, RANGE_NUM, start,
262 endx + 1);
Yinghai Lu97445c32010-02-10 01:20:10 -0800263 printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
Yinghai Lu6e184f22008-03-06 01:15:31 -0800264 start = fam10h_mmconf_end + 1;
265 changed = 1;
266 }
267 if (changed) {
268 if (start <= end) {
Yinghai Lu97445c32010-02-10 01:20:10 -0800269 printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
Yinghai Lu6e184f22008-03-06 01:15:31 -0800270 } else {
271 printk(KERN_CONT "%s\n", endx?"":" ==> none");
272 continue;
273 }
274 }
275 }
276
Yinghai Lu9ad3f2c2010-02-10 01:20:11 -0800277 update_res(info, cap_resource(start), cap_resource(end),
278 IORESOURCE_MEM, 1);
Yinghai Lue9a00642010-02-10 01:20:13 -0800279 subtract_range(range, RANGE_NUM, start, end + 1);
Yinghai Lu6e184f22008-03-06 01:15:31 -0800280 printk(KERN_CONT "\n");
Yinghai Lu30a18d62008-02-19 03:21:20 -0800281 }
282
283 /* need to take out [4G, TOM2) for RAM*/
284 /* SYS_CFG */
285 address = MSR_K8_SYSCFG;
286 rdmsrl(address, val);
287 /* TOP_MEM2 is enabled? */
288 if (val & (1<<21)) {
289 /* TOP_MEM2 */
290 address = MSR_K8_TOP_MEM2;
291 rdmsrl(address, val);
Yinghai Lu8004dd92008-05-12 17:40:39 -0700292 end = (val & 0xffffff800000ULL);
Yinghai Lu97445c32010-02-10 01:20:10 -0800293 printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
Yinghai Lue9a00642010-02-10 01:20:13 -0800294 subtract_range(range, RANGE_NUM, 1ULL<<32, end);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800295 }
296
297 /*
298 * add left over mmio range to def node/link ?
299 * that is tricky, just record range in from start_min to 4G
300 */
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700301 info = find_pci_root_info(def_node, def_link);
302 if (info) {
Yinghai Lu30a18d62008-02-19 03:21:20 -0800303 for (i = 0; i < RANGE_NUM; i++) {
304 if (!range[i].end)
305 continue;
306
Yinghai Lu9ad3f2c2010-02-10 01:20:11 -0800307 update_res(info, cap_resource(range[i].start),
Yinghai Lue9a00642010-02-10 01:20:13 -0800308 cap_resource(range[i].end - 1),
Yinghai Lu30a18d62008-02-19 03:21:20 -0800309 IORESOURCE_MEM, 1);
310 }
311 }
312
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700313 list_for_each_entry(info, &pci_root_infos, list) {
Yinghai Lu30a18d62008-02-19 03:21:20 -0800314 int busnum;
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700315 struct pci_root_res *root_res;
Yinghai Lu30a18d62008-02-19 03:21:20 -0800316
Yinghai Lua10bb122012-05-17 18:51:12 -0700317 busnum = info->busn.start;
318 printk(KERN_DEBUG "bus: %pR on node %x link %x\n",
319 &info->busn, info->node, info->link);
Yinghai Lud28e5ac2012-04-02 18:31:54 -0700320 list_for_each_entry(root_res, &info->resources, list)
321 printk(KERN_DEBUG "bus: %02x %pR\n",
322 busnum, &root_res->res);
Yinghai Lu30a18d62008-02-19 03:21:20 -0800323 }
324
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 return 0;
326}
327
Robert Richter3a27dd12008-06-12 20:19:23 +0200328#define ENABLE_CF8_EXT_CFG (1ULL << 46)
329
Sebastian Andrzej Siewiorc8b877a2016-11-17 19:35:41 +0100330static int amd_bus_cpu_online(unsigned int cpu)
Robert Richter3a27dd12008-06-12 20:19:23 +0200331{
332 u64 reg;
Sebastian Andrzej Siewiorc8b877a2016-11-17 19:35:41 +0100333
Robert Richter3a27dd12008-06-12 20:19:23 +0200334 rdmsrl(MSR_AMD64_NB_CFG, reg);
335 if (!(reg & ENABLE_CF8_EXT_CFG)) {
336 reg |= ENABLE_CF8_EXT_CFG;
337 wrmsrl(MSR_AMD64_NB_CFG, reg);
338 }
Sebastian Andrzej Siewiorc8b877a2016-11-17 19:35:41 +0100339 return 0;
Robert Richter3a27dd12008-06-12 20:19:23 +0200340}
341
Jan Beulich24d9b702011-01-10 16:20:23 +0000342static void __init pci_enable_pci_io_ecs(void)
343{
344#ifdef CONFIG_AMD_NB
345 unsigned int i, n;
346
347 for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
348 u8 bus = amd_nb_bus_dev_ranges[i].bus;
349 u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
350 u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
351
352 for (; slot < limit; ++slot) {
353 u32 val = read_pci_config(bus, slot, 3, 0);
354
355 if (!early_is_amd_nb(val))
356 continue;
357
358 val = read_pci_config(bus, slot, 3, 0x8c);
359 if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
360 val |= ENABLE_CF8_EXT_CFG >> 32;
361 write_pci_config(bus, slot, 3, 0x8c, val);
362 }
363 ++n;
364 }
365 }
Jan Beulich24d9b702011-01-10 16:20:23 +0000366#endif
367}
368
Robert Richter91ede002008-08-22 20:23:38 +0200369static int __init pci_io_ecs_init(void)
370{
Sebastian Andrzej Siewiorc8b877a2016-11-17 19:35:41 +0100371 int ret;
Robert Richter91ede002008-08-22 20:23:38 +0200372
Robert Richter3a27dd12008-06-12 20:19:23 +0200373 /* assume all cpus from fam10h have IO ECS */
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -0500374 if (boot_cpu_data.x86 < 0x10)
Robert Richter3a27dd12008-06-12 20:19:23 +0200375 return 0;
Robert Richter91ede002008-08-22 20:23:38 +0200376
Jan Beulich24d9b702011-01-10 16:20:23 +0000377 /* Try the PCI method first. */
378 if (early_pci_allowed())
379 pci_enable_pci_io_ecs();
380
Sebastian Andrzej Siewiorc8b877a2016-11-17 19:35:41 +0100381 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/amd_bus:online",
382 amd_bus_cpu_online, NULL);
383 WARN_ON(ret < 0);
Srivatsa S. Bhat9f668f62014-03-11 02:08:43 +0530384
Robert Richter3a27dd12008-06-12 20:19:23 +0200385 pci_probe |= PCI_HAS_IO_ECS;
Robert Richter91ede002008-08-22 20:23:38 +0200386
Robert Richter3a27dd12008-06-12 20:19:23 +0200387 return 0;
388}
389
Robert Richter9b4e27b2008-08-22 20:23:37 +0200390static int __init amd_postcore_init(void)
391{
392 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
393 return 0;
394
Suravee Suthikulpanit9e7f7232014-05-08 11:44:19 -0500395 early_root_info_init();
Robert Richter91ede002008-08-22 20:23:38 +0200396 pci_io_ecs_init();
Robert Richter9b4e27b2008-08-22 20:23:37 +0200397
398 return 0;
399}
400
401postcore_initcall(amd_postcore_init);