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Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +09001/*
2 * Device Tree Source for the r8a7791 SoC
3 *
Kazuya Mizuguchi118e4e62015-02-19 10:43:10 -05004 * Copyright (C) 2013-2015 Renesas Electronics Corporation
Sergei Shtylyov2e5d55c2014-02-20 02:27:04 +03005 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +09007 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
Laurent Pinchart59e79892013-12-11 15:05:16 +010013#include <dt-bindings/clock/r8a7791-clock.h>
Laurent Pinchart5f75e732013-11-19 03:18:25 +010014#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +090017/ {
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
Wolfram Sang5bd3de72014-02-17 11:44:41 +010023 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
Wolfram Sang36408d92014-03-10 12:26:58 +010030 i2c6 = &i2c6;
31 i2c7 = &i2c7;
32 i2c8 = &i2c8;
Geert Uytterhoeven6f3e4ee2014-02-25 11:30:14 +010033 spi0 = &qspi;
Geert Uytterhoeven7713d3a2014-02-25 11:30:16 +010034 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
Sergei Shtylyov0b8d1d52014-08-02 04:04:21 +040037 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
Wolfram Sang5bd3de72014-02-17 11:44:41 +010040 };
41
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +090042 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
Magnus Damm896b79d2014-03-06 12:15:36 +090050 clock-frequency = <1500000000>;
Gaku Inamia57004ec2014-06-03 21:03:10 +090051 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
Geert Uytterhoeven8ffe93a2015-06-02 14:33:46 +020054 next-level-cache = <&L2_CA15>;
Gaku Inamia57004ec2014-06-03 21:03:10 +090055
56 /* kHz - uV - OPPs unknown yet */
57 operating-points = <1500000 1000000>,
58 <1312500 1000000>,
59 <1125000 1000000>,
60 < 937500 1000000>,
61 < 750000 1000000>,
62 < 375000 1000000>;
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +090063 };
Magnus Damm15ab4262013-10-01 17:13:07 +090064
65 cpu1: cpu@1 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <1>;
Magnus Damm896b79d2014-03-06 12:15:36 +090069 clock-frequency = <1500000000>;
Geert Uytterhoeven8ffe93a2015-06-02 14:33:46 +020070 next-level-cache = <&L2_CA15>;
Magnus Damm15ab4262013-10-01 17:13:07 +090071 };
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +090072 };
73
Kuninori Morimotocac68a52016-01-28 02:46:01 +000074 thermal-zones {
75 cpu_thermal: cpu-thermal {
76 polling-delay-passive = <0>;
77 polling-delay = <0>;
78
79 thermal-sensors = <&thermal>;
80
81 trips {
82 cpu-crit {
83 temperature = <115000>;
84 hysteresis = <0>;
85 type = "critical";
86 };
87 };
88 cooling-maps {
89 };
90 };
91 };
92
Geert Uytterhoeven8ffe93a2015-06-02 14:33:46 +020093 L2_CA15: cache-controller@0 {
94 compatible = "cache";
95 cache-unified;
96 cache-level = <2>;
97 };
98
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +090099 gic: interrupt-controller@f1001000 {
Geert Uytterhoevend238b5e2015-06-17 15:03:34 +0200100 compatible = "arm,gic-400";
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +0900101 #interrupt-cells = <3>;
102 #address-cells = <0>;
103 interrupt-controller;
104 reg = <0 0xf1001000 0 0x1000>,
105 <0 0xf1002000 0 0x1000>,
106 <0 0xf1004000 0 0x2000>,
107 <0 0xf1006000 0 0x2000>;
Simon Horman386a9292016-01-15 11:44:16 +0900108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +0900109 };
Magnus Dammd77db732013-10-01 17:12:29 +0900110
Magnus Damm89fbba12013-11-21 14:22:00 +0900111 gpio0: gpio@e6050000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900112 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900113 reg = <0 0xe6050000 0 0x50>;
Simon Horman386a9292016-01-15 11:44:16 +0900114 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900115 #gpio-cells = <2>;
116 gpio-controller;
117 gpio-ranges = <&pfc 0 0 32>;
118 #interrupt-cells = <2>;
119 interrupt-controller;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +0200120 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200121 power-domains = <&cpg_clocks>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900122 };
123
Magnus Damm89fbba12013-11-21 14:22:00 +0900124 gpio1: gpio@e6051000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900125 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900126 reg = <0 0xe6051000 0 0x50>;
Simon Horman386a9292016-01-15 11:44:16 +0900127 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900128 #gpio-cells = <2>;
129 gpio-controller;
Sergei Shtylyov1329f6d2015-10-22 02:05:19 +0300130 gpio-ranges = <&pfc 0 32 26>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900131 #interrupt-cells = <2>;
132 interrupt-controller;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +0200133 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200134 power-domains = <&cpg_clocks>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900135 };
136
Magnus Damm89fbba12013-11-21 14:22:00 +0900137 gpio2: gpio@e6052000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900138 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900139 reg = <0 0xe6052000 0 0x50>;
Simon Horman386a9292016-01-15 11:44:16 +0900140 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900141 #gpio-cells = <2>;
142 gpio-controller;
143 gpio-ranges = <&pfc 0 64 32>;
144 #interrupt-cells = <2>;
145 interrupt-controller;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +0200146 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200147 power-domains = <&cpg_clocks>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900148 };
149
Magnus Damm89fbba12013-11-21 14:22:00 +0900150 gpio3: gpio@e6053000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900151 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900152 reg = <0 0xe6053000 0 0x50>;
Simon Horman386a9292016-01-15 11:44:16 +0900153 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 96 32>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +0200159 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200160 power-domains = <&cpg_clocks>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900161 };
162
Magnus Damm89fbba12013-11-21 14:22:00 +0900163 gpio4: gpio@e6054000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900164 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900165 reg = <0 0xe6054000 0 0x50>;
Simon Horman386a9292016-01-15 11:44:16 +0900166 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 128 32>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +0200172 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200173 power-domains = <&cpg_clocks>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900174 };
175
Magnus Damm89fbba12013-11-21 14:22:00 +0900176 gpio5: gpio@e6055000 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900177 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900178 reg = <0 0xe6055000 0 0x50>;
Simon Horman386a9292016-01-15 11:44:16 +0900179 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900180 #gpio-cells = <2>;
181 gpio-controller;
182 gpio-ranges = <&pfc 0 160 32>;
183 #interrupt-cells = <2>;
184 interrupt-controller;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +0200185 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200186 power-domains = <&cpg_clocks>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900187 };
188
Magnus Damm89fbba12013-11-21 14:22:00 +0900189 gpio6: gpio@e6055400 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900190 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900191 reg = <0 0xe6055400 0 0x50>;
Simon Horman386a9292016-01-15 11:44:16 +0900192 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900193 #gpio-cells = <2>;
194 gpio-controller;
195 gpio-ranges = <&pfc 0 192 32>;
196 #interrupt-cells = <2>;
197 interrupt-controller;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +0200198 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200199 power-domains = <&cpg_clocks>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900200 };
201
Magnus Damm89fbba12013-11-21 14:22:00 +0900202 gpio7: gpio@e6055800 {
Magnus Dammab87e3f2013-10-08 12:39:30 +0900203 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
Magnus Damm89fbba12013-11-21 14:22:00 +0900204 reg = <0 0xe6055800 0 0x50>;
Simon Horman386a9292016-01-15 11:44:16 +0900205 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900206 #gpio-cells = <2>;
207 gpio-controller;
208 gpio-ranges = <&pfc 0 224 26>;
209 #interrupt-cells = <2>;
210 interrupt-controller;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +0200211 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200212 power-domains = <&cpg_clocks>;
Magnus Dammab87e3f2013-10-08 12:39:30 +0900213 };
214
Kuninori Morimotocac68a52016-01-28 02:46:01 +0000215 thermal: thermal@e61f0000 {
216 compatible = "renesas,thermal-r8a7791",
217 "renesas,rcar-gen2-thermal",
218 "renesas,rcar-thermal";
Magnus Dammd103f4d2013-11-20 16:59:48 +0900219 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
Simon Horman386a9292016-01-15 11:44:16 +0900220 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven563bc8e2014-01-07 19:57:13 +0100221 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200222 power-domains = <&cpg_clocks>;
Kuninori Morimotocac68a52016-01-28 02:46:01 +0000223 #thermal-sensor-cells = <0>;
Magnus Dammd103f4d2013-11-20 16:59:48 +0900224 };
225
Magnus Damm03586ac2013-10-01 17:12:38 +0900226 timer {
227 compatible = "arm,armv7-timer";
Simon Horman386a9292016-01-15 11:44:16 +0900228 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
229 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
230 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
231 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
Magnus Damm03586ac2013-10-01 17:12:38 +0900232 };
233
Laurent Pinchartceaa1892014-07-09 15:12:38 +0200234 cmt0: timer@ffca0000 {
Simon Horman4217f322014-09-08 09:27:46 +0900235 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
Laurent Pinchartceaa1892014-07-09 15:12:38 +0200236 reg = <0 0xffca0000 0 0x1004>;
Simon Horman386a9292016-01-15 11:44:16 +0900237 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartceaa1892014-07-09 15:12:38 +0200239 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
240 clock-names = "fck";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200241 power-domains = <&cpg_clocks>;
Laurent Pinchartceaa1892014-07-09 15:12:38 +0200242
243 renesas,channels-mask = <0x60>;
244
245 status = "disabled";
246 };
247
248 cmt1: timer@e6130000 {
Simon Horman4217f322014-09-08 09:27:46 +0900249 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
Laurent Pinchartceaa1892014-07-09 15:12:38 +0200250 reg = <0 0xe6130000 0 0x1004>;
Simon Horman386a9292016-01-15 11:44:16 +0900251 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartceaa1892014-07-09 15:12:38 +0200259 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
260 clock-names = "fck";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200261 power-domains = <&cpg_clocks>;
Laurent Pinchartceaa1892014-07-09 15:12:38 +0200262
263 renesas,channels-mask = <0xff>;
264
265 status = "disabled";
266 };
267
Magnus Dammd77db732013-10-01 17:12:29 +0900268 irqc0: interrupt-controller@e61c0000 {
Magnus Damm26041b02013-11-20 13:18:05 +0900269 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
Magnus Dammd77db732013-10-01 17:12:29 +0900270 #interrupt-cells = <2>;
271 interrupt-controller;
272 reg = <0 0xe61c0000 0 0x200>;
Simon Horman386a9292016-01-15 11:44:16 +0900273 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven62d386c2015-03-18 19:56:00 +0100283 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200284 power-domains = <&cpg_clocks>;
Magnus Dammd77db732013-10-01 17:12:29 +0900285 };
Magnus Damm55146922013-10-08 12:39:01 +0900286
Laurent Pinchartfde8fee2014-07-19 01:50:25 +0200287 dmac0: dma-controller@e6700000 {
Simon Hormane6d12b42015-11-13 11:23:49 +0900288 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
Laurent Pinchartfde8fee2014-07-19 01:50:25 +0200289 reg = <0 0xe6700000 0 0x20000>;
Simon Horman386a9292016-01-15 11:44:16 +0900290 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
291 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
293 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
296 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
297 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartfde8fee2014-07-19 01:50:25 +0200306 interrupt-names = "error",
307 "ch0", "ch1", "ch2", "ch3",
308 "ch4", "ch5", "ch6", "ch7",
309 "ch8", "ch9", "ch10", "ch11",
310 "ch12", "ch13", "ch14";
311 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
312 clock-names = "fck";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200313 power-domains = <&cpg_clocks>;
Laurent Pinchartfde8fee2014-07-19 01:50:25 +0200314 #dma-cells = <1>;
315 dma-channels = <15>;
316 };
317
318 dmac1: dma-controller@e6720000 {
Simon Hormane6d12b42015-11-13 11:23:49 +0900319 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
Laurent Pinchartfde8fee2014-07-19 01:50:25 +0200320 reg = <0 0xe6720000 0 0x20000>;
Simon Horman386a9292016-01-15 11:44:16 +0900321 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartfde8fee2014-07-19 01:50:25 +0200337 interrupt-names = "error",
338 "ch0", "ch1", "ch2", "ch3",
339 "ch4", "ch5", "ch6", "ch7",
340 "ch8", "ch9", "ch10", "ch11",
341 "ch12", "ch13", "ch14";
342 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
343 clock-names = "fck";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200344 power-domains = <&cpg_clocks>;
Laurent Pinchartfde8fee2014-07-19 01:50:25 +0200345 #dma-cells = <1>;
346 dma-channels = <15>;
347 };
348
Kuninori Morimoto8994fff2014-11-03 17:45:37 -0800349 audma0: dma-controller@ec700000 {
Simon Hormane6d12b42015-11-13 11:23:49 +0900350 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
Kuninori Morimoto8994fff2014-11-03 17:45:37 -0800351 reg = <0 0xec700000 0 0x10000>;
Simon Horman386a9292016-01-15 11:44:16 +0900352 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto8994fff2014-11-03 17:45:37 -0800366 interrupt-names = "error",
367 "ch0", "ch1", "ch2", "ch3",
368 "ch4", "ch5", "ch6", "ch7",
369 "ch8", "ch9", "ch10", "ch11",
370 "ch12";
371 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
372 clock-names = "fck";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200373 power-domains = <&cpg_clocks>;
Kuninori Morimoto8994fff2014-11-03 17:45:37 -0800374 #dma-cells = <1>;
375 dma-channels = <13>;
376 };
377
378 audma1: dma-controller@ec720000 {
Simon Hormane6d12b42015-11-13 11:23:49 +0900379 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
Kuninori Morimoto8994fff2014-11-03 17:45:37 -0800380 reg = <0 0xec720000 0 0x10000>;
Simon Horman386a9292016-01-15 11:44:16 +0900381 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto8994fff2014-11-03 17:45:37 -0800395 interrupt-names = "error",
396 "ch0", "ch1", "ch2", "ch3",
397 "ch4", "ch5", "ch6", "ch7",
398 "ch8", "ch9", "ch10", "ch11",
399 "ch12";
400 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
401 clock-names = "fck";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200402 power-domains = <&cpg_clocks>;
Kuninori Morimoto8994fff2014-11-03 17:45:37 -0800403 #dma-cells = <1>;
404 dma-channels = <13>;
405 };
406
Yoshihiro Shimodae3e25ed2015-05-08 16:13:33 +0900407 usb_dmac0: dma-controller@e65a0000 {
Simon Hormand01c8be2015-12-11 11:59:38 +0900408 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
Yoshihiro Shimodae3e25ed2015-05-08 16:13:33 +0900409 reg = <0 0xe65a0000 0 0x100>;
Simon Horman386a9292016-01-15 11:44:16 +0900410 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
Yoshihiro Shimodae3e25ed2015-05-08 16:13:33 +0900412 interrupt-names = "ch0", "ch1";
413 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200414 power-domains = <&cpg_clocks>;
Yoshihiro Shimodae3e25ed2015-05-08 16:13:33 +0900415 #dma-cells = <1>;
416 dma-channels = <2>;
417 };
418
419 usb_dmac1: dma-controller@e65b0000 {
Simon Hormand01c8be2015-12-11 11:59:38 +0900420 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
Yoshihiro Shimodae3e25ed2015-05-08 16:13:33 +0900421 reg = <0 0xe65b0000 0 0x100>;
Simon Horman386a9292016-01-15 11:44:16 +0900422 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
Yoshihiro Shimodae3e25ed2015-05-08 16:13:33 +0900424 interrupt-names = "ch0", "ch1";
425 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200426 power-domains = <&cpg_clocks>;
Yoshihiro Shimodae3e25ed2015-05-08 16:13:33 +0900427 #dma-cells = <1>;
428 dma-channels = <2>;
429 };
430
Wolfram Sang36408d92014-03-10 12:26:58 +0100431 /* The memory map in the User's Manual maps the cores to bus numbers */
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100432 i2c0: i2c@e6508000 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "renesas,i2c-r8a7791";
436 reg = <0 0xe6508000 0 0x40>;
Simon Horman386a9292016-01-15 11:44:16 +0900437 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100438 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200439 power-domains = <&cpg_clocks>;
Wolfram Sang49160dc2015-12-08 10:37:51 +0100440 i2c-scl-internal-delay-ns = <6>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100441 status = "disabled";
442 };
443
444 i2c1: i2c@e6518000 {
445 #address-cells = <1>;
446 #size-cells = <0>;
447 compatible = "renesas,i2c-r8a7791";
448 reg = <0 0xe6518000 0 0x40>;
Simon Horman386a9292016-01-15 11:44:16 +0900449 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100450 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200451 power-domains = <&cpg_clocks>;
Wolfram Sang49160dc2015-12-08 10:37:51 +0100452 i2c-scl-internal-delay-ns = <6>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100453 status = "disabled";
454 };
455
456 i2c2: i2c@e6530000 {
457 #address-cells = <1>;
458 #size-cells = <0>;
459 compatible = "renesas,i2c-r8a7791";
460 reg = <0 0xe6530000 0 0x40>;
Simon Horman386a9292016-01-15 11:44:16 +0900461 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100462 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200463 power-domains = <&cpg_clocks>;
Wolfram Sang49160dc2015-12-08 10:37:51 +0100464 i2c-scl-internal-delay-ns = <6>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100465 status = "disabled";
466 };
467
468 i2c3: i2c@e6540000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "renesas,i2c-r8a7791";
472 reg = <0 0xe6540000 0 0x40>;
Simon Horman386a9292016-01-15 11:44:16 +0900473 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100474 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200475 power-domains = <&cpg_clocks>;
Wolfram Sang49160dc2015-12-08 10:37:51 +0100476 i2c-scl-internal-delay-ns = <6>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100477 status = "disabled";
478 };
479
480 i2c4: i2c@e6520000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "renesas,i2c-r8a7791";
484 reg = <0 0xe6520000 0 0x40>;
Simon Horman386a9292016-01-15 11:44:16 +0900485 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100486 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200487 power-domains = <&cpg_clocks>;
Wolfram Sang49160dc2015-12-08 10:37:51 +0100488 i2c-scl-internal-delay-ns = <6>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100489 status = "disabled";
490 };
491
492 i2c5: i2c@e6528000 {
Wolfram Sang36408d92014-03-10 12:26:58 +0100493 /* doesn't need pinmux */
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "renesas,i2c-r8a7791";
497 reg = <0 0xe6528000 0 0x40>;
Simon Horman386a9292016-01-15 11:44:16 +0900498 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100499 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200500 power-domains = <&cpg_clocks>;
Wolfram Sang49160dc2015-12-08 10:37:51 +0100501 i2c-scl-internal-delay-ns = <110>;
Wolfram Sang5bd3de72014-02-17 11:44:41 +0100502 status = "disabled";
503 };
504
Wolfram Sang36408d92014-03-10 12:26:58 +0100505 i2c6: i2c@e60b0000 {
506 /* doesn't need pinmux */
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
510 reg = <0 0xe60b0000 0 0x425>;
Simon Horman386a9292016-01-15 11:44:16 +0900511 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang36408d92014-03-10 12:26:58 +0100512 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
Wolfram Sang3f58c542014-11-07 11:11:44 +0100513 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
514 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200515 power-domains = <&cpg_clocks>;
Wolfram Sang36408d92014-03-10 12:26:58 +0100516 status = "disabled";
517 };
518
519 i2c7: i2c@e6500000 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
523 reg = <0 0xe6500000 0 0x425>;
Simon Horman386a9292016-01-15 11:44:16 +0900524 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang36408d92014-03-10 12:26:58 +0100525 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
Wolfram Sang3f58c542014-11-07 11:11:44 +0100526 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
527 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200528 power-domains = <&cpg_clocks>;
Wolfram Sang36408d92014-03-10 12:26:58 +0100529 status = "disabled";
530 };
531
532 i2c8: i2c@e6510000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
536 reg = <0 0xe6510000 0 0x425>;
Simon Horman386a9292016-01-15 11:44:16 +0900537 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang36408d92014-03-10 12:26:58 +0100538 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
Wolfram Sang3f58c542014-11-07 11:11:44 +0100539 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
540 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200541 power-domains = <&cpg_clocks>;
Wolfram Sang36408d92014-03-10 12:26:58 +0100542 status = "disabled";
543 };
544
Magnus Damm55146922013-10-08 12:39:01 +0900545 pfc: pfc@e6060000 {
546 compatible = "renesas,pfc-r8a7791";
547 reg = <0 0xe6060000 0 0x250>;
Magnus Damm55146922013-10-08 12:39:01 +0900548 };
Laurent Pinchart59e79892013-12-11 15:05:16 +0100549
Laurent Pinchart8edae492014-10-26 19:40:12 +0200550 mmcif0: mmc@ee200000 {
551 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
552 reg = <0 0xee200000 0 0x80>;
Simon Horman386a9292016-01-15 11:44:16 +0900553 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart8edae492014-10-26 19:40:12 +0200554 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
Laurent Pinchart16b355b2014-10-26 19:40:14 +0200555 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
556 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200557 power-domains = <&cpg_clocks>;
Laurent Pinchart8edae492014-10-26 19:40:12 +0200558 reg-io-width = <4>;
559 status = "disabled";
Kuninori Morimotod957ab82015-05-14 07:23:20 +0000560 max-frequency = <97500000>;
Laurent Pinchart8edae492014-10-26 19:40:12 +0200561 };
562
Magnus Dammb7ed8a02014-02-12 18:53:55 +0900563 sdhi0: sd@ee100000 {
564 compatible = "renesas,sdhi-r8a7791";
Kuninori Morimotoe849b062015-02-24 02:20:52 +0000565 reg = <0 0xee100000 0 0x328>;
Simon Horman386a9292016-01-15 11:44:16 +0900566 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammb7ed8a02014-02-12 18:53:55 +0900567 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
Laurent Pinchartae67fa22015-02-24 02:20:19 +0000568 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
569 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200570 power-domains = <&cpg_clocks>;
Magnus Dammb7ed8a02014-02-12 18:53:55 +0900571 status = "disabled";
572 };
573
574 sdhi1: sd@ee140000 {
575 compatible = "renesas,sdhi-r8a7791";
576 reg = <0 0xee140000 0 0x100>;
Simon Horman386a9292016-01-15 11:44:16 +0900577 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammb7ed8a02014-02-12 18:53:55 +0900578 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
Laurent Pinchartae67fa22015-02-24 02:20:19 +0000579 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
580 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200581 power-domains = <&cpg_clocks>;
Magnus Dammb7ed8a02014-02-12 18:53:55 +0900582 status = "disabled";
583 };
584
585 sdhi2: sd@ee160000 {
586 compatible = "renesas,sdhi-r8a7791";
587 reg = <0 0xee160000 0 0x100>;
Simon Horman386a9292016-01-15 11:44:16 +0900588 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
Magnus Dammb7ed8a02014-02-12 18:53:55 +0900589 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
Laurent Pinchartae67fa22015-02-24 02:20:19 +0000590 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
591 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200592 power-domains = <&cpg_clocks>;
Magnus Dammb7ed8a02014-02-12 18:53:55 +0900593 status = "disabled";
594 };
595
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100596 scifa0: serial@e6c40000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100597 compatible = "renesas,scifa-r8a7791",
598 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100599 reg = <0 0xe6c40000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900600 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100601 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100602 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200603 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
604 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200605 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100606 status = "disabled";
607 };
608
609 scifa1: serial@e6c50000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100610 compatible = "renesas,scifa-r8a7791",
611 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100612 reg = <0 0xe6c50000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900613 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100614 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100615 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200616 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
617 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200618 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100619 status = "disabled";
620 };
621
622 scifa2: serial@e6c60000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100623 compatible = "renesas,scifa-r8a7791",
624 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100625 reg = <0 0xe6c60000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900626 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100627 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100628 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200629 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
630 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200631 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100632 status = "disabled";
633 };
634
635 scifa3: serial@e6c70000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100636 compatible = "renesas,scifa-r8a7791",
637 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100638 reg = <0 0xe6c70000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900639 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100640 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100641 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200642 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
643 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200644 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100645 status = "disabled";
646 };
647
648 scifa4: serial@e6c78000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100649 compatible = "renesas,scifa-r8a7791",
650 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100651 reg = <0 0xe6c78000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900652 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100653 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100654 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200655 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
656 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200657 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100658 status = "disabled";
659 };
660
661 scifa5: serial@e6c80000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100662 compatible = "renesas,scifa-r8a7791",
663 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100664 reg = <0 0xe6c80000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900665 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100666 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100667 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200668 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
669 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200670 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100671 status = "disabled";
672 };
673
674 scifb0: serial@e6c20000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100675 compatible = "renesas,scifb-r8a7791",
676 "renesas,rcar-gen2-scifb", "renesas,scifb";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100677 reg = <0 0xe6c20000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900678 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100679 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100680 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200681 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
682 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200683 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100684 status = "disabled";
685 };
686
687 scifb1: serial@e6c30000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100688 compatible = "renesas,scifb-r8a7791",
689 "renesas,rcar-gen2-scifb", "renesas,scifb";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100690 reg = <0 0xe6c30000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900691 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100692 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100693 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200694 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
695 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200696 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100697 status = "disabled";
698 };
699
700 scifb2: serial@e6ce0000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100701 compatible = "renesas,scifb-r8a7791",
702 "renesas,rcar-gen2-scifb", "renesas,scifb";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100703 reg = <0 0xe6ce0000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900704 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100705 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
Laurent Pinchartbb7ca192016-01-29 10:47:38 +0100706 clock-names = "fck";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200707 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
708 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200709 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100710 status = "disabled";
711 };
712
713 scif0: serial@e6e60000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100714 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
715 "renesas,scif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100716 reg = <0 0xe6e60000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900717 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100718 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
719 <&scif_clk>;
720 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200721 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
722 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200723 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100724 status = "disabled";
725 };
726
727 scif1: serial@e6e68000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100728 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
729 "renesas,scif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100730 reg = <0 0xe6e68000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900731 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100732 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
733 <&scif_clk>;
734 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200735 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
736 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200737 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100738 status = "disabled";
739 };
740
741 scif2: serial@e6e58000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100742 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
743 "renesas,scif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100744 reg = <0 0xe6e58000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900745 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100746 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
747 <&scif_clk>;
748 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200749 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
750 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200751 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100752 status = "disabled";
753 };
754
755 scif3: serial@e6ea8000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100756 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
757 "renesas,scif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100758 reg = <0 0xe6ea8000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900759 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100760 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
761 <&scif_clk>;
762 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200763 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
764 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200765 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100766 status = "disabled";
767 };
768
769 scif4: serial@e6ee0000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100770 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
771 "renesas,scif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100772 reg = <0 0xe6ee0000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900773 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100774 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
775 <&scif_clk>;
776 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200777 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
778 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200779 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100780 status = "disabled";
781 };
782
783 scif5: serial@e6ee8000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100784 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
785 "renesas,scif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100786 reg = <0 0xe6ee8000 0 64>;
Simon Horman386a9292016-01-15 11:44:16 +0900787 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100788 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
789 <&scif_clk>;
790 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200791 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
792 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200793 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100794 status = "disabled";
795 };
796
797 hscif0: serial@e62c0000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100798 compatible = "renesas,hscif-r8a7791",
799 "renesas,rcar-gen2-hscif", "renesas,hscif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100800 reg = <0 0xe62c0000 0 96>;
Simon Horman386a9292016-01-15 11:44:16 +0900801 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100802 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
803 <&scif_clk>;
804 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200805 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
806 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200807 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100808 status = "disabled";
809 };
810
811 hscif1: serial@e62c8000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100812 compatible = "renesas,hscif-r8a7791",
813 "renesas,rcar-gen2-hscif", "renesas,hscif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100814 reg = <0 0xe62c8000 0 96>;
Simon Horman386a9292016-01-15 11:44:16 +0900815 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100816 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
817 <&scif_clk>;
818 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200819 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
820 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200821 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100822 status = "disabled";
823 };
824
825 hscif2: serial@e62d0000 {
Geert Uytterhoevenb5b52dd2016-01-29 10:32:05 +0100826 compatible = "renesas,hscif-r8a7791",
827 "renesas,rcar-gen2-hscif", "renesas,hscif";
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100828 reg = <0 0xe62d0000 0 96>;
Simon Horman386a9292016-01-15 11:44:16 +0900829 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven394730a2016-01-29 11:04:40 +0100830 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
831 <&scif_clk>;
832 clock-names = "fck", "brg_int", "scif_clk";
Geert Uytterhoeven558d6562015-05-20 19:46:26 +0200833 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
834 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200835 power-domains = <&cpg_clocks>;
Laurent Pinchart9640cf22013-12-11 14:14:22 +0100836 status = "disabled";
837 };
838
Sergei Shtylyov2e5d55c2014-02-20 02:27:04 +0300839 ether: ethernet@ee700000 {
840 compatible = "renesas,ether-r8a7791";
841 reg = <0 0xee700000 0 0x400>;
Simon Horman386a9292016-01-15 11:44:16 +0900842 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov2e5d55c2014-02-20 02:27:04 +0300843 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200844 power-domains = <&cpg_clocks>;
Sergei Shtylyov2e5d55c2014-02-20 02:27:04 +0300845 phy-mode = "rmii";
846 #address-cells = <1>;
847 #size-cells = <0>;
848 status = "disabled";
849 };
850
Sergei Shtylyov46ece342015-12-03 01:23:03 +0300851 avb: ethernet@e6800000 {
852 compatible = "renesas,etheravb-r8a7791",
853 "renesas,etheravb-rcar-gen2";
854 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
Simon Horman386a9292016-01-15 11:44:16 +0900855 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov46ece342015-12-03 01:23:03 +0300856 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
857 power-domains = <&cpg_clocks>;
858 #address-cells = <1>;
859 #size-cells = <0>;
860 status = "disabled";
861 };
862
Valentine Barshakb8532c62014-01-14 21:05:40 +0400863 sata0: sata@ee300000 {
864 compatible = "renesas,sata-r8a7791";
865 reg = <0 0xee300000 0 0x2000>;
Simon Horman386a9292016-01-15 11:44:16 +0900866 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
Valentine Barshakb8532c62014-01-14 21:05:40 +0400867 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200868 power-domains = <&cpg_clocks>;
Valentine Barshakb8532c62014-01-14 21:05:40 +0400869 status = "disabled";
870 };
871
872 sata1: sata@ee500000 {
873 compatible = "renesas,sata-r8a7791";
874 reg = <0 0xee500000 0 0x2000>;
Simon Horman386a9292016-01-15 11:44:16 +0900875 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
Valentine Barshakb8532c62014-01-14 21:05:40 +0400876 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200877 power-domains = <&cpg_clocks>;
Valentine Barshakb8532c62014-01-14 21:05:40 +0400878 status = "disabled";
879 };
880
Yoshihiro Shimoda1c1fee72014-10-24 19:45:06 +0900881 hsusb: usb@e6590000 {
Simon Horman8cf1d452016-01-04 08:20:18 +1100882 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
Yoshihiro Shimoda1c1fee72014-10-24 19:45:06 +0900883 reg = <0 0xe6590000 0 0x100>;
Simon Horman386a9292016-01-15 11:44:16 +0900884 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
Yoshihiro Shimoda1c1fee72014-10-24 19:45:06 +0900885 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
Yoshihiro Shimoda77069932015-05-08 16:13:34 +0900886 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
887 <&usb_dmac1 0>, <&usb_dmac1 1>;
888 dma-names = "ch0", "ch1", "ch2", "ch3";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200889 power-domains = <&cpg_clocks>;
890 renesas,buswait = <4>;
891 phys = <&usb0 1>;
892 phy-names = "usb";
Yoshihiro Shimoda1c1fee72014-10-24 19:45:06 +0900893 status = "disabled";
894 };
895
Sergei Shtylyov3b7e5302014-09-27 01:08:12 +0400896 usbphy: usb-phy@e6590100 {
897 compatible = "renesas,usb-phy-r8a7791";
898 reg = <0 0xe6590100 0 0x100>;
899 #address-cells = <1>;
900 #size-cells = <0>;
901 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
902 clock-names = "usbhs";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200903 power-domains = <&cpg_clocks>;
Sergei Shtylyov3b7e5302014-09-27 01:08:12 +0400904 status = "disabled";
905
906 usb0: usb-channel@0 {
907 reg = <0>;
908 #phy-cells = <1>;
909 };
910 usb2: usb-channel@2 {
911 reg = <2>;
912 #phy-cells = <1>;
913 };
914 };
915
Sergei Shtylyov0b8d1d52014-08-02 04:04:21 +0400916 vin0: video@e6ef0000 {
917 compatible = "renesas,vin-r8a7791";
Sergei Shtylyov0b8d1d52014-08-02 04:04:21 +0400918 reg = <0 0xe6ef0000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +0900919 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200920 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
921 power-domains = <&cpg_clocks>;
Sergei Shtylyov0b8d1d52014-08-02 04:04:21 +0400922 status = "disabled";
923 };
924
925 vin1: video@e6ef1000 {
926 compatible = "renesas,vin-r8a7791";
Sergei Shtylyov0b8d1d52014-08-02 04:04:21 +0400927 reg = <0 0xe6ef1000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +0900928 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200929 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
930 power-domains = <&cpg_clocks>;
Sergei Shtylyov0b8d1d52014-08-02 04:04:21 +0400931 status = "disabled";
932 };
933
934 vin2: video@e6ef2000 {
935 compatible = "renesas,vin-r8a7791";
Sergei Shtylyov0b8d1d52014-08-02 04:04:21 +0400936 reg = <0 0xe6ef2000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +0900937 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200938 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
939 power-domains = <&cpg_clocks>;
Sergei Shtylyov0b8d1d52014-08-02 04:04:21 +0400940 status = "disabled";
941 };
942
Laurent Pinchart8eefac22014-01-21 16:00:46 +0100943 vsp1@fe928000 {
944 compatible = "renesas,vsp1";
945 reg = <0 0xfe928000 0 0x8000>;
Simon Horman386a9292016-01-15 11:44:16 +0900946 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart8eefac22014-01-21 16:00:46 +0100947 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200948 power-domains = <&cpg_clocks>;
Laurent Pinchart8eefac22014-01-21 16:00:46 +0100949
950 renesas,has-lut;
951 renesas,has-sru;
952 renesas,#rpf = <5>;
953 renesas,#uds = <3>;
954 renesas,#wpf = <4>;
955 };
956
957 vsp1@fe930000 {
958 compatible = "renesas,vsp1";
959 reg = <0 0xfe930000 0 0x8000>;
Simon Horman386a9292016-01-15 11:44:16 +0900960 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart8eefac22014-01-21 16:00:46 +0100961 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200962 power-domains = <&cpg_clocks>;
Laurent Pinchart8eefac22014-01-21 16:00:46 +0100963
964 renesas,has-lif;
965 renesas,has-lut;
966 renesas,#rpf = <4>;
967 renesas,#uds = <1>;
968 renesas,#wpf = <4>;
969 };
970
971 vsp1@fe938000 {
972 compatible = "renesas,vsp1";
973 reg = <0 0xfe938000 0 0x8000>;
Simon Horman386a9292016-01-15 11:44:16 +0900974 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart8eefac22014-01-21 16:00:46 +0100975 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +0200976 power-domains = <&cpg_clocks>;
Laurent Pinchart8eefac22014-01-21 16:00:46 +0100977
978 renesas,has-lif;
979 renesas,has-lut;
980 renesas,#rpf = <4>;
981 renesas,#uds = <1>;
982 renesas,#wpf = <4>;
983 };
984
985 du: display@feb00000 {
986 compatible = "renesas,du-r8a7791";
987 reg = <0 0xfeb00000 0 0x40000>,
988 <0 0xfeb90000 0 0x1c>;
989 reg-names = "du", "lvds.0";
Simon Horman386a9292016-01-15 11:44:16 +0900990 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart8eefac22014-01-21 16:00:46 +0100992 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
993 <&mstp7_clks R8A7791_CLK_DU1>,
994 <&mstp7_clks R8A7791_CLK_LVDS0>;
995 clock-names = "du.0", "du.1", "lvds.0";
996 status = "disabled";
997
998 ports {
999 #address-cells = <1>;
1000 #size-cells = <0>;
1001
1002 port@0 {
1003 reg = <0>;
1004 du_out_rgb: endpoint {
1005 };
1006 };
1007 port@1 {
1008 reg = <1>;
1009 du_out_lvds0: endpoint {
1010 };
1011 };
1012 };
1013 };
1014
Sergei Shtylyov3cf01882015-01-06 01:25:25 +03001015 can0: can@e6e80000 {
1016 compatible = "renesas,can-r8a7791";
1017 reg = <0 0xe6e80000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001018 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov3cf01882015-01-06 01:25:25 +03001019 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
1020 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1021 clock-names = "clkp1", "clkp2", "can_clk";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001022 power-domains = <&cpg_clocks>;
Sergei Shtylyov3cf01882015-01-06 01:25:25 +03001023 status = "disabled";
1024 };
1025
1026 can1: can@e6e88000 {
1027 compatible = "renesas,can-r8a7791";
1028 reg = <0 0xe6e88000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001029 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov3cf01882015-01-06 01:25:25 +03001030 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
1031 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1032 clock-names = "clkp1", "clkp2", "can_clk";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001033 power-domains = <&cpg_clocks>;
Sergei Shtylyov3cf01882015-01-06 01:25:25 +03001034 status = "disabled";
1035 };
1036
Mikhail Ulyanov0caa3662015-07-24 16:25:46 +03001037 jpu: jpeg-codec@fe980000 {
1038 compatible = "renesas,jpu-r8a7791";
1039 reg = <0 0xfe980000 0 0x10300>;
Simon Horman386a9292016-01-15 11:44:16 +09001040 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
Mikhail Ulyanov0caa3662015-07-24 16:25:46 +03001041 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001042 power-domains = <&cpg_clocks>;
Mikhail Ulyanov0caa3662015-07-24 16:25:46 +03001043 };
1044
Laurent Pinchart59e79892013-12-11 15:05:16 +01001045 clocks {
1046 #address-cells = <2>;
1047 #size-cells = <2>;
1048 ranges;
1049
1050 /* External root clock */
1051 extal_clk: extal_clk {
1052 compatible = "fixed-clock";
1053 #clock-cells = <0>;
1054 /* This value must be overriden by the board. */
1055 clock-frequency = <0>;
1056 clock-output-names = "extal";
1057 };
1058
Kuninori Morimoto0d3dbde2014-06-11 21:44:04 -07001059 /*
1060 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1061 * default. Boards that provide audio clocks should override them.
1062 */
1063 audio_clk_a: audio_clk_a {
1064 compatible = "fixed-clock";
1065 #clock-cells = <0>;
1066 clock-frequency = <0>;
1067 clock-output-names = "audio_clk_a";
1068 };
1069 audio_clk_b: audio_clk_b {
1070 compatible = "fixed-clock";
1071 #clock-cells = <0>;
1072 clock-frequency = <0>;
1073 clock-output-names = "audio_clk_b";
1074 };
1075 audio_clk_c: audio_clk_c {
1076 compatible = "fixed-clock";
1077 #clock-cells = <0>;
1078 clock-frequency = <0>;
1079 clock-output-names = "audio_clk_c";
1080 };
1081
Phil Edworthy66c405e2014-06-13 10:37:19 +01001082 /* External PCIe clock - can be overridden by the board */
1083 pcie_bus_clk: pcie_bus_clk {
1084 compatible = "fixed-clock";
1085 #clock-cells = <0>;
1086 clock-frequency = <100000000>;
1087 clock-output-names = "pcie_bus";
1088 status = "disabled";
1089 };
1090
Geert Uytterhoeven394730a2016-01-29 11:04:40 +01001091 /* External SCIF clock */
1092 scif_clk: scif {
1093 compatible = "fixed-clock";
1094 #clock-cells = <0>;
1095 /* This value must be overridden by the board. */
1096 clock-frequency = <0>;
1097 status = "disabled";
1098 };
1099
Sergei Shtylyovb3242522015-01-06 01:24:08 +03001100 /* External USB clock - can be overridden by the board */
1101 usb_extal_clk: usb_extal_clk {
1102 compatible = "fixed-clock";
1103 #clock-cells = <0>;
1104 clock-frequency = <48000000>;
1105 clock-output-names = "usb_extal";
1106 };
1107
1108 /* External CAN clock */
1109 can_clk: can_clk {
1110 compatible = "fixed-clock";
1111 #clock-cells = <0>;
1112 /* This value must be overridden by the board. */
1113 clock-frequency = <0>;
1114 clock-output-names = "can_clk";
1115 status = "disabled";
1116 };
1117
Laurent Pinchart59e79892013-12-11 15:05:16 +01001118 /* Special CPG clocks */
1119 cpg_clocks: cpg_clocks@e6150000 {
1120 compatible = "renesas,r8a7791-cpg-clocks",
1121 "renesas,rcar-gen2-cpg-clocks";
1122 reg = <0 0xe6150000 0 0x1000>;
Sergei Shtylyovb3242522015-01-06 01:24:08 +03001123 clocks = <&extal_clk &usb_extal_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001124 #clock-cells = <1>;
1125 clock-output-names = "main", "pll0", "pll1", "pll3",
Sergei Shtylyovb3242522015-01-06 01:24:08 +03001126 "lb", "qspi", "sdh", "sd0", "z",
Sergei Shtylyovae65a8a2014-12-30 23:20:34 +03001127 "rcan", "adsp";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001128 #power-domain-cells = <0>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001129 };
1130
1131 /* Variable factor clocks */
Simon Horman2ea0d4e2015-01-29 10:41:24 +09001132 sd2_clk: sd2_clk@e6150078 {
Laurent Pinchart59e79892013-12-11 15:05:16 +01001133 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1134 reg = <0 0xe6150078 0 4>;
1135 clocks = <&pll1_div2_clk>;
1136 #clock-cells = <0>;
Simon Horman2ea0d4e2015-01-29 10:41:24 +09001137 clock-output-names = "sd2";
Laurent Pinchart59e79892013-12-11 15:05:16 +01001138 };
Simon Horman2ea0d4e2015-01-29 10:41:24 +09001139 sd3_clk: sd3_clk@e615026c {
Laurent Pinchart59e79892013-12-11 15:05:16 +01001140 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
Shinobu Ueharac9b22772014-07-21 22:04:29 -07001141 reg = <0 0xe615026c 0 4>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001142 clocks = <&pll1_div2_clk>;
1143 #clock-cells = <0>;
Simon Horman2ea0d4e2015-01-29 10:41:24 +09001144 clock-output-names = "sd3";
Laurent Pinchart59e79892013-12-11 15:05:16 +01001145 };
1146 mmc0_clk: mmc0_clk@e6150240 {
1147 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1148 reg = <0 0xe6150240 0 4>;
1149 clocks = <&pll1_div2_clk>;
1150 #clock-cells = <0>;
1151 clock-output-names = "mmc0";
1152 };
1153 ssp_clk: ssp_clk@e6150248 {
1154 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1155 reg = <0 0xe6150248 0 4>;
1156 clocks = <&pll1_div2_clk>;
1157 #clock-cells = <0>;
1158 clock-output-names = "ssp";
1159 };
1160 ssprs_clk: ssprs_clk@e615024c {
1161 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1162 reg = <0 0xe615024c 0 4>;
1163 clocks = <&pll1_div2_clk>;
1164 #clock-cells = <0>;
1165 clock-output-names = "ssprs";
1166 };
1167
1168 /* Fixed factor clocks */
1169 pll1_div2_clk: pll1_div2_clk {
1170 compatible = "fixed-factor-clock";
1171 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1172 #clock-cells = <0>;
1173 clock-div = <2>;
1174 clock-mult = <1>;
1175 clock-output-names = "pll1_div2";
1176 };
1177 zg_clk: zg_clk {
1178 compatible = "fixed-factor-clock";
1179 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1180 #clock-cells = <0>;
1181 clock-div = <3>;
1182 clock-mult = <1>;
1183 clock-output-names = "zg";
1184 };
1185 zx_clk: zx_clk {
1186 compatible = "fixed-factor-clock";
1187 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1188 #clock-cells = <0>;
1189 clock-div = <3>;
1190 clock-mult = <1>;
1191 clock-output-names = "zx";
1192 };
1193 zs_clk: zs_clk {
1194 compatible = "fixed-factor-clock";
1195 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1196 #clock-cells = <0>;
1197 clock-div = <6>;
1198 clock-mult = <1>;
1199 clock-output-names = "zs";
1200 };
1201 hp_clk: hp_clk {
1202 compatible = "fixed-factor-clock";
1203 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1204 #clock-cells = <0>;
1205 clock-div = <12>;
1206 clock-mult = <1>;
1207 clock-output-names = "hp";
1208 };
1209 i_clk: i_clk {
1210 compatible = "fixed-factor-clock";
1211 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1212 #clock-cells = <0>;
1213 clock-div = <2>;
1214 clock-mult = <1>;
1215 clock-output-names = "i";
1216 };
1217 b_clk: b_clk {
1218 compatible = "fixed-factor-clock";
1219 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1220 #clock-cells = <0>;
1221 clock-div = <12>;
1222 clock-mult = <1>;
1223 clock-output-names = "b";
1224 };
1225 p_clk: p_clk {
1226 compatible = "fixed-factor-clock";
1227 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1228 #clock-cells = <0>;
1229 clock-div = <24>;
1230 clock-mult = <1>;
1231 clock-output-names = "p";
1232 };
1233 cl_clk: cl_clk {
1234 compatible = "fixed-factor-clock";
1235 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1236 #clock-cells = <0>;
1237 clock-div = <48>;
1238 clock-mult = <1>;
1239 clock-output-names = "cl";
1240 };
1241 m2_clk: m2_clk {
1242 compatible = "fixed-factor-clock";
1243 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1244 #clock-cells = <0>;
1245 clock-div = <8>;
1246 clock-mult = <1>;
1247 clock-output-names = "m2";
1248 };
Laurent Pinchart59e79892013-12-11 15:05:16 +01001249 rclk_clk: rclk_clk {
1250 compatible = "fixed-factor-clock";
1251 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1252 #clock-cells = <0>;
1253 clock-div = <(48 * 1024)>;
1254 clock-mult = <1>;
1255 clock-output-names = "rclk";
1256 };
1257 oscclk_clk: oscclk_clk {
1258 compatible = "fixed-factor-clock";
1259 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1260 #clock-cells = <0>;
1261 clock-div = <(12 * 1024)>;
1262 clock-mult = <1>;
1263 clock-output-names = "oscclk";
1264 };
1265 zb3_clk: zb3_clk {
1266 compatible = "fixed-factor-clock";
1267 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1268 #clock-cells = <0>;
1269 clock-div = <4>;
1270 clock-mult = <1>;
1271 clock-output-names = "zb3";
1272 };
1273 zb3d2_clk: zb3d2_clk {
1274 compatible = "fixed-factor-clock";
1275 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1276 #clock-cells = <0>;
1277 clock-div = <8>;
1278 clock-mult = <1>;
1279 clock-output-names = "zb3d2";
1280 };
1281 ddr_clk: ddr_clk {
1282 compatible = "fixed-factor-clock";
1283 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1284 #clock-cells = <0>;
1285 clock-div = <8>;
1286 clock-mult = <1>;
1287 clock-output-names = "ddr";
1288 };
1289 mp_clk: mp_clk {
1290 compatible = "fixed-factor-clock";
1291 clocks = <&pll1_div2_clk>;
1292 #clock-cells = <0>;
1293 clock-div = <15>;
1294 clock-mult = <1>;
1295 clock-output-names = "mp";
1296 };
1297 cp_clk: cp_clk {
1298 compatible = "fixed-factor-clock";
1299 clocks = <&extal_clk>;
1300 #clock-cells = <0>;
1301 clock-div = <2>;
1302 clock-mult = <1>;
1303 clock-output-names = "cp";
1304 };
1305
1306 /* Gate clocks */
Laurent Pinchartcded80f2013-12-19 16:51:02 +01001307 mstp0_clks: mstp0_clks@e6150130 {
1308 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1309 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1310 clocks = <&mp_clk>;
1311 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001312 clock-indices = <R8A7791_CLK_MSIOF0>;
Laurent Pinchartcded80f2013-12-19 16:51:02 +01001313 clock-output-names = "msiof0";
1314 };
Laurent Pinchart59e79892013-12-11 15:05:16 +01001315 mstp1_clks: mstp1_clks@e6150134 {
1316 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1317 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
Yoshifumi Hosoya74d89d22014-10-14 16:01:43 +09001318 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1319 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1320 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1321 <&zs_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001322 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001323 clock-indices = <
Yoshifumi Hosoya74d89d22014-10-14 16:01:43 +09001324 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1325 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1326 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1327 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1328 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1329 R8A7791_CLK_VSP1_S
Laurent Pinchart59e79892013-12-11 15:05:16 +01001330 >;
1331 clock-output-names =
Yoshifumi Hosoya74d89d22014-10-14 16:01:43 +09001332 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1333 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1334 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
Laurent Pinchart59e79892013-12-11 15:05:16 +01001335 };
1336 mstp2_clks: mstp2_clks@e6150138 {
1337 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1338 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1339 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
Geert Uytterhoeven4e074bc2014-06-02 15:42:07 +02001340 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1341 <&zs_clk>, <&zs_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001342 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001343 clock-indices = <
Laurent Pinchart59e79892013-12-11 15:05:16 +01001344 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
Laurent Pinchartcded80f2013-12-19 16:51:02 +01001345 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1346 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
Geert Uytterhoeven4e074bc2014-06-02 15:42:07 +02001347 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
Laurent Pinchart59e79892013-12-11 15:05:16 +01001348 >;
1349 clock-output-names =
Geert Uytterhoeven0c002ef2014-02-20 15:49:29 +01001350 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
Geert Uytterhoeven4e074bc2014-06-02 15:42:07 +02001351 "scifb1", "msiof1", "scifb2",
1352 "sys-dmac1", "sys-dmac0";
Laurent Pinchart59e79892013-12-11 15:05:16 +01001353 };
1354 mstp3_clks: mstp3_clks@e615013c {
1355 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1356 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
Simon Horman2ea0d4e2015-01-29 10:41:24 +09001357 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
Yoshihiro Shimodab9473d92014-11-17 18:25:25 +09001358 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1359 <&hp_clk>, <&hp_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001360 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001361 clock-indices = <
Wolfram Sangc08691b2014-03-10 12:26:57 +01001362 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
Phil Edworthy4bfb3762014-06-13 10:37:18 +01001363 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1364 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
Yoshihiro Shimodab9473d92014-11-17 18:25:25 +09001365 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
Laurent Pinchart59e79892013-12-11 15:05:16 +01001366 >;
1367 clock-output-names =
Wolfram Sangc08691b2014-03-10 12:26:57 +01001368 "tpu0", "sdhi2", "sdhi1", "sdhi0",
Yoshihiro Shimodab9473d92014-11-17 18:25:25 +09001369 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1370 "usbdmac0", "usbdmac1";
Laurent Pinchart59e79892013-12-11 15:05:16 +01001371 };
Geert Uytterhoeven62d386c2015-03-18 19:56:00 +01001372 mstp4_clks: mstp4_clks@e6150140 {
1373 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1374 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1375 clocks = <&cp_clk>;
1376 #clock-cells = <1>;
1377 clock-indices = <R8A7791_CLK_IRQC>;
1378 clock-output-names = "irqc";
1379 };
Laurent Pinchart59e79892013-12-11 15:05:16 +01001380 mstp5_clks: mstp5_clks@e6150144 {
1381 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1382 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
Sergei Shtylyovae65a8a2014-12-30 23:20:34 +03001383 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1384 <&extal_clk>, <&p_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001385 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001386 clock-indices = <
1387 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
Sergei Shtylyovae65a8a2014-12-30 23:20:34 +03001388 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1389 R8A7791_CLK_PWM
Ben Dookscb0bf852014-11-10 19:49:38 +01001390 >;
Sergei Shtylyovae65a8a2014-12-30 23:20:34 +03001391 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1392 "thermal", "pwm";
Laurent Pinchart59e79892013-12-11 15:05:16 +01001393 };
1394 mstp7_clks: mstp7_clks@e615014c {
1395 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1396 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
Kazuya Mizuguchi118e4e62015-02-19 10:43:10 -05001397 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
Laurent Pinchart59e79892013-12-11 15:05:16 +01001398 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1399 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1400 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001401 clock-indices = <
Magnus Damm6225b992014-04-07 15:04:21 +09001402 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
Laurent Pinchart59e79892013-12-11 15:05:16 +01001403 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1404 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1405 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1406 R8A7791_CLK_LVDS0
1407 >;
1408 clock-output-names =
Magnus Damm6225b992014-04-07 15:04:21 +09001409 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
Laurent Pinchart59e79892013-12-11 15:05:16 +01001410 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1411 };
1412 mstp8_clks: mstp8_clks@e6150990 {
1413 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1414 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
Ryo Kataoka75a499a2015-02-19 22:29:06 +09001415 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
Sergei Shtylyoveaa870b2015-12-03 01:21:49 +03001416 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1417 <&zs_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001418 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001419 clock-indices = <
Andrey Gusakov7408d302014-12-18 23:43:03 +03001420 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
Laurent Pinchart09c98342014-01-07 09:22:54 +01001421 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
Sergei Shtylyoveaa870b2015-12-03 01:21:49 +03001422 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1423 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
Laurent Pinchart09c98342014-01-07 09:22:54 +01001424 >;
Laurent Pinchart65f05c32014-01-07 09:22:56 +01001425 clock-output-names =
Sergei Shtylyoveaa870b2015-12-03 01:21:49 +03001426 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1427 "etheravb", "ether", "sata1", "sata0";
Laurent Pinchart59e79892013-12-11 15:05:16 +01001428 };
1429 mstp9_clks: mstp9_clks@e6150994 {
1430 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1431 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +02001432 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1433 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1434 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
Laurent Pinchart11b48db2014-04-01 13:02:18 +02001435 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1436 <&hp_clk>, <&hp_clk>;
Laurent Pinchart59e79892013-12-11 15:05:16 +01001437 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001438 clock-indices = <
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +02001439 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1440 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
Wolfram Sangc08691b2014-03-10 12:26:57 +01001441 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1442 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1443 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
Laurent Pinchart59e79892013-12-11 15:05:16 +01001444 >;
1445 clock-output-names =
Geert Uytterhoeven4faf9c52014-04-23 10:25:28 +02001446 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1447 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1448 "i2c1", "i2c0";
Laurent Pinchart59e79892013-12-11 15:05:16 +01001449 };
Kuninori Morimotoee914152014-06-11 21:44:16 -07001450 mstp10_clks: mstp10_clks@e6150998 {
1451 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1452 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1453 clocks = <&p_clk>,
1454 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1455 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1456 <&p_clk>,
1457 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1458 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1459 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1460 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1461 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
Kuninori Morimoto88401702015-07-21 00:27:03 +00001462 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
Kuninori Morimotoee914152014-06-11 21:44:16 -07001463 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1464
1465 #clock-cells = <1>;
1466 clock-indices = <
1467 R8A7791_CLK_SSI_ALL
1468 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1469 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1470 R8A7791_CLK_SCU_ALL
1471 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
Kuninori Morimoto88401702015-07-21 00:27:03 +00001472 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
Kuninori Morimotoee914152014-06-11 21:44:16 -07001473 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1474 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1475 >;
1476 clock-output-names =
1477 "ssi-all",
1478 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1479 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1480 "scu-all",
1481 "scu-dvc1", "scu-dvc0",
Kuninori Morimoto88401702015-07-21 00:27:03 +00001482 "scu-ctu1-mix1", "scu-ctu0-mix0",
Kuninori Morimotoee914152014-06-11 21:44:16 -07001483 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1484 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1485 };
Laurent Pinchart59e79892013-12-11 15:05:16 +01001486 mstp11_clks: mstp11_clks@e615099c {
1487 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1488 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1489 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1490 #clock-cells = <1>;
Ben Dookscb0bf852014-11-10 19:49:38 +01001491 clock-indices = <
Laurent Pinchart59e79892013-12-11 15:05:16 +01001492 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1493 >;
1494 clock-output-names = "scifa3", "scifa4", "scifa5";
1495 };
1496 };
Geert Uytterhoeven4d5b59c2014-02-04 16:24:03 +01001497
Geert Uytterhoeven6f3e4ee2014-02-25 11:30:14 +01001498 qspi: spi@e6b10000 {
Geert Uytterhoeven4d5b59c2014-02-04 16:24:03 +01001499 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1500 reg = <0 0xe6b10000 0 0x2c>;
Simon Horman386a9292016-01-15 11:44:16 +09001501 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven4d5b59c2014-02-04 16:24:03 +01001502 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
Geert Uytterhoeven591f2fa2014-08-06 14:59:06 +02001503 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1504 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001505 power-domains = <&cpg_clocks>;
Geert Uytterhoeven4d5b59c2014-02-04 16:24:03 +01001506 num-cs = <1>;
1507 #address-cells = <1>;
1508 #size-cells = <0>;
1509 status = "disabled";
1510 };
Geert Uytterhoeven7713d3a2014-02-25 11:30:16 +01001511
1512 msiof0: spi@e6e20000 {
1513 compatible = "renesas,msiof-r8a7791";
Ryo Kataokacb6d08a2015-04-05 01:55:12 +09001514 reg = <0 0xe6e20000 0 0x0064>;
Simon Horman386a9292016-01-15 11:44:16 +09001515 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven7713d3a2014-02-25 11:30:16 +01001516 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
Geert Uytterhoevena5ce27f2014-08-06 14:59:07 +02001517 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1518 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001519 power-domains = <&cpg_clocks>;
Geert Uytterhoeven7713d3a2014-02-25 11:30:16 +01001520 #address-cells = <1>;
1521 #size-cells = <0>;
1522 status = "disabled";
1523 };
1524
1525 msiof1: spi@e6e10000 {
1526 compatible = "renesas,msiof-r8a7791";
Ryo Kataokacb6d08a2015-04-05 01:55:12 +09001527 reg = <0 0xe6e10000 0 0x0064>;
Simon Horman386a9292016-01-15 11:44:16 +09001528 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven7713d3a2014-02-25 11:30:16 +01001529 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
Geert Uytterhoevena5ce27f2014-08-06 14:59:07 +02001530 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1531 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001532 power-domains = <&cpg_clocks>;
Geert Uytterhoeven7713d3a2014-02-25 11:30:16 +01001533 #address-cells = <1>;
1534 #size-cells = <0>;
1535 status = "disabled";
1536 };
1537
1538 msiof2: spi@e6e00000 {
1539 compatible = "renesas,msiof-r8a7791";
Ryo Kataokacb6d08a2015-04-05 01:55:12 +09001540 reg = <0 0xe6e00000 0 0x0064>;
Simon Horman386a9292016-01-15 11:44:16 +09001541 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven7713d3a2014-02-25 11:30:16 +01001542 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
Geert Uytterhoevena5ce27f2014-08-06 14:59:07 +02001543 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1544 dma-names = "tx", "rx";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001545 power-domains = <&cpg_clocks>;
Geert Uytterhoeven7713d3a2014-02-25 11:30:16 +01001546 #address-cells = <1>;
1547 #size-cells = <0>;
1548 status = "disabled";
1549 };
Phil Edworthy811cdfa2014-06-13 10:37:20 +01001550
Yoshihiro Shimodac1969312014-10-24 19:43:02 +09001551 xhci: usb@ee000000 {
1552 compatible = "renesas,xhci-r8a7791";
1553 reg = <0 0xee000000 0 0xc00>;
Simon Horman386a9292016-01-15 11:44:16 +09001554 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
Yoshihiro Shimodac1969312014-10-24 19:43:02 +09001555 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001556 power-domains = <&cpg_clocks>;
Yoshihiro Shimodac1969312014-10-24 19:43:02 +09001557 phys = <&usb2 1>;
1558 phy-names = "usb";
1559 status = "disabled";
1560 };
1561
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001562 pci0: pci@ee090000 {
Simon Hormand4809682015-12-18 11:42:38 +09001563 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001564 device_type = "pci";
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001565 reg = <0 0xee090000 0 0xc00>,
1566 <0 0xee080000 0 0x1100>;
Simon Horman386a9292016-01-15 11:44:16 +09001567 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001568 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1569 power-domains = <&cpg_clocks>;
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001570 status = "disabled";
1571
1572 bus-range = <0 0>;
1573 #address-cells = <3>;
1574 #size-cells = <2>;
1575 #interrupt-cells = <1>;
1576 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1577 interrupt-map-mask = <0xff00 0 0 0x7>;
Simon Horman386a9292016-01-15 11:44:16 +09001578 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1579 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1580 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove1bce122014-09-29 22:23:11 +04001581
1582 usb@0,1 {
1583 reg = <0x800 0 0 0 0>;
1584 device_type = "pci";
1585 phys = <&usb0 0>;
1586 phy-names = "usb";
1587 };
1588
1589 usb@0,2 {
1590 reg = <0x1000 0 0 0 0>;
1591 device_type = "pci";
1592 phys = <&usb0 0>;
1593 phy-names = "usb";
1594 };
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001595 };
1596
1597 pci1: pci@ee0d0000 {
Simon Hormand4809682015-12-18 11:42:38 +09001598 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001599 device_type = "pci";
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001600 reg = <0 0xee0d0000 0 0xc00>,
1601 <0 0xee0c0000 0 0x1100>;
Simon Horman386a9292016-01-15 11:44:16 +09001602 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001603 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1604 power-domains = <&cpg_clocks>;
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001605 status = "disabled";
1606
1607 bus-range = <1 1>;
1608 #address-cells = <3>;
1609 #size-cells = <2>;
1610 #interrupt-cells = <1>;
1611 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1612 interrupt-map-mask = <0xff00 0 0 0x7>;
Simon Horman386a9292016-01-15 11:44:16 +09001613 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1614 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1615 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyove1bce122014-09-29 22:23:11 +04001616
1617 usb@0,1 {
1618 reg = <0x800 0 0 0 0>;
1619 device_type = "pci";
1620 phys = <&usb2 0>;
1621 phy-names = "usb";
1622 };
1623
1624 usb@0,2 {
1625 reg = <0x1000 0 0 0 0>;
1626 device_type = "pci";
1627 phys = <&usb2 0>;
1628 phy-names = "usb";
1629 };
Sergei Shtylyovaace0802014-06-24 22:10:05 +04001630 };
1631
Phil Edworthy811cdfa2014-06-13 10:37:20 +01001632 pciec: pcie@fe000000 {
Simon Hormanbbb45f62015-12-18 11:36:03 +09001633 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
Phil Edworthy811cdfa2014-06-13 10:37:20 +01001634 reg = <0 0xfe000000 0 0x80000>;
1635 #address-cells = <3>;
1636 #size-cells = <2>;
1637 bus-range = <0x00 0xff>;
1638 device_type = "pci";
1639 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1640 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1641 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1642 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1643 /* Map all possible DDR as inbound ranges */
1644 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1645 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
Simon Horman386a9292016-01-15 11:44:16 +09001646 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1647 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1648 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
Phil Edworthy811cdfa2014-06-13 10:37:20 +01001649 #interrupt-cells = <1>;
1650 interrupt-map-mask = <0 0 0 0>;
Simon Horman386a9292016-01-15 11:44:16 +09001651 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
Phil Edworthy811cdfa2014-06-13 10:37:20 +01001652 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1653 clock-names = "pcie", "pcie_bus";
Geert Uytterhoeven797a0622015-08-04 14:28:11 +02001654 power-domains = <&cpg_clocks>;
Phil Edworthy811cdfa2014-06-13 10:37:20 +01001655 status = "disabled";
1656 };
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001657
Laurent Pinchartf1951852015-01-27 11:13:24 +02001658 ipmmu_sy0: mmu@e6280000 {
Magnus Damm3c8ab0c2015-11-17 13:31:05 +09001659 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
Laurent Pinchartf1951852015-01-27 11:13:24 +02001660 reg = <0 0xe6280000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001661 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1662 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf1951852015-01-27 11:13:24 +02001663 #iommu-cells = <1>;
1664 status = "disabled";
1665 };
1666
1667 ipmmu_sy1: mmu@e6290000 {
Magnus Damm3c8ab0c2015-11-17 13:31:05 +09001668 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
Laurent Pinchartf1951852015-01-27 11:13:24 +02001669 reg = <0 0xe6290000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001670 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf1951852015-01-27 11:13:24 +02001671 #iommu-cells = <1>;
1672 status = "disabled";
1673 };
1674
1675 ipmmu_ds: mmu@e6740000 {
Magnus Damm3c8ab0c2015-11-17 13:31:05 +09001676 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
Laurent Pinchartf1951852015-01-27 11:13:24 +02001677 reg = <0 0xe6740000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001678 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1679 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf1951852015-01-27 11:13:24 +02001680 #iommu-cells = <1>;
1681 status = "disabled";
1682 };
1683
1684 ipmmu_mp: mmu@ec680000 {
Magnus Damm3c8ab0c2015-11-17 13:31:05 +09001685 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
Laurent Pinchartf1951852015-01-27 11:13:24 +02001686 reg = <0 0xec680000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001687 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf1951852015-01-27 11:13:24 +02001688 #iommu-cells = <1>;
1689 status = "disabled";
1690 };
1691
1692 ipmmu_mx: mmu@fe951000 {
Magnus Damm3c8ab0c2015-11-17 13:31:05 +09001693 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
Laurent Pinchartf1951852015-01-27 11:13:24 +02001694 reg = <0 0xfe951000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001695 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1696 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf1951852015-01-27 11:13:24 +02001697 #iommu-cells = <1>;
1698 status = "disabled";
1699 };
1700
1701 ipmmu_rt: mmu@ffc80000 {
Magnus Damm3c8ab0c2015-11-17 13:31:05 +09001702 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
Laurent Pinchartf1951852015-01-27 11:13:24 +02001703 reg = <0 0xffc80000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001704 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf1951852015-01-27 11:13:24 +02001705 #iommu-cells = <1>;
1706 status = "disabled";
1707 };
1708
1709 ipmmu_gp: mmu@e62a0000 {
Magnus Damm3c8ab0c2015-11-17 13:31:05 +09001710 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
Laurent Pinchartf1951852015-01-27 11:13:24 +02001711 reg = <0 0xe62a0000 0 0x1000>;
Simon Horman386a9292016-01-15 11:44:16 +09001712 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1713 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf1951852015-01-27 11:13:24 +02001714 #iommu-cells = <1>;
1715 status = "disabled";
1716 };
1717
Geert Uytterhoeven6c63e072015-04-27 14:55:29 +02001718 rcar_sound: sound@ec500000 {
Kuninori Morimotod2b541c2014-12-17 06:12:02 +00001719 /*
1720 * #sound-dai-cells is required
1721 *
1722 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1723 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1724 */
Geert Uytterhoevenf49cd2b2015-01-06 21:01:53 +01001725 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001726 reg = <0 0xec500000 0 0x1000>, /* SCU */
1727 <0 0xec5a0000 0 0x100>, /* ADG */
1728 <0 0xec540000 0 0x1000>, /* SSIU */
Kuninori Morimoto8c3f9032015-08-24 08:28:17 +00001729 <0 0xec541000 0 0x280>, /* SSI */
Kuninori Morimotod73a5012015-03-10 01:39:55 +00001730 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1731 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
Kuninori Morimotod88a6a22015-03-10 01:39:18 +00001732
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001733 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1734 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1735 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1736 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1737 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1738 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1739 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1740 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1741 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1742 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1743 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
Kuninori Morimoto88401702015-07-21 00:27:03 +00001744 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
Kuninori Morimoto7fd6e112015-07-21 00:27:24 +00001745 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
Kuninori Morimoto150c8ad2014-06-25 17:52:33 -07001746 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001747 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1748 clock-names = "ssi-all",
1749 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1750 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1751 "src.9", "src.8", "src.7", "src.6", "src.5",
1752 "src.4", "src.3", "src.2", "src.1", "src.0",
Kuninori Morimoto88401702015-07-21 00:27:03 +00001753 "ctu.0", "ctu.1",
Kuninori Morimoto7fd6e112015-07-21 00:27:24 +00001754 "mix.0", "mix.1",
Kuninori Morimoto150c8ad2014-06-25 17:52:33 -07001755 "dvc.0", "dvc.1",
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001756 "clk_a", "clk_b", "clk_c", "clk_i";
Geert Uytterhoeven56e86dd2015-08-20 01:25:20 +00001757 power-domains = <&cpg_clocks>;
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001758
1759 status = "disabled";
1760
Kuninori Morimoto150c8ad2014-06-25 17:52:33 -07001761 rcar_sound,dvc {
Kuninori Morimoto63573332015-03-10 01:40:27 +00001762 dvc0: dvc@0 {
1763 dmas = <&audma0 0xbc>;
1764 dma-names = "tx";
1765 };
1766 dvc1: dvc@1 {
1767 dmas = <&audma0 0xbe>;
1768 dma-names = "tx";
1769 };
Kuninori Morimoto150c8ad2014-06-25 17:52:33 -07001770 };
1771
Kuninori Morimoto7fd6e112015-07-21 00:27:24 +00001772 rcar_sound,mix {
1773 mix0: mix@0 { };
1774 mix1: mix@1 { };
1775 };
1776
Kuninori Morimoto88401702015-07-21 00:27:03 +00001777 rcar_sound,ctu {
1778 ctu00: ctu@0 { };
1779 ctu01: ctu@1 { };
1780 ctu02: ctu@2 { };
1781 ctu03: ctu@3 { };
1782 ctu10: ctu@4 { };
1783 ctu11: ctu@5 { };
1784 ctu12: ctu@6 { };
1785 ctu13: ctu@7 { };
1786 };
1787
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001788 rcar_sound,src {
Kuninori Morimoto63573332015-03-10 01:40:27 +00001789 src0: src@0 {
Simon Horman386a9292016-01-15 11:44:16 +09001790 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001791 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1792 dma-names = "rx", "tx";
1793 };
1794 src1: src@1 {
Simon Horman386a9292016-01-15 11:44:16 +09001795 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001796 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1797 dma-names = "rx", "tx";
1798 };
1799 src2: src@2 {
Simon Horman386a9292016-01-15 11:44:16 +09001800 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001801 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1802 dma-names = "rx", "tx";
1803 };
1804 src3: src@3 {
Simon Horman386a9292016-01-15 11:44:16 +09001805 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001806 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1807 dma-names = "rx", "tx";
1808 };
1809 src4: src@4 {
Simon Horman386a9292016-01-15 11:44:16 +09001810 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001811 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1812 dma-names = "rx", "tx";
1813 };
1814 src5: src@5 {
Simon Horman386a9292016-01-15 11:44:16 +09001815 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001816 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1817 dma-names = "rx", "tx";
1818 };
1819 src6: src@6 {
Simon Horman386a9292016-01-15 11:44:16 +09001820 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001821 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1822 dma-names = "rx", "tx";
1823 };
1824 src7: src@7 {
Simon Horman386a9292016-01-15 11:44:16 +09001825 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001826 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1827 dma-names = "rx", "tx";
1828 };
1829 src8: src@8 {
Simon Horman386a9292016-01-15 11:44:16 +09001830 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001831 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1832 dma-names = "rx", "tx";
1833 };
1834 src9: src@9 {
Simon Horman386a9292016-01-15 11:44:16 +09001835 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001836 dmas = <&audma0 0x97>, <&audma1 0xba>;
1837 dma-names = "rx", "tx";
1838 };
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001839 };
1840
1841 rcar_sound,ssi {
Kuninori Morimoto63573332015-03-10 01:40:27 +00001842 ssi0: ssi@0 {
Simon Horman386a9292016-01-15 11:44:16 +09001843 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001844 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1845 dma-names = "rx", "tx", "rxu", "txu";
1846 };
1847 ssi1: ssi@1 {
Simon Horman386a9292016-01-15 11:44:16 +09001848 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001849 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1850 dma-names = "rx", "tx", "rxu", "txu";
1851 };
1852 ssi2: ssi@2 {
Simon Horman386a9292016-01-15 11:44:16 +09001853 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001854 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1855 dma-names = "rx", "tx", "rxu", "txu";
1856 };
1857 ssi3: ssi@3 {
Simon Horman386a9292016-01-15 11:44:16 +09001858 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001859 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1860 dma-names = "rx", "tx", "rxu", "txu";
1861 };
1862 ssi4: ssi@4 {
Simon Horman386a9292016-01-15 11:44:16 +09001863 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001864 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1865 dma-names = "rx", "tx", "rxu", "txu";
1866 };
1867 ssi5: ssi@5 {
Simon Horman386a9292016-01-15 11:44:16 +09001868 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001869 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1870 dma-names = "rx", "tx", "rxu", "txu";
1871 };
1872 ssi6: ssi@6 {
Simon Horman386a9292016-01-15 11:44:16 +09001873 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001874 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1875 dma-names = "rx", "tx", "rxu", "txu";
1876 };
1877 ssi7: ssi@7 {
Simon Horman386a9292016-01-15 11:44:16 +09001878 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001879 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1880 dma-names = "rx", "tx", "rxu", "txu";
1881 };
1882 ssi8: ssi@8 {
Simon Horman386a9292016-01-15 11:44:16 +09001883 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001884 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1885 dma-names = "rx", "tx", "rxu", "txu";
1886 };
1887 ssi9: ssi@9 {
Simon Horman386a9292016-01-15 11:44:16 +09001888 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto63573332015-03-10 01:40:27 +00001889 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1890 dma-names = "rx", "tx", "rxu", "txu";
1891 };
Kuninori Morimoto09abd1f2014-06-11 21:44:26 -07001892 };
1893 };
Hisashi Nakamura0d0771ab2013-09-04 12:45:57 +09001894};