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gerrit-public.fairphone.software / kernel / msm-4.19 / c2791b806988100cc1c047e2b0b5c5d0914aa3b6 / . / drivers / pci / host / pcie-designware.h
blob: d0bbd276840dfcac4e7a66ba7ca7ad1f7a623e6e [file] [log] [blame]
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]1/*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
Seungwon Jeon18edf452013-10-09 09:12:21 -0600[diff] [blame]14#ifndef _PCIE_DESIGNWARE_H
15#define _PCIE_DESIGNWARE_H
16
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]17/*
18 * Maximum number of MSI IRQs can be 256 per controller. But keep
19 * it 32 as of now. Probably we will never need more than 32. If needed,
20 * then increment it in multiple of 32.
21 */
22#define MAX_MSI_IRQS 32
23#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
24
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]25struct pcie_port {
26 struct device *dev;
27 u8 root_bus_nr;
28 void __iomem *dbi_base;
29 u64 cfg0_base;
Kishon Vijay Abraham If4c55c52014-07-17 14:30:41 +0530[diff] [blame]30 u64 cfg0_mod_base;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]31 void __iomem *va_cfg0_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600[diff] [blame]32 u32 cfg0_size;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]33 u64 cfg1_base;
Kishon Vijay Abraham If4c55c52014-07-17 14:30:41 +0530[diff] [blame]34 u64 cfg1_mod_base;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]35 void __iomem *va_cfg1_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600[diff] [blame]36 u32 cfg1_size;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]37 u64 io_base;
Kishon Vijay Abraham If4c55c52014-07-17 14:30:41 +0530[diff] [blame]38 u64 io_mod_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600[diff] [blame]39 phys_addr_t io_bus_addr;
40 u32 io_size;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]41 u64 mem_base;
Kishon Vijay Abraham If4c55c52014-07-17 14:30:41 +0530[diff] [blame]42 u64 mem_mod_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600[diff] [blame]43 phys_addr_t mem_bus_addr;
44 u32 mem_size;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]45 struct resource cfg;
46 struct resource io;
47 struct resource mem;
Lucas Stach4f2ebe02014-07-23 19:52:38 +0200[diff] [blame]48 struct resource busn;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]49 int irq;
50 u32 lanes;
51 struct pcie_host_ops *ops;
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]52 int msi_irq;
Pratyush Anand904d0e72013-10-09 21:32:12 +0900[diff] [blame]53 struct irq_domain *irq_domain;
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]54 unsigned long msi_data;
55 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]56};
57
58struct pcie_host_ops {
59 void (*readl_rc)(struct pcie_port *pp,
60 void __iomem *dbi_base, u32 *val);
61 void (*writel_rc)(struct pcie_port *pp,
62 u32 val, void __iomem *dbi_base);
63 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
64 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
Murali Karicheria1c0ae92014-07-21 12:58:41 -0400[diff] [blame]65 int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
66 unsigned int devfn, int where, int size, u32 *val);
67 int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
68 unsigned int devfn, int where, int size, u32 val);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]69 int (*link_up)(struct pcie_port *pp);
70 void (*host_init)(struct pcie_port *pp);
Murali Karicheri2f37c5a2014-07-21 12:58:42 -0400[diff] [blame]71 void (*msi_set_irq)(struct pcie_port *pp, int irq);
72 void (*msi_clear_irq)(struct pcie_port *pp, int irq);
Minghuan Lian450e3442014-09-23 22:28:58 +0800[diff] [blame]73 u32 (*get_msi_addr)(struct pcie_port *pp);
Minghuan Lian24832b42014-09-23 22:28:59 +0800[diff] [blame]74 u32 (*get_msi_data)(struct pcie_port *pp, int pos);
Murali Karicherib14a3d12014-07-23 14:54:51 -0400[diff] [blame]75 void (*scan_bus)(struct pcie_port *pp);
Yijing Wangc2791b82014-11-11 17:45:45 -0700[diff] [blame^]76 int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]77};
78
Pratyush Ananda01ef592013-12-11 15:08:32 +0530[diff] [blame]79int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
80int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
Lucas Stach7f4f16e2014-03-28 17:52:58 +0100[diff] [blame]81irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
Jingoo Hanf342d942013-09-06 15:54:59 +0900[diff] [blame]82void dw_pcie_msi_init(struct pcie_port *pp);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900[diff] [blame]83int dw_pcie_link_up(struct pcie_port *pp);
84void dw_pcie_setup_rc(struct pcie_port *pp);
85int dw_pcie_host_init(struct pcie_port *pp);
Seungwon Jeon18edf452013-10-09 09:12:21 -0600[diff] [blame]86
87#endif /* _PCIE_DESIGNWARE_H */