Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 1 | /* |
Vineet Gupta | c4c9a04 | 2016-10-31 13:46:38 -0700 | [diff] [blame] | 2 | * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 3 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 8 | */ |
| 9 | |
Vineet Gupta | c4c9a04 | 2016-10-31 13:46:38 -0700 | [diff] [blame] | 10 | /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be |
| 11 | * programmed to go from @count to @limit and optionally interrupt. |
| 12 | * We've designated TIMER0 for clockevents and TIMER1 for clocksource |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 13 | * |
Vineet Gupta | c4c9a04 | 2016-10-31 13:46:38 -0700 | [diff] [blame] | 14 | * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP) |
| 15 | * which are suitable for UP and SMP based clocksources respectively |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 16 | */ |
| 17 | |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 18 | #include <linux/interrupt.h> |
Noam Camus | 69fbd09 | 2016-01-14 12:20:08 +0530 | [diff] [blame] | 19 | #include <linux/clk.h> |
| 20 | #include <linux/clk-provider.h> |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 21 | #include <linux/clocksource.h> |
| 22 | #include <linux/clockchips.h> |
Noam Camus | eec3c58 | 2016-01-01 15:48:49 +0530 | [diff] [blame] | 23 | #include <linux/cpu.h> |
Vineet Gupta | 77c8d0d | 2016-01-01 17:58:45 +0530 | [diff] [blame] | 24 | #include <linux/of.h> |
| 25 | #include <linux/of_irq.h> |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 26 | |
Vineet Gupta | b26c2e3 | 2016-10-31 13:06:19 -0700 | [diff] [blame] | 27 | #include <soc/arc/timers.h> |
Vineet Gupta | 2d7f5c4 | 2016-10-31 11:27:08 -0700 | [diff] [blame] | 28 | #include <soc/arc/mcip.h> |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 29 | |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 30 | |
Vineet Gupta | 77c8d0d | 2016-01-01 17:58:45 +0530 | [diff] [blame] | 31 | static unsigned long arc_timer_freq; |
| 32 | |
| 33 | static int noinline arc_get_timer_clk(struct device_node *node) |
| 34 | { |
| 35 | struct clk *clk; |
| 36 | int ret; |
| 37 | |
| 38 | clk = of_clk_get(node, 0); |
| 39 | if (IS_ERR(clk)) { |
| 40 | pr_err("timer missing clk"); |
| 41 | return PTR_ERR(clk); |
| 42 | } |
| 43 | |
| 44 | ret = clk_prepare_enable(clk); |
| 45 | if (ret) { |
| 46 | pr_err("Couldn't enable parent clk\n"); |
| 47 | return ret; |
| 48 | } |
| 49 | |
| 50 | arc_timer_freq = clk_get_rate(clk); |
| 51 | |
| 52 | return 0; |
| 53 | } |
| 54 | |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 55 | /********** Clock Source Device *********/ |
| 56 | |
Vineet Gupta | 0442142 | 2016-10-31 14:26:41 -0700 | [diff] [blame] | 57 | #ifdef CONFIG_ARC_TIMERS_64BIT |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 58 | |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 59 | static u64 arc_read_gfrc(struct clocksource *cs) |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 60 | { |
| 61 | unsigned long flags; |
Vineet Gupta | 2cd690e | 2016-11-03 11:38:52 -0700 | [diff] [blame] | 62 | u32 l, h; |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 63 | |
| 64 | local_irq_save(flags); |
| 65 | |
Vineet Gupta | d584f0f | 2016-01-22 14:27:50 +0530 | [diff] [blame] | 66 | __mcip_cmd(CMD_GFRC_READ_LO, 0); |
Vineet Gupta | 2cd690e | 2016-11-03 11:38:52 -0700 | [diff] [blame] | 67 | l = read_aux_reg(ARC_REG_MCIP_READBACK); |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 68 | |
Vineet Gupta | d584f0f | 2016-01-22 14:27:50 +0530 | [diff] [blame] | 69 | __mcip_cmd(CMD_GFRC_READ_HI, 0); |
Vineet Gupta | 2cd690e | 2016-11-03 11:38:52 -0700 | [diff] [blame] | 70 | h = read_aux_reg(ARC_REG_MCIP_READBACK); |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 71 | |
| 72 | local_irq_restore(flags); |
| 73 | |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 74 | return (((u64)h) << 32) | l; |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 75 | } |
| 76 | |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 77 | static struct clocksource arc_counter_gfrc = { |
Vineet Gupta | d584f0f | 2016-01-22 14:27:50 +0530 | [diff] [blame] | 78 | .name = "ARConnect GFRC", |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 79 | .rating = 400, |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 80 | .read = arc_read_gfrc, |
Vineet Gupta | 72d7288 | 2014-12-24 18:41:55 +0530 | [diff] [blame] | 81 | .mask = CLOCKSOURCE_MASK(64), |
| 82 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 83 | }; |
| 84 | |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 85 | static int __init arc_cs_setup_gfrc(struct device_node *node) |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 86 | { |
Vineet Gupta | ec7cb87 | 2016-10-31 13:02:31 -0700 | [diff] [blame] | 87 | struct mcip_bcr mp; |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 88 | int ret; |
| 89 | |
Vineet Gupta | ec7cb87 | 2016-10-31 13:02:31 -0700 | [diff] [blame] | 90 | READ_BCR(ARC_REG_MCIP_BCR, mp); |
| 91 | if (!mp.gfrc) { |
| 92 | pr_warn("Global-64-bit-Ctr clocksource not detected"); |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 93 | return -ENXIO; |
Vineet Gupta | ec7cb87 | 2016-10-31 13:02:31 -0700 | [diff] [blame] | 94 | } |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 95 | |
| 96 | ret = arc_get_timer_clk(node); |
| 97 | if (ret) |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 98 | return ret; |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 99 | |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 100 | return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 101 | } |
Daniel Lezcano | 177cf6e | 2016-06-07 00:27:44 +0200 | [diff] [blame] | 102 | CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 103 | |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 104 | #define AUX_RTC_CTRL 0x103 |
| 105 | #define AUX_RTC_LOW 0x104 |
| 106 | #define AUX_RTC_HIGH 0x105 |
| 107 | |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 108 | static u64 arc_read_rtc(struct clocksource *cs) |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 109 | { |
| 110 | unsigned long status; |
Vineet Gupta | 2cd690e | 2016-11-03 11:38:52 -0700 | [diff] [blame] | 111 | u32 l, h; |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 112 | |
Vineet Gupta | 922cc17 | 2016-10-31 14:09:52 -0700 | [diff] [blame] | 113 | /* |
| 114 | * hardware has an internal state machine which tracks readout of |
| 115 | * low/high and updates the CTRL.status if |
| 116 | * - interrupt/exception taken between the two reads |
| 117 | * - high increments after low has been read |
| 118 | */ |
| 119 | do { |
Vineet Gupta | 2cd690e | 2016-11-03 11:38:52 -0700 | [diff] [blame] | 120 | l = read_aux_reg(AUX_RTC_LOW); |
| 121 | h = read_aux_reg(AUX_RTC_HIGH); |
Vineet Gupta | 922cc17 | 2016-10-31 14:09:52 -0700 | [diff] [blame] | 122 | status = read_aux_reg(AUX_RTC_CTRL); |
| 123 | } while (!(status & _BITUL(31))); |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 124 | |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 125 | return (((u64)h) << 32) | l; |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 126 | } |
| 127 | |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 128 | static struct clocksource arc_counter_rtc = { |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 129 | .name = "ARCv2 RTC", |
| 130 | .rating = 350, |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 131 | .read = arc_read_rtc, |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 132 | .mask = CLOCKSOURCE_MASK(64), |
| 133 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 134 | }; |
| 135 | |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 136 | static int __init arc_cs_setup_rtc(struct device_node *node) |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 137 | { |
Vineet Gupta | ec7cb87 | 2016-10-31 13:02:31 -0700 | [diff] [blame] | 138 | struct bcr_timer timer; |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 139 | int ret; |
| 140 | |
Vineet Gupta | ec7cb87 | 2016-10-31 13:02:31 -0700 | [diff] [blame] | 141 | READ_BCR(ARC_REG_TIMERS_BCR, timer); |
| 142 | if (!timer.rtc) { |
| 143 | pr_warn("Local-64-bit-Ctr clocksource not detected"); |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 144 | return -ENXIO; |
Vineet Gupta | ec7cb87 | 2016-10-31 13:02:31 -0700 | [diff] [blame] | 145 | } |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 146 | |
| 147 | /* Local to CPU hence not usable in SMP */ |
Vineet Gupta | ec7cb87 | 2016-10-31 13:02:31 -0700 | [diff] [blame] | 148 | if (IS_ENABLED(CONFIG_SMP)) { |
| 149 | pr_warn("Local-64-bit-Ctr not usable in SMP"); |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 150 | return -EINVAL; |
Vineet Gupta | ec7cb87 | 2016-10-31 13:02:31 -0700 | [diff] [blame] | 151 | } |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 152 | |
| 153 | ret = arc_get_timer_clk(node); |
| 154 | if (ret) |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 155 | return ret; |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 156 | |
| 157 | write_aux_reg(AUX_RTC_CTRL, 1); |
| 158 | |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 159 | return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 160 | } |
Daniel Lezcano | 177cf6e | 2016-06-07 00:27:44 +0200 | [diff] [blame] | 161 | CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 162 | |
| 163 | #endif |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 164 | |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 165 | /* |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 166 | * 32bit TIMER1 to keep counting monotonically and wraparound |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 167 | */ |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 168 | |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 169 | static u64 arc_read_timer1(struct clocksource *cs) |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 170 | { |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 171 | return (u64) read_aux_reg(ARC_REG_TIMER1_CNT); |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 172 | } |
| 173 | |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 174 | static struct clocksource arc_counter_timer1 = { |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 175 | .name = "ARC Timer1", |
| 176 | .rating = 300, |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 177 | .read = arc_read_timer1, |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 178 | .mask = CLOCKSOURCE_MASK(32), |
| 179 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 180 | }; |
| 181 | |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 182 | static int __init arc_cs_setup_timer1(struct device_node *node) |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 183 | { |
| 184 | int ret; |
| 185 | |
| 186 | /* Local to CPU hence not usable in SMP */ |
| 187 | if (IS_ENABLED(CONFIG_SMP)) |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 188 | return -EINVAL; |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 189 | |
| 190 | ret = arc_get_timer_clk(node); |
| 191 | if (ret) |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 192 | return ret; |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 193 | |
Vineet Gupta | b26c2e3 | 2016-10-31 13:06:19 -0700 | [diff] [blame] | 194 | write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 195 | write_aux_reg(ARC_REG_TIMER1_CNT, 0); |
| 196 | write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); |
| 197 | |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 198 | return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq); |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 199 | } |
Vineet Gupta | aa93e8e | 2013-11-07 14:57:16 +0530 | [diff] [blame] | 200 | |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 201 | /********** Clock Event Device *********/ |
| 202 | |
Vineet Gupta | 77c8d0d | 2016-01-01 17:58:45 +0530 | [diff] [blame] | 203 | static int arc_timer_irq; |
Noam Camus | eec3c58 | 2016-01-01 15:48:49 +0530 | [diff] [blame] | 204 | |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 205 | /* |
Vineet Gupta | c9a98e18 | 2014-06-25 17:14:03 +0530 | [diff] [blame] | 206 | * Arm the timer to interrupt after @cycles |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 207 | * The distinction for oneshot/periodic is done in arc_event_timer_ack() below |
| 208 | */ |
Vineet Gupta | c9a98e18 | 2014-06-25 17:14:03 +0530 | [diff] [blame] | 209 | static void arc_timer_event_setup(unsigned int cycles) |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 210 | { |
Vineet Gupta | c9a98e18 | 2014-06-25 17:14:03 +0530 | [diff] [blame] | 211 | write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 212 | write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ |
| 213 | |
| 214 | write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); |
| 215 | } |
| 216 | |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 217 | |
| 218 | static int arc_clkevent_set_next_event(unsigned long delta, |
| 219 | struct clock_event_device *dev) |
| 220 | { |
| 221 | arc_timer_event_setup(delta); |
| 222 | return 0; |
| 223 | } |
| 224 | |
Viresh Kumar | aeec6cd | 2015-07-16 16:56:14 +0530 | [diff] [blame] | 225 | static int arc_clkevent_set_periodic(struct clock_event_device *dev) |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 226 | { |
Viresh Kumar | aeec6cd | 2015-07-16 16:56:14 +0530 | [diff] [blame] | 227 | /* |
| 228 | * At X Hz, 1 sec = 1000ms -> X cycles; |
| 229 | * 10ms -> X / 100 cycles |
| 230 | */ |
Vineet Gupta | 77c8d0d | 2016-01-01 17:58:45 +0530 | [diff] [blame] | 231 | arc_timer_event_setup(arc_timer_freq / HZ); |
Viresh Kumar | aeec6cd | 2015-07-16 16:56:14 +0530 | [diff] [blame] | 232 | return 0; |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 233 | } |
| 234 | |
| 235 | static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { |
Viresh Kumar | aeec6cd | 2015-07-16 16:56:14 +0530 | [diff] [blame] | 236 | .name = "ARC Timer0", |
| 237 | .features = CLOCK_EVT_FEAT_ONESHOT | |
| 238 | CLOCK_EVT_FEAT_PERIODIC, |
| 239 | .rating = 300, |
Viresh Kumar | aeec6cd | 2015-07-16 16:56:14 +0530 | [diff] [blame] | 240 | .set_next_event = arc_clkevent_set_next_event, |
| 241 | .set_state_periodic = arc_clkevent_set_periodic, |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 242 | }; |
| 243 | |
| 244 | static irqreturn_t timer_irq_handler(int irq, void *dev_id) |
| 245 | { |
Vineet Gupta | f8b34c3 | 2014-01-25 00:42:37 +0530 | [diff] [blame] | 246 | /* |
| 247 | * Note that generic IRQ core could have passed @evt for @dev_id if |
| 248 | * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() |
| 249 | */ |
| 250 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); |
Viresh Kumar | aeec6cd | 2015-07-16 16:56:14 +0530 | [diff] [blame] | 251 | int irq_reenable = clockevent_state_periodic(evt); |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 252 | |
Vineet Gupta | f8b34c3 | 2014-01-25 00:42:37 +0530 | [diff] [blame] | 253 | /* |
| 254 | * Any write to CTRL reg ACks the interrupt, we rewrite the |
| 255 | * Count when [N]ot [H]alted bit. |
| 256 | * And re-arm it if perioid by [I]nterrupt [E]nable bit |
| 257 | */ |
| 258 | write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); |
| 259 | |
| 260 | evt->event_handler(evt); |
| 261 | |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 262 | return IRQ_HANDLED; |
| 263 | } |
| 264 | |
Anna-Maria Gleixner | ecd8081 | 2016-07-13 17:17:07 +0000 | [diff] [blame] | 265 | |
| 266 | static int arc_timer_starting_cpu(unsigned int cpu) |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 267 | { |
Vineet Gupta | 2d4899f | 2014-05-08 14:06:38 +0530 | [diff] [blame] | 268 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 269 | |
Noam Camus | eec3c58 | 2016-01-01 15:48:49 +0530 | [diff] [blame] | 270 | evt->cpumask = cpumask_of(smp_processor_id()); |
| 271 | |
Vineet Gupta | b26c2e3 | 2016-10-31 13:06:19 -0700 | [diff] [blame] | 272 | clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX); |
Anna-Maria Gleixner | ecd8081 | 2016-07-13 17:17:07 +0000 | [diff] [blame] | 273 | enable_percpu_irq(arc_timer_irq, 0); |
| 274 | return 0; |
Noam Camus | eec3c58 | 2016-01-01 15:48:49 +0530 | [diff] [blame] | 275 | } |
| 276 | |
Anna-Maria Gleixner | ecd8081 | 2016-07-13 17:17:07 +0000 | [diff] [blame] | 277 | static int arc_timer_dying_cpu(unsigned int cpu) |
| 278 | { |
| 279 | disable_percpu_irq(arc_timer_irq); |
| 280 | return 0; |
| 281 | } |
Noam Camus | eec3c58 | 2016-01-01 15:48:49 +0530 | [diff] [blame] | 282 | |
| 283 | /* |
| 284 | * clockevent setup for boot CPU |
| 285 | */ |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 286 | static int __init arc_clockevent_setup(struct device_node *node) |
Noam Camus | eec3c58 | 2016-01-01 15:48:49 +0530 | [diff] [blame] | 287 | { |
| 288 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); |
| 289 | int ret; |
| 290 | |
Vineet Gupta | 77c8d0d | 2016-01-01 17:58:45 +0530 | [diff] [blame] | 291 | arc_timer_irq = irq_of_parse_and_map(node, 0); |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 292 | if (arc_timer_irq <= 0) { |
| 293 | pr_err("clockevent: missing irq"); |
| 294 | return -EINVAL; |
| 295 | } |
Vineet Gupta | 77c8d0d | 2016-01-01 17:58:45 +0530 | [diff] [blame] | 296 | |
| 297 | ret = arc_get_timer_clk(node); |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 298 | if (ret) { |
| 299 | pr_err("clockevent: missing clk"); |
| 300 | return ret; |
| 301 | } |
Vineet Gupta | 77c8d0d | 2016-01-01 17:58:45 +0530 | [diff] [blame] | 302 | |
Noam Camus | eec3c58 | 2016-01-01 15:48:49 +0530 | [diff] [blame] | 303 | /* Needs apriori irq_set_percpu_devid() done in intc map function */ |
| 304 | ret = request_percpu_irq(arc_timer_irq, timer_irq_handler, |
| 305 | "Timer0 (per-cpu-tick)", evt); |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 306 | if (ret) { |
| 307 | pr_err("clockevent: unable to request irq\n"); |
| 308 | return ret; |
| 309 | } |
Vineet Gupta | 5695794 | 2016-01-28 12:56:03 +0530 | [diff] [blame] | 310 | |
Anna-Maria Gleixner | ecd8081 | 2016-07-13 17:17:07 +0000 | [diff] [blame] | 311 | ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING, |
Thomas Gleixner | 73c1b41 | 2016-12-21 20:19:54 +0100 | [diff] [blame] | 312 | "clockevents/arc/timer:starting", |
Anna-Maria Gleixner | ecd8081 | 2016-07-13 17:17:07 +0000 | [diff] [blame] | 313 | arc_timer_starting_cpu, |
| 314 | arc_timer_dying_cpu); |
| 315 | if (ret) { |
| 316 | pr_err("Failed to setup hotplug state"); |
| 317 | return ret; |
| 318 | } |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 319 | return 0; |
Vineet Gupta | d8005e6 | 2013-01-18 15:12:18 +0530 | [diff] [blame] | 320 | } |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 321 | |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 322 | static int __init arc_of_timer_init(struct device_node *np) |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 323 | { |
| 324 | static int init_count = 0; |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 325 | int ret; |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 326 | |
| 327 | if (!init_count) { |
| 328 | init_count = 1; |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 329 | ret = arc_clockevent_setup(np); |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 330 | } else { |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 331 | ret = arc_cs_setup_timer1(np); |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 332 | } |
Daniel Lezcano | 43d7560 | 2016-06-15 14:50:12 +0200 | [diff] [blame] | 333 | |
| 334 | return ret; |
Vineet Gupta | e608b53 | 2016-01-01 18:05:48 +0530 | [diff] [blame] | 335 | } |
Daniel Lezcano | 177cf6e | 2016-06-07 00:27:44 +0200 | [diff] [blame] | 336 | CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init); |