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Stephen Warrena50a3992011-01-07 22:36:15 -07001/*
2 * tegra_asoc_utils.c - Harmony machine ASoC driver
3 *
4 * Author: Stephen Warren <swarren@nvidia.com>
Stephen Warrenc2f67022012-04-06 11:15:55 -06005 * Copyright (C) 2010,2012 - NVIDIA, Inc.
Stephen Warrena50a3992011-01-07 22:36:15 -07006 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#include <linux/clk.h>
Stephen Warrend64e57c2011-01-28 14:26:40 -070024#include <linux/device.h>
Stephen Warrena50a3992011-01-07 22:36:15 -070025#include <linux/err.h>
26#include <linux/kernel.h>
Paul Gortmakerda155d52011-07-15 12:38:28 -040027#include <linux/module.h>
Stephen Warrenc2f67022012-04-06 11:15:55 -060028#include <linux/of.h>
Stephen Warrena50a3992011-01-07 22:36:15 -070029
30#include "tegra_asoc_utils.h"
31
Stephen Warrend64e57c2011-01-28 14:26:40 -070032int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
Stephen Warren07541392011-04-19 15:25:09 -060033 int mclk)
Stephen Warrena50a3992011-01-07 22:36:15 -070034{
35 int new_baseclock;
Stephen Warren07541392011-04-19 15:25:09 -060036 bool clk_change;
Stephen Warrena50a3992011-01-07 22:36:15 -070037 int err;
38
39 switch (srate) {
40 case 11025:
41 case 22050:
42 case 44100:
43 case 88200:
Stephen Warrenc2f67022012-04-06 11:15:55 -060044 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
45 new_baseclock = 56448000;
46 else
47 new_baseclock = 564480000;
Stephen Warrena50a3992011-01-07 22:36:15 -070048 break;
49 case 8000:
50 case 16000:
51 case 32000:
52 case 48000:
53 case 64000:
54 case 96000:
Stephen Warrenc2f67022012-04-06 11:15:55 -060055 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
56 new_baseclock = 73728000;
57 else
58 new_baseclock = 552960000;
Stephen Warrena50a3992011-01-07 22:36:15 -070059 break;
60 default:
61 return -EINVAL;
62 }
63
Stephen Warren07541392011-04-19 15:25:09 -060064 clk_change = ((new_baseclock != data->set_baseclock) ||
Stephen Warrend64e57c2011-01-28 14:26:40 -070065 (mclk != data->set_mclk));
Stephen Warren07541392011-04-19 15:25:09 -060066 if (!clk_change)
67 return 0;
Stephen Warrena50a3992011-01-07 22:36:15 -070068
Stephen Warrend64e57c2011-01-28 14:26:40 -070069 data->set_baseclock = 0;
70 data->set_mclk = 0;
Stephen Warrena50a3992011-01-07 22:36:15 -070071
Stephen Warrend64e57c2011-01-28 14:26:40 -070072 clk_disable(data->clk_cdev1);
73 clk_disable(data->clk_pll_a_out0);
74 clk_disable(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -070075
Stephen Warrend64e57c2011-01-28 14:26:40 -070076 err = clk_set_rate(data->clk_pll_a, new_baseclock);
Stephen Warrena50a3992011-01-07 22:36:15 -070077 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070078 dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070079 return err;
80 }
81
Stephen Warrend64e57c2011-01-28 14:26:40 -070082 err = clk_set_rate(data->clk_pll_a_out0, mclk);
Stephen Warrena50a3992011-01-07 22:36:15 -070083 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070084 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070085 return err;
86 }
87
Stephen Warrenc2f67022012-04-06 11:15:55 -060088 /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
Stephen Warrena50a3992011-01-07 22:36:15 -070089
Stephen Warrend64e57c2011-01-28 14:26:40 -070090 err = clk_enable(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -070091 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070092 dev_err(data->dev, "Can't enable pll_a: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070093 return err;
94 }
95
Stephen Warrend64e57c2011-01-28 14:26:40 -070096 err = clk_enable(data->clk_pll_a_out0);
Stephen Warrena50a3992011-01-07 22:36:15 -070097 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070098 dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070099 return err;
100 }
101
Stephen Warrend64e57c2011-01-28 14:26:40 -0700102 err = clk_enable(data->clk_cdev1);
Stephen Warrena50a3992011-01-07 22:36:15 -0700103 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -0700104 dev_err(data->dev, "Can't enable cdev1: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -0700105 return err;
106 }
107
Stephen Warrend64e57c2011-01-28 14:26:40 -0700108 data->set_baseclock = new_baseclock;
109 data->set_mclk = mclk;
Stephen Warrena50a3992011-01-07 22:36:15 -0700110
111 return 0;
112}
Stephen Warrena3cd50d2011-02-22 17:23:56 -0700113EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
Stephen Warrena50a3992011-01-07 22:36:15 -0700114
Stephen Warrend64e57c2011-01-28 14:26:40 -0700115int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
116 struct device *dev)
Stephen Warrena50a3992011-01-07 22:36:15 -0700117{
118 int ret;
119
Stephen Warrend64e57c2011-01-28 14:26:40 -0700120 data->dev = dev;
121
Stephen Warrenc2f67022012-04-06 11:15:55 -0600122 if (!of_have_populated_dt())
123 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
124 else if (of_machine_is_compatible("nvidia,tegra20"))
125 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
126 else if (of_machine_is_compatible("nvidia,tegra30"))
127 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30;
128 else
129 return -EINVAL;
130
Stephen Warrend64e57c2011-01-28 14:26:40 -0700131 data->clk_pll_a = clk_get_sys(NULL, "pll_a");
132 if (IS_ERR(data->clk_pll_a)) {
133 dev_err(data->dev, "Can't retrieve clk pll_a\n");
134 ret = PTR_ERR(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -0700135 goto err;
136 }
137
Stephen Warrend64e57c2011-01-28 14:26:40 -0700138 data->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
139 if (IS_ERR(data->clk_pll_a_out0)) {
140 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
141 ret = PTR_ERR(data->clk_pll_a_out0);
Stephen Warren422650e2011-01-11 12:48:53 -0700142 goto err_put_pll_a;
Stephen Warrena50a3992011-01-07 22:36:15 -0700143 }
144
Stephen Warrenc2f67022012-04-06 11:15:55 -0600145 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
146 data->clk_cdev1 = clk_get_sys(NULL, "cdev1");
147 else
148 data->clk_cdev1 = clk_get_sys("extern1", NULL);
Stephen Warrend64e57c2011-01-28 14:26:40 -0700149 if (IS_ERR(data->clk_cdev1)) {
150 dev_err(data->dev, "Can't retrieve clk cdev1\n");
151 ret = PTR_ERR(data->clk_cdev1);
Stephen Warren422650e2011-01-11 12:48:53 -0700152 goto err_put_pll_a_out0;
Stephen Warrena50a3992011-01-07 22:36:15 -0700153 }
154
Stephen Warrena9005b62012-04-06 11:18:16 -0600155 ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
156 if (ret)
157 goto err_put_cdev1;
158
Stephen Warrena50a3992011-01-07 22:36:15 -0700159 return 0;
160
Stephen Warrena9005b62012-04-06 11:18:16 -0600161err_put_cdev1:
162 clk_put(data->clk_cdev1);
Stephen Warren422650e2011-01-11 12:48:53 -0700163err_put_pll_a_out0:
Stephen Warrend64e57c2011-01-28 14:26:40 -0700164 clk_put(data->clk_pll_a_out0);
Stephen Warren422650e2011-01-11 12:48:53 -0700165err_put_pll_a:
Stephen Warrend64e57c2011-01-28 14:26:40 -0700166 clk_put(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -0700167err:
Stephen Warrena50a3992011-01-07 22:36:15 -0700168 return ret;
169}
Stephen Warrena3cd50d2011-02-22 17:23:56 -0700170EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
Stephen Warrena50a3992011-01-07 22:36:15 -0700171
Stephen Warrend64e57c2011-01-28 14:26:40 -0700172void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
Stephen Warrena50a3992011-01-07 22:36:15 -0700173{
Stephen Warrend64e57c2011-01-28 14:26:40 -0700174 clk_put(data->clk_cdev1);
175 clk_put(data->clk_pll_a_out0);
176 clk_put(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -0700177}
Stephen Warrena3cd50d2011-02-22 17:23:56 -0700178EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
Stephen Warrena50a3992011-01-07 22:36:15 -0700179
Stephen Warrena3cd50d2011-02-22 17:23:56 -0700180MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
181MODULE_DESCRIPTION("Tegra ASoC utility code");
182MODULE_LICENSE("GPL");