Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
Alexander Duyck | 86d5d38 | 2009-02-06 23:23:12 +0000 | [diff] [blame] | 4 | Copyright(c) 2007-2009 Intel Corporation. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | |
| 29 | /* Linux PRO/1000 Ethernet Driver main header file */ |
| 30 | |
| 31 | #ifndef _IGB_H_ |
| 32 | #define _IGB_H_ |
| 33 | |
| 34 | #include "e1000_mac.h" |
| 35 | #include "e1000_82575.h" |
| 36 | |
Patrick Ohly | 38c845c | 2009-02-12 05:03:41 +0000 | [diff] [blame] | 37 | #include <linux/clocksource.h> |
Patrick Ohly | 33af6bc | 2009-02-12 05:03:43 +0000 | [diff] [blame] | 38 | #include <linux/timecompare.h> |
| 39 | #include <linux/net_tstamp.h> |
Patrick Ohly | 38c845c | 2009-02-12 05:03:41 +0000 | [diff] [blame] | 40 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 41 | struct igb_adapter; |
| 42 | |
Alexander Duyck | 6eb5a7f | 2008-07-08 15:14:44 -0700 | [diff] [blame] | 43 | /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ |
| 44 | #define IGB_START_ITR 648 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 45 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 46 | /* TX/RX descriptor defines */ |
| 47 | #define IGB_DEFAULT_TXD 256 |
| 48 | #define IGB_MIN_TXD 80 |
| 49 | #define IGB_MAX_TXD 4096 |
| 50 | |
| 51 | #define IGB_DEFAULT_RXD 256 |
| 52 | #define IGB_MIN_RXD 80 |
| 53 | #define IGB_MAX_RXD 4096 |
| 54 | |
| 55 | #define IGB_DEFAULT_ITR 3 /* dynamic */ |
| 56 | #define IGB_MAX_ITR_USECS 10000 |
| 57 | #define IGB_MIN_ITR_USECS 10 |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 58 | #define NON_Q_VECTORS 1 |
| 59 | #define MAX_Q_VECTORS 8 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 60 | |
| 61 | /* Transmit and receive queues */ |
Alexander Duyck | 1bfaf07 | 2009-02-19 20:39:23 -0800 | [diff] [blame] | 62 | #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? \ |
| 63 | (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4) |
| 64 | #define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES |
| 65 | #define IGB_ABS_MAX_TX_QUEUES 4 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 66 | |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 67 | #define IGB_MAX_VF_MC_ENTRIES 30 |
| 68 | #define IGB_MAX_VF_FUNCTIONS 8 |
| 69 | #define IGB_MAX_VFTA_ENTRIES 128 |
| 70 | |
| 71 | struct vf_data_storage { |
| 72 | unsigned char vf_mac_addresses[ETH_ALEN]; |
| 73 | u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; |
| 74 | u16 num_vf_mc_hashes; |
Alexander Duyck | ae641bd | 2009-09-03 14:49:33 +0000 | [diff] [blame] | 75 | u16 vlans_enabled; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 76 | bool clear_to_send; |
| 77 | }; |
| 78 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 79 | /* RX descriptor control thresholds. |
| 80 | * PTHRESH - MAC will consider prefetch if it has fewer than this number of |
| 81 | * descriptors available in its onboard memory. |
| 82 | * Setting this to 0 disables RX descriptor prefetch. |
| 83 | * HTHRESH - MAC will only prefetch if there are at least this many descriptors |
| 84 | * available in host memory. |
| 85 | * If PTHRESH is 0, this should also be 0. |
| 86 | * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back |
| 87 | * descriptors until either it has this many to write back, or the |
| 88 | * ITR timer expires. |
| 89 | */ |
Alexander Duyck | 85b430b | 2009-10-27 15:50:29 +0000 | [diff] [blame] | 90 | #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 91 | #define IGB_RX_HTHRESH 8 |
| 92 | #define IGB_RX_WTHRESH 1 |
Alexander Duyck | 85b430b | 2009-10-27 15:50:29 +0000 | [diff] [blame] | 93 | #define IGB_TX_PTHRESH 8 |
| 94 | #define IGB_TX_HTHRESH 1 |
| 95 | #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
| 96 | adapter->msix_entries) ? 0 : 16) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 97 | |
| 98 | /* this is the size past which hardware will drop packets when setting LPE=0 */ |
| 99 | #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 |
| 100 | |
| 101 | /* Supported Rx Buffer Sizes */ |
| 102 | #define IGB_RXBUFFER_128 128 /* Used for packet split */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 103 | #define IGB_RXBUFFER_1024 1024 |
| 104 | #define IGB_RXBUFFER_2048 2048 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 105 | #define IGB_RXBUFFER_16384 16384 |
| 106 | |
Alexander Duyck | e173952 | 2009-02-19 20:39:44 -0800 | [diff] [blame] | 107 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 108 | |
| 109 | /* How many Tx Descriptors do we need to call netif_wake_queue ? */ |
| 110 | #define IGB_TX_QUEUE_WAKE 16 |
| 111 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
| 112 | #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
| 113 | |
| 114 | #define AUTO_ALL_MODES 0 |
| 115 | #define IGB_EEPROM_APME 0x0400 |
| 116 | |
| 117 | #ifndef IGB_MASTER_SLAVE |
| 118 | /* Switch to override PHY master/slave setting */ |
| 119 | #define IGB_MASTER_SLAVE e1000_ms_hw_default |
| 120 | #endif |
| 121 | |
| 122 | #define IGB_MNG_VLAN_NONE -1 |
| 123 | |
| 124 | /* wrapper around a pointer to a socket buffer, |
| 125 | * so a DMA handle can be stored along with the buffer */ |
| 126 | struct igb_buffer { |
| 127 | struct sk_buff *skb; |
| 128 | dma_addr_t dma; |
| 129 | union { |
| 130 | /* TX */ |
| 131 | struct { |
| 132 | unsigned long time_stamp; |
Alexander Duyck | 0e014cb | 2008-12-26 01:33:18 -0800 | [diff] [blame] | 133 | u16 length; |
| 134 | u16 next_to_watch; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 135 | }; |
| 136 | /* RX */ |
| 137 | struct { |
| 138 | struct page *page; |
| 139 | u64 page_dma; |
Alexander Duyck | bf36c1a | 2008-07-08 15:11:40 -0700 | [diff] [blame] | 140 | unsigned int page_offset; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 141 | }; |
| 142 | }; |
| 143 | }; |
| 144 | |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 145 | struct igb_tx_queue_stats { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 146 | u64 packets; |
| 147 | u64 bytes; |
Alexander Duyck | 04a5fcaa | 2009-10-27 15:52:27 +0000 | [diff] [blame] | 148 | u64 restart_queue; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 149 | }; |
| 150 | |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 151 | struct igb_rx_queue_stats { |
| 152 | u64 packets; |
| 153 | u64 bytes; |
| 154 | u64 drops; |
Alexander Duyck | 04a5fcaa | 2009-10-27 15:52:27 +0000 | [diff] [blame] | 155 | u64 csum_err; |
| 156 | u64 alloc_failed; |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 157 | }; |
| 158 | |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 159 | struct igb_q_vector { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 160 | struct igb_adapter *adapter; /* backlink */ |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 161 | struct igb_ring *rx_ring; |
| 162 | struct igb_ring *tx_ring; |
| 163 | struct napi_struct napi; |
| 164 | |
| 165 | u32 eims_value; |
| 166 | u16 cpu; |
| 167 | |
| 168 | u16 itr_val; |
| 169 | u8 set_itr; |
| 170 | u8 itr_shift; |
| 171 | void __iomem *itr_register; |
| 172 | |
| 173 | char name[IFNAMSIZ + 9]; |
| 174 | }; |
| 175 | |
| 176 | struct igb_ring { |
| 177 | struct igb_q_vector *q_vector; /* backlink to q_vector */ |
Alexander Duyck | e694e96 | 2009-10-27 15:53:06 +0000 | [diff] [blame] | 178 | struct net_device *netdev; /* back pointer to net_device */ |
Alexander Duyck | 8078529 | 2009-10-27 15:51:47 +0000 | [diff] [blame] | 179 | struct pci_dev *pdev; /* pci device for dma mapping */ |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 180 | dma_addr_t dma; /* phys address of the ring */ |
Alexander Duyck | e694e96 | 2009-10-27 15:53:06 +0000 | [diff] [blame] | 181 | void *desc; /* descriptor ring memory */ |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 182 | unsigned int size; /* length of desc. ring in bytes */ |
| 183 | unsigned int count; /* number of desc. in the ring */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 184 | u16 next_to_use; |
| 185 | u16 next_to_clean; |
Alexander Duyck | fce99e3 | 2009-10-27 15:51:27 +0000 | [diff] [blame] | 186 | void __iomem *head; |
| 187 | void __iomem *tail; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 188 | struct igb_buffer *buffer_info; /* array of buffer info structs */ |
| 189 | |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 190 | u8 queue_index; |
| 191 | u8 reg_idx; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 192 | |
| 193 | unsigned int total_bytes; |
| 194 | unsigned int total_packets; |
| 195 | |
Alexander Duyck | 85ad76b | 2009-10-27 15:52:46 +0000 | [diff] [blame] | 196 | u32 flags; |
| 197 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 198 | union { |
| 199 | /* TX */ |
| 200 | struct { |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 201 | struct igb_tx_queue_stats tx_stats; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 202 | bool detect_tx_hung; |
| 203 | }; |
| 204 | /* RX */ |
| 205 | struct { |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 206 | struct igb_rx_queue_stats rx_stats; |
Alexander Duyck | 4c84485 | 2009-10-27 15:52:07 +0000 | [diff] [blame] | 207 | u32 rx_buffer_len; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 208 | }; |
| 209 | }; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 210 | }; |
| 211 | |
Alexander Duyck | 85ad76b | 2009-10-27 15:52:46 +0000 | [diff] [blame] | 212 | #define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */ |
| 213 | #define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */ |
| 214 | |
| 215 | #define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */ |
| 216 | |
| 217 | #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS) |
| 218 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 219 | #define E1000_RX_DESC_ADV(R, i) \ |
| 220 | (&(((union e1000_adv_rx_desc *)((R).desc))[i])) |
| 221 | #define E1000_TX_DESC_ADV(R, i) \ |
| 222 | (&(((union e1000_adv_tx_desc *)((R).desc))[i])) |
| 223 | #define E1000_TX_CTXTDESC_ADV(R, i) \ |
| 224 | (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i])) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 225 | |
Alexander Duyck | d7ee5b3 | 2009-10-27 15:54:23 +0000 | [diff] [blame] | 226 | /* igb_desc_unused - calculate if we have unused descriptors */ |
| 227 | static inline int igb_desc_unused(struct igb_ring *ring) |
| 228 | { |
| 229 | if (ring->next_to_clean > ring->next_to_use) |
| 230 | return ring->next_to_clean - ring->next_to_use - 1; |
| 231 | |
| 232 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; |
| 233 | } |
| 234 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 235 | /* board specific private data structure */ |
| 236 | |
| 237 | struct igb_adapter { |
| 238 | struct timer_list watchdog_timer; |
| 239 | struct timer_list phy_info_timer; |
| 240 | struct vlan_group *vlgrp; |
| 241 | u16 mng_vlan_id; |
| 242 | u32 bd_number; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 243 | u32 wol; |
| 244 | u32 en_mng_pt; |
| 245 | u16 link_speed; |
| 246 | u16 link_duplex; |
| 247 | unsigned int total_tx_bytes; |
| 248 | unsigned int total_tx_packets; |
| 249 | unsigned int total_rx_bytes; |
| 250 | unsigned int total_rx_packets; |
| 251 | /* Interrupt Throttle Rate */ |
Alexander Duyck | 4fc82ad | 2009-10-27 23:45:42 +0000 | [diff] [blame^] | 252 | u32 rx_itr_setting; |
| 253 | u32 tx_itr_setting; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 254 | u16 tx_itr; |
| 255 | u16 rx_itr; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 256 | |
| 257 | struct work_struct reset_task; |
| 258 | struct work_struct watchdog_task; |
| 259 | bool fc_autoneg; |
| 260 | u8 tx_timeout_factor; |
| 261 | struct timer_list blink_timer; |
| 262 | unsigned long led_status; |
| 263 | |
| 264 | /* TX */ |
| 265 | struct igb_ring *tx_ring; /* One per active queue */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 266 | unsigned long tx_queue_len; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 267 | u32 gotc; |
| 268 | u64 gotc_old; |
| 269 | u64 tpt_old; |
| 270 | u64 colc_old; |
| 271 | u32 tx_timeout_count; |
| 272 | |
| 273 | /* RX */ |
| 274 | struct igb_ring *rx_ring; /* One per active queue */ |
| 275 | int num_tx_queues; |
| 276 | int num_rx_queues; |
| 277 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 278 | u32 gorc; |
| 279 | u64 gorc_old; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 280 | u32 max_frame_size; |
| 281 | u32 min_frame_size; |
| 282 | |
| 283 | /* OS defined structs */ |
| 284 | struct net_device *netdev; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 285 | struct pci_dev *pdev; |
Patrick Ohly | 38c845c | 2009-02-12 05:03:41 +0000 | [diff] [blame] | 286 | struct cyclecounter cycles; |
| 287 | struct timecounter clock; |
Patrick Ohly | 33af6bc | 2009-02-12 05:03:43 +0000 | [diff] [blame] | 288 | struct timecompare compare; |
| 289 | struct hwtstamp_config hwtstamp_config; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 290 | |
| 291 | /* structs defined in e1000_hw.h */ |
| 292 | struct e1000_hw hw; |
| 293 | struct e1000_hw_stats stats; |
| 294 | struct e1000_phy_info phy_info; |
| 295 | struct e1000_phy_stats phy_stats; |
| 296 | |
| 297 | u32 test_icr; |
| 298 | struct igb_ring test_tx_ring; |
| 299 | struct igb_ring test_rx_ring; |
| 300 | |
| 301 | int msg_enable; |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 302 | |
| 303 | unsigned int num_q_vectors; |
| 304 | struct igb_q_vector *q_vector[MAX_Q_VECTORS]; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 305 | struct msix_entry *msix_entries; |
| 306 | u32 eims_enable_mask; |
PJ Waskiewicz | 844290e | 2008-06-27 11:00:39 -0700 | [diff] [blame] | 307 | u32 eims_other; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 308 | |
| 309 | /* to not mess up cache alignment, always add to the bottom */ |
| 310 | unsigned long state; |
Alexander Duyck | 7dfc16f | 2008-07-08 15:10:46 -0700 | [diff] [blame] | 311 | unsigned int flags; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 312 | u32 eeprom_wol; |
Taku Izumi | 42bfd33a | 2008-06-20 12:10:30 +0900 | [diff] [blame] | 313 | |
Alexander Duyck | 1bfaf07 | 2009-02-19 20:39:23 -0800 | [diff] [blame] | 314 | struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES]; |
Alexander Duyck | 68fd991 | 2008-11-20 00:48:10 -0800 | [diff] [blame] | 315 | unsigned int tx_ring_count; |
| 316 | unsigned int rx_ring_count; |
Alexander Duyck | 1bfaf07 | 2009-02-19 20:39:23 -0800 | [diff] [blame] | 317 | unsigned int vfs_allocated_count; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 318 | struct vf_data_storage *vf_data; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 319 | }; |
| 320 | |
Alexander Duyck | 7dfc16f | 2008-07-08 15:10:46 -0700 | [diff] [blame] | 321 | #define IGB_FLAG_HAS_MSI (1 << 0) |
Alexander Duyck | cbd347a | 2009-02-15 23:59:44 -0800 | [diff] [blame] | 322 | #define IGB_FLAG_DCA_ENABLED (1 << 1) |
| 323 | #define IGB_FLAG_QUAD_PORT_A (1 << 2) |
Alexander Duyck | 4fc82ad | 2009-10-27 23:45:42 +0000 | [diff] [blame^] | 324 | #define IGB_FLAG_QUEUE_PAIRS (1 << 3) |
Alexander Duyck | 7dfc16f | 2008-07-08 15:10:46 -0700 | [diff] [blame] | 325 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 326 | enum e1000_state_t { |
| 327 | __IGB_TESTING, |
| 328 | __IGB_RESETTING, |
| 329 | __IGB_DOWN |
| 330 | }; |
| 331 | |
| 332 | enum igb_boards { |
| 333 | board_82575, |
| 334 | }; |
| 335 | |
| 336 | extern char igb_driver_name[]; |
| 337 | extern char igb_driver_version[]; |
| 338 | |
| 339 | extern char *igb_get_hw_dev_name(struct e1000_hw *hw); |
| 340 | extern int igb_up(struct igb_adapter *); |
| 341 | extern void igb_down(struct igb_adapter *); |
| 342 | extern void igb_reinit_locked(struct igb_adapter *); |
| 343 | extern void igb_reset(struct igb_adapter *); |
| 344 | extern int igb_set_spd_dplx(struct igb_adapter *, u16); |
Alexander Duyck | 8078529 | 2009-10-27 15:51:47 +0000 | [diff] [blame] | 345 | extern int igb_setup_tx_resources(struct igb_ring *); |
| 346 | extern int igb_setup_rx_resources(struct igb_ring *); |
Alexander Duyck | 68fd991 | 2008-11-20 00:48:10 -0800 | [diff] [blame] | 347 | extern void igb_free_tx_resources(struct igb_ring *); |
| 348 | extern void igb_free_rx_resources(struct igb_ring *); |
Alexander Duyck | d7ee5b3 | 2009-10-27 15:54:23 +0000 | [diff] [blame] | 349 | extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); |
| 350 | extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); |
| 351 | extern void igb_setup_tctl(struct igb_adapter *); |
| 352 | extern void igb_setup_rctl(struct igb_adapter *); |
Alexander Duyck | b1a436c | 2009-10-27 15:54:43 +0000 | [diff] [blame] | 353 | extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *); |
| 354 | extern void igb_unmap_and_free_tx_resource(struct igb_ring *, |
| 355 | struct igb_buffer *); |
Alexander Duyck | d7ee5b3 | 2009-10-27 15:54:23 +0000 | [diff] [blame] | 356 | extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 357 | extern void igb_update_stats(struct igb_adapter *); |
| 358 | extern void igb_set_ethtool_ops(struct net_device *); |
| 359 | |
Alexander Duyck | f5f4cf0 | 2008-11-21 21:30:24 -0800 | [diff] [blame] | 360 | static inline s32 igb_reset_phy(struct e1000_hw *hw) |
| 361 | { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 362 | if (hw->phy.ops.reset) |
| 363 | return hw->phy.ops.reset(hw); |
Alexander Duyck | f5f4cf0 | 2008-11-21 21:30:24 -0800 | [diff] [blame] | 364 | |
| 365 | return 0; |
| 366 | } |
| 367 | |
| 368 | static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
| 369 | { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 370 | if (hw->phy.ops.read_reg) |
| 371 | return hw->phy.ops.read_reg(hw, offset, data); |
Alexander Duyck | f5f4cf0 | 2008-11-21 21:30:24 -0800 | [diff] [blame] | 372 | |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) |
| 377 | { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 378 | if (hw->phy.ops.write_reg) |
| 379 | return hw->phy.ops.write_reg(hw, offset, data); |
Alexander Duyck | f5f4cf0 | 2008-11-21 21:30:24 -0800 | [diff] [blame] | 380 | |
| 381 | return 0; |
| 382 | } |
| 383 | |
| 384 | static inline s32 igb_get_phy_info(struct e1000_hw *hw) |
| 385 | { |
| 386 | if (hw->phy.ops.get_phy_info) |
| 387 | return hw->phy.ops.get_phy_info(hw); |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 392 | #endif /* _IGB_H_ */ |