Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 1 | # |
| 2 | # DMA engine configuration |
| 3 | # |
| 4 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 5 | menuconfig DMADEVICES |
Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 6 | bool "DMA Engine support" |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 7 | depends on HAS_DMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 8 | help |
Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 9 | DMA engines can do asynchronous data transfers without |
| 10 | involving the host CPU. Currently, this framework can be |
| 11 | used to offload memory copies in the network stack and |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 12 | RAID operations in the MD driver. This menu only presents |
| 13 | DMA Device drivers supported by the configured arch, it may |
| 14 | be empty in some cases. |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 15 | |
Linus Walleij | 6c664a8 | 2010-02-09 22:34:54 +0100 | [diff] [blame] | 16 | config DMADEVICES_DEBUG |
| 17 | bool "DMA Engine debugging" |
| 18 | depends on DMADEVICES != n |
| 19 | help |
| 20 | This is an option for use by developers; most people should |
| 21 | say N here. This enables DMA engine core and driver debugging. |
| 22 | |
| 23 | config DMADEVICES_VDEBUG |
| 24 | bool "DMA Engine verbose debugging" |
| 25 | depends on DMADEVICES_DEBUG != n |
| 26 | help |
| 27 | This is an option for use by developers; most people should |
| 28 | say N here. This enables deeper (more verbose) debugging of |
| 29 | the DMA engine core and drivers. |
| 30 | |
| 31 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 32 | if DMADEVICES |
Chris Leech | db21733 | 2006-06-17 21:24:58 -0700 | [diff] [blame] | 33 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 34 | comment "DMA Devices" |
| 35 | |
Vinod Koul | b3c567e | 2010-07-21 13:28:10 +0530 | [diff] [blame] | 36 | config INTEL_MID_DMAC |
| 37 | tristate "Intel MID DMA support for Peripheral DMA controllers" |
| 38 | depends on PCI && X86 |
| 39 | select DMA_ENGINE |
| 40 | default n |
| 41 | help |
| 42 | Enable support for the Intel(R) MID DMA engine present |
| 43 | in Intel MID chipsets. |
| 44 | |
| 45 | Say Y here if you have such a chipset. |
| 46 | |
| 47 | If unsure, say N. |
| 48 | |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 49 | config ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 50 | bool |
| 51 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 52 | config AMBA_PL08X |
| 53 | bool "ARM PrimeCell PL080 or PL081 support" |
| 54 | depends on ARM_AMBA && EXPERIMENTAL |
| 55 | select DMA_ENGINE |
| 56 | help |
| 57 | Platform has a PL08x DMAC device |
| 58 | which can provide DMA engine support |
| 59 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 60 | config INTEL_IOATDMA |
| 61 | tristate "Intel I/OAT DMA support" |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 62 | depends on PCI && X86 |
| 63 | select DMA_ENGINE |
| 64 | select DCA |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 65 | select ASYNC_TX_DISABLE_PQ_VAL_DMA |
| 66 | select ASYNC_TX_DISABLE_XOR_VAL_DMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 67 | help |
| 68 | Enable support for the Intel(R) I/OAT DMA engine present |
| 69 | in recent Intel Xeon chipsets. |
| 70 | |
| 71 | Say Y here if you have such a chipset. |
| 72 | |
| 73 | If unsure, say N. |
Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 74 | |
| 75 | config INTEL_IOP_ADMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 76 | tristate "Intel IOP ADMA support" |
| 77 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 78 | select DMA_ENGINE |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 79 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 80 | help |
| 81 | Enable support for the Intel(R) IOP Series RAID engines. |
Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 82 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 83 | config DW_DMAC |
| 84 | tristate "Synopsys DesignWare AHB DMA support" |
Viresh Kumar | f44ad7e | 2011-03-03 15:47:14 +0530 | [diff] [blame] | 85 | depends on HAVE_CLK |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 86 | select DMA_ENGINE |
| 87 | default y if CPU_AT32AP7000 |
| 88 | help |
| 89 | Support the Synopsys DesignWare AHB DMA controller. This |
| 90 | can be integrated in chips such as the Atmel AT32ap7000. |
| 91 | |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 92 | config AT_HDMAC |
| 93 | tristate "Atmel AHB DMA support" |
Nicolas Ferre | f898fed | 2012-03-15 11:31:58 +0100 | [diff] [blame] | 94 | depends on ARCH_AT91 |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 95 | select DMA_ENGINE |
| 96 | help |
Nicolas Ferre | f898fed | 2012-03-15 11:31:58 +0100 | [diff] [blame] | 97 | Support the Atmel AHB DMA controller. |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 98 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 99 | config FSL_DMA |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 100 | tristate "Freescale Elo and Elo Plus DMA support" |
| 101 | depends on FSL_SOC |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 102 | select DMA_ENGINE |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 103 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 104 | ---help--- |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 105 | Enable support for the Freescale Elo and Elo Plus DMA controllers. |
| 106 | The Elo is the DMA controller on some 82xx and 83xx parts, and the |
| 107 | Elo Plus is the DMA controller on 85xx and 86xx parts. |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 108 | |
Piotr Ziecik | 0fb6f73 | 2010-02-05 03:42:52 +0000 | [diff] [blame] | 109 | config MPC512X_DMA |
| 110 | tristate "Freescale MPC512x built-in DMA engine support" |
Ilya Yanok | ba2eea2 | 2010-10-27 01:52:57 +0200 | [diff] [blame] | 111 | depends on PPC_MPC512x || PPC_MPC831x |
Piotr Ziecik | 0fb6f73 | 2010-02-05 03:42:52 +0000 | [diff] [blame] | 112 | select DMA_ENGINE |
| 113 | ---help--- |
| 114 | Enable support for the Freescale MPC512x built-in DMA engine. |
| 115 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 116 | config MV_XOR |
| 117 | bool "Marvell XOR engine support" |
| 118 | depends on PLAT_ORION |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 119 | select DMA_ENGINE |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 120 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 121 | ---help--- |
| 122 | Enable support for the Marvell XOR engine. |
| 123 | |
Guennadi Liakhovetski | 5296b56 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 124 | config MX3_IPU |
| 125 | bool "MX3x Image Processing Unit support" |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 126 | depends on ARCH_MXC |
Guennadi Liakhovetski | 5296b56 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 127 | select DMA_ENGINE |
| 128 | default y |
| 129 | help |
| 130 | If you plan to use the Image Processing unit in the i.MX3x, say |
| 131 | Y here. If unsure, select Y. |
| 132 | |
| 133 | config MX3_IPU_IRQS |
| 134 | int "Number of dynamically mapped interrupts for IPU" |
| 135 | depends on MX3_IPU |
| 136 | range 2 137 |
| 137 | default 4 |
| 138 | help |
| 139 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. |
| 140 | To avoid bloating the irq_desc[] array we allocate a sufficient |
| 141 | number of IRQ slots and map them dynamically to specific sources. |
| 142 | |
Atsushi Nemoto | ea76f0b | 2009-04-23 00:40:30 +0900 | [diff] [blame] | 143 | config TXX9_DMAC |
| 144 | tristate "Toshiba TXx9 SoC DMA support" |
| 145 | depends on MACH_TX49XX || MACH_TX39XX |
| 146 | select DMA_ENGINE |
| 147 | help |
| 148 | Support the TXx9 SoC internal DMA controller. This can be |
| 149 | integrated in chips such as the Toshiba TX4927/38/39. |
| 150 | |
Laxman Dewangan | ec8a158 | 2012-06-06 10:55:27 +0530 | [diff] [blame] | 151 | config TEGRA20_APB_DMA |
| 152 | bool "NVIDIA Tegra20 APB DMA support" |
| 153 | depends on ARCH_TEGRA |
| 154 | select DMA_ENGINE |
| 155 | help |
| 156 | Support for the NVIDIA Tegra20 APB DMA controller driver. The |
| 157 | DMA controller is having multiple DMA channel which can be |
| 158 | configured for different peripherals like audio, UART, SPI, |
| 159 | I2C etc which is in APB bus. |
| 160 | This DMA controller transfers data from memory to peripheral fifo |
| 161 | or vice versa. It does not support memory to memory data transfer. |
| 162 | |
| 163 | |
| 164 | |
Nobuhiro Iwamatsu | d8902ad | 2009-09-07 03:26:23 +0000 | [diff] [blame] | 165 | config SH_DMAE |
| 166 | tristate "Renesas SuperH DMAC support" |
Magnus Damm | 927a7c9 | 2010-03-19 04:47:19 +0000 | [diff] [blame] | 167 | depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE) |
Nobuhiro Iwamatsu | d8902ad | 2009-09-07 03:26:23 +0000 | [diff] [blame] | 168 | depends on !SH_DMA_API |
| 169 | select DMA_ENGINE |
| 170 | help |
| 171 | Enable support for the Renesas SuperH DMA controllers. |
| 172 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 173 | config COH901318 |
| 174 | bool "ST-Ericsson COH901318 DMA support" |
| 175 | select DMA_ENGINE |
| 176 | depends on ARCH_U300 |
| 177 | help |
| 178 | Enable support for ST-Ericsson COH 901 318 DMA. |
| 179 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 180 | config STE_DMA40 |
| 181 | bool "ST-Ericsson DMA40 support" |
| 182 | depends on ARCH_U8500 |
| 183 | select DMA_ENGINE |
| 184 | help |
| 185 | Support for ST-Ericsson DMA40 controller |
| 186 | |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 187 | config AMCC_PPC440SPE_ADMA |
| 188 | tristate "AMCC PPC440SPe ADMA support" |
| 189 | depends on 440SPe || 440SP |
| 190 | select DMA_ENGINE |
| 191 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 192 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 193 | help |
| 194 | Enable support for the AMCC PPC440SPe RAID engines. |
| 195 | |
Richard Röjfors | de5d445 | 2010-03-25 19:44:21 +0100 | [diff] [blame] | 196 | config TIMB_DMA |
| 197 | tristate "Timberdale FPGA DMA support" |
| 198 | depends on MFD_TIMBERDALE || HAS_IOMEM |
| 199 | select DMA_ENGINE |
| 200 | help |
| 201 | Enable support for the Timberdale FPGA DMA engine. |
| 202 | |
Rongjun Ying | ca21a14 | 2011-10-27 19:22:39 -0700 | [diff] [blame] | 203 | config SIRF_DMA |
| 204 | tristate "CSR SiRFprimaII DMA support" |
| 205 | depends on ARCH_PRIMA2 |
| 206 | select DMA_ENGINE |
| 207 | help |
| 208 | Enable support for the CSR SiRFprimaII DMA engine. |
| 209 | |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 210 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
| 211 | bool |
| 212 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 213 | config PL330_DMA |
| 214 | tristate "DMA API Driver for PL330" |
| 215 | select DMA_ENGINE |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 216 | depends on ARM_AMBA |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 217 | help |
| 218 | Select if your platform has one or more PL330 DMACs. |
| 219 | You need to provide platform specific settings via |
| 220 | platform_data for a dma-pl330 device. |
| 221 | |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 222 | config PCH_DMA |
Tomoya MORINAGA | ca7fe2d | 2011-11-17 16:14:23 +0900 | [diff] [blame] | 223 | tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA" |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 224 | depends on PCI && X86 |
| 225 | select DMA_ENGINE |
| 226 | help |
Tomoya MORINAGA | 2cdf245 | 2011-01-05 17:43:52 +0900 | [diff] [blame] | 227 | Enable support for Intel EG20T PCH DMA engine. |
| 228 | |
Tomoya MORINAGA | e79e72b | 2011-11-17 16:14:22 +0900 | [diff] [blame] | 229 | This driver also can be used for LAPIS Semiconductor IOH(Input/ |
Tomoya MORINAGA | ca7fe2d | 2011-11-17 16:14:23 +0900 | [diff] [blame] | 230 | Output Hub), ML7213, ML7223 and ML7831. |
| 231 | ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is |
| 232 | for MP(Media Phone) use and ML7831 IOH is for general purpose use. |
| 233 | ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. |
| 234 | ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 235 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 236 | config IMX_SDMA |
| 237 | tristate "i.MX SDMA support" |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 238 | depends on ARCH_MXC |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 239 | select DMA_ENGINE |
| 240 | help |
| 241 | Support the i.MX SDMA engine. This engine is integrated into |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 242 | Freescale i.MX25/31/35/51/53 chips. |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 243 | |
Sascha Hauer | 1f1846c | 2010-10-06 10:25:55 +0200 | [diff] [blame] | 244 | config IMX_DMA |
| 245 | tristate "i.MX DMA support" |
Vinod Koul | 5b2e02e | 2012-03-27 13:53:00 +0530 | [diff] [blame] | 246 | depends on ARCH_MXC |
Sascha Hauer | 1f1846c | 2010-10-06 10:25:55 +0200 | [diff] [blame] | 247 | select DMA_ENGINE |
| 248 | help |
| 249 | Support the i.MX DMA engine. This engine is integrated into |
| 250 | Freescale i.MX1/21/27 chips. |
| 251 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 252 | config MXS_DMA |
| 253 | bool "MXS DMA support" |
Huang Shijie | f5c5584 | 2012-06-06 21:22:59 -0400 | [diff] [blame] | 254 | depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 255 | select STMP_DEVICE |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 256 | select DMA_ENGINE |
| 257 | help |
| 258 | Support the MXS DMA engine. This engine including APBH-DMA |
| 259 | and APBX-DMA is integrated into Freescale i.MX23/28 chips. |
| 260 | |
Mika Westerberg | 760ee1c | 2011-05-29 13:10:02 +0300 | [diff] [blame] | 261 | config EP93XX_DMA |
| 262 | bool "Cirrus Logic EP93xx DMA support" |
| 263 | depends on ARCH_EP93XX |
| 264 | select DMA_ENGINE |
| 265 | help |
| 266 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. |
| 267 | |
Russell King | 6365bea | 2012-01-09 21:44:07 +0000 | [diff] [blame] | 268 | config DMA_SA11X0 |
| 269 | tristate "SA-11x0 DMA support" |
| 270 | depends on ARCH_SA1100 |
| 271 | select DMA_ENGINE |
| 272 | help |
| 273 | Support the DMA engine found on Intel StrongARM SA-1100 and |
| 274 | SA-1110 SoCs. This DMA engine can only be used with on-chip |
| 275 | devices. |
| 276 | |
Zhangfei Gao | c6da0ba | 2012-06-15 11:04:08 +0800 | [diff] [blame^] | 277 | config MMP_TDMA |
| 278 | bool "MMP Two-Channel DMA support" |
| 279 | default ARCH_MMP |
| 280 | select DMA_ENGINE |
| 281 | help |
| 282 | Support the MMP Two-Channel DMA engine. |
| 283 | This engine used for MMP Audio DMA and pxa910 SQU. |
| 284 | |
| 285 | Say Y here if you enabled MMP ADMA, otherwise say N. |
| 286 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 287 | config DMA_ENGINE |
| 288 | bool |
| 289 | |
| 290 | comment "DMA Clients" |
| 291 | depends on DMA_ENGINE |
| 292 | |
| 293 | config NET_DMA |
| 294 | bool "Network: TCP receive copy offload" |
| 295 | depends on DMA_ENGINE && NET |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 296 | default (INTEL_IOATDMA || FSL_DMA) |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 297 | help |
| 298 | This enables the use of DMA engines in the network stack to |
| 299 | offload receive copy-to-user operations, freeing CPU cycles. |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 300 | |
| 301 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise |
| 302 | say N. |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 303 | |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 304 | config ASYNC_TX_DMA |
| 305 | bool "Async_tx: Offload support for the async_tx api" |
Dan Williams | 9a8de63 | 2009-09-08 15:06:10 -0700 | [diff] [blame] | 306 | depends on DMA_ENGINE |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 307 | help |
| 308 | This allows the async_tx api to take advantage of offload engines for |
| 309 | memcpy, memset, xor, and raid6 p+q operations. If your platform has |
| 310 | a dma engine that can perform raid operations and you have enabled |
| 311 | MD_RAID456 say Y. |
| 312 | |
| 313 | If unsure, say N. |
| 314 | |
Haavard Skinnemoen | 4a776f0 | 2008-07-08 11:58:45 -0700 | [diff] [blame] | 315 | config DMATEST |
| 316 | tristate "DMA Test client" |
| 317 | depends on DMA_ENGINE |
| 318 | help |
| 319 | Simple DMA test client. Say N unless you're debugging a |
| 320 | DMA Device driver. |
| 321 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 322 | endif |