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Sreedhara DS9a58a332010-04-26 18:13:05 +01001/*
2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
3 *
4 * (C) Copyright 2008-2010 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 *
Lucas De Marchic8440332011-03-17 17:18:22 -030012 * SCU running in ARC processor communicates with other entity running in IA
Sreedhara DS9a58a332010-04-26 18:13:05 +010013 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
18 */
19#include <linux/delay.h>
20#include <linux/errno.h>
21#include <linux/init.h>
Kay Sieversedbaa602011-12-21 16:26:03 -080022#include <linux/device.h>
Sreedhara DS9a58a332010-04-26 18:13:05 +010023#include <linux/pm.h>
24#include <linux/pci.h>
25#include <linux/interrupt.h>
Alan Cox209009b2010-09-13 15:55:05 +010026#include <linux/sfi.h>
Paul Gortmaker7c52d552011-05-27 12:33:10 -040027#include <linux/module.h>
Kuppuswamy Sathyanarayanan05454c22013-10-17 15:35:27 -070028#include <asm/intel-mid.h>
Sreedhara DS9a58a332010-04-26 18:13:05 +010029#include <asm/intel_scu_ipc.h>
30
31/* IPC defines the following message types */
32#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
33#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
34#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
35#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
36#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
37
38/* Command id associated with message IPCMSG_PCNTRL */
39#define IPC_CMD_PCNTRL_W 0 /* Register write */
40#define IPC_CMD_PCNTRL_R 1 /* Register read */
41#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
42
Sreedhara DS9a58a332010-04-26 18:13:05 +010043/*
44 * IPC register summary
45 *
46 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
47 * To read or write information to the SCU, driver writes to IPC-1 memory
48 * mapped registers (base address 0xFF11C000). The following is the IPC
49 * mechanism
50 *
51 * 1. IA core cDMI interface claims this transaction and converts it to a
52 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
53 *
54 * 2. South Complex cDMI block receives this message and writes it to
55 * the IPC-1 register block, causing an interrupt to the SCU
56 *
57 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
58 * message handler is called within firmware.
59 */
60
Arjan van de Ven51cd5252010-07-26 10:04:24 +010061#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
62#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
Kuppuswamy Sathyanarayanane97a1c92013-11-14 14:15:04 -080063
64enum {
65 SCU_IPC_LINCROFT,
Kuppuswamy Sathyanarayanan7f95afb2013-11-14 14:15:05 -080066 SCU_IPC_PENWELL,
67 SCU_IPC_CLOVERVIEW,
68 SCU_IPC_TANGIER,
Kuppuswamy Sathyanarayanane97a1c92013-11-14 14:15:04 -080069};
70
71/* intel scu ipc driver data*/
72struct intel_scu_ipc_pdata_t {
73 u32 ipc_base;
74 u32 i2c_base;
75 u32 ipc_len;
76 u32 i2c_len;
77};
78
79static struct intel_scu_ipc_pdata_t intel_scu_ipc_pdata[] = {
80 [SCU_IPC_LINCROFT] = {
81 .ipc_base = 0xff11c000,
82 .i2c_base = 0xff12b000,
83 .ipc_len = 0x100,
84 .i2c_len = 0x10,
85 },
Kuppuswamy Sathyanarayanan7f95afb2013-11-14 14:15:05 -080086 [SCU_IPC_PENWELL] = {
87 .ipc_base = 0xff11c000,
88 .i2c_base = 0xff12b000,
89 .ipc_len = 0x100,
90 .i2c_len = 0x10,
91 },
92 [SCU_IPC_CLOVERVIEW] = {
93 .ipc_base = 0xff11c000,
94 .i2c_base = 0xff12b000,
95 .ipc_len = 0x100,
96 .i2c_len = 0x10,
97 },
98 [SCU_IPC_TANGIER] = {
99 .ipc_base = 0xff009000,
100 .i2c_base = 0xff00d000,
101 .ipc_len = 0x100,
102 .i2c_len = 0x10,
103 },
Kuppuswamy Sathyanarayanane97a1c92013-11-14 14:15:04 -0800104};
Sreedhara DS9a58a332010-04-26 18:13:05 +0100105
106static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
107static void ipc_remove(struct pci_dev *pdev);
108
109struct intel_scu_ipc_dev {
110 struct pci_dev *pdev;
111 void __iomem *ipc_base;
112 void __iomem *i2c_base;
113};
114
115static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
116
Sreedhara DS14d10f02010-07-26 10:02:25 +0100117static int platform; /* Platform type */
Sreedhara DS9a58a332010-04-26 18:13:05 +0100118
119/*
120 * IPC Read Buffer (Read Only):
121 * 16 byte buffer for receiving data from SCU, if IPC command
122 * processing results in response data
123 */
124#define IPC_READ_BUFFER 0x90
125
126#define IPC_I2C_CNTRL_ADDR 0
127#define I2C_DATA_ADDR 0x04
128
129static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
130
131/*
132 * Command Register (Write Only):
133 * A write to this register results in an interrupt to the SCU core processor
134 * Format:
135 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
136 */
137static inline void ipc_command(u32 cmd) /* Send ipc command */
138{
139 writel(cmd, ipcdev.ipc_base);
140}
141
142/*
143 * IPC Write Buffer (Write Only):
144 * 16-byte buffer for sending data associated with IPC command to
145 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
146 */
147static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
148{
149 writel(data, ipcdev.ipc_base + 0x80 + offset);
150}
151
152/*
Sreedhara DS9a58a332010-04-26 18:13:05 +0100153 * Status Register (Read Only):
154 * Driver will read this register to get the ready/busy status of the IPC
155 * block and error status of the IPC command that was just processed by SCU
156 * Format:
157 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
158 */
159
160static inline u8 ipc_read_status(void)
161{
162 return __raw_readl(ipcdev.ipc_base + 0x04);
163}
164
165static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
166{
167 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
168}
169
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100170static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
Sreedhara DS9a58a332010-04-26 18:13:05 +0100171{
172 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
173}
174
175static inline int busy_loop(void) /* Wait till scu status is busy */
176{
177 u32 status = 0;
178 u32 loop_count = 0;
179
180 status = ipc_read_status();
181 while (status & 1) {
182 udelay(1); /* scu processing time is in few u secods */
183 status = ipc_read_status();
184 loop_count++;
185 /* break if scu doesn't reset busy bit after huge retry */
186 if (loop_count > 100000) {
187 dev_err(&ipcdev.pdev->dev, "IPC timed out");
188 return -ETIMEDOUT;
189 }
190 }
Hong Liu77e01d62010-07-26 10:06:12 +0100191 if ((status >> 1) & 1)
192 return -EIO;
193
194 return 0;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100195}
196
197/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
198static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
199{
Alan Cox47073752012-03-05 15:01:02 -0800200 int nc;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100201 u32 offset = 0;
Axel Linecb56462011-01-25 14:12:12 +0000202 int err;
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100203 u8 cbuf[IPC_WWBUF_SIZE] = { };
Sreedhara DS9a58a332010-04-26 18:13:05 +0100204 u32 *wbuf = (u32 *)&cbuf;
205
206 mutex_lock(&ipclock);
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100207
Arjan van de Vened6f2b42010-07-26 10:04:37 +0100208 memset(cbuf, 0, sizeof(cbuf));
209
Sreedhara DS9a58a332010-04-26 18:13:05 +0100210 if (ipcdev.pdev == NULL) {
211 mutex_unlock(&ipclock);
212 return -ENODEV;
213 }
214
Alan Cox47073752012-03-05 15:01:02 -0800215 for (nc = 0; nc < count; nc++, offset += 2) {
216 cbuf[offset] = addr[nc];
217 cbuf[offset + 1] = addr[nc] >> 8;
218 }
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100219
Alan Cox47073752012-03-05 15:01:02 -0800220 if (id == IPC_CMD_PCNTRL_R) {
221 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
222 ipc_data_writel(wbuf[nc], offset);
223 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
224 } else if (id == IPC_CMD_PCNTRL_W) {
225 for (nc = 0; nc < count; nc++, offset += 1)
226 cbuf[offset] = data[nc];
227 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
228 ipc_data_writel(wbuf[nc], offset);
229 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
230 } else if (id == IPC_CMD_PCNTRL_M) {
231 cbuf[offset] = data[0];
232 cbuf[offset + 1] = data[1];
233 ipc_data_writel(wbuf[0], 0); /* Write wbuff */
234 ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100235 }
236
Sreedhara DS9a58a332010-04-26 18:13:05 +0100237 err = busy_loop();
Sreedhara DS9a58a332010-04-26 18:13:05 +0100238 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
239 /* Workaround: values are read as 0 without memcpy_fromio */
Sreedhara DSe3359fd2010-07-26 10:02:46 +0100240 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
Alan Cox47073752012-03-05 15:01:02 -0800241 for (nc = 0; nc < count; nc++)
242 data[nc] = ipc_data_readb(nc);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100243 }
244 mutex_unlock(&ipclock);
245 return err;
246}
247
248/**
249 * intel_scu_ipc_ioread8 - read a word via the SCU
250 * @addr: register on SCU
251 * @data: return pointer for read byte
252 *
253 * Read a single register. Returns 0 on success or an error code. All
254 * locking between SCU accesses is handled for the caller.
255 *
256 * This function may sleep.
257 */
258int intel_scu_ipc_ioread8(u16 addr, u8 *data)
259{
260 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
261}
262EXPORT_SYMBOL(intel_scu_ipc_ioread8);
263
264/**
265 * intel_scu_ipc_ioread16 - read a word via the SCU
266 * @addr: register on SCU
267 * @data: return pointer for read word
268 *
269 * Read a register pair. Returns 0 on success or an error code. All
270 * locking between SCU accesses is handled for the caller.
271 *
272 * This function may sleep.
273 */
274int intel_scu_ipc_ioread16(u16 addr, u16 *data)
275{
276 u16 x[2] = {addr, addr + 1 };
277 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
278}
279EXPORT_SYMBOL(intel_scu_ipc_ioread16);
280
281/**
282 * intel_scu_ipc_ioread32 - read a dword via the SCU
283 * @addr: register on SCU
284 * @data: return pointer for read dword
285 *
286 * Read four registers. Returns 0 on success or an error code. All
287 * locking between SCU accesses is handled for the caller.
288 *
289 * This function may sleep.
290 */
291int intel_scu_ipc_ioread32(u16 addr, u32 *data)
292{
293 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
294 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
295}
296EXPORT_SYMBOL(intel_scu_ipc_ioread32);
297
298/**
299 * intel_scu_ipc_iowrite8 - write a byte via the SCU
300 * @addr: register on SCU
301 * @data: byte to write
302 *
303 * Write a single register. Returns 0 on success or an error code. All
304 * locking between SCU accesses is handled for the caller.
305 *
306 * This function may sleep.
307 */
308int intel_scu_ipc_iowrite8(u16 addr, u8 data)
309{
310 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
311}
312EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
313
314/**
315 * intel_scu_ipc_iowrite16 - write a word via the SCU
316 * @addr: register on SCU
317 * @data: word to write
318 *
319 * Write two registers. Returns 0 on success or an error code. All
320 * locking between SCU accesses is handled for the caller.
321 *
322 * This function may sleep.
323 */
324int intel_scu_ipc_iowrite16(u16 addr, u16 data)
325{
326 u16 x[2] = {addr, addr + 1 };
327 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
328}
329EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
330
331/**
332 * intel_scu_ipc_iowrite32 - write a dword via the SCU
333 * @addr: register on SCU
334 * @data: dword to write
335 *
336 * Write four registers. Returns 0 on success or an error code. All
337 * locking between SCU accesses is handled for the caller.
338 *
339 * This function may sleep.
340 */
341int intel_scu_ipc_iowrite32(u16 addr, u32 data)
342{
343 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
344 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
345}
346EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
347
348/**
349 * intel_scu_ipc_readvv - read a set of registers
350 * @addr: register list
351 * @data: bytes to return
352 * @len: length of array
353 *
354 * Read registers. Returns 0 on success or an error code. All
355 * locking between SCU accesses is handled for the caller.
356 *
357 * The largest array length permitted by the hardware is 5 items.
358 *
359 * This function may sleep.
360 */
361int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
362{
363 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
364}
365EXPORT_SYMBOL(intel_scu_ipc_readv);
366
367/**
368 * intel_scu_ipc_writev - write a set of registers
369 * @addr: register list
370 * @data: bytes to write
371 * @len: length of array
372 *
373 * Write registers. Returns 0 on success or an error code. All
374 * locking between SCU accesses is handled for the caller.
375 *
376 * The largest array length permitted by the hardware is 5 items.
377 *
378 * This function may sleep.
379 *
380 */
381int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
382{
383 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
384}
385EXPORT_SYMBOL(intel_scu_ipc_writev);
386
387
388/**
389 * intel_scu_ipc_update_register - r/m/w a register
390 * @addr: register address
391 * @bits: bits to update
392 * @mask: mask of bits to update
393 *
394 * Read-modify-write power control unit register. The first data argument
395 * must be register value and second is mask value
396 * mask is a bitmap that indicates which bits to update.
397 * 0 = masked. Don't modify this bit, 1 = modify this bit.
398 * returns 0 on success or an error code.
399 *
400 * This function may sleep. Locking between SCU accesses is handled
401 * for the caller.
402 */
403int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
404{
405 u8 data[2] = { bits, mask };
406 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
407}
408EXPORT_SYMBOL(intel_scu_ipc_update_register);
409
410/**
Sreedhara DS9a58a332010-04-26 18:13:05 +0100411 * intel_scu_ipc_simple_command - send a simple command
412 * @cmd: command
413 * @sub: sub type
414 *
415 * Issue a simple command to the SCU. Do not use this interface if
416 * you must then access data as any data values may be overwritten
417 * by another SCU access by the time this function returns.
418 *
419 * This function may sleep. Locking for SCU accesses is handled for
420 * the caller.
421 */
422int intel_scu_ipc_simple_command(int cmd, int sub)
423{
Axel Linecb56462011-01-25 14:12:12 +0000424 int err;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100425
426 mutex_lock(&ipclock);
427 if (ipcdev.pdev == NULL) {
428 mutex_unlock(&ipclock);
429 return -ENODEV;
430 }
Sreedhara DSb4fd4f82010-07-19 09:37:42 +0100431 ipc_command(sub << 12 | cmd);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100432 err = busy_loop();
433 mutex_unlock(&ipclock);
434 return err;
435}
436EXPORT_SYMBOL(intel_scu_ipc_simple_command);
437
438/**
439 * intel_scu_ipc_command - command with data
440 * @cmd: command
441 * @sub: sub type
442 * @in: input data
Sreedhara DSb4fd4f82010-07-19 09:37:42 +0100443 * @inlen: input length in dwords
Sreedhara DS9a58a332010-04-26 18:13:05 +0100444 * @out: output data
Sreedhara DSb4fd4f82010-07-19 09:37:42 +0100445 * @outlein: output length in dwords
Sreedhara DS9a58a332010-04-26 18:13:05 +0100446 *
447 * Issue a command to the SCU which involves data transfers. Do the
448 * data copies under the lock but leave it for the caller to interpret
449 */
450
451int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
452 u32 *out, int outlen)
453{
Axel Linecb56462011-01-25 14:12:12 +0000454 int i, err;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100455
456 mutex_lock(&ipclock);
457 if (ipcdev.pdev == NULL) {
458 mutex_unlock(&ipclock);
459 return -ENODEV;
460 }
461
462 for (i = 0; i < inlen; i++)
463 ipc_data_writel(*in++, 4 * i);
464
Hong Liu5aa06932010-07-26 10:06:31 +0100465 ipc_command((inlen << 16) | (sub << 12) | cmd);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100466 err = busy_loop();
467
468 for (i = 0; i < outlen; i++)
469 *out++ = ipc_data_readl(4 * i);
470
471 mutex_unlock(&ipclock);
472 return err;
473}
474EXPORT_SYMBOL(intel_scu_ipc_command);
475
476/*I2C commands */
477#define IPC_I2C_WRITE 1 /* I2C Write command */
478#define IPC_I2C_READ 2 /* I2C Read command */
479
480/**
481 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
482 * @addr: I2C address + command bits
483 * @data: data to read/write
484 *
485 * Perform an an I2C read/write operation via the SCU. All locking is
486 * handled for the caller. This function may sleep.
487 *
488 * Returns an error code or 0 on success.
489 *
490 * This has to be in the IPC driver for the locking.
491 */
492int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
493{
494 u32 cmd = 0;
495
496 mutex_lock(&ipclock);
Sreedhara DSb4fd4f82010-07-19 09:37:42 +0100497 if (ipcdev.pdev == NULL) {
498 mutex_unlock(&ipclock);
499 return -ENODEV;
500 }
Sreedhara DS9a58a332010-04-26 18:13:05 +0100501 cmd = (addr >> 24) & 0xFF;
502 if (cmd == IPC_I2C_READ) {
503 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
504 /* Write not getting updated without delay */
505 mdelay(1);
506 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
507 } else if (cmd == IPC_I2C_WRITE) {
Jianwei Yang32e2f632010-08-24 14:32:38 +0100508 writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100509 mdelay(1);
510 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
511 } else {
512 dev_err(&ipcdev.pdev->dev,
513 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
514
515 mutex_unlock(&ipclock);
Sreedhara DS5369c02d2010-10-22 15:43:55 +0100516 return -EIO;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100517 }
518 mutex_unlock(&ipclock);
519 return 0;
520}
521EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
522
Sreedhara DS9a58a332010-04-26 18:13:05 +0100523/*
524 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
525 * When ioc bit is set to 1, caller api must wait for interrupt handler called
526 * which in turn unlocks the caller api. Currently this is not used
527 *
528 * This is edge triggered so we need take no action to clear anything
529 */
530static irqreturn_t ioc(int irq, void *dev_id)
531{
532 return IRQ_HANDLED;
533}
534
535/**
536 * ipc_probe - probe an Intel SCU IPC
537 * @dev: the PCI device matching
538 * @id: entry in the match table
539 *
540 * Enable and install an intel SCU IPC. This appears in the PCI space
541 * but uses some hard coded addresses as well.
542 */
543static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
544{
Kuppuswamy Sathyanarayanane97a1c92013-11-14 14:15:04 -0800545 int err, pid;
546 struct intel_scu_ipc_pdata_t *pdata;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100547 resource_size_t pci_resource;
548
549 if (ipcdev.pdev) /* We support only one SCU */
550 return -EBUSY;
551
Kuppuswamy Sathyanarayanane97a1c92013-11-14 14:15:04 -0800552 pid = id->driver_data;
553 pdata = &intel_scu_ipc_pdata[pid];
554
Sreedhara DS9a58a332010-04-26 18:13:05 +0100555 ipcdev.pdev = pci_dev_get(dev);
556
557 err = pci_enable_device(dev);
558 if (err)
559 return err;
560
561 err = pci_request_regions(dev, "intel_scu_ipc");
562 if (err)
563 return err;
564
565 pci_resource = pci_resource_start(dev, 0);
566 if (!pci_resource)
567 return -ENOMEM;
568
569 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
570 return -EBUSY;
571
Kuppuswamy Sathyanarayanane97a1c92013-11-14 14:15:04 -0800572 ipcdev.ipc_base = ioremap_nocache(pdata->ipc_base, pdata->ipc_len);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100573 if (!ipcdev.ipc_base)
574 return -ENOMEM;
575
Kuppuswamy Sathyanarayanane97a1c92013-11-14 14:15:04 -0800576 ipcdev.i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
Sreedhara DS9a58a332010-04-26 18:13:05 +0100577 if (!ipcdev.i2c_base) {
578 iounmap(ipcdev.ipc_base);
579 return -ENOMEM;
580 }
Feng Tang1da4b1c2010-11-09 11:22:58 +0000581
582 intel_scu_devices_create();
583
Sreedhara DS9a58a332010-04-26 18:13:05 +0100584 return 0;
585}
586
587/**
588 * ipc_remove - remove a bound IPC device
589 * @pdev: PCI device
590 *
591 * In practice the SCU is not removable but this function is also
592 * called for each device on a module unload or cleanup which is the
593 * path that will get used.
594 *
595 * Free up the mappings and release the PCI resources
596 */
597static void ipc_remove(struct pci_dev *pdev)
598{
599 free_irq(pdev->irq, &ipcdev);
600 pci_release_regions(pdev);
601 pci_dev_put(ipcdev.pdev);
602 iounmap(ipcdev.ipc_base);
603 iounmap(ipcdev.i2c_base);
604 ipcdev.pdev = NULL;
Feng Tang1da4b1c2010-11-09 11:22:58 +0000605 intel_scu_devices_destroy();
Sreedhara DS9a58a332010-04-26 18:13:05 +0100606}
607
Axel Lindaa77692011-07-07 10:22:46 +0800608static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
Kuppuswamy Sathyanarayanane97a1c92013-11-14 14:15:04 -0800609 {PCI_VDEVICE(INTEL, 0x082a), SCU_IPC_LINCROFT},
Kuppuswamy Sathyanarayanan7f95afb2013-11-14 14:15:05 -0800610 {PCI_VDEVICE(INTEL, 0x080e), SCU_IPC_PENWELL},
611 {PCI_VDEVICE(INTEL, 0x08ea), SCU_IPC_CLOVERVIEW},
612 {PCI_VDEVICE(INTEL, 0x11a0), SCU_IPC_TANGIER},
Sreedhara DS9a58a332010-04-26 18:13:05 +0100613 { 0,}
614};
615MODULE_DEVICE_TABLE(pci, pci_ids);
616
617static struct pci_driver ipc_driver = {
618 .name = "intel_scu_ipc",
619 .id_table = pci_ids,
620 .probe = ipc_probe,
621 .remove = ipc_remove,
622};
623
624
625static int __init intel_scu_ipc_init(void)
626{
Kuppuswamy Sathyanarayanan712b6aa2013-10-17 15:35:29 -0700627 platform = intel_mid_identify_cpu();
Alan Cox9dd3ade2010-07-26 10:03:58 +0100628 if (platform == 0)
629 return -ENODEV;
Sreedhara DS9a58a332010-04-26 18:13:05 +0100630 return pci_register_driver(&ipc_driver);
631}
632
633static void __exit intel_scu_ipc_exit(void)
634{
635 pci_unregister_driver(&ipc_driver);
636}
637
638MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
639MODULE_DESCRIPTION("Intel SCU IPC driver");
640MODULE_LICENSE("GPL");
641
642module_init(intel_scu_ipc_init);
643module_exit(intel_scu_ipc_exit);