blob: ab40f961384f1ac2a57390e70fa4a3e1891d92b4 [file] [log] [blame]
Thomas Petazzonif3b42b72012-09-13 17:41:48 +02001/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78230 SoC that are not
13 * common to all Armada XP SoCs.
14 */
15
16/include/ "armada-xp.dtsi"
17
18/ {
19 model = "Marvell Armada XP MV78230 SoC";
20 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
21
Thomas Petazzoni397d59f2012-09-19 22:53:01 +020022 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 };
26
Gregory CLEMENT9d202782012-11-17 15:22:24 +010027 cpus {
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020028 #address-cells = <1>;
29 #size-cells = <0>;
Gregory CLEMENT9d202782012-11-17 15:22:24 +010030
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020031 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7";
34 reg = <0>;
35 clocks = <&cpuclk 0>;
36 };
Thomas Petazzoni44cfae92013-01-06 11:10:40 +010037
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020038 cpu@1 {
39 device_type = "cpu";
40 compatible = "marvell,sheeva-v7";
41 reg = <1>;
42 clocks = <&cpuclk 1>;
43 };
Andrew Lunn41be8dc2013-01-06 11:10:42 +010044 };
Gregory CLEMENT9d202782012-11-17 15:22:24 +010045
Thomas Petazzonif3b42b72012-09-13 17:41:48 +020046 soc {
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020047 internal-regs {
48 pinctrl {
49 compatible = "marvell,mv78230-pinctrl";
50 reg = <0x18000 0x38>;
Thomas Petazzoni6d36e8e2012-12-21 15:49:06 +010051
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020052 sdio_pins: sdio-pins {
53 marvell,pins = "mpp30", "mpp31", "mpp32",
54 "mpp33", "mpp34", "mpp35";
55 marvell,function = "sd0";
56 };
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +020057 };
58
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020059 gpio0: gpio@18100 {
60 compatible = "marvell,orion-gpio";
61 reg = <0x18100 0x40>;
62 ngpios = <32>;
63 gpio-controller;
64 #gpio-cells = <2>;
65 interrupt-controller;
Thomas Petazzonica609852013-07-30 16:59:02 +020066 #interrupt-cells = <2>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020067 interrupts = <82>, <83>, <84>, <85>;
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +020068 };
69
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020070 gpio1: gpio@18140 {
71 compatible = "marvell,orion-gpio";
72 reg = <0x18140 0x40>;
73 ngpios = <17>;
74 gpio-controller;
75 #gpio-cells = <2>;
76 interrupt-controller;
Thomas Petazzonica609852013-07-30 16:59:02 +020077 #interrupt-cells = <2>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020078 interrupts = <87>, <88>, <89>;
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +020079 };
80
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020081 /*
82 * MV78230 has 2 PCIe units Gen2.0: One unit can be
83 * configured as x4 or quad x1 lanes. One unit is
84 * x4/x1.
85 */
86 pcie-controller {
87 compatible = "marvell,armada-xp-pcie";
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +020088 status = "disabled";
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020089 device_type = "pci";
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +020090
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020091#address-cells = <3>;
92#size-cells = <2>;
93
94 bus-range = <0x00 0xff>;
95
96 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
97 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
98 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
99 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
100 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
101 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
102 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
103
104 pcie@1,0 {
105 device_type = "pci";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 #address-cells = <3>;
109 #size-cells = <2>;
110 #interrupt-cells = <1>;
111 ranges;
112 interrupt-map-mask = <0 0 0 0>;
113 interrupt-map = <0 0 0 0 &mpic 58>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 5>;
117 status = "disabled";
118 };
119
120 pcie@2,0 {
121 device_type = "pci";
122 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
123 reg = <0x1000 0 0 0 0>;
124 #address-cells = <3>;
125 #size-cells = <2>;
126 #interrupt-cells = <1>;
127 ranges;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &mpic 59>;
130 marvell,pcie-port = <0>;
131 marvell,pcie-lane = <1>;
132 clocks = <&gateclk 6>;
133 status = "disabled";
134 };
135
136 pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 ranges;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 60>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <2>;
148 clocks = <&gateclk 7>;
149 status = "disabled";
150 };
151
152 pcie@4,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 61>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <3>;
164 clocks = <&gateclk 8>;
165 status = "disabled";
166 };
167
168 pcie@9,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171 reg = <0x4800 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 99>;
178 marvell,pcie-port = <2>;
179 marvell,pcie-lane = <0>;
180 clocks = <&gateclk 26>;
181 status = "disabled";
182 };
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +0200183 };
184 };
Thomas Petazzonif3b42b72012-09-13 17:41:48 +0200185 };
186};