blob: 23373543a149cb90c2ffa0d53552bd59c23927cd [file] [log] [blame]
Alexander Shishkine443b332012-05-11 17:25:46 +03001/*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
Peter Chen58ce8492014-05-23 08:12:47 +080026 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
Alexander Shishkine443b332012-05-11 17:25:46 +030027 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
Alexander Shishkine443b332012-05-11 17:25:46 +030045 * - Suspend & Remote Wakeup
46 */
47#include <linux/delay.h>
48#include <linux/device.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030049#include <linux/dma-mapping.h>
Antoine Tenart1e5e2d32014-10-30 18:41:19 +010050#include <linux/phy/phy.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030051#include <linux/platform_device.h>
52#include <linux/module.h>
Richard Zhaofe6e1252012-07-07 22:56:42 +080053#include <linux/idr.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030054#include <linux/interrupt.h>
55#include <linux/io.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030056#include <linux/kernel.h>
57#include <linux/slab.h>
58#include <linux/pm_runtime.h>
59#include <linux/usb/ch9.h>
60#include <linux/usb/gadget.h>
61#include <linux/usb/otg.h>
62#include <linux/usb/chipidea.h>
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +030063#include <linux/usb/of.h>
Michael Grzeschik4f6743d2014-02-19 13:41:43 +080064#include <linux/of.h>
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +030065#include <linux/phy.h>
Peter Chen1542d9c2013-08-14 12:44:03 +030066#include <linux/regulator/consumer.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030067
68#include "ci.h"
69#include "udc.h"
70#include "bits.h"
Alexander Shishkineb70e5a2012-05-11 17:25:54 +030071#include "host.h"
Alexander Shishkine443b332012-05-11 17:25:46 +030072#include "debug.h"
Peter Chenc10b4f02013-08-14 12:44:06 +030073#include "otg.h"
Li Jun4dcf7202014-04-23 15:56:50 +080074#include "otg_fsm.h"
Alexander Shishkine443b332012-05-11 17:25:46 +030075
Alexander Shishkin5f36e232012-05-11 17:25:47 +030076/* Controller register map */
Marc Kleine-Budde987e7bc2014-01-06 10:10:39 +080077static const u8 ci_regs_nolpm[] = {
78 [CAP_CAPLENGTH] = 0x00U,
79 [CAP_HCCPARAMS] = 0x08U,
80 [CAP_DCCPARAMS] = 0x24U,
81 [CAP_TESTMODE] = 0x38U,
82 [OP_USBCMD] = 0x00U,
83 [OP_USBSTS] = 0x04U,
84 [OP_USBINTR] = 0x08U,
85 [OP_DEVICEADDR] = 0x14U,
86 [OP_ENDPTLISTADDR] = 0x18U,
87 [OP_PORTSC] = 0x44U,
88 [OP_DEVLC] = 0x84U,
89 [OP_OTGSC] = 0x64U,
90 [OP_USBMODE] = 0x68U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
Alexander Shishkine443b332012-05-11 17:25:46 +030097};
98
Marc Kleine-Budde987e7bc2014-01-06 10:10:39 +080099static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
104 [OP_USBCMD] = 0x00U,
105 [OP_USBSTS] = 0x04U,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_PORTSC] = 0x44U,
110 [OP_DEVLC] = 0x84U,
111 [OP_OTGSC] = 0xC4U,
112 [OP_USBMODE] = 0xC8U,
113 [OP_ENDPTSETUPSTAT] = 0xD8U,
114 [OP_ENDPTPRIME] = 0xDCU,
115 [OP_ENDPTFLUSH] = 0xE0U,
116 [OP_ENDPTSTAT] = 0xE4U,
117 [OP_ENDPTCOMPLETE] = 0xE8U,
118 [OP_ENDPTCTRL] = 0xECU,
Alexander Shishkine443b332012-05-11 17:25:46 +0300119};
120
Alexander Shishkin8e229782013-06-24 14:46:36 +0300121static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
Alexander Shishkine443b332012-05-11 17:25:46 +0300122{
123 int i;
124
Alexander Shishkine443b332012-05-11 17:25:46 +0300125 for (i = 0; i < OP_ENDPTCTRL; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300126 ci->hw_bank.regmap[i] =
127 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
Alexander Shishkine443b332012-05-11 17:25:46 +0300128 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
129
130 for (; i <= OP_LAST; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300131 ci->hw_bank.regmap[i] = ci->hw_bank.op +
Alexander Shishkine443b332012-05-11 17:25:46 +0300132 4 * (i - OP_ENDPTCTRL) +
133 (is_lpm
134 ? ci_regs_lpm[OP_ENDPTCTRL]
135 : ci_regs_nolpm[OP_ENDPTCTRL]);
136
137 return 0;
138}
139
140/**
Li Jun36304b02014-04-23 15:56:39 +0800141 * hw_read_intr_enable: returns interrupt enable register
142 *
Peter Chen19353882014-09-22 08:14:17 +0800143 * @ci: the controller
144 *
Li Jun36304b02014-04-23 15:56:39 +0800145 * This function returns register data
146 */
147u32 hw_read_intr_enable(struct ci_hdrc *ci)
148{
149 return hw_read(ci, OP_USBINTR, ~0);
150}
151
152/**
153 * hw_read_intr_status: returns interrupt status register
154 *
Peter Chen19353882014-09-22 08:14:17 +0800155 * @ci: the controller
156 *
Li Jun36304b02014-04-23 15:56:39 +0800157 * This function returns register data
158 */
159u32 hw_read_intr_status(struct ci_hdrc *ci)
160{
161 return hw_read(ci, OP_USBSTS, ~0);
162}
163
164/**
Alexander Shishkine443b332012-05-11 17:25:46 +0300165 * hw_port_test_set: writes port test mode (execute without interruption)
166 * @mode: new value
167 *
168 * This function returns an error code
169 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300170int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
Alexander Shishkine443b332012-05-11 17:25:46 +0300171{
172 const u8 TEST_MODE_MAX = 7;
173
174 if (mode > TEST_MODE_MAX)
175 return -EINVAL;
176
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200177 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
Alexander Shishkine443b332012-05-11 17:25:46 +0300178 return 0;
179}
180
181/**
182 * hw_port_test_get: reads port test mode value
183 *
Peter Chen19353882014-09-22 08:14:17 +0800184 * @ci: the controller
185 *
Alexander Shishkine443b332012-05-11 17:25:46 +0300186 * This function returns port test mode value
187 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300188u8 hw_port_test_get(struct ci_hdrc *ci)
Alexander Shishkine443b332012-05-11 17:25:46 +0300189{
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200190 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
Alexander Shishkine443b332012-05-11 17:25:46 +0300191}
192
Peter Chenb82613c2014-11-26 13:44:28 +0800193static void hw_wait_phy_stable(void)
194{
195 /*
196 * The phy needs some delay to output the stable status from low
197 * power mode. And for OTGSC, the status inputs are debounced
198 * using a 1 ms time constant, so, delay 2ms for controller to get
199 * the stable status, like vbus and id when the phy leaves low power.
200 */
201 usleep_range(2000, 2500);
202}
203
Peter Chen864cf942013-09-24 12:47:55 +0800204/* The PHY enters/leaves low power mode */
205static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
206{
207 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
208 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
209
Peter Chen6d037db2014-11-26 13:44:27 +0800210 if (enable && !lpm)
Peter Chen864cf942013-09-24 12:47:55 +0800211 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
212 PORTSC_PHCD(ci->hw_bank.lpm));
Peter Chen6d037db2014-11-26 13:44:27 +0800213 else if (!enable && lpm)
Peter Chen864cf942013-09-24 12:47:55 +0800214 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
215 0);
Peter Chen864cf942013-09-24 12:47:55 +0800216}
217
Alexander Shishkin8e229782013-06-24 14:46:36 +0300218static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
Alexander Shishkine443b332012-05-11 17:25:46 +0300219{
220 u32 reg;
221
222 /* bank is a module variable */
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300223 ci->hw_bank.abs = base;
Alexander Shishkine443b332012-05-11 17:25:46 +0300224
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300225 ci->hw_bank.cap = ci->hw_bank.abs;
Richard Zhao77c44002012-06-29 17:48:53 +0800226 ci->hw_bank.cap += ci->platdata->capoffset;
Svetoslav Neykov938d3232013-03-30 12:54:03 +0200227 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
Alexander Shishkine443b332012-05-11 17:25:46 +0300228
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300229 hw_alloc_regmap(ci, false);
230 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200231 __ffs(HCCPARAMS_LEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300232 ci->hw_bank.lpm = reg;
Chris Ruehlaeb2c122013-12-06 16:35:12 +0800233 if (reg)
234 hw_alloc_regmap(ci, !!reg);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300235 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
236 ci->hw_bank.size += OP_LAST;
237 ci->hw_bank.size /= sizeof(u32);
Alexander Shishkine443b332012-05-11 17:25:46 +0300238
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300239 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200240 __ffs(DCCPARAMS_DEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300241 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
Alexander Shishkine443b332012-05-11 17:25:46 +0300242
Richard Zhao09c94e62012-05-15 21:58:18 +0800243 if (ci->hw_ep_max > ENDPT_MAX)
Alexander Shishkine443b332012-05-11 17:25:46 +0300244 return -ENODEV;
245
Peter Chen864cf942013-09-24 12:47:55 +0800246 ci_hdrc_enter_lpm(ci, false);
247
Peter Chenc344b512013-08-14 12:44:09 +0300248 /* Disable all interrupts bits */
249 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
250
251 /* Clear all interrupts status bits*/
252 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
253
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300254 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
255 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
Alexander Shishkine443b332012-05-11 17:25:46 +0300256
257 /* setup lock mode ? */
258
259 /* ENDPTSETUPSTAT is '0' by default */
260
261 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
262
263 return 0;
264}
265
Alexander Shishkin8e229782013-06-24 14:46:36 +0300266static void hw_phymode_configure(struct ci_hdrc *ci)
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300267{
Chris Ruehl3b5d3e62014-01-10 13:51:29 +0800268 u32 portsc, lpm, sts = 0;
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300269
270 switch (ci->platdata->phy_mode) {
271 case USBPHY_INTERFACE_MODE_UTMI:
272 portsc = PORTSC_PTS(PTS_UTMI);
273 lpm = DEVLC_PTS(PTS_UTMI);
274 break;
275 case USBPHY_INTERFACE_MODE_UTMIW:
276 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
277 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
278 break;
279 case USBPHY_INTERFACE_MODE_ULPI:
280 portsc = PORTSC_PTS(PTS_ULPI);
281 lpm = DEVLC_PTS(PTS_ULPI);
282 break;
283 case USBPHY_INTERFACE_MODE_SERIAL:
284 portsc = PORTSC_PTS(PTS_SERIAL);
285 lpm = DEVLC_PTS(PTS_SERIAL);
286 sts = 1;
287 break;
288 case USBPHY_INTERFACE_MODE_HSIC:
289 portsc = PORTSC_PTS(PTS_HSIC);
290 lpm = DEVLC_PTS(PTS_HSIC);
291 break;
292 default:
293 return;
294 }
295
296 if (ci->hw_bank.lpm) {
297 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
Chris Ruehl3b5d3e62014-01-10 13:51:29 +0800298 if (sts)
299 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300300 } else {
301 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
Chris Ruehl3b5d3e62014-01-10 13:51:29 +0800302 if (sts)
303 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300304 }
305}
306
Alexander Shishkine443b332012-05-11 17:25:46 +0300307/**
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100308 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
309 * interfaces
310 * @ci: the controller
311 *
312 * This function returns an error code if the phy failed to init
313 */
314static int _ci_usb_phy_init(struct ci_hdrc *ci)
315{
316 int ret;
317
318 if (ci->phy) {
319 ret = phy_init(ci->phy);
320 if (ret)
321 return ret;
322
323 ret = phy_power_on(ci->phy);
324 if (ret) {
325 phy_exit(ci->phy);
326 return ret;
327 }
328 } else {
329 ret = usb_phy_init(ci->usb_phy);
330 }
331
332 return ret;
333}
334
335/**
336 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
337 * interfaces
338 * @ci: the controller
339 */
340static void ci_usb_phy_exit(struct ci_hdrc *ci)
341{
342 if (ci->phy) {
343 phy_power_off(ci->phy);
344 phy_exit(ci->phy);
345 } else {
346 usb_phy_shutdown(ci->usb_phy);
347 }
348}
349
350/**
Peter Chend03cccf2014-04-23 15:56:37 +0800351 * ci_usb_phy_init: initialize phy according to different phy type
352 * @ci: the controller
Peter Chen19353882014-09-22 08:14:17 +0800353 *
Peter Chend03cccf2014-04-23 15:56:37 +0800354 * This function returns an error code if usb_phy_init has failed
355 */
356static int ci_usb_phy_init(struct ci_hdrc *ci)
357{
358 int ret;
359
360 switch (ci->platdata->phy_mode) {
361 case USBPHY_INTERFACE_MODE_UTMI:
362 case USBPHY_INTERFACE_MODE_UTMIW:
363 case USBPHY_INTERFACE_MODE_HSIC:
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100364 ret = _ci_usb_phy_init(ci);
Peter Chenb82613c2014-11-26 13:44:28 +0800365 if (!ret)
366 hw_wait_phy_stable();
367 else
Peter Chend03cccf2014-04-23 15:56:37 +0800368 return ret;
369 hw_phymode_configure(ci);
370 break;
371 case USBPHY_INTERFACE_MODE_ULPI:
372 case USBPHY_INTERFACE_MODE_SERIAL:
373 hw_phymode_configure(ci);
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100374 ret = _ci_usb_phy_init(ci);
Peter Chend03cccf2014-04-23 15:56:37 +0800375 if (ret)
376 return ret;
377 break;
378 default:
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100379 ret = _ci_usb_phy_init(ci);
Peter Chenb82613c2014-11-26 13:44:28 +0800380 if (!ret)
381 hw_wait_phy_stable();
Peter Chend03cccf2014-04-23 15:56:37 +0800382 }
383
384 return ret;
385}
386
387/**
Peter Chencdd278f2014-11-26 13:44:32 +0800388 * hw_controller_reset: do controller reset
Alexander Shishkine443b332012-05-11 17:25:46 +0300389 * @ci: the controller
390 *
391 * This function returns an error code
392 */
Peter Chencdd278f2014-11-26 13:44:32 +0800393static int hw_controller_reset(struct ci_hdrc *ci)
394{
395 int count = 0;
396
397 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
398 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
399 udelay(10);
400 if (count++ > 1000)
401 return -ETIMEDOUT;
402 }
403
404 return 0;
405}
406
407/**
408 * hw_device_reset: resets chip (execute without interruption)
409 * @ci: the controller
410 *
411 * This function returns an error code
412 */
Peter Chen5b157302014-11-26 13:44:33 +0800413int hw_device_reset(struct ci_hdrc *ci)
Alexander Shishkine443b332012-05-11 17:25:46 +0300414{
Peter Chencdd278f2014-11-26 13:44:32 +0800415 int ret;
416
Alexander Shishkine443b332012-05-11 17:25:46 +0300417 /* should flush & stop before reset */
418 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
419 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
420
Peter Chencdd278f2014-11-26 13:44:32 +0800421 ret = hw_controller_reset(ci);
422 if (ret) {
423 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
424 return ret;
425 }
Alexander Shishkine443b332012-05-11 17:25:46 +0300426
Richard Zhao77c44002012-06-29 17:48:53 +0800427 if (ci->platdata->notify_event)
428 ci->platdata->notify_event(ci,
Alexander Shishkin8e229782013-06-24 14:46:36 +0300429 CI_HDRC_CONTROLLER_RESET_EVENT);
Alexander Shishkine443b332012-05-11 17:25:46 +0300430
Alexander Shishkin8e229782013-06-24 14:46:36 +0300431 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
Alexander Shishkin758fc982012-05-11 17:25:53 +0300432 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
Alexander Shishkine443b332012-05-11 17:25:46 +0300433
Michael Grzeschik4f6743d2014-02-19 13:41:43 +0800434 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
435 if (ci->hw_bank.lpm)
436 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
437 else
438 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
439 }
440
Alexander Shishkine443b332012-05-11 17:25:46 +0300441 /* USBMODE should be configured step by step */
442 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
Peter Chen5b157302014-11-26 13:44:33 +0800443 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
Alexander Shishkine443b332012-05-11 17:25:46 +0300444 /* HW >= 2.3 */
445 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
446
Peter Chen5b157302014-11-26 13:44:33 +0800447 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
448 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
Alexander Shishkine443b332012-05-11 17:25:46 +0300449 pr_err("lpm = %i", ci->hw_bank.lpm);
450 return -ENODEV;
451 }
452
453 return 0;
454}
455
Peter Chen22fa8442013-08-14 12:44:12 +0300456/**
457 * hw_wait_reg: wait the register value
458 *
459 * Sometimes, it needs to wait register value before going on.
460 * Eg, when switch to device mode, the vbus value should be lower
461 * than OTGSC_BSV before connects to host.
462 *
463 * @ci: the controller
464 * @reg: register index
465 * @mask: mast bit
466 * @value: the bit value to wait
467 * @timeout_ms: timeout in millisecond
468 *
469 * This function returns an error code if timeout
470 */
471int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
472 u32 value, unsigned int timeout_ms)
473{
474 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
475
476 while (hw_read(ci, reg, mask) != value) {
477 if (time_after(jiffies, elapse)) {
478 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
479 mask, reg);
480 return -ETIMEDOUT;
481 }
482 msleep(20);
483 }
484
485 return 0;
486}
487
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300488static irqreturn_t ci_irq(int irq, void *data)
489{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300490 struct ci_hdrc *ci = data;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300491 irqreturn_t ret = IRQ_NONE;
Richard Zhaob183c192012-09-12 14:58:11 +0300492 u32 otgsc = 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300493
Peter Chen1f874ed2015-02-11 12:44:45 +0800494 if (ci->in_lpm) {
495 disable_irq_nosync(irq);
496 ci->wakeup_int = true;
497 pm_runtime_get(ci->dev);
498 return IRQ_HANDLED;
499 }
500
Li Jun4dcf7202014-04-23 15:56:50 +0800501 if (ci->is_otg) {
Li Jun0c33bf72014-04-23 15:56:38 +0800502 otgsc = hw_read_otgsc(ci, ~0);
Li Jun4dcf7202014-04-23 15:56:50 +0800503 if (ci_otg_is_fsm_mode(ci)) {
504 ret = ci_otg_fsm_irq(ci);
505 if (ret == IRQ_HANDLED)
506 return ret;
507 }
508 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300509
Peter Chena107f8c2013-08-14 12:44:11 +0300510 /*
511 * Handle id change interrupt, it indicates device/host function
512 * switch.
513 */
514 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
515 ci->id_event = true;
Li Jun0c33bf72014-04-23 15:56:38 +0800516 /* Clear ID change irq status */
517 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
Peter Chenbe6b0c12014-05-23 08:12:49 +0800518 ci_otg_queue_work(ci);
Peter Chena107f8c2013-08-14 12:44:11 +0300519 return IRQ_HANDLED;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300520 }
521
Peter Chena107f8c2013-08-14 12:44:11 +0300522 /*
523 * Handle vbus change interrupt, it indicates device connection
524 * and disconnection events.
525 */
526 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
527 ci->b_sess_valid_event = true;
Li Jun0c33bf72014-04-23 15:56:38 +0800528 /* Clear BSV irq */
529 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
Peter Chenbe6b0c12014-05-23 08:12:49 +0800530 ci_otg_queue_work(ci);
Peter Chena107f8c2013-08-14 12:44:11 +0300531 return IRQ_HANDLED;
532 }
533
534 /* Handle device/host interrupt */
535 if (ci->role != CI_ROLE_END)
536 ret = ci_role(ci)->irq(ci);
537
Richard Zhaob183c192012-09-12 14:58:11 +0300538 return ret;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300539}
540
Peter Chen1542d9c2013-08-14 12:44:03 +0300541static int ci_get_platdata(struct device *dev,
542 struct ci_hdrc_platform_data *platdata)
543{
Peter Chenc22600c2013-09-17 12:37:22 +0800544 if (!platdata->phy_mode)
545 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
546
547 if (!platdata->dr_mode)
548 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
549
550 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
551 platdata->dr_mode = USB_DR_MODE_OTG;
552
Peter Chenc2ec3a72013-10-30 09:19:29 +0800553 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
554 /* Get the vbus regulator */
555 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
556 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
557 return -EPROBE_DEFER;
558 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
Mickael Maison66294672014-11-26 13:44:38 +0800559 /* no vbus regulator is needed */
Peter Chenc2ec3a72013-10-30 09:19:29 +0800560 platdata->reg_vbus = NULL;
561 } else if (IS_ERR(platdata->reg_vbus)) {
562 dev_err(dev, "Getting regulator error: %ld\n",
563 PTR_ERR(platdata->reg_vbus));
564 return PTR_ERR(platdata->reg_vbus);
565 }
Peter Chenf6a9ff02014-08-19 09:51:56 +0800566 /* Get TPL support */
567 if (!platdata->tpl_support)
568 platdata->tpl_support =
569 of_usb_host_tpl_support(dev->of_node);
Peter Chenc2ec3a72013-10-30 09:19:29 +0800570 }
571
Michael Grzeschik4f6743d2014-02-19 13:41:43 +0800572 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
573 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
574
Peter Chen1542d9c2013-08-14 12:44:03 +0300575 return 0;
576}
577
Richard Zhaofe6e1252012-07-07 22:56:42 +0800578static DEFINE_IDA(ci_ida);
579
Alexander Shishkin8e229782013-06-24 14:46:36 +0300580struct platform_device *ci_hdrc_add_device(struct device *dev,
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800581 struct resource *res, int nres,
Alexander Shishkin8e229782013-06-24 14:46:36 +0300582 struct ci_hdrc_platform_data *platdata)
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800583{
584 struct platform_device *pdev;
Richard Zhaofe6e1252012-07-07 22:56:42 +0800585 int id, ret;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800586
Peter Chen1542d9c2013-08-14 12:44:03 +0300587 ret = ci_get_platdata(dev, platdata);
588 if (ret)
589 return ERR_PTR(ret);
590
Richard Zhaofe6e1252012-07-07 22:56:42 +0800591 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
592 if (id < 0)
593 return ERR_PTR(id);
594
595 pdev = platform_device_alloc("ci_hdrc", id);
596 if (!pdev) {
597 ret = -ENOMEM;
598 goto put_id;
599 }
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800600
601 pdev->dev.parent = dev;
602 pdev->dev.dma_mask = dev->dma_mask;
603 pdev->dev.dma_parms = dev->dma_parms;
604 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
605
606 ret = platform_device_add_resources(pdev, res, nres);
607 if (ret)
608 goto err;
609
610 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
611 if (ret)
612 goto err;
613
614 ret = platform_device_add(pdev);
615 if (ret)
616 goto err;
617
618 return pdev;
619
620err:
621 platform_device_put(pdev);
Richard Zhaofe6e1252012-07-07 22:56:42 +0800622put_id:
623 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800624 return ERR_PTR(ret);
625}
Alexander Shishkin8e229782013-06-24 14:46:36 +0300626EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800627
Alexander Shishkin8e229782013-06-24 14:46:36 +0300628void ci_hdrc_remove_device(struct platform_device *pdev)
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800629{
Lothar Waßmann98c35532012-11-22 10:11:25 +0100630 int id = pdev->id;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800631 platform_device_unregister(pdev);
Lothar Waßmann98c35532012-11-22 10:11:25 +0100632 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800633}
Alexander Shishkin8e229782013-06-24 14:46:36 +0300634EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800635
Peter Chen3f124d22013-08-14 12:44:07 +0300636static inline void ci_role_destroy(struct ci_hdrc *ci)
637{
638 ci_hdrc_gadget_destroy(ci);
639 ci_hdrc_host_destroy(ci);
Peter Chencbec6bd2013-08-14 12:44:10 +0300640 if (ci->is_otg)
641 ci_hdrc_otg_destroy(ci);
Peter Chen3f124d22013-08-14 12:44:07 +0300642}
643
Peter Chen577b2322013-08-14 12:44:08 +0300644static void ci_get_otg_capable(struct ci_hdrc *ci)
645{
646 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
647 ci->is_otg = false;
648 else
649 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
650 DCCPARAMS_DC | DCCPARAMS_HC)
651 == (DCCPARAMS_DC | DCCPARAMS_HC));
Peter Chen2e37cfd2015-02-11 12:44:51 +0800652 if (ci->is_otg) {
Peter Chen577b2322013-08-14 12:44:08 +0300653 dev_dbg(ci->dev, "It is OTG capable controller\n");
Peter Chen2e37cfd2015-02-11 12:44:51 +0800654 /* Disable and clear all OTG irq */
655 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
656 OTGSC_INT_STATUS_BITS);
657 }
Peter Chen577b2322013-08-14 12:44:08 +0300658}
659
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500660static int ci_hdrc_probe(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300661{
662 struct device *dev = &pdev->dev;
Alexander Shishkin8e229782013-06-24 14:46:36 +0300663 struct ci_hdrc *ci;
Alexander Shishkine443b332012-05-11 17:25:46 +0300664 struct resource *res;
665 void __iomem *base;
666 int ret;
Sascha Hauer691962d2013-06-13 17:59:57 +0300667 enum usb_dr_mode dr_mode;
Alexander Shishkine443b332012-05-11 17:25:46 +0300668
Jingoo Hanfad56742014-02-19 13:41:42 +0800669 if (!dev_get_platdata(dev)) {
Alexander Shishkine443b332012-05-11 17:25:46 +0300670 dev_err(dev, "platform data missing\n");
671 return -ENODEV;
672 }
673
674 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Felipe Balbi19290812013-03-30 02:46:27 +0200675 base = devm_ioremap_resource(dev, res);
676 if (IS_ERR(base))
677 return PTR_ERR(base);
Alexander Shishkine443b332012-05-11 17:25:46 +0300678
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300679 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
Fabio Estevamd0f99242014-11-26 13:44:23 +0800680 if (!ci)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300681 return -ENOMEM;
Alexander Shishkine443b332012-05-11 17:25:46 +0300682
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300683 ci->dev = dev;
Jingoo Hanfad56742014-02-19 13:41:42 +0800684 ci->platdata = dev_get_platdata(dev);
Peter Chened8f8312014-01-10 13:51:27 +0800685 ci->imx28_write_fix = !!(ci->platdata->flags &
686 CI_HDRC_IMX28_WRITE_FIX);
Peter Chen1f874ed2015-02-11 12:44:45 +0800687 ci->supports_runtime_pm = !!(ci->platdata->flags &
688 CI_HDRC_SUPPORTS_RUNTIME_PM);
Alexander Shishkine443b332012-05-11 17:25:46 +0300689
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300690 ret = hw_device_init(ci, base);
691 if (ret < 0) {
692 dev_err(dev, "can't initialize hardware\n");
693 return -ENODEV;
694 }
695
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100696 if (ci->platdata->phy) {
697 ci->phy = ci->platdata->phy;
698 } else if (ci->platdata->usb_phy) {
Antoine Tenartef44cb42014-10-30 18:41:16 +0100699 ci->usb_phy = ci->platdata->usb_phy;
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100700 } else {
Antoine Tenart21a5b572014-11-26 13:44:35 +0800701 ci->phy = devm_phy_get(dev->parent, "usb-phy");
702 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
Peter Chenc859aa652014-02-19 13:41:40 +0800703
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100704 /* if both generic PHY and USB PHY layers aren't enabled */
705 if (PTR_ERR(ci->phy) == -ENOSYS &&
706 PTR_ERR(ci->usb_phy) == -ENXIO)
707 return -ENXIO;
Peter Chenc859aa652014-02-19 13:41:40 +0800708
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100709 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
710 return -EPROBE_DEFER;
711
712 if (IS_ERR(ci->phy))
713 ci->phy = NULL;
714 else if (IS_ERR(ci->usb_phy))
715 ci->usb_phy = NULL;
Peter Chenc859aa652014-02-19 13:41:40 +0800716 }
717
Peter Chend03cccf2014-04-23 15:56:37 +0800718 ret = ci_usb_phy_init(ci);
Peter Chen74475ed2013-09-24 12:47:53 +0800719 if (ret) {
720 dev_err(dev, "unable to init phy: %d\n", ret);
721 return ret;
722 }
723
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300724 ci->hw_bank.phys = res->start;
725
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300726 ci->irq = platform_get_irq(pdev, 0);
727 if (ci->irq < 0) {
728 dev_err(dev, "missing IRQ\n");
Fabio Estevam42d18212014-02-19 13:41:44 +0800729 ret = ci->irq;
Peter Chenc859aa652014-02-19 13:41:40 +0800730 goto deinit_phy;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300731 }
732
Peter Chen577b2322013-08-14 12:44:08 +0300733 ci_get_otg_capable(ci);
734
Sascha Hauer691962d2013-06-13 17:59:57 +0300735 dr_mode = ci->platdata->dr_mode;
736 /* initialize role(s) before the interrupt is requested */
737 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
738 ret = ci_hdrc_host_init(ci);
739 if (ret)
740 dev_info(dev, "doesn't support host\n");
741 }
742
743 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
744 ret = ci_hdrc_gadget_init(ci);
745 if (ret)
746 dev_info(dev, "doesn't support gadget\n");
747 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300748
749 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
750 dev_err(dev, "no supported roles\n");
Peter Chen74475ed2013-09-24 12:47:53 +0800751 ret = -ENODEV;
Peter Chenc859aa652014-02-19 13:41:40 +0800752 goto deinit_phy;
Peter Chencbec6bd2013-08-14 12:44:10 +0300753 }
754
Peter Chen27c62c22014-09-22 08:14:16 +0800755 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
Peter Chencbec6bd2013-08-14 12:44:10 +0300756 ret = ci_hdrc_otg_init(ci);
757 if (ret) {
758 dev_err(dev, "init otg fails, ret = %d\n", ret);
759 goto stop;
760 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300761 }
762
763 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
Peter Chen577b2322013-08-14 12:44:08 +0300764 if (ci->is_otg) {
Peter Chen577b2322013-08-14 12:44:08 +0300765 ci->role = ci_otg_role(ci);
Li Jun0c33bf72014-04-23 15:56:38 +0800766 /* Enable ID change irq */
767 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
Peter Chen577b2322013-08-14 12:44:08 +0300768 } else {
769 /*
770 * If the controller is not OTG capable, but support
771 * role switch, the defalt role is gadget, and the
772 * user can switch it through debugfs.
773 */
774 ci->role = CI_ROLE_GADGET;
775 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300776 } else {
777 ci->role = ci->roles[CI_ROLE_HOST]
778 ? CI_ROLE_HOST
779 : CI_ROLE_GADGET;
780 }
781
Peter Chen5a1e1452013-12-05 15:20:50 +0800782 /* only update vbus status for peripheral */
783 if (ci->role == CI_ROLE_GADGET)
784 ci_handle_vbus_change(ci);
785
Li Jun4dcf7202014-04-23 15:56:50 +0800786 if (!ci_otg_is_fsm_mode(ci)) {
787 ret = ci_role_start(ci, ci->role);
788 if (ret) {
789 dev_err(dev, "can't start %s role\n",
790 ci_role(ci)->name);
791 goto stop;
792 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300793 }
794
Peter Chen24c498d2014-12-24 11:33:17 +0800795 platform_set_drvdata(pdev, ci);
Peter Chen4c503dd2014-11-26 13:44:22 +0800796 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
797 ci->platdata->name, ci);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300798 if (ret)
799 goto stop;
800
Peter Chen1f874ed2015-02-11 12:44:45 +0800801 if (ci->supports_runtime_pm) {
802 pm_runtime_set_active(&pdev->dev);
803 pm_runtime_enable(&pdev->dev);
804 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
805 pm_runtime_mark_last_busy(ci->dev);
806 pm_runtime_use_autosuspend(&pdev->dev);
807 }
808
Li Jun4dcf7202014-04-23 15:56:50 +0800809 if (ci_otg_is_fsm_mode(ci))
810 ci_hdrc_otg_fsm_start(ci);
811
Peter Chenf8efa762015-02-11 12:44:48 +0800812 device_set_wakeup_capable(&pdev->dev, true);
813
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200814 ret = dbg_create_files(ci);
815 if (!ret)
816 return 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300817
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300818stop:
Peter Chen3f124d22013-08-14 12:44:07 +0300819 ci_role_destroy(ci);
Peter Chenc859aa652014-02-19 13:41:40 +0800820deinit_phy:
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100821 ci_usb_phy_exit(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300822
823 return ret;
824}
825
Bill Pembertonfb4e98a2012-11-19 13:26:20 -0500826static int ci_hdrc_remove(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300827{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300828 struct ci_hdrc *ci = platform_get_drvdata(pdev);
Alexander Shishkine443b332012-05-11 17:25:46 +0300829
Peter Chen1f874ed2015-02-11 12:44:45 +0800830 if (ci->supports_runtime_pm) {
831 pm_runtime_get_sync(&pdev->dev);
832 pm_runtime_disable(&pdev->dev);
833 pm_runtime_put_noidle(&pdev->dev);
834 }
835
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200836 dbg_remove_files(ci);
Peter Chen3f124d22013-08-14 12:44:07 +0300837 ci_role_destroy(ci);
Peter Chen864cf942013-09-24 12:47:55 +0800838 ci_hdrc_enter_lpm(ci, true);
Antoine Tenart1e5e2d32014-10-30 18:41:19 +0100839 ci_usb_phy_exit(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300840
841 return 0;
842}
843
Peter Chen1f874ed2015-02-11 12:44:45 +0800844#ifdef CONFIG_PM
Peter Chen80769322014-11-26 13:44:29 +0800845static void ci_controller_suspend(struct ci_hdrc *ci)
846{
Peter Chen1f874ed2015-02-11 12:44:45 +0800847 disable_irq(ci->irq);
Peter Chen80769322014-11-26 13:44:29 +0800848 ci_hdrc_enter_lpm(ci, true);
Peter Chen1f874ed2015-02-11 12:44:45 +0800849 usb_phy_set_suspend(ci->usb_phy, 1);
850 ci->in_lpm = true;
851 enable_irq(ci->irq);
Peter Chen80769322014-11-26 13:44:29 +0800852}
853
854static int ci_controller_resume(struct device *dev)
855{
856 struct ci_hdrc *ci = dev_get_drvdata(dev);
857
858 dev_dbg(dev, "at %s\n", __func__);
859
Peter Chen1f874ed2015-02-11 12:44:45 +0800860 if (!ci->in_lpm) {
861 WARN_ON(1);
862 return 0;
863 }
Peter Chen80769322014-11-26 13:44:29 +0800864
Peter Chen1f874ed2015-02-11 12:44:45 +0800865 ci_hdrc_enter_lpm(ci, false);
Peter Chen80769322014-11-26 13:44:29 +0800866 if (ci->usb_phy) {
867 usb_phy_set_suspend(ci->usb_phy, 0);
868 usb_phy_set_wakeup(ci->usb_phy, false);
869 hw_wait_phy_stable();
870 }
871
Peter Chen1f874ed2015-02-11 12:44:45 +0800872 ci->in_lpm = false;
873 if (ci->wakeup_int) {
874 ci->wakeup_int = false;
875 pm_runtime_mark_last_busy(ci->dev);
876 pm_runtime_put_autosuspend(ci->dev);
877 enable_irq(ci->irq);
878 }
879
Peter Chen80769322014-11-26 13:44:29 +0800880 return 0;
881}
882
Peter Chen1f874ed2015-02-11 12:44:45 +0800883#ifdef CONFIG_PM_SLEEP
Peter Chen80769322014-11-26 13:44:29 +0800884static int ci_suspend(struct device *dev)
885{
886 struct ci_hdrc *ci = dev_get_drvdata(dev);
887
888 if (ci->wq)
889 flush_workqueue(ci->wq);
Peter Chen1f874ed2015-02-11 12:44:45 +0800890 /*
891 * Controller needs to be active during suspend, otherwise the core
892 * may run resume when the parent is at suspend if other driver's
893 * suspend fails, it occurs before parent's suspend has not started,
894 * but the core suspend has finished.
895 */
896 if (ci->in_lpm)
897 pm_runtime_resume(dev);
898
899 if (ci->in_lpm) {
900 WARN_ON(1);
901 return 0;
902 }
Peter Chen80769322014-11-26 13:44:29 +0800903
Peter Chenf8efa762015-02-11 12:44:48 +0800904 if (device_may_wakeup(dev)) {
905 usb_phy_set_wakeup(ci->usb_phy, true);
906 enable_irq_wake(ci->irq);
907 }
908
Peter Chen80769322014-11-26 13:44:29 +0800909 ci_controller_suspend(ci);
910
911 return 0;
912}
913
914static int ci_resume(struct device *dev)
915{
Peter Chen1f874ed2015-02-11 12:44:45 +0800916 struct ci_hdrc *ci = dev_get_drvdata(dev);
917 int ret;
918
Peter Chenf8efa762015-02-11 12:44:48 +0800919 if (device_may_wakeup(dev))
920 disable_irq_wake(ci->irq);
921
Peter Chen1f874ed2015-02-11 12:44:45 +0800922 ret = ci_controller_resume(dev);
923 if (ret)
924 return ret;
925
926 if (ci->supports_runtime_pm) {
927 pm_runtime_disable(dev);
928 pm_runtime_set_active(dev);
929 pm_runtime_enable(dev);
930 }
931
932 return ret;
Peter Chen80769322014-11-26 13:44:29 +0800933}
934#endif /* CONFIG_PM_SLEEP */
935
Peter Chen1f874ed2015-02-11 12:44:45 +0800936static int ci_runtime_suspend(struct device *dev)
937{
938 struct ci_hdrc *ci = dev_get_drvdata(dev);
939
940 dev_dbg(dev, "at %s\n", __func__);
941
942 if (ci->in_lpm) {
943 WARN_ON(1);
944 return 0;
945 }
946
947 usb_phy_set_wakeup(ci->usb_phy, true);
948 ci_controller_suspend(ci);
949
950 return 0;
951}
952
953static int ci_runtime_resume(struct device *dev)
954{
955 return ci_controller_resume(dev);
956}
957
958#endif /* CONFIG_PM */
Peter Chen80769322014-11-26 13:44:29 +0800959static const struct dev_pm_ops ci_pm_ops = {
960 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
Peter Chen1f874ed2015-02-11 12:44:45 +0800961 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
Peter Chen80769322014-11-26 13:44:29 +0800962};
Peter Chen1f874ed2015-02-11 12:44:45 +0800963
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300964static struct platform_driver ci_hdrc_driver = {
965 .probe = ci_hdrc_probe,
Bill Pemberton76904172012-11-19 13:21:08 -0500966 .remove = ci_hdrc_remove,
Alexander Shishkine443b332012-05-11 17:25:46 +0300967 .driver = {
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300968 .name = "ci_hdrc",
Peter Chen80769322014-11-26 13:44:29 +0800969 .pm = &ci_pm_ops,
Alexander Shishkine443b332012-05-11 17:25:46 +0300970 },
971};
972
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300973module_platform_driver(ci_hdrc_driver);
Alexander Shishkine443b332012-05-11 17:25:46 +0300974
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300975MODULE_ALIAS("platform:ci_hdrc");
Alexander Shishkine443b332012-05-11 17:25:46 +0300976MODULE_LICENSE("GPL v2");
977MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300978MODULE_DESCRIPTION("ChipIdea HDRC Driver");