blob: 2828605aef3fcdeb76b529e7b478bdc866d1a27f [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/drmP.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031#include "radeon_reg.h"
32#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +000033#include "radeon_asic.h"
Jerome Glisse9f022dd2009-09-11 15:35:22 +020034#include "atom.h"
Corbin Simpson62cdc0c2010-01-06 19:28:48 +010035#include "r100d.h"
Jerome Glisse905b6822009-09-09 22:24:20 +020036#include "r420d.h"
Alex Deucher804c7552010-01-08 15:58:49 -050037#include "r420_reg_safe.h"
38
Alex Deucherce8f5372010-05-07 15:10:16 -040039void r420_pm_init_profile(struct radeon_device *rdev)
40{
41 /* default */
42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
46 /* low sh */
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -040048 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -040049 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -040051 /* mid sh */
52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -040056 /* high sh */
57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
61 /* low mh */
62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -040066 /* mid mh */
67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -040071 /* high mh */
72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
76}
77
Alex Deucher804c7552010-01-08 15:58:49 -050078static void r420_set_reg_safe(struct radeon_device *rdev)
79{
80 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
81 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
82}
Jerome Glisse771fe6b2009-06-05 14:42:42 +020083
Jerome Glisse771fe6b2009-06-05 14:42:42 +020084void r420_pipes_init(struct radeon_device *rdev)
85{
86 unsigned tmp;
87 unsigned gb_pipe_select;
88 unsigned num_pipes;
89
90 /* GA_ENHANCE workaround TCL deadlock issue */
Alex Deucher4612dc92010-02-05 01:58:28 -050091 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
92 (1 << 2) | (1 << 3));
Dave Airlie18a4cd2e2009-09-21 14:15:10 +100093 /* add idle wait as per freedesktop.org bug 24041 */
94 if (r100_gui_wait_for_idle(rdev)) {
95 printk(KERN_WARNING "Failed to wait GUI idle while "
96 "programming pipes. Bad things might happen.\n");
97 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +020098 /* get max number of pipes */
Alex Deucherd75ee3b2011-01-24 23:24:59 -050099 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200100 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
Tormod Volden94f7bf62010-04-22 16:57:32 -0400101
102 /* SE chips have 1 pipe */
103 if ((rdev->pdev->device == 0x5e4c) ||
104 (rdev->pdev->device == 0x5e4f))
105 num_pipes = 1;
106
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200107 rdev->num_gb_pipes = num_pipes;
108 tmp = 0;
109 switch (num_pipes) {
110 default:
111 /* force to 1 pipe */
112 num_pipes = 1;
113 case 1:
114 tmp = (0 << 1);
115 break;
116 case 2:
117 tmp = (3 << 1);
118 break;
119 case 3:
120 tmp = (6 << 1);
121 break;
122 case 4:
123 tmp = (7 << 1);
124 break;
125 }
Alex Deucher4612dc92010-02-05 01:58:28 -0500126 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200127 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
Alex Deucher4612dc92010-02-05 01:58:28 -0500128 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
129 WREG32(R300_GB_TILE_CONFIG, tmp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200130 if (r100_gui_wait_for_idle(rdev)) {
131 printk(KERN_WARNING "Failed to wait GUI idle while "
132 "programming pipes. Bad things might happen.\n");
133 }
134
Alex Deucher4612dc92010-02-05 01:58:28 -0500135 tmp = RREG32(R300_DST_PIPE_CONFIG);
136 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200137
138 WREG32(R300_RB2D_DSTCACHE_MODE,
139 RREG32(R300_RB2D_DSTCACHE_MODE) |
140 R300_DC_AUTOFLUSH_ENABLE |
141 R300_DC_DC_DISABLE_IGNORE_PE);
142
143 if (r100_gui_wait_for_idle(rdev)) {
144 printk(KERN_WARNING "Failed to wait GUI idle while "
145 "programming pipes. Bad things might happen.\n");
146 }
Alex Deucherf779b3e2009-08-19 19:11:39 -0400147
148 if (rdev->family == CHIP_RV530) {
149 tmp = RREG32(RV530_GB_PIPE_SELECT2);
150 if ((tmp & 3) == 3)
151 rdev->num_z_pipes = 2;
152 else
153 rdev->num_z_pipes = 1;
154 } else
155 rdev->num_z_pipes = 1;
156
157 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
158 rdev->num_gb_pipes, rdev->num_z_pipes);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159}
160
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200161u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200162{
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400163 unsigned long flags;
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200164 u32 r;
165
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400166 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200167 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
168 r = RREG32(R_0001FC_MC_IND_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400169 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200170 return r;
171}
172
173void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
174{
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400175 unsigned long flags;
176
177 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200178 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
179 S_0001F8_MC_IND_WR_EN(1));
180 WREG32(R_0001FC_MC_IND_DATA, v);
Alex Deucher0a5b7b02013-09-03 19:00:09 -0400181 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200182}
183
184static void r420_debugfs(struct radeon_device *rdev)
185{
186 if (r100_debugfs_rbbm_init(rdev)) {
187 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
188 }
189 if (r420_debugfs_pipes_info_init(rdev)) {
190 DRM_ERROR("Failed to register debugfs file for pipes !\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200191 }
192}
193
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200194static void r420_clock_resume(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200195{
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200196 u32 sclk_cntl;
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200197
198 if (radeon_dynclks != -1 && radeon_dynclks)
199 radeon_atom_set_clock_gating(rdev, 1);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200200 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
201 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
202 if (rdev->family == CHIP_R420)
203 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
204 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200205}
206
Corbin Simpson62cdc0c2010-01-06 19:28:48 +0100207static void r420_cp_errata_init(struct radeon_device *rdev)
208{
Christian Könige32eb502011-10-23 12:56:27 +0200209 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Christian König7b1f2482011-09-23 15:11:23 +0200210
Corbin Simpson62cdc0c2010-01-06 19:28:48 +0100211 /* RV410 and R420 can lock up if CP DMA to host memory happens
212 * while the 2D engine is busy.
213 *
214 * The proper workaround is to queue a RESYNC at the beginning
215 * of the CP init, apparently.
216 */
217 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
Christian Könige32eb502011-10-23 12:56:27 +0200218 radeon_ring_lock(rdev, ring, 8);
219 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
220 radeon_ring_write(ring, rdev->config.r300.resync_scratch);
221 radeon_ring_write(ring, 0xDEADBEEF);
Michel Dänzer1538a9e2014-08-18 17:34:55 +0900222 radeon_ring_unlock_commit(rdev, ring, false);
Corbin Simpson62cdc0c2010-01-06 19:28:48 +0100223}
224
225static void r420_cp_errata_fini(struct radeon_device *rdev)
226{
Christian Könige32eb502011-10-23 12:56:27 +0200227 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Christian König7b1f2482011-09-23 15:11:23 +0200228
Corbin Simpson62cdc0c2010-01-06 19:28:48 +0100229 /* Catch the RESYNC we dispatched all the way back,
230 * at the very beginning of the CP init.
231 */
Christian Könige32eb502011-10-23 12:56:27 +0200232 radeon_ring_lock(rdev, ring, 8);
233 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
234 radeon_ring_write(ring, R300_RB3D_DC_FINISH);
Michel Dänzer1538a9e2014-08-18 17:34:55 +0900235 radeon_ring_unlock_commit(rdev, ring, false);
Corbin Simpson62cdc0c2010-01-06 19:28:48 +0100236 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
237}
238
Dave Airliefc30b8e2009-09-18 15:19:37 +1000239static int r420_startup(struct radeon_device *rdev)
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200240{
241 int r;
242
Alex Deucher92cde002009-12-04 10:55:12 -0500243 /* set common regs */
244 r100_set_common_regs(rdev);
245 /* program mc */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200246 r300_mc_program(rdev);
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200247 /* Resume clock */
248 r420_clock_resume(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200249 /* Initialize GART (initialize after TTM so we can allocate
250 * memory through TTM but finalize after TTM) */
Jerome Glisse4aac0472009-09-14 18:29:49 +0200251 if (rdev->flags & RADEON_IS_PCIE) {
252 r = rv370_pcie_gart_enable(rdev);
253 if (r)
254 return r;
255 }
256 if (rdev->flags & RADEON_IS_PCI) {
257 r = r100_pci_gart_enable(rdev);
258 if (r)
259 return r;
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200260 }
261 r420_pipes_init(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400262
263 /* allocate wb buffer */
264 r = radeon_wb_init(rdev);
265 if (r)
266 return r;
267
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000268 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
269 if (r) {
270 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
271 return r;
272 }
273
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200274 /* Enable IRQ */
Adis Hamziće49f3952013-06-02 16:47:54 +0200275 if (!rdev->irq.installed) {
276 r = radeon_irq_kms_init(rdev);
277 if (r)
278 return r;
279 }
280
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200281 r100_irq_set(rdev);
Jerome Glissecafe6602010-01-07 12:39:21 +0100282 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200283 /* 1M ring buffer */
284 r = r100_cp_init(rdev, 1024 * 1024);
285 if (r) {
Paul Bolleec4f2ac2011-01-28 23:32:04 +0100286 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200287 return r;
288 }
Corbin Simpson62cdc0c2010-01-06 19:28:48 +0100289 r420_cp_errata_init(rdev);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500290
Christian König2898c342012-07-05 11:55:34 +0200291 r = radeon_ib_pool_init(rdev);
292 if (r) {
293 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500294 return r;
Christian König2898c342012-07-05 11:55:34 +0200295 }
Jerome Glisseb15ba512011-11-15 11:48:34 -0500296
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200297 return 0;
298}
299
Dave Airliefc30b8e2009-09-18 15:19:37 +1000300int r420_resume(struct radeon_device *rdev)
301{
Jerome Glisse6b7746e2012-02-20 17:57:20 -0500302 int r;
303
Dave Airliefc30b8e2009-09-18 15:19:37 +1000304 /* Make sur GART are not working */
305 if (rdev->flags & RADEON_IS_PCIE)
306 rv370_pcie_gart_disable(rdev);
307 if (rdev->flags & RADEON_IS_PCI)
308 r100_pci_gart_disable(rdev);
309 /* Resume clock before doing reset */
310 r420_clock_resume(rdev);
311 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
Jerome Glissea2d07b72010-03-09 14:45:11 +0000312 if (radeon_asic_reset(rdev)) {
Dave Airliefc30b8e2009-09-18 15:19:37 +1000313 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
314 RREG32(R_000E40_RBBM_STATUS),
315 RREG32(R_0007C0_CP_STAT));
316 }
317 /* check if cards are posted or not */
318 if (rdev->is_atom_bios) {
319 atom_asic_init(rdev->mode_info.atom_context);
320 } else {
321 radeon_combios_asic_init(rdev->ddev);
322 }
323 /* Resume clock after posting */
324 r420_clock_resume(rdev);
Dave Airlie550e2d92009-12-09 14:15:38 +1000325 /* Initialize surface registers */
326 radeon_surface_init(rdev);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500327
328 rdev->accel_working = true;
Jerome Glisse6b7746e2012-02-20 17:57:20 -0500329 r = r420_startup(rdev);
330 if (r) {
331 rdev->accel_working = false;
332 }
333 return r;
Dave Airliefc30b8e2009-09-18 15:19:37 +1000334}
335
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200336int r420_suspend(struct radeon_device *rdev)
337{
Alex Deucher6c7bcce2013-12-18 14:07:14 -0500338 radeon_pm_suspend(rdev);
Corbin Simpson62cdc0c2010-01-06 19:28:48 +0100339 r420_cp_errata_fini(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200340 r100_cp_disable(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400341 radeon_wb_disable(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200342 r100_irq_disable(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200343 if (rdev->flags & RADEON_IS_PCIE)
344 rv370_pcie_gart_disable(rdev);
345 if (rdev->flags & RADEON_IS_PCI)
346 r100_pci_gart_disable(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200347 return 0;
348}
349
350void r420_fini(struct radeon_device *rdev)
351{
Alex Deucher6c7bcce2013-12-18 14:07:14 -0500352 radeon_pm_fini(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200353 r100_cp_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400354 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +0200355 radeon_ib_pool_fini(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200356 radeon_gem_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200357 if (rdev->flags & RADEON_IS_PCIE)
358 rv370_pcie_gart_fini(rdev);
359 if (rdev->flags & RADEON_IS_PCI)
360 r100_pci_gart_fini(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200361 radeon_agp_fini(rdev);
362 radeon_irq_kms_fini(rdev);
363 radeon_fence_driver_fini(rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +0100364 radeon_bo_fini(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200365 if (rdev->is_atom_bios) {
366 radeon_atombios_fini(rdev);
367 } else {
368 radeon_combios_fini(rdev);
369 }
370 kfree(rdev->bios);
371 rdev->bios = NULL;
372}
373
374int r420_init(struct radeon_device *rdev)
375{
376 int r;
377
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200378 /* Initialize scratch registers */
379 radeon_scratch_init(rdev);
380 /* Initialize surface registers */
381 radeon_surface_init(rdev);
382 /* TODO: disable VGA need to use VGA request */
Dave Airlie4c712e62010-07-15 12:13:50 +1000383 /* restore some register to sane defaults */
384 r100_restore_sanity(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200385 /* BIOS*/
386 if (!radeon_get_bios(rdev)) {
387 if (ASIC_IS_AVIVO(rdev))
388 return -EINVAL;
389 }
390 if (rdev->is_atom_bios) {
391 r = radeon_atombios_init(rdev);
392 if (r) {
393 return r;
394 }
395 } else {
396 r = radeon_combios_init(rdev);
397 if (r) {
398 return r;
399 }
400 }
401 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
Jerome Glissea2d07b72010-03-09 14:45:11 +0000402 if (radeon_asic_reset(rdev)) {
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200403 dev_warn(rdev->dev,
404 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
405 RREG32(R_000E40_RBBM_STATUS),
406 RREG32(R_0007C0_CP_STAT));
407 }
408 /* check if cards are posted or not */
Dave Airlie72542d72009-12-01 14:06:31 +1000409 if (radeon_boot_test_post_card(rdev) == false)
410 return -EINVAL;
411
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200412 /* Initialize clocks */
413 radeon_get_clock_info(rdev->ddev);
Jerome Glissed594e462010-02-17 21:54:29 +0000414 /* initialize AGP */
415 if (rdev->flags & RADEON_IS_AGP) {
416 r = radeon_agp_init(rdev);
417 if (r) {
418 radeon_agp_disable(rdev);
419 }
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200420 }
Jerome Glissed594e462010-02-17 21:54:29 +0000421 /* initialize memory controller */
422 r300_mc_init(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200423 r420_debugfs(rdev);
424 /* Fence driver */
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000425 r = radeon_fence_driver_init(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200426 if (r) {
427 return r;
428 }
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200429 /* Memory manager */
Jerome Glisse4c788672009-11-20 14:29:23 +0100430 r = radeon_bo_init(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200431 if (r) {
432 return r;
433 }
Dave Airlie17e15b02009-11-05 15:36:53 +1000434 if (rdev->family == CHIP_R420)
435 r100_enable_bm(rdev);
436
Jerome Glisse4aac0472009-09-14 18:29:49 +0200437 if (rdev->flags & RADEON_IS_PCIE) {
438 r = rv370_pcie_gart_init(rdev);
439 if (r)
440 return r;
441 }
442 if (rdev->flags & RADEON_IS_PCI) {
443 r = r100_pci_gart_init(rdev);
444 if (r)
445 return r;
446 }
Alex Deucher804c7552010-01-08 15:58:49 -0500447 r420_set_reg_safe(rdev);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500448
Alex Deucher6c7bcce2013-12-18 14:07:14 -0500449 /* Initialize power management */
450 radeon_pm_init(rdev);
451
Jerome Glisse733289c2009-09-16 15:24:21 +0200452 rdev->accel_working = true;
Dave Airliefc30b8e2009-09-18 15:19:37 +1000453 r = r420_startup(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200454 if (r) {
455 /* Somethings want wront with the accel init stop accel */
456 dev_err(rdev->dev, "Disabling GPU acceleration\n");
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200457 r100_cp_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400458 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +0200459 radeon_ib_pool_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +0100460 radeon_irq_kms_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200461 if (rdev->flags & RADEON_IS_PCIE)
462 rv370_pcie_gart_fini(rdev);
463 if (rdev->flags & RADEON_IS_PCI)
464 r100_pci_gart_fini(rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200465 radeon_agp_fini(rdev);
Jerome Glisse733289c2009-09-16 15:24:21 +0200466 rdev->accel_working = false;
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200467 }
468 return 0;
469}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200470
471/*
472 * Debugfs info
473 */
474#if defined(CONFIG_DEBUG_FS)
475static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
476{
477 struct drm_info_node *node = (struct drm_info_node *) m->private;
478 struct drm_device *dev = node->minor->dev;
479 struct radeon_device *rdev = dev->dev_private;
480 uint32_t tmp;
481
482 tmp = RREG32(R400_GB_PIPE_SELECT);
483 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
484 tmp = RREG32(R300_GB_TILE_CONFIG);
485 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
486 tmp = RREG32(R300_DST_PIPE_CONFIG);
487 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
488 return 0;
489}
490
491static struct drm_info_list r420_pipes_info_list[] = {
492 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
493};
494#endif
495
496int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
497{
498#if defined(CONFIG_DEBUG_FS)
499 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
500#else
501 return 0;
502#endif
503}