blob: 0b1d562ec4a2aae19b20b2e64ffcede838228b7b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
Ayaz Abdulla87046e52006-12-19 23:33:32 -05006 * and Andrew de Quincey.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
Manfred Spraul18360982005-12-24 14:19:24 +010012 * Copyright (C) 2003,4,5 Manfred Spraul
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
Ayaz Abdullaf1405d322009-01-09 11:03:54 +000016 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
Joe Perches294a5542010-11-29 07:41:56 +000042
43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
Ayaz Abdulla3e1a3ce2009-03-05 08:02:38 +000045#define FORCEDETH_VERSION "0.64"
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#define DRV_NAME "forcedeth"
47
48#include <linux/module.h>
49#include <linux/types.h>
50#include <linux/pci.h>
51#include <linux/interrupt.h>
52#include <linux/netdevice.h>
53#include <linux/etherdevice.h>
54#include <linux/delay.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040055#include <linux/sched.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056#include <linux/spinlock.h>
57#include <linux/ethtool.h>
58#include <linux/timer.h>
59#include <linux/skbuff.h>
60#include <linux/mii.h>
61#include <linux/random.h>
62#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +020063#include <linux/if_vlan.h>
Matthias Gehre910638a2006-03-28 01:56:48 -080064#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090065#include <linux/slab.h>
Szymon Janc5504e132010-11-27 08:39:45 +000066#include <linux/uaccess.h>
67#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
69#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070070#include <asm/system.h>
71
Stephen Hemmingerbea33482007-10-03 16:41:36 -070072#define TX_WORK_PER_LOOP 64
73#define RX_WORK_PER_LOOP 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75/*
76 * Hardware access:
77 */
78
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000079#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
80#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
81#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
82#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
83#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
84#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
85#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
86#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
87#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
88#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
Mike Ditto7b5e0782010-07-25 21:54:28 -070089#define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
90#define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
91#define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
92#define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000093#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
94#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
95#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
96#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
97#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
98#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
99#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
100#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
101#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
102#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
103#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
104#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
105#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106
107enum {
108 NvRegIrqStatus = 0x000,
109#define NVREG_IRQSTAT_MIIEVENT 0x040
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800110#define NVREG_IRQSTAT_MASK 0x83ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 NvRegIrqMask = 0x004,
112#define NVREG_IRQ_RX_ERROR 0x0001
113#define NVREG_IRQ_RX 0x0002
114#define NVREG_IRQ_RX_NOBUF 0x0004
115#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200116#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117#define NVREG_IRQ_TIMER 0x0020
118#define NVREG_IRQ_LINK 0x0040
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500119#define NVREG_IRQ_RX_FORCED 0x0080
120#define NVREG_IRQ_TX_FORCED 0x0100
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800121#define NVREG_IRQ_RECOVER_ERROR 0x8200
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500122#define NVREG_IRQMASK_THROUGHPUT 0x00df
Ayaz Abdulla096a4582007-05-21 20:23:11 -0400123#define NVREG_IRQMASK_CPU 0x0060
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500124#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
125#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500126#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200127
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 NvRegUnknownSetupReg6 = 0x008,
129#define NVREG_UNKSETUP6_VAL 3
130
131/*
132 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
133 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
134 */
135 NvRegPollingInterval = 0x00c,
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000136#define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500137#define NVREG_POLL_DEFAULT_CPU 13
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500138 NvRegMSIMap0 = 0x020,
139 NvRegMSIMap1 = 0x024,
140 NvRegMSIIrqMask = 0x030,
141#define NVREG_MSI_VECTOR_0_ENABLED 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142 NvRegMisc1 = 0x080,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400143#define NVREG_MISC1_PAUSE_TX 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144#define NVREG_MISC1_HD 0x02
145#define NVREG_MISC1_FORCE 0x3b0f3c
146
Ayaz Abdulla0a626772008-01-13 16:02:42 -0500147 NvRegMacReset = 0x34,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400148#define NVREG_MAC_RESET_ASSERT 0x0F3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 NvRegTransmitterControl = 0x084,
150#define NVREG_XMITCTL_START 0x01
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500151#define NVREG_XMITCTL_MGMT_ST 0x40000000
152#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
153#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
154#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
155#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
156#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
157#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
158#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
159#define NVREG_XMITCTL_HOST_LOADED 0x00004000
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500160#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800161#define NVREG_XMITCTL_DATA_START 0x00100000
162#define NVREG_XMITCTL_DATA_READY 0x00010000
163#define NVREG_XMITCTL_DATA_ERROR 0x00020000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 NvRegTransmitterStatus = 0x088,
165#define NVREG_XMITSTAT_BUSY 0x01
166
167 NvRegPacketFilterFlags = 0x8c,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400168#define NVREG_PFF_PAUSE_RX 0x08
169#define NVREG_PFF_ALWAYS 0x7F0000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170#define NVREG_PFF_PROMISC 0x80
171#define NVREG_PFF_MYADDR 0x20
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400172#define NVREG_PFF_LOOPBACK 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173
174 NvRegOffloadConfig = 0x90,
175#define NVREG_OFFLOAD_HOMEPHY 0x601
176#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
177 NvRegReceiverControl = 0x094,
178#define NVREG_RCVCTL_START 0x01
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500179#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 NvRegReceiverStatus = 0x98,
181#define NVREG_RCVSTAT_BUSY 0x01
182
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700183 NvRegSlotTime = 0x9c,
184#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
185#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
Szymon Janc78aea4f2010-11-27 08:39:43 +0000186#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700187#define NVREG_SLOTTIME_HALF 0x0000ff00
Szymon Janc78aea4f2010-11-27 08:39:43 +0000188#define NVREG_SLOTTIME_DEFAULT 0x00007f00
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700189#define NVREG_SLOTTIME_MASK 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400191 NvRegTxDeferral = 0xA0,
Ayaz Abdullafd9b5582008-02-05 12:29:49 -0500192#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
193#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
194#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
195#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
196#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
197#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400198 NvRegRxDeferral = 0xA4,
199#define NVREG_RX_DEFERRAL_DEFAULT 0x16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 NvRegMacAddrA = 0xA8,
201 NvRegMacAddrB = 0xAC,
202 NvRegMulticastAddrA = 0xB0,
203#define NVREG_MCASTADDRA_FORCE 0x01
204 NvRegMulticastAddrB = 0xB4,
205 NvRegMulticastMaskA = 0xB8,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500206#define NVREG_MCASTMASKA_NONE 0xffffffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207 NvRegMulticastMaskB = 0xBC,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500208#define NVREG_MCASTMASKB_NONE 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209
210 NvRegPhyInterface = 0xC0,
211#define PHY_RGMII 0x10000000
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700212 NvRegBackOffControl = 0xC4,
213#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
214#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
215#define NVREG_BKOFFCTRL_SELECT 24
216#define NVREG_BKOFFCTRL_GEAR 12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217
218 NvRegTxRingPhysAddr = 0x100,
219 NvRegRxRingPhysAddr = 0x104,
220 NvRegRingSizes = 0x108,
221#define NVREG_RINGSZ_TXSHIFT 0
222#define NVREG_RINGSZ_RXSHIFT 16
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400223 NvRegTransmitPoll = 0x10c,
224#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 NvRegLinkSpeed = 0x110,
226#define NVREG_LINKSPEED_FORCE 0x10000
227#define NVREG_LINKSPEED_10 1000
228#define NVREG_LINKSPEED_100 100
229#define NVREG_LINKSPEED_1000 50
230#define NVREG_LINKSPEED_MASK (0xFFF)
231 NvRegUnknownSetupReg5 = 0x130,
232#define NVREG_UNKSETUP5_BIT31 (1<<31)
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400233 NvRegTxWatermark = 0x13c,
234#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
235#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
236#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 NvRegTxRxControl = 0x144,
238#define NVREG_TXRXCTL_KICK 0x0001
239#define NVREG_TXRXCTL_BIT1 0x0002
240#define NVREG_TXRXCTL_BIT2 0x0004
241#define NVREG_TXRXCTL_IDLE 0x0008
242#define NVREG_TXRXCTL_RESET 0x0010
243#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400244#define NVREG_TXRXCTL_DESC_1 0
Ayaz Abdullad2f78412007-01-09 13:30:02 -0500245#define NVREG_TXRXCTL_DESC_2 0x002100
246#define NVREG_TXRXCTL_DESC_3 0xc02200
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500247#define NVREG_TXRXCTL_VLANSTRIP 0x00040
248#define NVREG_TXRXCTL_VLANINS 0x00080
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500249 NvRegTxRingPhysAddrHigh = 0x148,
250 NvRegRxRingPhysAddrHigh = 0x14C,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400251 NvRegTxPauseFrame = 0x170,
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500252#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
253#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
254#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
255#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
Ayaz Abdulla9a33e882008-08-06 12:12:34 -0400256 NvRegTxPauseFrameLimit = 0x174,
257#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 NvRegMIIStatus = 0x180,
259#define NVREG_MIISTAT_ERROR 0x0001
260#define NVREG_MIISTAT_LINKCHANGE 0x0008
Ayaz Abdullaeb798422008-02-04 15:14:04 -0500261#define NVREG_MIISTAT_MASK_RW 0x0007
262#define NVREG_MIISTAT_MASK_ALL 0x000f
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500263 NvRegMIIMask = 0x184,
264#define NVREG_MII_LINKCHANGE 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
266 NvRegAdapterControl = 0x188,
267#define NVREG_ADAPTCTL_START 0x02
268#define NVREG_ADAPTCTL_LINKUP 0x04
269#define NVREG_ADAPTCTL_PHYVALID 0x40000
270#define NVREG_ADAPTCTL_RUNNING 0x100000
271#define NVREG_ADAPTCTL_PHYSHIFT 24
272 NvRegMIISpeed = 0x18c,
273#define NVREG_MIISPEED_BIT8 (1<<8)
274#define NVREG_MIIDELAY 5
275 NvRegMIIControl = 0x190,
276#define NVREG_MIICTL_INUSE 0x08000
277#define NVREG_MIICTL_WRITE 0x00400
278#define NVREG_MIICTL_ADDRSHIFT 5
279 NvRegMIIData = 0x194,
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400280 NvRegTxUnicast = 0x1a0,
281 NvRegTxMulticast = 0x1a4,
282 NvRegTxBroadcast = 0x1a8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 NvRegWakeUpFlags = 0x200,
284#define NVREG_WAKEUPFLAGS_VAL 0x7770
285#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
286#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
287#define NVREG_WAKEUPFLAGS_D3SHIFT 12
288#define NVREG_WAKEUPFLAGS_D2SHIFT 8
289#define NVREG_WAKEUPFLAGS_D1SHIFT 4
290#define NVREG_WAKEUPFLAGS_D0SHIFT 0
291#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
292#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
293#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
294#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
295
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800296 NvRegMgmtUnitGetVersion = 0x204,
Szymon Janc78aea4f2010-11-27 08:39:43 +0000297#define NVREG_MGMTUNITGETVERSION 0x01
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800298 NvRegMgmtUnitVersion = 0x208,
299#define NVREG_MGMTUNITVERSION 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300 NvRegPowerCap = 0x268,
301#define NVREG_POWERCAP_D3SUPP (1<<30)
302#define NVREG_POWERCAP_D2SUPP (1<<26)
303#define NVREG_POWERCAP_D1SUPP (1<<25)
304 NvRegPowerState = 0x26c,
305#define NVREG_POWERSTATE_POWEREDUP 0x8000
306#define NVREG_POWERSTATE_VALID 0x0100
307#define NVREG_POWERSTATE_MASK 0x0003
308#define NVREG_POWERSTATE_D0 0x0000
309#define NVREG_POWERSTATE_D1 0x0001
310#define NVREG_POWERSTATE_D2 0x0002
311#define NVREG_POWERSTATE_D3 0x0003
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800312 NvRegMgmtUnitControl = 0x278,
313#define NVREG_MGMTUNITCONTROL_INUSE 0x20000
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400314 NvRegTxCnt = 0x280,
315 NvRegTxZeroReXmt = 0x284,
316 NvRegTxOneReXmt = 0x288,
317 NvRegTxManyReXmt = 0x28c,
318 NvRegTxLateCol = 0x290,
319 NvRegTxUnderflow = 0x294,
320 NvRegTxLossCarrier = 0x298,
321 NvRegTxExcessDef = 0x29c,
322 NvRegTxRetryErr = 0x2a0,
323 NvRegRxFrameErr = 0x2a4,
324 NvRegRxExtraByte = 0x2a8,
325 NvRegRxLateCol = 0x2ac,
326 NvRegRxRunt = 0x2b0,
327 NvRegRxFrameTooLong = 0x2b4,
328 NvRegRxOverflow = 0x2b8,
329 NvRegRxFCSErr = 0x2bc,
330 NvRegRxFrameAlignErr = 0x2c0,
331 NvRegRxLenErr = 0x2c4,
332 NvRegRxUnicast = 0x2c8,
333 NvRegRxMulticast = 0x2cc,
334 NvRegRxBroadcast = 0x2d0,
335 NvRegTxDef = 0x2d4,
336 NvRegTxFrame = 0x2d8,
337 NvRegRxCnt = 0x2dc,
338 NvRegTxPause = 0x2e0,
339 NvRegRxPause = 0x2e4,
340 NvRegRxDropFrame = 0x2e8,
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500341 NvRegVlanControl = 0x300,
342#define NVREG_VLANCONTROL_ENABLE 0x2000
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500343 NvRegMSIXMap0 = 0x3e0,
344 NvRegMSIXMap1 = 0x3e4,
345 NvRegMSIXIrqStatus = 0x3f0,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400346
347 NvRegPowerState2 = 0x600,
Ayaz Abdulla1545e202008-09-22 09:55:35 -0400348#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400349#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400350#define NVREG_POWERSTATE2_PHY_RESET 0x0004
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +0000351#define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352};
353
354/* Big endian: should work, but is untested */
355struct ring_desc {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700356 __le32 buf;
357 __le32 flaglen;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358};
359
Manfred Spraulee733622005-07-31 18:32:26 +0200360struct ring_desc_ex {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700361 __le32 bufhigh;
362 __le32 buflow;
363 __le32 txvlan;
364 __le32 flaglen;
Manfred Spraulee733622005-07-31 18:32:26 +0200365};
366
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700367union ring_type {
Szymon Janc78aea4f2010-11-27 08:39:43 +0000368 struct ring_desc *orig;
369 struct ring_desc_ex *ex;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700370};
Manfred Spraulee733622005-07-31 18:32:26 +0200371
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372#define FLAG_MASK_V1 0xffff0000
373#define FLAG_MASK_V2 0xffffc000
374#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
375#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
376
377#define NV_TX_LASTPACKET (1<<16)
378#define NV_TX_RETRYERROR (1<<19)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700379#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200380#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381#define NV_TX_DEFERRED (1<<26)
382#define NV_TX_CARRIERLOST (1<<27)
383#define NV_TX_LATECOLLISION (1<<28)
384#define NV_TX_UNDERFLOW (1<<29)
385#define NV_TX_ERROR (1<<30)
386#define NV_TX_VALID (1<<31)
387
388#define NV_TX2_LASTPACKET (1<<29)
389#define NV_TX2_RETRYERROR (1<<18)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700390#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200391#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392#define NV_TX2_DEFERRED (1<<25)
393#define NV_TX2_CARRIERLOST (1<<26)
394#define NV_TX2_LATECOLLISION (1<<27)
395#define NV_TX2_UNDERFLOW (1<<28)
396/* error and valid are the same for both */
397#define NV_TX2_ERROR (1<<30)
398#define NV_TX2_VALID (1<<31)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400399#define NV_TX2_TSO (1<<28)
400#define NV_TX2_TSO_SHIFT 14
Ayaz Abdullafa454592006-01-05 22:45:45 -0800401#define NV_TX2_TSO_MAX_SHIFT 14
402#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400403#define NV_TX2_CHECKSUM_L3 (1<<27)
404#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500406#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
407
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408#define NV_RX_DESCRIPTORVALID (1<<16)
409#define NV_RX_MISSEDFRAME (1<<17)
410#define NV_RX_SUBSTRACT1 (1<<18)
411#define NV_RX_ERROR1 (1<<23)
412#define NV_RX_ERROR2 (1<<24)
413#define NV_RX_ERROR3 (1<<25)
414#define NV_RX_ERROR4 (1<<26)
415#define NV_RX_CRCERR (1<<27)
416#define NV_RX_OVERFLOW (1<<28)
417#define NV_RX_FRAMINGERR (1<<29)
418#define NV_RX_ERROR (1<<30)
419#define NV_RX_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400420#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421
422#define NV_RX2_CHECKSUMMASK (0x1C000000)
Ayaz Abdullabfaffe82008-01-13 16:02:55 -0500423#define NV_RX2_CHECKSUM_IP (0x10000000)
424#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
425#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426#define NV_RX2_DESCRIPTORVALID (1<<29)
427#define NV_RX2_SUBSTRACT1 (1<<25)
428#define NV_RX2_ERROR1 (1<<18)
429#define NV_RX2_ERROR2 (1<<19)
430#define NV_RX2_ERROR3 (1<<20)
431#define NV_RX2_ERROR4 (1<<21)
432#define NV_RX2_CRCERR (1<<22)
433#define NV_RX2_OVERFLOW (1<<23)
434#define NV_RX2_FRAMINGERR (1<<24)
435/* error and avail are the same for both */
436#define NV_RX2_ERROR (1<<30)
437#define NV_RX2_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400438#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500440#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
441#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
442
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443/* Miscelaneous hardware related defines: */
Szymon Janc78aea4f2010-11-27 08:39:43 +0000444#define NV_PCI_REGSZ_VER1 0x270
445#define NV_PCI_REGSZ_VER2 0x2d4
446#define NV_PCI_REGSZ_VER3 0x604
447#define NV_PCI_REGSZ_MAX 0x604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
449/* various timeout delays: all in usec */
450#define NV_TXRX_RESET_DELAY 4
451#define NV_TXSTOP_DELAY1 10
452#define NV_TXSTOP_DELAY1MAX 500000
453#define NV_TXSTOP_DELAY2 100
454#define NV_RXSTOP_DELAY1 10
455#define NV_RXSTOP_DELAY1MAX 500000
456#define NV_RXSTOP_DELAY2 100
457#define NV_SETUP5_DELAY 5
458#define NV_SETUP5_DELAYMAX 50000
459#define NV_POWERUP_DELAY 5
460#define NV_POWERUP_DELAYMAX 5000
461#define NV_MIIBUSY_DELAY 50
462#define NV_MIIPHY_DELAY 10
463#define NV_MIIPHY_DELAYMAX 10000
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400464#define NV_MAC_RESET_DELAY 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
466#define NV_WAKEUPPATTERNS 5
467#define NV_WAKEUPMASKENTRIES 4
468
469/* General driver defaults */
470#define NV_WATCHDOG_TIMEO (5*HZ)
471
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000472#define RX_RING_DEFAULT 512
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400473#define TX_RING_DEFAULT 256
474#define RX_RING_MIN 128
475#define TX_RING_MIN 64
476#define RING_MAX_DESC_VER_1 1024
477#define RING_MAX_DESC_VER_2_3 16384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478
479/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200480#define NV_RX_HEADERS (64)
481/* even more slack. */
482#define NV_RX_ALLOC_PAD (64)
483
484/* maximum mtu size */
485#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
486#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487
488#define OOM_REFILL (1+HZ/20)
489#define POLL_WAIT (1+HZ/100)
490#define LINK_TIMEOUT (3*HZ)
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400491#define STATS_INTERVAL (10*HZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400493/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400495 * The nic supports three different descriptor types:
496 * - DESC_VER_1: Original
497 * - DESC_VER_2: support for jumbo frames.
498 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400500#define DESC_VER_1 1
501#define DESC_VER_2 2
502#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503
504/* PHY defines */
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400505#define PHY_OUI_MARVELL 0x5043
506#define PHY_OUI_CICADA 0x03f1
507#define PHY_OUI_VITESSE 0x01c1
508#define PHY_OUI_REALTEK 0x0732
509#define PHY_OUI_REALTEK2 0x0020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510#define PHYID1_OUI_MASK 0x03ff
511#define PHYID1_OUI_SHFT 6
512#define PHYID2_OUI_MASK 0xfc00
513#define PHYID2_OUI_SHFT 10
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400514#define PHYID2_MODEL_MASK 0x03f0
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400515#define PHY_MODEL_REALTEK_8211 0x0110
516#define PHY_REV_MASK 0x0001
517#define PHY_REV_REALTEK_8211B 0x0000
518#define PHY_REV_REALTEK_8211C 0x0001
519#define PHY_MODEL_REALTEK_8201 0x0200
520#define PHY_MODEL_MARVELL_E3016 0x0220
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400521#define PHY_MARVELL_E3016_INITMASK 0x0300
Ayaz Abdulla14a67f32007-07-15 06:50:28 -0400522#define PHY_CICADA_INIT1 0x0f000
523#define PHY_CICADA_INIT2 0x0e00
524#define PHY_CICADA_INIT3 0x01000
525#define PHY_CICADA_INIT4 0x0200
526#define PHY_CICADA_INIT5 0x0004
527#define PHY_CICADA_INIT6 0x02000
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400528#define PHY_VITESSE_INIT_REG1 0x1f
529#define PHY_VITESSE_INIT_REG2 0x10
530#define PHY_VITESSE_INIT_REG3 0x11
531#define PHY_VITESSE_INIT_REG4 0x12
532#define PHY_VITESSE_INIT_MSK1 0xc
533#define PHY_VITESSE_INIT_MSK2 0x0180
534#define PHY_VITESSE_INIT1 0x52b5
535#define PHY_VITESSE_INIT2 0xaf8a
536#define PHY_VITESSE_INIT3 0x8
537#define PHY_VITESSE_INIT4 0x8f8a
538#define PHY_VITESSE_INIT5 0xaf86
539#define PHY_VITESSE_INIT6 0x8f86
540#define PHY_VITESSE_INIT7 0xaf82
541#define PHY_VITESSE_INIT8 0x0100
542#define PHY_VITESSE_INIT9 0x8f82
543#define PHY_VITESSE_INIT10 0x0
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400544#define PHY_REALTEK_INIT_REG1 0x1f
545#define PHY_REALTEK_INIT_REG2 0x19
546#define PHY_REALTEK_INIT_REG3 0x13
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400547#define PHY_REALTEK_INIT_REG4 0x14
548#define PHY_REALTEK_INIT_REG5 0x18
549#define PHY_REALTEK_INIT_REG6 0x11
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400550#define PHY_REALTEK_INIT_REG7 0x01
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400551#define PHY_REALTEK_INIT1 0x0000
552#define PHY_REALTEK_INIT2 0x8e00
553#define PHY_REALTEK_INIT3 0x0001
554#define PHY_REALTEK_INIT4 0xad17
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400555#define PHY_REALTEK_INIT5 0xfb54
556#define PHY_REALTEK_INIT6 0xf5c7
557#define PHY_REALTEK_INIT7 0x1000
558#define PHY_REALTEK_INIT8 0x0003
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400559#define PHY_REALTEK_INIT9 0x0008
560#define PHY_REALTEK_INIT10 0x0005
561#define PHY_REALTEK_INIT11 0x0200
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400562#define PHY_REALTEK_INIT_MSK1 0x0003
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400563
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564#define PHY_GIGABIT 0x0100
565
566#define PHY_TIMEOUT 0x1
567#define PHY_ERROR 0x2
568
569#define PHY_100 0x1
570#define PHY_1000 0x2
571#define PHY_HALF 0x100
572
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400573#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
574#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
575#define NV_PAUSEFRAME_RX_ENABLE 0x0004
576#define NV_PAUSEFRAME_TX_ENABLE 0x0008
Ayaz Abdullab6d07732006-06-10 22:47:42 -0400577#define NV_PAUSEFRAME_RX_REQ 0x0010
578#define NV_PAUSEFRAME_TX_REQ 0x0020
579#define NV_PAUSEFRAME_AUTONEG 0x0040
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500581/* MSI/MSI-X defines */
582#define NV_MSI_X_MAX_VECTORS 8
583#define NV_MSI_X_VECTORS_MASK 0x000f
584#define NV_MSI_CAPABLE 0x0010
585#define NV_MSI_X_CAPABLE 0x0020
586#define NV_MSI_ENABLED 0x0040
587#define NV_MSI_X_ENABLED 0x0080
588
589#define NV_MSI_X_VECTOR_ALL 0x0
590#define NV_MSI_X_VECTOR_RX 0x0
591#define NV_MSI_X_VECTOR_TX 0x1
592#define NV_MSI_X_VECTOR_OTHER 0x2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593
Ayaz Abdullab6e44052009-02-07 00:24:15 -0800594#define NV_MSI_PRIV_OFFSET 0x68
595#define NV_MSI_PRIV_VALUE 0xffffffff
596
Ayaz Abdullab2976d22008-02-04 15:13:59 -0500597#define NV_RESTART_TX 0x1
598#define NV_RESTART_RX 0x2
599
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500600#define NV_TX_LIMIT_COUNT 16
601
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000602#define NV_DYNAMIC_THRESHOLD 4
603#define NV_DYNAMIC_MAX_QUIET_COUNT 2048
604
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400605/* statistics */
606struct nv_ethtool_str {
607 char name[ETH_GSTRING_LEN];
608};
609
610static const struct nv_ethtool_str nv_estats_str[] = {
611 { "tx_bytes" },
612 { "tx_zero_rexmt" },
613 { "tx_one_rexmt" },
614 { "tx_many_rexmt" },
615 { "tx_late_collision" },
616 { "tx_fifo_errors" },
617 { "tx_carrier_errors" },
618 { "tx_excess_deferral" },
619 { "tx_retry_error" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400620 { "rx_frame_error" },
621 { "rx_extra_byte" },
622 { "rx_late_collision" },
623 { "rx_runt" },
624 { "rx_frame_too_long" },
625 { "rx_over_errors" },
626 { "rx_crc_errors" },
627 { "rx_frame_align_error" },
628 { "rx_length_error" },
629 { "rx_unicast" },
630 { "rx_multicast" },
631 { "rx_broadcast" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400632 { "rx_packets" },
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500633 { "rx_errors_total" },
634 { "tx_errors_total" },
635
636 /* version 2 stats */
637 { "tx_deferral" },
638 { "tx_packets" },
639 { "rx_bytes" },
640 { "tx_pause" },
641 { "rx_pause" },
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400642 { "rx_drop_frame" },
643
644 /* version 3 stats */
645 { "tx_unicast" },
646 { "tx_multicast" },
647 { "tx_broadcast" }
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400648};
649
650struct nv_ethtool_stats {
651 u64 tx_bytes;
652 u64 tx_zero_rexmt;
653 u64 tx_one_rexmt;
654 u64 tx_many_rexmt;
655 u64 tx_late_collision;
656 u64 tx_fifo_errors;
657 u64 tx_carrier_errors;
658 u64 tx_excess_deferral;
659 u64 tx_retry_error;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400660 u64 rx_frame_error;
661 u64 rx_extra_byte;
662 u64 rx_late_collision;
663 u64 rx_runt;
664 u64 rx_frame_too_long;
665 u64 rx_over_errors;
666 u64 rx_crc_errors;
667 u64 rx_frame_align_error;
668 u64 rx_length_error;
669 u64 rx_unicast;
670 u64 rx_multicast;
671 u64 rx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400672 u64 rx_packets;
673 u64 rx_errors_total;
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500674 u64 tx_errors_total;
675
676 /* version 2 stats */
677 u64 tx_deferral;
678 u64 tx_packets;
679 u64 rx_bytes;
680 u64 tx_pause;
681 u64 rx_pause;
682 u64 rx_drop_frame;
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400683
684 /* version 3 stats */
685 u64 tx_unicast;
686 u64 tx_multicast;
687 u64 tx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400688};
689
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400690#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
691#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500692#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
693
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400694/* diagnostics */
695#define NV_TEST_COUNT_BASE 3
696#define NV_TEST_COUNT_EXTENDED 4
697
698static const struct nv_ethtool_str nv_etests_str[] = {
699 { "link (online/offline)" },
700 { "register (offline) " },
701 { "interrupt (offline) " },
702 { "loopback (offline) " }
703};
704
705struct register_test {
Al Viro5bb7ea22007-12-09 16:06:41 +0000706 __u32 reg;
707 __u32 mask;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400708};
709
710static const struct register_test nv_registers_test[] = {
711 { NvRegUnknownSetupReg6, 0x01 },
712 { NvRegMisc1, 0x03c },
713 { NvRegOffloadConfig, 0x03ff },
714 { NvRegMulticastAddrA, 0xffffffff },
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400715 { NvRegTxWatermark, 0x0ff },
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400716 { NvRegWakeUpFlags, 0x07777 },
Szymon Janc78aea4f2010-11-27 08:39:43 +0000717 { 0, 0 }
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400718};
719
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500720struct nv_skb_map {
721 struct sk_buff *skb;
722 dma_addr_t dma;
Eric Dumazet73a37072009-06-17 21:17:59 +0000723 unsigned int dma_len:31;
724 unsigned int dma_single:1;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500725 struct ring_desc_ex *first_tx_desc;
726 struct nv_skb_map *next_tx_ctx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500727};
728
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729/*
730 * SMP locking:
Wang Chenb74ca3a2008-12-08 01:14:16 -0800731 * All hardware access under netdev_priv(dev)->lock, except the performance
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 * critical parts:
733 * - rx is (pseudo-) lockless: it relies on the single-threading provided
734 * by the arch code for interrupts.
Herbert Xu932ff272006-06-09 12:20:56 -0700735 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
Wang Chenb74ca3a2008-12-08 01:14:16 -0800736 * needs netdev_priv(dev)->lock :-(
Herbert Xu932ff272006-06-09 12:20:56 -0700737 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738 */
739
740/* in dev: base, irq */
741struct fe_priv {
742 spinlock_t lock;
743
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700744 struct net_device *dev;
745 struct napi_struct napi;
746
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 /* General data:
748 * Locking: spin_lock(&np->lock); */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400749 struct nv_ethtool_stats estats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750 int in_shutdown;
751 u32 linkspeed;
752 int duplex;
753 int autoneg;
754 int fixed_mode;
755 int phyaddr;
756 int wolenabled;
757 unsigned int phy_oui;
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400758 unsigned int phy_model;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400759 unsigned int phy_rev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 u16 gigabit;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400761 int intr_test;
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500762 int recover_error;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000763 int quiet_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764
765 /* General data: RO fields */
766 dma_addr_t ring_addr;
767 struct pci_dev *pci_dev;
768 u32 orig_mac[2];
Ayaz Abdulla582806b2009-03-05 08:02:03 +0000769 u32 events;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 u32 irqmask;
771 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400772 u32 txrxctl_bits;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500773 u32 vlanctl_bits;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400774 u32 driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400775 u32 device_id;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400776 u32 register_size;
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -0400777 int rx_csum;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500778 u32 mac_in_use;
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800779 int mgmt_version;
780 int mgmt_sema;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
782 void __iomem *base;
783
784 /* rx specific fields.
785 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
786 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500787 union ring_type get_rx, put_rx, first_rx, last_rx;
788 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
789 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
790 struct nv_skb_map *rx_skb;
791
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700792 union ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200794 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 struct timer_list oom_kick;
796 struct timer_list nic_poll;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400797 struct timer_list stats_poll;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500798 u32 nic_poll_irq;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400799 int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800
801 /* media detection workaround.
802 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
803 */
804 int need_linktimer;
805 unsigned long link_timeout;
806 /*
807 * tx specific fields.
808 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500809 union ring_type get_tx, put_tx, first_tx, last_tx;
810 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
811 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
812 struct nv_skb_map *tx_skb;
813
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700814 union ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815 u32 tx_flags;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400816 int tx_ring_size;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500817 int tx_limit;
818 u32 tx_pkts_in_progress;
819 struct nv_skb_map *tx_change_owner;
820 struct nv_skb_map *tx_end_flip;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -0500821 int tx_stop;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500822
823 /* vlan fields */
824 struct vlan_group *vlangrp;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500825
826 /* msi/msi-x fields */
827 u32 msi_flags;
828 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400829
830 /* flow control */
831 u32 pause_flags;
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200832
833 /* power saved state */
834 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
Yinghai Luddb213f2009-02-06 01:29:23 -0800835
836 /* for different msi-x irq type */
837 char name_rx[IFNAMSIZ + 3]; /* -rx */
838 char name_tx[IFNAMSIZ + 3]; /* -tx */
839 char name_other[IFNAMSIZ + 6]; /* -other */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840};
841
842/*
843 * Maximum number of loops until we assume that a bit in the irq mask
844 * is stuck. Overridable with module param.
845 */
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000846static int max_interrupt_work = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500848/*
849 * Optimization can be either throuput mode or cpu mode
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400850 *
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500851 * Throughput Mode: Every tx and rx packet will generate an interrupt.
852 * CPU Mode: Interrupts are controlled by a timer.
853 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400854enum {
855 NV_OPTIMIZATION_MODE_THROUGHPUT,
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000856 NV_OPTIMIZATION_MODE_CPU,
857 NV_OPTIMIZATION_MODE_DYNAMIC
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400858};
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000859static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500860
861/*
862 * Poll interval for timer irq
863 *
864 * This interval determines how frequent an interrupt is generated.
865 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
866 * Min = 0, and Max = 65535
867 */
868static int poll_interval = -1;
869
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500870/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400871 * MSI interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500872 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400873enum {
874 NV_MSI_INT_DISABLED,
875 NV_MSI_INT_ENABLED
876};
877static int msi = NV_MSI_INT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500878
879/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400880 * MSIX interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500881 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400882enum {
883 NV_MSIX_INT_DISABLED,
884 NV_MSIX_INT_ENABLED
885};
Yinghai Lu39482792009-02-06 01:31:12 -0800886static int msix = NV_MSIX_INT_ENABLED;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400887
888/*
889 * DMA 64bit
890 */
891enum {
892 NV_DMA_64BIT_DISABLED,
893 NV_DMA_64BIT_ENABLED
894};
895static int dma_64bit = NV_DMA_64BIT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500896
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400897/*
898 * Crossover Detection
899 * Realtek 8201 phy + some OEM boards do not work properly.
900 */
901enum {
902 NV_CROSSOVER_DETECTION_DISABLED,
903 NV_CROSSOVER_DETECTION_ENABLED
904};
905static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
906
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700907/*
908 * Power down phy when interface is down (persists through reboot;
909 * older Linux and other OSes may not power it up again)
910 */
Szymon Janc78aea4f2010-11-27 08:39:43 +0000911static int phy_power_down;
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700912
Linus Torvalds1da177e2005-04-16 15:20:36 -0700913static inline struct fe_priv *get_nvpriv(struct net_device *dev)
914{
915 return netdev_priv(dev);
916}
917
918static inline u8 __iomem *get_hwbase(struct net_device *dev)
919{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400920 return ((struct fe_priv *)netdev_priv(dev))->base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921}
922
923static inline void pci_push(u8 __iomem *base)
924{
925 /* force out pending posted writes */
926 readl(base);
927}
928
929static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
930{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700931 return le32_to_cpu(prd->flaglen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
933}
934
Manfred Spraulee733622005-07-31 18:32:26 +0200935static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
936{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700937 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
Manfred Spraulee733622005-07-31 18:32:26 +0200938}
939
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400940static bool nv_optimized(struct fe_priv *np)
941{
942 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
943 return false;
944 return true;
945}
946
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
Joe Perches344d0dc2010-11-29 07:41:52 +0000948 int delay, int delaymax)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949{
950 u8 __iomem *base = get_hwbase(dev);
951
952 pci_push(base);
953 do {
954 udelay(delay);
955 delaymax -= delay;
Joe Perches344d0dc2010-11-29 07:41:52 +0000956 if (delaymax < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958 } while ((readl(base + offset) & mask) != target);
959 return 0;
960}
961
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500962#define NV_SETUP_RX_RING 0x01
963#define NV_SETUP_TX_RING 0x02
964
Al Viro5bb7ea22007-12-09 16:06:41 +0000965static inline u32 dma_low(dma_addr_t addr)
966{
967 return addr;
968}
969
970static inline u32 dma_high(dma_addr_t addr)
971{
972 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
973}
974
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500975static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
976{
977 struct fe_priv *np = get_nvpriv(dev);
978 u8 __iomem *base = get_hwbase(dev);
979
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400980 if (!nv_optimized(np)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +0000981 if (rxtx_flags & NV_SETUP_RX_RING)
Al Viro5bb7ea22007-12-09 16:06:41 +0000982 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
Szymon Janc78aea4f2010-11-27 08:39:43 +0000983 if (rxtx_flags & NV_SETUP_TX_RING)
Al Viro5bb7ea22007-12-09 16:06:41 +0000984 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500985 } else {
986 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000987 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
988 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500989 }
990 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000991 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
992 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500993 }
994 }
995}
996
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400997static void free_rings(struct net_device *dev)
998{
999 struct fe_priv *np = get_nvpriv(dev);
1000
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001001 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001002 if (np->rx_ring.orig)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001003 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1004 np->rx_ring.orig, np->ring_addr);
1005 } else {
1006 if (np->rx_ring.ex)
1007 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1008 np->rx_ring.ex, np->ring_addr);
1009 }
Szymon Janc9b03b062010-11-27 08:39:44 +00001010 kfree(np->rx_skb);
1011 kfree(np->tx_skb);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001012}
1013
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001014static int using_multi_irqs(struct net_device *dev)
1015{
1016 struct fe_priv *np = get_nvpriv(dev);
1017
1018 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1019 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1020 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1021 return 0;
1022 else
1023 return 1;
1024}
1025
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00001026static void nv_txrx_gate(struct net_device *dev, bool gate)
1027{
1028 struct fe_priv *np = get_nvpriv(dev);
1029 u8 __iomem *base = get_hwbase(dev);
1030 u32 powerstate;
1031
1032 if (!np->mac_in_use &&
1033 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1034 powerstate = readl(base + NvRegPowerState2);
1035 if (gate)
1036 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1037 else
1038 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1039 writel(powerstate, base + NvRegPowerState2);
1040 }
1041}
1042
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001043static void nv_enable_irq(struct net_device *dev)
1044{
1045 struct fe_priv *np = get_nvpriv(dev);
1046
1047 if (!using_multi_irqs(dev)) {
1048 if (np->msi_flags & NV_MSI_X_ENABLED)
1049 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1050 else
Manfred Spraula7475902007-10-17 21:52:33 +02001051 enable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001052 } else {
1053 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1054 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1055 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1056 }
1057}
1058
1059static void nv_disable_irq(struct net_device *dev)
1060{
1061 struct fe_priv *np = get_nvpriv(dev);
1062
1063 if (!using_multi_irqs(dev)) {
1064 if (np->msi_flags & NV_MSI_X_ENABLED)
1065 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1066 else
Manfred Spraula7475902007-10-17 21:52:33 +02001067 disable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001068 } else {
1069 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1070 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1071 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1072 }
1073}
1074
1075/* In MSIX mode, a write to irqmask behaves as XOR */
1076static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1077{
1078 u8 __iomem *base = get_hwbase(dev);
1079
1080 writel(mask, base + NvRegIrqMask);
1081}
1082
1083static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1084{
1085 struct fe_priv *np = get_nvpriv(dev);
1086 u8 __iomem *base = get_hwbase(dev);
1087
1088 if (np->msi_flags & NV_MSI_X_ENABLED) {
1089 writel(mask, base + NvRegIrqMask);
1090 } else {
1091 if (np->msi_flags & NV_MSI_ENABLED)
1092 writel(0, base + NvRegMSIIrqMask);
1093 writel(0, base + NvRegIrqMask);
1094 }
1095}
1096
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001097static void nv_napi_enable(struct net_device *dev)
1098{
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001099 struct fe_priv *np = get_nvpriv(dev);
1100
1101 napi_enable(&np->napi);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001102}
1103
1104static void nv_napi_disable(struct net_device *dev)
1105{
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001106 struct fe_priv *np = get_nvpriv(dev);
1107
1108 napi_disable(&np->napi);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001109}
1110
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111#define MII_READ (-1)
1112/* mii_rw: read/write a register on the PHY.
1113 *
1114 * Caller must guarantee serialization
1115 */
1116static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1117{
1118 u8 __iomem *base = get_hwbase(dev);
1119 u32 reg;
1120 int retval;
1121
Ayaz Abdullaeb798422008-02-04 15:14:04 -05001122 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123
1124 reg = readl(base + NvRegMIIControl);
1125 if (reg & NVREG_MIICTL_INUSE) {
1126 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1127 udelay(NV_MIIBUSY_DELAY);
1128 }
1129
1130 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1131 if (value != MII_READ) {
1132 writel(value, base + NvRegMIIData);
1133 reg |= NVREG_MIICTL_WRITE;
1134 }
1135 writel(reg, base + NvRegMIIControl);
1136
1137 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
Joe Perches344d0dc2010-11-29 07:41:52 +00001138 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
Joe Perches6b808582010-11-29 07:41:53 +00001139 netdev_dbg(dev, "mii_rw of reg %d at PHY %d timed out\n",
1140 miireg, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 retval = -1;
1142 } else if (value != MII_READ) {
1143 /* it was a write operation - fewer failures are detectable */
Joe Perches6b808582010-11-29 07:41:53 +00001144 netdev_dbg(dev, "mii_rw wrote 0x%x to reg %d at PHY %d\n",
1145 value, miireg, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 retval = 0;
1147 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
Joe Perches6b808582010-11-29 07:41:53 +00001148 netdev_dbg(dev, "mii_rw of reg %d at PHY %d failed\n",
1149 miireg, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150 retval = -1;
1151 } else {
1152 retval = readl(base + NvRegMIIData);
Joe Perches6b808582010-11-29 07:41:53 +00001153 netdev_dbg(dev, "mii_rw read from reg %d at PHY %d: 0x%x\n",
1154 miireg, addr, retval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155 }
1156
1157 return retval;
1158}
1159
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001160static int phy_reset(struct net_device *dev, u32 bmcr_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001162 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163 u32 miicontrol;
1164 unsigned int tries = 0;
1165
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001166 miicontrol = BMCR_RESET | bmcr_setup;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001167 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001169
1170 /* wait for 500ms */
1171 msleep(500);
1172
1173 /* must wait till reset is deasserted */
1174 while (miicontrol & BMCR_RESET) {
Szymon Jancde855b92010-11-27 08:39:48 +00001175 usleep_range(10000, 20000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1177 /* FIXME: 100 tries seem excessive */
1178 if (tries++ > 100)
1179 return -1;
1180 }
1181 return 0;
1182}
1183
Joe Perchesc41d41e2010-11-29 07:41:58 +00001184static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1185{
1186 static const struct {
1187 int reg;
1188 int init;
1189 } ri[] = {
1190 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1191 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1192 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1193 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1194 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1195 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1196 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1197 };
1198 int i;
1199
1200 for (i = 0; i < ARRAY_SIZE(ri); i++) {
Joe Perchescd663282010-11-29 07:41:59 +00001201 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
Joe Perchesc41d41e2010-11-29 07:41:58 +00001202 return PHY_ERROR;
Joe Perchesc41d41e2010-11-29 07:41:58 +00001203 }
1204
1205 return 0;
1206}
1207
Joe Perchescd663282010-11-29 07:41:59 +00001208static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1209{
1210 u32 reg;
1211 u8 __iomem *base = get_hwbase(dev);
1212 u32 powerstate = readl(base + NvRegPowerState2);
1213
1214 /* need to perform hw phy reset */
1215 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1216 writel(powerstate, base + NvRegPowerState2);
1217 msleep(25);
1218
1219 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1220 writel(powerstate, base + NvRegPowerState2);
1221 msleep(25);
1222
1223 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1224 reg |= PHY_REALTEK_INIT9;
1225 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1226 return PHY_ERROR;
1227 if (mii_rw(dev, np->phyaddr,
1228 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1229 return PHY_ERROR;
1230 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1231 if (!(reg & PHY_REALTEK_INIT11)) {
1232 reg |= PHY_REALTEK_INIT11;
1233 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1234 return PHY_ERROR;
1235 }
1236 if (mii_rw(dev, np->phyaddr,
1237 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1238 return PHY_ERROR;
1239
1240 return 0;
1241}
1242
1243static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1244{
1245 u32 phy_reserved;
1246
1247 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1248 phy_reserved = mii_rw(dev, np->phyaddr,
1249 PHY_REALTEK_INIT_REG6, MII_READ);
1250 phy_reserved |= PHY_REALTEK_INIT7;
1251 if (mii_rw(dev, np->phyaddr,
1252 PHY_REALTEK_INIT_REG6, phy_reserved))
1253 return PHY_ERROR;
1254 }
1255
1256 return 0;
1257}
1258
1259static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1260{
1261 u32 phy_reserved;
1262
1263 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1264 if (mii_rw(dev, np->phyaddr,
1265 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1266 return PHY_ERROR;
1267 phy_reserved = mii_rw(dev, np->phyaddr,
1268 PHY_REALTEK_INIT_REG2, MII_READ);
1269 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1270 phy_reserved |= PHY_REALTEK_INIT3;
1271 if (mii_rw(dev, np->phyaddr,
1272 PHY_REALTEK_INIT_REG2, phy_reserved))
1273 return PHY_ERROR;
1274 if (mii_rw(dev, np->phyaddr,
1275 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1276 return PHY_ERROR;
1277 }
1278
1279 return 0;
1280}
1281
1282static int init_cicada(struct net_device *dev, struct fe_priv *np,
1283 u32 phyinterface)
1284{
1285 u32 phy_reserved;
1286
1287 if (phyinterface & PHY_RGMII) {
1288 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1289 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1290 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1291 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1292 return PHY_ERROR;
1293 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1294 phy_reserved |= PHY_CICADA_INIT5;
1295 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1296 return PHY_ERROR;
1297 }
1298 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1299 phy_reserved |= PHY_CICADA_INIT6;
1300 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1301 return PHY_ERROR;
1302
1303 return 0;
1304}
1305
1306static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1307{
1308 u32 phy_reserved;
1309
1310 if (mii_rw(dev, np->phyaddr,
1311 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1312 return PHY_ERROR;
1313 if (mii_rw(dev, np->phyaddr,
1314 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1315 return PHY_ERROR;
1316 phy_reserved = mii_rw(dev, np->phyaddr,
1317 PHY_VITESSE_INIT_REG4, MII_READ);
1318 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1319 return PHY_ERROR;
1320 phy_reserved = mii_rw(dev, np->phyaddr,
1321 PHY_VITESSE_INIT_REG3, MII_READ);
1322 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1323 phy_reserved |= PHY_VITESSE_INIT3;
1324 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1325 return PHY_ERROR;
1326 if (mii_rw(dev, np->phyaddr,
1327 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1328 return PHY_ERROR;
1329 if (mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1331 return PHY_ERROR;
1332 phy_reserved = mii_rw(dev, np->phyaddr,
1333 PHY_VITESSE_INIT_REG4, MII_READ);
1334 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1335 phy_reserved |= PHY_VITESSE_INIT3;
1336 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1337 return PHY_ERROR;
1338 phy_reserved = mii_rw(dev, np->phyaddr,
1339 PHY_VITESSE_INIT_REG3, MII_READ);
1340 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1341 return PHY_ERROR;
1342 if (mii_rw(dev, np->phyaddr,
1343 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1344 return PHY_ERROR;
1345 if (mii_rw(dev, np->phyaddr,
1346 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1347 return PHY_ERROR;
1348 phy_reserved = mii_rw(dev, np->phyaddr,
1349 PHY_VITESSE_INIT_REG4, MII_READ);
1350 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1351 return PHY_ERROR;
1352 phy_reserved = mii_rw(dev, np->phyaddr,
1353 PHY_VITESSE_INIT_REG3, MII_READ);
1354 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1355 phy_reserved |= PHY_VITESSE_INIT8;
1356 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1357 return PHY_ERROR;
1358 if (mii_rw(dev, np->phyaddr,
1359 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1360 return PHY_ERROR;
1361 if (mii_rw(dev, np->phyaddr,
1362 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1363 return PHY_ERROR;
1364
1365 return 0;
1366}
1367
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368static int phy_init(struct net_device *dev)
1369{
1370 struct fe_priv *np = get_nvpriv(dev);
1371 u8 __iomem *base = get_hwbase(dev);
Joe Perchescd663282010-11-29 07:41:59 +00001372 u32 phyinterface;
1373 u32 mii_status, mii_control, mii_control_1000, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001375 /* phy errata for E3016 phy */
1376 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1377 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1378 reg &= ~PHY_MARVELL_E3016_INITMASK;
1379 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001380 netdev_info(dev, "%s: phy write to errata reg failed\n",
1381 pci_name(np->pci_dev));
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001382 return PHY_ERROR;
1383 }
1384 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001385 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001386 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1387 np->phy_rev == PHY_REV_REALTEK_8211B) {
Joe Perchescd663282010-11-29 07:41:59 +00001388 if (init_realtek_8211b(dev, np)) {
1389 netdev_info(dev, "%s: phy init failed\n",
1390 pci_name(np->pci_dev));
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001391 return PHY_ERROR;
Joe Perchescd663282010-11-29 07:41:59 +00001392 }
Joe Perchesc41d41e2010-11-29 07:41:58 +00001393 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1394 np->phy_rev == PHY_REV_REALTEK_8211C) {
Joe Perchescd663282010-11-29 07:41:59 +00001395 if (init_realtek_8211c(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001396 netdev_info(dev, "%s: phy init failed\n",
1397 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001398 return PHY_ERROR;
1399 }
Joe Perchescd663282010-11-29 07:41:59 +00001400 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1401 if (init_realtek_8201(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001402 netdev_info(dev, "%s: phy init failed\n",
1403 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001404 return PHY_ERROR;
1405 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001406 }
1407 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001408
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409 /* set advertise register */
1410 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Joe Perchescd663282010-11-29 07:41:59 +00001411 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1412 ADVERTISE_100HALF | ADVERTISE_100FULL |
1413 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001415 netdev_info(dev, "%s: phy write to advertise failed\n",
1416 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417 return PHY_ERROR;
1418 }
1419
1420 /* get phy interface type */
1421 phyinterface = readl(base + NvRegPhyInterface);
1422
1423 /* see if gigabit phy */
1424 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1425 if (mii_status & PHY_GIGABIT) {
1426 np->gigabit = PHY_GIGABIT;
Joe Perchescd663282010-11-29 07:41:59 +00001427 mii_control_1000 = mii_rw(dev, np->phyaddr,
1428 MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429 mii_control_1000 &= ~ADVERTISE_1000HALF;
1430 if (phyinterface & PHY_RGMII)
1431 mii_control_1000 |= ADVERTISE_1000FULL;
1432 else
1433 mii_control_1000 &= ~ADVERTISE_1000FULL;
1434
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001435 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001436 netdev_info(dev, "%s: phy init failed\n",
1437 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438 return PHY_ERROR;
1439 }
Szymon Janc78aea4f2010-11-27 08:39:43 +00001440 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001441 np->gigabit = 0;
1442
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001443 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1444 mii_control |= BMCR_ANENABLE;
1445
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001446 if (np->phy_oui == PHY_OUI_REALTEK &&
1447 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1448 np->phy_rev == PHY_REV_REALTEK_8211C) {
1449 /* start autoneg since we already performed hw reset above */
1450 mii_control |= BMCR_ANRESTART;
1451 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001452 netdev_info(dev, "%s: phy init failed\n",
1453 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001454 return PHY_ERROR;
1455 }
1456 } else {
1457 /* reset the phy
1458 * (certain phys need bmcr to be setup with reset)
1459 */
1460 if (phy_reset(dev, mii_control)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001461 netdev_info(dev, "%s: phy reset failed\n",
1462 pci_name(np->pci_dev));
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001463 return PHY_ERROR;
1464 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465 }
1466
1467 /* phy vendor specific configuration */
Joe Perchescd663282010-11-29 07:41:59 +00001468 if ((np->phy_oui == PHY_OUI_CICADA)) {
1469 if (init_cicada(dev, np, phyinterface)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001470 netdev_info(dev, "%s: phy init failed\n",
1471 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001472 return PHY_ERROR;
1473 }
Joe Perchescd663282010-11-29 07:41:59 +00001474 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1475 if (init_vitesse(dev, np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00001476 netdev_info(dev, "%s: phy init failed\n",
1477 pci_name(np->pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478 return PHY_ERROR;
1479 }
Joe Perchescd663282010-11-29 07:41:59 +00001480 } else if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001481 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1482 np->phy_rev == PHY_REV_REALTEK_8211B) {
1483 /* reset could have cleared these out, set them back */
Joe Perchescd663282010-11-29 07:41:59 +00001484 if (init_realtek_8211b(dev, np)) {
1485 netdev_info(dev, "%s: phy init failed\n",
1486 pci_name(np->pci_dev));
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001487 return PHY_ERROR;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001488 }
Joe Perchescd663282010-11-29 07:41:59 +00001489 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1490 if (init_realtek_8201(dev, np) ||
1491 init_realtek_8201_cross(dev, np)) {
1492 netdev_info(dev, "%s: phy init failed\n",
1493 pci_name(np->pci_dev));
1494 return PHY_ERROR;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001495 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001496 }
1497 }
1498
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001499 /* some phys clear out pause advertisment on reset, set it back */
1500 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501
Ed Swierkcb52deb2008-12-01 12:24:43 +00001502 /* restart auto negotiation, power down phy */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001503 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001504 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001505 if (phy_power_down)
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001506 mii_control |= BMCR_PDOWN;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001507 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001508 return PHY_ERROR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509
1510 return 0;
1511}
1512
1513static void nv_start_rx(struct net_device *dev)
1514{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001515 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001517 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518
Joe Perches6b808582010-11-29 07:41:53 +00001519 netdev_dbg(dev, "%s\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001520 /* Already running? Stop it. */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001521 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1522 rx_ctrl &= ~NVREG_RCVCTL_START;
1523 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524 pci_push(base);
1525 }
1526 writel(np->linkspeed, base + NvRegLinkSpeed);
1527 pci_push(base);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001528 rx_ctrl |= NVREG_RCVCTL_START;
1529 if (np->mac_in_use)
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001530 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1531 writel(rx_ctrl, base + NvRegReceiverControl);
Joe Perches6b808582010-11-29 07:41:53 +00001532 netdev_dbg(dev, "%s: duplex %d, speed 0x%08x\n",
1533 __func__, np->duplex, np->linkspeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534 pci_push(base);
1535}
1536
1537static void nv_stop_rx(struct net_device *dev)
1538{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001539 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001541 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001542
Joe Perches6b808582010-11-29 07:41:53 +00001543 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001544 if (!np->mac_in_use)
1545 rx_ctrl &= ~NVREG_RCVCTL_START;
1546 else
1547 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1548 writel(rx_ctrl, base + NvRegReceiverControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00001549 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1550 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
Joe Perches1d397f32010-11-29 07:41:57 +00001551 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1552 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553
1554 udelay(NV_RXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001555 if (!np->mac_in_use)
1556 writel(0, base + NvRegLinkSpeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557}
1558
1559static void nv_start_tx(struct net_device *dev)
1560{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001561 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001563 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001564
Joe Perches6b808582010-11-29 07:41:53 +00001565 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001566 tx_ctrl |= NVREG_XMITCTL_START;
1567 if (np->mac_in_use)
1568 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1569 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001570 pci_push(base);
1571}
1572
1573static void nv_stop_tx(struct net_device *dev)
1574{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001575 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001577 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001578
Joe Perches6b808582010-11-29 07:41:53 +00001579 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001580 if (!np->mac_in_use)
1581 tx_ctrl &= ~NVREG_XMITCTL_START;
1582 else
1583 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1584 writel(tx_ctrl, base + NvRegTransmitterControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00001585 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1586 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
Joe Perches1d397f32010-11-29 07:41:57 +00001587 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1588 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589
1590 udelay(NV_TXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001591 if (!np->mac_in_use)
1592 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1593 base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594}
1595
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001596static void nv_start_rxtx(struct net_device *dev)
1597{
1598 nv_start_rx(dev);
1599 nv_start_tx(dev);
1600}
1601
1602static void nv_stop_rxtx(struct net_device *dev)
1603{
1604 nv_stop_rx(dev);
1605 nv_stop_tx(dev);
1606}
1607
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608static void nv_txrx_reset(struct net_device *dev)
1609{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001610 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 u8 __iomem *base = get_hwbase(dev);
1612
Joe Perches6b808582010-11-29 07:41:53 +00001613 netdev_dbg(dev, "%s\n", __func__);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001614 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001615 pci_push(base);
1616 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001617 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001618 pci_push(base);
1619}
1620
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001621static void nv_mac_reset(struct net_device *dev)
1622{
1623 struct fe_priv *np = netdev_priv(dev);
1624 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001625 u32 temp1, temp2, temp3;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001626
Joe Perches6b808582010-11-29 07:41:53 +00001627 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001628
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001629 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1630 pci_push(base);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001631
1632 /* save registers since they will be cleared on reset */
1633 temp1 = readl(base + NvRegMacAddrA);
1634 temp2 = readl(base + NvRegMacAddrB);
1635 temp3 = readl(base + NvRegTransmitPoll);
1636
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001637 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1638 pci_push(base);
1639 udelay(NV_MAC_RESET_DELAY);
1640 writel(0, base + NvRegMacReset);
1641 pci_push(base);
1642 udelay(NV_MAC_RESET_DELAY);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001643
1644 /* restore saved registers */
1645 writel(temp1, base + NvRegMacAddrA);
1646 writel(temp2, base + NvRegMacAddrB);
1647 writel(temp3, base + NvRegTransmitPoll);
1648
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001649 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1650 pci_push(base);
1651}
1652
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001653static void nv_get_hw_stats(struct net_device *dev)
1654{
1655 struct fe_priv *np = netdev_priv(dev);
1656 u8 __iomem *base = get_hwbase(dev);
1657
1658 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1659 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1660 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1661 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1662 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1663 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1664 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1665 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1666 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1667 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1668 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1669 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1670 np->estats.rx_runt += readl(base + NvRegRxRunt);
1671 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1672 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1673 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1674 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1675 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1676 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1677 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1678 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1679 np->estats.rx_packets =
1680 np->estats.rx_unicast +
1681 np->estats.rx_multicast +
1682 np->estats.rx_broadcast;
1683 np->estats.rx_errors_total =
1684 np->estats.rx_crc_errors +
1685 np->estats.rx_over_errors +
1686 np->estats.rx_frame_error +
1687 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1688 np->estats.rx_late_collision +
1689 np->estats.rx_runt +
1690 np->estats.rx_frame_too_long;
1691 np->estats.tx_errors_total =
1692 np->estats.tx_late_collision +
1693 np->estats.tx_fifo_errors +
1694 np->estats.tx_carrier_errors +
1695 np->estats.tx_excess_deferral +
1696 np->estats.tx_retry_error;
1697
1698 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1699 np->estats.tx_deferral += readl(base + NvRegTxDef);
1700 np->estats.tx_packets += readl(base + NvRegTxFrame);
1701 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1702 np->estats.tx_pause += readl(base + NvRegTxPause);
1703 np->estats.rx_pause += readl(base + NvRegRxPause);
1704 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1705 }
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001706
1707 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1708 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1709 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1710 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1711 }
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001712}
1713
Linus Torvalds1da177e2005-04-16 15:20:36 -07001714/*
1715 * nv_get_stats: dev->get_stats function
1716 * Get latest stats value from the nic.
1717 * Called with read_lock(&dev_base_lock) held for read -
1718 * only synchronized against unregister_netdevice.
1719 */
1720static struct net_device_stats *nv_get_stats(struct net_device *dev)
1721{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001722 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723
Ayaz Abdulla21828162007-01-23 12:27:21 -05001724 /* If the nic supports hw counters then retrieve latest values */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001725 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05001726 nv_get_hw_stats(dev);
1727
1728 /* copy to net_device stats */
Jeff Garzik8148ff42007-10-16 20:56:09 -04001729 dev->stats.tx_bytes = np->estats.tx_bytes;
1730 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1731 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1732 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1733 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1734 dev->stats.rx_errors = np->estats.rx_errors_total;
1735 dev->stats.tx_errors = np->estats.tx_errors_total;
Ayaz Abdulla21828162007-01-23 12:27:21 -05001736 }
Jeff Garzik8148ff42007-10-16 20:56:09 -04001737
1738 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739}
1740
1741/*
1742 * nv_alloc_rx: fill rx ring entries.
1743 * Return 1 if the allocations for the skbs failed and the
1744 * rx engine is without Available descriptors
1745 */
1746static int nv_alloc_rx(struct net_device *dev)
1747{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001748 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001749 struct ring_desc *less_rx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001750
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001751 less_rx = np->get_rx.orig;
1752 if (less_rx-- == np->first_rx.orig)
1753 less_rx = np->last_rx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001754
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001755 while (np->put_rx.orig != less_rx) {
1756 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001757 if (skb) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001758 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001759 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1760 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001761 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001762 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001763 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001764 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1765 wmb();
1766 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001767 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001768 np->put_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001769 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001770 np->put_rx_ctx = np->first_rx_ctx;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001771 } else
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001772 return 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001773 }
1774 return 0;
1775}
1776
1777static int nv_alloc_rx_optimized(struct net_device *dev)
1778{
1779 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001780 struct ring_desc_ex *less_rx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001781
1782 less_rx = np->get_rx.ex;
1783 if (less_rx-- == np->first_rx.ex)
1784 less_rx = np->last_rx.ex;
1785
1786 while (np->put_rx.ex != less_rx) {
1787 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1788 if (skb) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001789 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001790 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1791 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001792 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001793 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001794 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Al Viro5bb7ea22007-12-09 16:06:41 +00001795 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1796 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001797 wmb();
1798 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001799 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001800 np->put_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001801 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001802 np->put_rx_ctx = np->first_rx_ctx;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001803 } else
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001804 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001806 return 0;
1807}
1808
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001809/* If rx bufs are exhausted called after 50ms to attempt to refresh */
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001810static void nv_do_rx_refill(unsigned long data)
1811{
1812 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001813 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001814
1815 /* Just reschedule NAPI rx processing */
Ben Hutchings288379f2009-01-19 16:43:59 -08001816 napi_schedule(&np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001817}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001818
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001819static void nv_init_rx(struct net_device *dev)
Manfred Sprauld81c0982005-07-31 18:20:30 +02001820{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001821 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001822 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001823
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001824 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001825
1826 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001827 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1828 else
1829 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1830 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1831 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
Manfred Sprauld81c0982005-07-31 18:20:30 +02001832
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001833 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001834 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001835 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001836 np->rx_ring.orig[i].buf = 0;
1837 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001838 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001839 np->rx_ring.ex[i].txvlan = 0;
1840 np->rx_ring.ex[i].bufhigh = 0;
1841 np->rx_ring.ex[i].buflow = 0;
1842 }
1843 np->rx_skb[i].skb = NULL;
1844 np->rx_skb[i].dma = 0;
1845 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001846}
1847
1848static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001850 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001852
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001853 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001854
1855 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001856 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1857 else
1858 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1859 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1860 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001861 np->tx_pkts_in_progress = 0;
1862 np->tx_change_owner = NULL;
1863 np->tx_end_flip = NULL;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00001864 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001865
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001866 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001867 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001868 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001869 np->tx_ring.orig[i].buf = 0;
1870 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001871 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001872 np->tx_ring.ex[i].txvlan = 0;
1873 np->tx_ring.ex[i].bufhigh = 0;
1874 np->tx_ring.ex[i].buflow = 0;
1875 }
1876 np->tx_skb[i].skb = NULL;
1877 np->tx_skb[i].dma = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001878 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001879 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001880 np->tx_skb[i].first_tx_desc = NULL;
1881 np->tx_skb[i].next_tx_ctx = NULL;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001882 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001883}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884
Manfred Sprauld81c0982005-07-31 18:20:30 +02001885static int nv_init_ring(struct net_device *dev)
1886{
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001887 struct fe_priv *np = netdev_priv(dev);
1888
Manfred Sprauld81c0982005-07-31 18:20:30 +02001889 nv_init_tx(dev);
1890 nv_init_rx(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001891
1892 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001893 return nv_alloc_rx(dev);
1894 else
1895 return nv_alloc_rx_optimized(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896}
1897
Eric Dumazet73a37072009-06-17 21:17:59 +00001898static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001899{
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001900 if (tx_skb->dma) {
Eric Dumazet73a37072009-06-17 21:17:59 +00001901 if (tx_skb->dma_single)
1902 pci_unmap_single(np->pci_dev, tx_skb->dma,
1903 tx_skb->dma_len,
1904 PCI_DMA_TODEVICE);
1905 else
1906 pci_unmap_page(np->pci_dev, tx_skb->dma,
1907 tx_skb->dma_len,
1908 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001909 tx_skb->dma = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001910 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001911}
1912
1913static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1914{
1915 nv_unmap_txskb(np, tx_skb);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001916 if (tx_skb->skb) {
1917 dev_kfree_skb_any(tx_skb->skb);
1918 tx_skb->skb = NULL;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001919 return 1;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001920 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001921 return 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001922}
1923
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924static void nv_drain_tx(struct net_device *dev)
1925{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001926 struct fe_priv *np = netdev_priv(dev);
1927 unsigned int i;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001928
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001929 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001930 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001931 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001932 np->tx_ring.orig[i].buf = 0;
1933 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001934 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001935 np->tx_ring.ex[i].txvlan = 0;
1936 np->tx_ring.ex[i].bufhigh = 0;
1937 np->tx_ring.ex[i].buflow = 0;
1938 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001939 if (nv_release_txskb(np, &np->tx_skb[i]))
Jeff Garzik8148ff42007-10-16 20:56:09 -04001940 dev->stats.tx_dropped++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001941 np->tx_skb[i].dma = 0;
1942 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001943 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001944 np->tx_skb[i].first_tx_desc = NULL;
1945 np->tx_skb[i].next_tx_ctx = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001946 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001947 np->tx_pkts_in_progress = 0;
1948 np->tx_change_owner = NULL;
1949 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950}
1951
1952static void nv_drain_rx(struct net_device *dev)
1953{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001954 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001955 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001956
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001957 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001958 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001959 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001960 np->rx_ring.orig[i].buf = 0;
1961 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001962 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001963 np->rx_ring.ex[i].txvlan = 0;
1964 np->rx_ring.ex[i].bufhigh = 0;
1965 np->rx_ring.ex[i].buflow = 0;
1966 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967 wmb();
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001968 if (np->rx_skb[i].skb) {
1969 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001970 (skb_end_pointer(np->rx_skb[i].skb) -
1971 np->rx_skb[i].skb->data),
1972 PCI_DMA_FROMDEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001973 dev_kfree_skb(np->rx_skb[i].skb);
1974 np->rx_skb[i].skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001975 }
1976 }
1977}
1978
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001979static void nv_drain_rxtx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001980{
1981 nv_drain_tx(dev);
1982 nv_drain_rx(dev);
1983}
1984
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001985static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1986{
1987 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1988}
1989
Ayaz Abdullaa4336862008-04-18 13:50:43 -07001990static void nv_legacybackoff_reseed(struct net_device *dev)
1991{
1992 u8 __iomem *base = get_hwbase(dev);
1993 u32 reg;
1994 u32 low;
1995 int tx_status = 0;
1996
1997 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1998 get_random_bytes(&low, sizeof(low));
1999 reg |= low & NVREG_SLOTTIME_MASK;
2000
2001 /* Need to stop tx before change takes effect.
2002 * Caller has already gained np->lock.
2003 */
2004 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2005 if (tx_status)
2006 nv_stop_tx(dev);
2007 nv_stop_rx(dev);
2008 writel(reg, base + NvRegSlotTime);
2009 if (tx_status)
2010 nv_start_tx(dev);
2011 nv_start_rx(dev);
2012}
2013
2014/* Gear Backoff Seeds */
2015#define BACKOFF_SEEDSET_ROWS 8
2016#define BACKOFF_SEEDSET_LFSRS 15
2017
2018/* Known Good seed sets */
2019static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002020 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2021 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2022 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2023 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2024 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2025 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2026 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2027 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002028
2029static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002030 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2031 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2032 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2033 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2034 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2035 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2036 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2037 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002038
2039static void nv_gear_backoff_reseed(struct net_device *dev)
2040{
2041 u8 __iomem *base = get_hwbase(dev);
2042 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2043 u32 temp, seedset, combinedSeed;
2044 int i;
2045
2046 /* Setup seed for free running LFSR */
2047 /* We are going to read the time stamp counter 3 times
2048 and swizzle bits around to increase randomness */
2049 get_random_bytes(&miniseed1, sizeof(miniseed1));
2050 miniseed1 &= 0x0fff;
2051 if (miniseed1 == 0)
2052 miniseed1 = 0xabc;
2053
2054 get_random_bytes(&miniseed2, sizeof(miniseed2));
2055 miniseed2 &= 0x0fff;
2056 if (miniseed2 == 0)
2057 miniseed2 = 0xabc;
2058 miniseed2_reversed =
2059 ((miniseed2 & 0xF00) >> 8) |
2060 (miniseed2 & 0x0F0) |
2061 ((miniseed2 & 0x00F) << 8);
2062
2063 get_random_bytes(&miniseed3, sizeof(miniseed3));
2064 miniseed3 &= 0x0fff;
2065 if (miniseed3 == 0)
2066 miniseed3 = 0xabc;
2067 miniseed3_reversed =
2068 ((miniseed3 & 0xF00) >> 8) |
2069 (miniseed3 & 0x0F0) |
2070 ((miniseed3 & 0x00F) << 8);
2071
2072 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2073 (miniseed2 ^ miniseed3_reversed);
2074
2075 /* Seeds can not be zero */
2076 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2077 combinedSeed |= 0x08;
2078 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2079 combinedSeed |= 0x8000;
2080
2081 /* No need to disable tx here */
2082 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2083 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2084 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002085 writel(temp, base + NvRegBackOffControl);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002086
Szymon Janc78aea4f2010-11-27 08:39:43 +00002087 /* Setup seeds for all gear LFSRs. */
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002088 get_random_bytes(&seedset, sizeof(seedset));
2089 seedset = seedset % BACKOFF_SEEDSET_ROWS;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002090 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002091 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2092 temp |= main_seedset[seedset][i-1] & 0x3ff;
2093 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2094 writel(temp, base + NvRegBackOffControl);
2095 }
2096}
2097
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098/*
2099 * nv_start_xmit: dev->hard_start_xmit function
Herbert Xu932ff272006-06-09 12:20:56 -07002100 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002101 */
Stephen Hemminger613573252009-08-31 19:50:58 +00002102static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002103{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002104 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002105 u32 tx_flags = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002106 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2107 unsigned int fragments = skb_shinfo(skb)->nr_frags;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002108 unsigned int i;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002109 u32 offset = 0;
2110 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002111 u32 size = skb_headlen(skb);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002112 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002113 u32 empty_slots;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002114 struct ring_desc *put_tx;
2115 struct ring_desc *start_tx;
2116 struct ring_desc *prev_tx;
2117 struct nv_skb_map *prev_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002118 unsigned long flags;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002119
2120 /* add fragments to entries count */
2121 for (i = 0; i < fragments; i++) {
2122 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2123 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2124 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002125
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002126 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002127 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002128 if (unlikely(empty_slots <= entries)) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002129 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002130 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002131 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002132 return NETDEV_TX_BUSY;
2133 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002134 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002135
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002136 start_tx = put_tx = np->put_tx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002137
Ayaz Abdullafa454592006-01-05 22:45:45 -08002138 /* setup the header buffer */
2139 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002140 prev_tx = put_tx;
2141 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002142 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002143 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
Ayaz Abdullafa454592006-01-05 22:45:45 -08002144 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002145 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002146 np->put_tx_ctx->dma_single = 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002147 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2148 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002149
Ayaz Abdullafa454592006-01-05 22:45:45 -08002150 tx_flags = np->tx_flags;
2151 offset += bcnt;
2152 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002153 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002154 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002155 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002156 np->put_tx_ctx = np->first_tx_ctx;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002157 } while (size);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002158
2159 /* setup the fragments */
2160 for (i = 0; i < fragments; i++) {
2161 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2162 u32 size = frag->size;
2163 offset = 0;
2164
2165 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002166 prev_tx = put_tx;
2167 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002168 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002169 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2170 PCI_DMA_TODEVICE);
2171 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002172 np->put_tx_ctx->dma_single = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002173 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2174 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002175
Ayaz Abdullafa454592006-01-05 22:45:45 -08002176 offset += bcnt;
2177 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002178 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002179 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002180 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002181 np->put_tx_ctx = np->first_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002182 } while (size);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002183 }
2184
Ayaz Abdullafa454592006-01-05 22:45:45 -08002185 /* set last fragment flag */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002186 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002187
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002188 /* save skb in this slot's context area */
2189 prev_tx_ctx->skb = skb;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002190
Herbert Xu89114af2006-07-08 13:34:32 -07002191 if (skb_is_gso(skb))
Herbert Xu79671682006-06-22 02:40:14 -07002192 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
Manfred Spraulee733622005-07-31 18:32:26 +02002193 else
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002194 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
Patrick McHardy84fa7932006-08-29 16:44:56 -07002195 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002196
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002197 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05002198
Ayaz Abdullafa454592006-01-05 22:45:45 -08002199 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002200 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2201 np->put_tx.orig = put_tx;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002202
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002203 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002204
Joe Perches6b808582010-11-29 07:41:53 +00002205 netdev_dbg(dev, "%s: entries %d queued for transmission. tx_flags_extra: %x\n",
2206 __func__, entries, tx_flags_extra);
Joe Perchese6499852010-11-29 07:41:54 +00002207#ifdef DEBUG
2208 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
2209 skb->data, 64, true);
2210#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002211
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002212 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002213 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214}
2215
Stephen Hemminger613573252009-08-31 19:50:58 +00002216static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2217 struct net_device *dev)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002218{
2219 struct fe_priv *np = netdev_priv(dev);
2220 u32 tx_flags = 0;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002221 u32 tx_flags_extra;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002222 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2223 unsigned int i;
2224 u32 offset = 0;
2225 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002226 u32 size = skb_headlen(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002227 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2228 u32 empty_slots;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002229 struct ring_desc_ex *put_tx;
2230 struct ring_desc_ex *start_tx;
2231 struct ring_desc_ex *prev_tx;
2232 struct nv_skb_map *prev_tx_ctx;
2233 struct nv_skb_map *start_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002234 unsigned long flags;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002235
2236 /* add fragments to entries count */
2237 for (i = 0; i < fragments; i++) {
2238 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2239 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2240 }
2241
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002242 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002243 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002244 if (unlikely(empty_slots <= entries)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002245 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002246 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002247 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002248 return NETDEV_TX_BUSY;
2249 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002250 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002251
2252 start_tx = put_tx = np->put_tx.ex;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002253 start_tx_ctx = np->put_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002254
2255 /* setup the header buffer */
2256 do {
2257 prev_tx = put_tx;
2258 prev_tx_ctx = np->put_tx_ctx;
2259 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2260 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2261 PCI_DMA_TODEVICE);
2262 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002263 np->put_tx_ctx->dma_single = 1;
Al Viro5bb7ea22007-12-09 16:06:41 +00002264 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2265 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002266 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002267
2268 tx_flags = NV_TX2_VALID;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002269 offset += bcnt;
2270 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002271 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002272 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002273 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002274 np->put_tx_ctx = np->first_tx_ctx;
2275 } while (size);
2276
2277 /* setup the fragments */
2278 for (i = 0; i < fragments; i++) {
2279 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2280 u32 size = frag->size;
2281 offset = 0;
2282
2283 do {
2284 prev_tx = put_tx;
2285 prev_tx_ctx = np->put_tx_ctx;
2286 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2287 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2288 PCI_DMA_TODEVICE);
2289 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002290 np->put_tx_ctx->dma_single = 0;
Al Viro5bb7ea22007-12-09 16:06:41 +00002291 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2292 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002293 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002294
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002295 offset += bcnt;
2296 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002297 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002298 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002299 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002300 np->put_tx_ctx = np->first_tx_ctx;
2301 } while (size);
2302 }
2303
2304 /* set last fragment flag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002305 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002306
2307 /* save skb in this slot's context area */
2308 prev_tx_ctx->skb = skb;
2309
2310 if (skb_is_gso(skb))
2311 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2312 else
2313 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2314 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2315
2316 /* vlan tag */
Jesse Grosseab6d182010-10-20 13:56:03 +00002317 if (vlan_tx_tag_present(skb))
2318 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2319 vlan_tx_tag_get(skb));
2320 else
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002321 start_tx->txvlan = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002322
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002323 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002324
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002325 if (np->tx_limit) {
2326 /* Limit the number of outstanding tx. Setup all fragments, but
2327 * do not set the VALID bit on the first descriptor. Save a pointer
2328 * to that descriptor and also for next skb_map element.
2329 */
2330
2331 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2332 if (!np->tx_change_owner)
2333 np->tx_change_owner = start_tx_ctx;
2334
2335 /* remove VALID bit */
2336 tx_flags &= ~NV_TX2_VALID;
2337 start_tx_ctx->first_tx_desc = start_tx;
2338 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2339 np->tx_end_flip = np->put_tx_ctx;
2340 } else {
2341 np->tx_pkts_in_progress++;
2342 }
2343 }
2344
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002345 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002346 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2347 np->put_tx.ex = put_tx;
2348
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002349 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002350
Joe Perches6b808582010-11-29 07:41:53 +00002351 netdev_dbg(dev, "%s: entries %d queued for transmission. tx_flags_extra: %x\n",
2352 __func__, entries, tx_flags_extra);
Joe Perchese6499852010-11-29 07:41:54 +00002353#ifdef DEBUG
2354 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
2355 skb->data, 64, true);
2356#endif
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002357
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002358 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002359 return NETDEV_TX_OK;
2360}
2361
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002362static inline void nv_tx_flip_ownership(struct net_device *dev)
2363{
2364 struct fe_priv *np = netdev_priv(dev);
2365
2366 np->tx_pkts_in_progress--;
2367 if (np->tx_change_owner) {
Al Viro30ecce92008-03-26 05:57:12 +00002368 np->tx_change_owner->first_tx_desc->flaglen |=
2369 cpu_to_le32(NV_TX2_VALID);
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002370 np->tx_pkts_in_progress++;
2371
2372 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2373 if (np->tx_change_owner == np->tx_end_flip)
2374 np->tx_change_owner = NULL;
2375
2376 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2377 }
2378}
2379
Linus Torvalds1da177e2005-04-16 15:20:36 -07002380/*
2381 * nv_tx_done: check for completed packets, release the skbs.
2382 *
2383 * Caller must own np->lock.
2384 */
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002385static int nv_tx_done(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002386{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002387 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002388 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002389 int tx_work = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002390 struct ring_desc *orig_get_tx = np->get_tx.orig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002391
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002392 while ((np->get_tx.orig != np->put_tx.orig) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002393 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2394 (tx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002395
Joe Perches6b808582010-11-29 07:41:53 +00002396 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002397
Eric Dumazet73a37072009-06-17 21:17:59 +00002398 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002399
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400 if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002401 if (flags & NV_TX_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002402 if (flags & NV_TX_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002403 if (flags & NV_TX_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002404 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002405 if (flags & NV_TX_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002406 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002407 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2408 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002409 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002410 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002411 dev->stats.tx_packets++;
2412 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002413 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002414 dev_kfree_skb_any(np->get_tx_ctx->skb);
2415 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002416 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002417 }
2418 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002419 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002420 if (flags & NV_TX2_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002421 if (flags & NV_TX2_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002422 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002423 if (flags & NV_TX2_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002424 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002425 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2426 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002427 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002428 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002429 dev->stats.tx_packets++;
2430 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002431 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002432 dev_kfree_skb_any(np->get_tx_ctx->skb);
2433 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002434 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002435 }
2436 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002437 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002438 np->get_tx.orig = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002439 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002440 np->get_tx_ctx = np->first_tx_ctx;
2441 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002442 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002443 np->tx_stop = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002444 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002445 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002446 return tx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002447}
2448
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002449static int nv_tx_done_optimized(struct net_device *dev, int limit)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002450{
2451 struct fe_priv *np = netdev_priv(dev);
2452 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002453 int tx_work = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002454 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002455
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002456 while ((np->get_tx.ex != np->put_tx.ex) &&
Julia Lawall217d32d2010-07-05 22:15:47 -07002457 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002458 (tx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002459
Joe Perches6b808582010-11-29 07:41:53 +00002460 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002461
Eric Dumazet73a37072009-06-17 21:17:59 +00002462 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002463
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002464 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05002465 if (!(flags & NV_TX2_ERROR))
Jeff Garzik8148ff42007-10-16 20:56:09 -04002466 dev->stats.tx_packets++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002467 else {
2468 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2469 if (np->driver_data & DEV_HAS_GEAR_MODE)
2470 nv_gear_backoff_reseed(dev);
2471 else
2472 nv_legacybackoff_reseed(dev);
2473 }
2474 }
2475
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002476 dev_kfree_skb_any(np->get_tx_ctx->skb);
2477 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002478 tx_work++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002479
Szymon Janc78aea4f2010-11-27 08:39:43 +00002480 if (np->tx_limit)
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002481 nv_tx_flip_ownership(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002482 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002483 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002484 np->get_tx.ex = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002485 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002486 np->get_tx_ctx = np->first_tx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002487 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002488 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002489 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002490 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002491 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002492 return tx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002493}
2494
2495/*
2496 * nv_tx_timeout: dev->tx_timeout function
Herbert Xu932ff272006-06-09 12:20:56 -07002497 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002498 */
2499static void nv_tx_timeout(struct net_device *dev)
2500{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002501 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002502 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002503 u32 status;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002504 union ring_type put_tx;
2505 int saved_tx_limit;
Joe Perches294a5542010-11-29 07:41:56 +00002506 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002507
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002508 if (np->msi_flags & NV_MSI_X_ENABLED)
2509 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2510 else
2511 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2512
Joe Perches1d397f32010-11-29 07:41:57 +00002513 netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002514
Joe Perches1d397f32010-11-29 07:41:57 +00002515 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2516 netdev_info(dev, "Dumping tx registers\n");
Joe Perches294a5542010-11-29 07:41:56 +00002517 for (i = 0; i <= np->register_size; i += 32) {
Joe Perches1d397f32010-11-29 07:41:57 +00002518 netdev_info(dev,
2519 "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2520 i,
2521 readl(base + i + 0), readl(base + i + 4),
2522 readl(base + i + 8), readl(base + i + 12),
2523 readl(base + i + 16), readl(base + i + 20),
2524 readl(base + i + 24), readl(base + i + 28));
Joe Perches294a5542010-11-29 07:41:56 +00002525 }
Joe Perches1d397f32010-11-29 07:41:57 +00002526 netdev_info(dev, "Dumping tx ring\n");
Joe Perches294a5542010-11-29 07:41:56 +00002527 for (i = 0; i < np->tx_ring_size; i += 4) {
2528 if (!nv_optimized(np)) {
Joe Perches1d397f32010-11-29 07:41:57 +00002529 netdev_info(dev,
2530 "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2531 i,
2532 le32_to_cpu(np->tx_ring.orig[i].buf),
2533 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2534 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2535 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2536 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2537 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2538 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2539 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
Joe Perches294a5542010-11-29 07:41:56 +00002540 } else {
Joe Perches1d397f32010-11-29 07:41:57 +00002541 netdev_info(dev,
2542 "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2543 i,
2544 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2545 le32_to_cpu(np->tx_ring.ex[i].buflow),
2546 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2547 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2548 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2549 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2550 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2551 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2552 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2553 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2554 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2555 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
Manfred Spraulc2dba062005-07-31 18:29:47 +02002556 }
2557 }
2558
Linus Torvalds1da177e2005-04-16 15:20:36 -07002559 spin_lock_irq(&np->lock);
2560
2561 /* 1) stop tx engine */
2562 nv_stop_tx(dev);
2563
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002564 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2565 saved_tx_limit = np->tx_limit;
2566 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2567 np->tx_stop = 0; /* prevent waking tx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002568 if (!nv_optimized(np))
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002569 nv_tx_done(dev, np->tx_ring_size);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002570 else
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002571 nv_tx_done_optimized(dev, np->tx_ring_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002572
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002573 /* save current HW postion */
2574 if (np->tx_change_owner)
2575 put_tx.ex = np->tx_change_owner->first_tx_desc;
2576 else
2577 put_tx = np->put_tx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002578
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002579 /* 3) clear all tx state */
2580 nv_drain_tx(dev);
2581 nv_init_tx(dev);
Ayaz Abdulla3ba4d092007-03-23 05:50:02 -05002582
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002583 /* 4) restore state to current HW position */
2584 np->get_tx = np->put_tx = put_tx;
2585 np->tx_limit = saved_tx_limit;
2586
2587 /* 5) restart tx engine */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002588 nv_start_tx(dev);
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002589 netif_wake_queue(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002590 spin_unlock_irq(&np->lock);
2591}
2592
Manfred Spraul22c6d142005-04-19 21:17:09 +02002593/*
2594 * Called when the nic notices a mismatch between the actual data len on the
2595 * wire and the len indicated in the 802 header
2596 */
2597static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2598{
2599 int hdrlen; /* length of the 802 header */
2600 int protolen; /* length as stored in the proto field */
2601
2602 /* 1) calculate len according to header */
Szymon Janc78aea4f2010-11-27 08:39:43 +00002603 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2604 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002605 hdrlen = VLAN_HLEN;
2606 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002607 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002608 hdrlen = ETH_HLEN;
2609 }
Joe Perches6b808582010-11-29 07:41:53 +00002610 netdev_dbg(dev, "%s: datalen %d, protolen %d, hdrlen %d\n",
2611 __func__, datalen, protolen, hdrlen);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002612 if (protolen > ETH_DATA_LEN)
2613 return datalen; /* Value in proto field not a len, no checks possible */
2614
2615 protolen += hdrlen;
2616 /* consistency checks: */
2617 if (datalen > ETH_ZLEN) {
2618 if (datalen >= protolen) {
2619 /* more data on wire than in 802 header, trim of
2620 * additional data.
2621 */
Joe Perches6b808582010-11-29 07:41:53 +00002622 netdev_dbg(dev, "%s: accepting %d bytes\n",
2623 __func__, protolen);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002624 return protolen;
2625 } else {
2626 /* less data on wire than mentioned in header.
2627 * Discard the packet.
2628 */
Joe Perches6b808582010-11-29 07:41:53 +00002629 netdev_dbg(dev, "%s: discarding long packet\n",
2630 __func__);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002631 return -1;
2632 }
2633 } else {
2634 /* short packet. Accept only if 802 values are also short */
2635 if (protolen > ETH_ZLEN) {
Joe Perches6b808582010-11-29 07:41:53 +00002636 netdev_dbg(dev, "%s: discarding short packet\n",
2637 __func__);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002638 return -1;
2639 }
Joe Perches6b808582010-11-29 07:41:53 +00002640 netdev_dbg(dev, "%s: accepting %d bytes\n", __func__, datalen);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002641 return datalen;
2642 }
2643}
2644
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002645static int nv_rx_process(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002646{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002647 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002648 u32 flags;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002649 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002650 struct sk_buff *skb;
2651 int len;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05002652
Szymon Janc78aea4f2010-11-27 08:39:43 +00002653 while ((np->get_rx.orig != np->put_rx.orig) &&
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002654 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002655 (rx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002656
Joe Perches6b808582010-11-29 07:41:53 +00002657 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002658
Linus Torvalds1da177e2005-04-16 15:20:36 -07002659 /*
2660 * the packet is for us - immediately tear down the pci mapping.
2661 * TODO: check if a prefetch of the first cacheline improves
2662 * the performance.
2663 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002664 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2665 np->get_rx_ctx->dma_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002666 PCI_DMA_FROMDEVICE);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002667 skb = np->get_rx_ctx->skb;
2668 np->get_rx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002669
Joe Perches6b808582010-11-29 07:41:53 +00002670 netdev_dbg(dev, "Dumping packet (flags 0x%x)\n", flags);
Joe Perchese6499852010-11-29 07:41:54 +00002671#ifdef DEBUG
2672 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET,
2673 16, 1, skb->data, 64, true);
2674#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002675 /* look at what we actually got: */
2676 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002677 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2678 len = flags & LEN_MASK_V1;
2679 if (unlikely(flags & NV_RX_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002680 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002681 len = nv_getlen(dev, skb->data, len);
2682 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002683 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002684 dev_kfree_skb(skb);
2685 goto next_pkt;
2686 }
2687 }
2688 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002689 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002690 if (flags & NV_RX_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002691 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002692 }
2693 /* the rest are hard errors */
2694 else {
2695 if (flags & NV_RX_MISSEDFRAME)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002696 dev->stats.rx_missed_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002697 if (flags & NV_RX_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002698 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002699 if (flags & NV_RX_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002700 dev->stats.rx_over_errors++;
2701 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002702 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002703 goto next_pkt;
2704 }
2705 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002706 } else {
2707 dev_kfree_skb(skb);
2708 goto next_pkt;
Manfred Spraul22c6d142005-04-19 21:17:09 +02002709 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002710 } else {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002711 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2712 len = flags & LEN_MASK_V2;
2713 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002714 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002715 len = nv_getlen(dev, skb->data, len);
2716 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002717 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002718 dev_kfree_skb(skb);
2719 goto next_pkt;
2720 }
2721 }
2722 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002723 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002724 if (flags & NV_RX2_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002725 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002726 }
2727 /* the rest are hard errors */
2728 else {
2729 if (flags & NV_RX2_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002730 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002731 if (flags & NV_RX2_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002732 dev->stats.rx_over_errors++;
2733 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002734 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002735 goto next_pkt;
2736 }
2737 }
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002738 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2739 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002740 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002741 } else {
2742 dev_kfree_skb(skb);
2743 goto next_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002744 }
2745 }
2746 /* got a valid packet - forward it to the network core */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002747 skb_put(skb, len);
2748 skb->protocol = eth_type_trans(skb, dev);
Joe Perches6b808582010-11-29 07:41:53 +00002749 netdev_dbg(dev, "%s: %d bytes, proto %d accepted\n",
2750 __func__, len, skb->protocol);
Tom Herbert53f224c2010-05-03 19:08:45 +00002751 napi_gro_receive(&np->napi, skb);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002752 dev->stats.rx_packets++;
2753 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002754next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002755 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002756 np->get_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002757 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002758 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002759
2760 rx_work++;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002761 }
2762
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002763 return rx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002764}
2765
2766static int nv_rx_process_optimized(struct net_device *dev, int limit)
2767{
2768 struct fe_priv *np = netdev_priv(dev);
2769 u32 flags;
2770 u32 vlanflags = 0;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002771 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002772 struct sk_buff *skb;
2773 int len;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002774
Szymon Janc78aea4f2010-11-27 08:39:43 +00002775 while ((np->get_rx.ex != np->put_rx.ex) &&
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002776 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
Ingo Molnarc1b71512007-10-17 12:18:23 +02002777 (rx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002778
Joe Perches6b808582010-11-29 07:41:53 +00002779 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002780
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002781 /*
2782 * the packet is for us - immediately tear down the pci mapping.
2783 * TODO: check if a prefetch of the first cacheline improves
2784 * the performance.
2785 */
2786 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2787 np->get_rx_ctx->dma_len,
2788 PCI_DMA_FROMDEVICE);
2789 skb = np->get_rx_ctx->skb;
2790 np->get_rx_ctx->skb = NULL;
2791
Joe Perchese6499852010-11-29 07:41:54 +00002792 netdev_dbg(dev, "Dumping packet (flags 0x%x)\n", flags);
2793#ifdef DEBUG
2794 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
2795 skb->data, 64, true);
2796#endif
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002797 /* look at what we actually got: */
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002798 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2799 len = flags & LEN_MASK_V2;
2800 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002801 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002802 len = nv_getlen(dev, skb->data, len);
2803 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002804 dev_kfree_skb(skb);
2805 goto next_pkt;
2806 }
2807 }
2808 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002809 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002810 if (flags & NV_RX2_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002811 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002812 }
2813 /* the rest are hard errors */
2814 else {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002815 dev_kfree_skb(skb);
2816 goto next_pkt;
2817 }
2818 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002819
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002820 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2821 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002822 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002823
2824 /* got a valid packet - forward it to the network core */
2825 skb_put(skb, len);
2826 skb->protocol = eth_type_trans(skb, dev);
2827 prefetch(skb->data);
2828
Joe Perches6b808582010-11-29 07:41:53 +00002829 netdev_dbg(dev, "%s: %d bytes, proto %d accepted\n",
2830 __func__, len, skb->protocol);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002831
2832 if (likely(!np->vlangrp)) {
Tom Herbert53f224c2010-05-03 19:08:45 +00002833 napi_gro_receive(&np->napi, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002834 } else {
2835 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2836 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
Tom Herbert53f224c2010-05-03 19:08:45 +00002837 vlan_gro_receive(&np->napi, np->vlangrp,
2838 vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002839 } else {
Tom Herbert53f224c2010-05-03 19:08:45 +00002840 napi_gro_receive(&np->napi, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002841 }
2842 }
2843
Jeff Garzik8148ff42007-10-16 20:56:09 -04002844 dev->stats.rx_packets++;
2845 dev->stats.rx_bytes += len;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002846 } else {
2847 dev_kfree_skb(skb);
2848 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002849next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002850 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002851 np->get_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002852 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002853 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002854
2855 rx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002856 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002857
Ingo Molnarc1b71512007-10-17 12:18:23 +02002858 return rx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002859}
2860
Manfred Sprauld81c0982005-07-31 18:20:30 +02002861static void set_bufsize(struct net_device *dev)
2862{
2863 struct fe_priv *np = netdev_priv(dev);
2864
2865 if (dev->mtu <= ETH_DATA_LEN)
2866 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2867 else
2868 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2869}
2870
Linus Torvalds1da177e2005-04-16 15:20:36 -07002871/*
2872 * nv_change_mtu: dev->change_mtu function
2873 * Called with dev_base_lock held for read.
2874 */
2875static int nv_change_mtu(struct net_device *dev, int new_mtu)
2876{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002877 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002878 int old_mtu;
2879
2880 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002881 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002882
2883 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002884 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002885
2886 /* return early if the buffer sizes will not change */
2887 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2888 return 0;
2889 if (old_mtu == new_mtu)
2890 return 0;
2891
2892 /* synchronized against open : rtnl_lock() held by caller */
2893 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002894 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002895 /*
2896 * It seems that the nic preloads valid ring entries into an
2897 * internal buffer. The procedure for flushing everything is
2898 * guessed, there is probably a simpler approach.
2899 * Changing the MTU is a rare event, it shouldn't matter.
2900 */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002901 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00002902 nv_napi_disable(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002903 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002904 netif_addr_lock(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002905 spin_lock(&np->lock);
2906 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002907 nv_stop_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002908 nv_txrx_reset(dev);
2909 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002910 nv_drain_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002911 /* reinit driver view of the rx queue */
Manfred Sprauld81c0982005-07-31 18:20:30 +02002912 set_bufsize(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002913 if (nv_init_ring(dev)) {
Manfred Sprauld81c0982005-07-31 18:20:30 +02002914 if (!np->in_shutdown)
2915 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2916 }
2917 /* reinit nic view of the rx queue */
2918 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002919 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002920 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Manfred Sprauld81c0982005-07-31 18:20:30 +02002921 base + NvRegRingSizes);
2922 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002923 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002924 pci_push(base);
2925
2926 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002927 nv_start_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002928 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002929 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002930 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00002931 nv_napi_enable(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002932 nv_enable_irq(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002933 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002934 return 0;
2935}
2936
Manfred Spraul72b31782005-07-31 18:33:34 +02002937static void nv_copy_mac_to_hw(struct net_device *dev)
2938{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002939 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002940 u32 mac[2];
2941
2942 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2943 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2944 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2945
2946 writel(mac[0], base + NvRegMacAddrA);
2947 writel(mac[1], base + NvRegMacAddrB);
2948}
2949
2950/*
2951 * nv_set_mac_address: dev->set_mac_address function
2952 * Called with rtnl_lock() held.
2953 */
2954static int nv_set_mac_address(struct net_device *dev, void *addr)
2955{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002956 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002957 struct sockaddr *macaddr = (struct sockaddr *)addr;
Manfred Spraul72b31782005-07-31 18:33:34 +02002958
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002959 if (!is_valid_ether_addr(macaddr->sa_data))
Manfred Spraul72b31782005-07-31 18:33:34 +02002960 return -EADDRNOTAVAIL;
2961
2962 /* synchronized against open : rtnl_lock() held by caller */
2963 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2964
2965 if (netif_running(dev)) {
Herbert Xu932ff272006-06-09 12:20:56 -07002966 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002967 netif_addr_lock(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002968 spin_lock_irq(&np->lock);
2969
2970 /* stop rx engine */
2971 nv_stop_rx(dev);
2972
2973 /* set mac address */
2974 nv_copy_mac_to_hw(dev);
2975
2976 /* restart rx engine */
2977 nv_start_rx(dev);
2978 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002979 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002980 netif_tx_unlock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002981 } else {
2982 nv_copy_mac_to_hw(dev);
2983 }
2984 return 0;
2985}
2986
Linus Torvalds1da177e2005-04-16 15:20:36 -07002987/*
2988 * nv_set_multicast: dev->set_multicast function
Herbert Xu932ff272006-06-09 12:20:56 -07002989 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002990 */
2991static void nv_set_multicast(struct net_device *dev)
2992{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002993 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002994 u8 __iomem *base = get_hwbase(dev);
2995 u32 addr[2];
2996 u32 mask[2];
Ayaz Abdullab6d07732006-06-10 22:47:42 -04002997 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002998
2999 memset(addr, 0, sizeof(addr));
3000 memset(mask, 0, sizeof(mask));
3001
3002 if (dev->flags & IFF_PROMISC) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003003 pff |= NVREG_PFF_PROMISC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003004 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003005 pff |= NVREG_PFF_MYADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003006
Jiri Pirko48e2f182010-02-22 09:22:26 +00003007 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003008 u32 alwaysOff[2];
3009 u32 alwaysOn[2];
3010
3011 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3012 if (dev->flags & IFF_ALLMULTI) {
3013 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3014 } else {
Jiri Pirko22bedad32010-04-01 21:22:57 +00003015 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003016
Jiri Pirko22bedad32010-04-01 21:22:57 +00003017 netdev_for_each_mc_addr(ha, dev) {
3018 unsigned char *addr = ha->addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003019 u32 a, b;
Jiri Pirko22bedad32010-04-01 21:22:57 +00003020
3021 a = le32_to_cpu(*(__le32 *) addr);
3022 b = le16_to_cpu(*(__le16 *) (&addr[4]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003023 alwaysOn[0] &= a;
3024 alwaysOff[0] &= ~a;
3025 alwaysOn[1] &= b;
3026 alwaysOff[1] &= ~b;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003027 }
3028 }
3029 addr[0] = alwaysOn[0];
3030 addr[1] = alwaysOn[1];
3031 mask[0] = alwaysOn[0] | alwaysOff[0];
3032 mask[1] = alwaysOn[1] | alwaysOff[1];
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05003033 } else {
3034 mask[0] = NVREG_MCASTMASKA_NONE;
3035 mask[1] = NVREG_MCASTMASKB_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003036 }
3037 }
3038 addr[0] |= NVREG_MCASTADDRA_FORCE;
3039 pff |= NVREG_PFF_ALWAYS;
3040 spin_lock_irq(&np->lock);
3041 nv_stop_rx(dev);
3042 writel(addr[0], base + NvRegMulticastAddrA);
3043 writel(addr[1], base + NvRegMulticastAddrB);
3044 writel(mask[0], base + NvRegMulticastMaskA);
3045 writel(mask[1], base + NvRegMulticastMaskB);
3046 writel(pff, base + NvRegPacketFilterFlags);
Joe Perchesf52dafc2010-11-29 07:41:55 +00003047 netdev_dbg(dev, "reconfiguration for multicast lists\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003048 nv_start_rx(dev);
3049 spin_unlock_irq(&np->lock);
3050}
3051
Adrian Bunkc7985052006-06-22 12:03:29 +02003052static void nv_update_pause(struct net_device *dev, u32 pause_flags)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003053{
3054 struct fe_priv *np = netdev_priv(dev);
3055 u8 __iomem *base = get_hwbase(dev);
3056
3057 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3058
3059 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3060 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3061 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3062 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3063 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3064 } else {
3065 writel(pff, base + NvRegPacketFilterFlags);
3066 }
3067 }
3068 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3069 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3070 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003071 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3072 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3073 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003074 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003075 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003076 /* limit the number of tx pause frames to a default of 8 */
3077 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3078 }
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003079 writel(pause_enable, base + NvRegTxPauseFrame);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003080 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3081 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3082 } else {
3083 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3084 writel(regmisc, base + NvRegMisc1);
3085 }
3086 }
3087}
3088
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003089/**
3090 * nv_update_linkspeed: Setup the MAC according to the link partner
3091 * @dev: Network device to be configured
3092 *
3093 * The function queries the PHY and checks if there is a link partner.
3094 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3095 * set to 10 MBit HD.
3096 *
3097 * The function returns 0 if there is no link partner and 1 if there is
3098 * a good link partner.
3099 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003100static int nv_update_linkspeed(struct net_device *dev)
3101{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003102 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003103 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003104 int adv = 0;
3105 int lpa = 0;
3106 int adv_lpa, adv_pause, lpa_pause;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003107 int newls = np->linkspeed;
3108 int newdup = np->duplex;
3109 int mii_status;
3110 int retval = 0;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003111 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003112 u32 txrxFlags = 0;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003113 u32 phy_exp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003114
3115 /* BMSR_LSTATUS is latched, read it twice:
3116 * we want the current value.
3117 */
3118 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3119 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3120
3121 if (!(mii_status & BMSR_LSTATUS)) {
Joe Perches6b808582010-11-29 07:41:53 +00003122 netdev_dbg(dev,
3123 "no link detected by phy - falling back to 10HD\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003124 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3125 newdup = 0;
3126 retval = 0;
3127 goto set_speed;
3128 }
3129
3130 if (np->autoneg == 0) {
Joe Perches6b808582010-11-29 07:41:53 +00003131 netdev_dbg(dev, "%s: autoneg off, PHY set to 0x%04x\n",
3132 __func__, np->fixed_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003133 if (np->fixed_mode & LPA_100FULL) {
3134 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3135 newdup = 1;
3136 } else if (np->fixed_mode & LPA_100HALF) {
3137 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3138 newdup = 0;
3139 } else if (np->fixed_mode & LPA_10FULL) {
3140 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3141 newdup = 1;
3142 } else {
3143 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3144 newdup = 0;
3145 }
3146 retval = 1;
3147 goto set_speed;
3148 }
3149 /* check auto negotiation is complete */
3150 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3151 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3152 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3153 newdup = 0;
3154 retval = 0;
Joe Perches6b808582010-11-29 07:41:53 +00003155 netdev_dbg(dev,
3156 "autoneg not completed - falling back to 10HD\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003157 goto set_speed;
3158 }
3159
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003160 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3161 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
Joe Perches6b808582010-11-29 07:41:53 +00003162 netdev_dbg(dev, "%s: PHY advertises 0x%04x, lpa 0x%04x\n",
3163 __func__, adv, lpa);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003164
Linus Torvalds1da177e2005-04-16 15:20:36 -07003165 retval = 1;
3166 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003167 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3168 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003169
3170 if ((control_1000 & ADVERTISE_1000FULL) &&
3171 (status_1000 & LPA_1000FULL)) {
Joe Perches6b808582010-11-29 07:41:53 +00003172 netdev_dbg(dev, "%s: GBit ethernet detected\n",
3173 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003174 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3175 newdup = 1;
3176 goto set_speed;
3177 }
3178 }
3179
Linus Torvalds1da177e2005-04-16 15:20:36 -07003180 /* FIXME: handle parallel detection properly */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003181 adv_lpa = lpa & adv;
3182 if (adv_lpa & LPA_100FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003183 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3184 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003185 } else if (adv_lpa & LPA_100HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003186 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3187 newdup = 0;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003188 } else if (adv_lpa & LPA_10FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003189 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3190 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003191 } else if (adv_lpa & LPA_10HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003192 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3193 newdup = 0;
3194 } else {
Joe Perches6b808582010-11-29 07:41:53 +00003195 netdev_dbg(dev, "bad ability %04x - falling back to 10HD\n",
3196 adv_lpa);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003197 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3198 newdup = 0;
3199 }
3200
3201set_speed:
3202 if (np->duplex == newdup && np->linkspeed == newls)
3203 return retval;
3204
Joe Perchesf52dafc2010-11-29 07:41:55 +00003205 netdev_dbg(dev, "changing link setting from %d/%d to %d/%d\n",
3206 np->linkspeed, np->duplex, newls, newdup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003207
3208 np->duplex = newdup;
3209 np->linkspeed = newls;
3210
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003211 /* The transmitter and receiver must be restarted for safe update */
3212 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3213 txrxFlags |= NV_RESTART_TX;
3214 nv_stop_tx(dev);
3215 }
3216 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3217 txrxFlags |= NV_RESTART_RX;
3218 nv_stop_rx(dev);
3219 }
3220
Linus Torvalds1da177e2005-04-16 15:20:36 -07003221 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003222 phyreg = readl(base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003223 phyreg &= ~(0x3FF00);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003224 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3225 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3226 phyreg |= NVREG_SLOTTIME_10_100_FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003227 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003228 phyreg |= NVREG_SLOTTIME_1000_FULL;
3229 writel(phyreg, base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003230 }
3231
3232 phyreg = readl(base + NvRegPhyInterface);
3233 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3234 if (np->duplex == 0)
3235 phyreg |= PHY_HALF;
3236 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3237 phyreg |= PHY_100;
3238 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3239 phyreg |= PHY_1000;
3240 writel(phyreg, base + NvRegPhyInterface);
3241
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003242 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003243 if (phyreg & PHY_RGMII) {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003244 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003245 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003246 } else {
3247 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3248 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3249 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3250 else
3251 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3252 } else {
3253 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3254 }
3255 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003256 } else {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003257 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3258 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3259 else
3260 txreg = NVREG_TX_DEFERRAL_DEFAULT;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003261 }
3262 writel(txreg, base + NvRegTxDeferral);
3263
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04003264 if (np->desc_ver == DESC_VER_1) {
3265 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3266 } else {
3267 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3268 txreg = NVREG_TX_WM_DESC2_3_1000;
3269 else
3270 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3271 }
3272 writel(txreg, base + NvRegTxWatermark);
3273
Szymon Janc78aea4f2010-11-27 08:39:43 +00003274 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
Linus Torvalds1da177e2005-04-16 15:20:36 -07003275 base + NvRegMisc1);
3276 pci_push(base);
3277 writel(np->linkspeed, base + NvRegLinkSpeed);
3278 pci_push(base);
3279
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003280 pause_flags = 0;
3281 /* setup pause frame */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003282 if (np->duplex != 0) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003283 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003284 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3285 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003286
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003287 switch (adv_pause) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003288 case ADVERTISE_PAUSE_CAP:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003289 if (lpa_pause & LPA_PAUSE_CAP) {
3290 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3291 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3292 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3293 }
3294 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003295 case ADVERTISE_PAUSE_ASYM:
Szymon Janc78aea4f2010-11-27 08:39:43 +00003296 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003297 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003298 break;
Szymon Janc78aea4f2010-11-27 08:39:43 +00003299 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3300 if (lpa_pause & LPA_PAUSE_CAP) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003301 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3302 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3303 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3304 }
3305 if (lpa_pause == LPA_PAUSE_ASYM)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003306 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003307 break;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003308 }
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003309 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003310 pause_flags = np->pause_flags;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003311 }
3312 }
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003313 nv_update_pause(dev, pause_flags);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003314
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003315 if (txrxFlags & NV_RESTART_TX)
3316 nv_start_tx(dev);
3317 if (txrxFlags & NV_RESTART_RX)
3318 nv_start_rx(dev);
3319
Linus Torvalds1da177e2005-04-16 15:20:36 -07003320 return retval;
3321}
3322
3323static void nv_linkchange(struct net_device *dev)
3324{
3325 if (nv_update_linkspeed(dev)) {
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003326 if (!netif_carrier_ok(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003327 netif_carrier_on(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00003328 netdev_info(dev, "link up\n");
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003329 nv_txrx_gate(dev, false);
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003330 nv_start_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003331 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003332 } else {
3333 if (netif_carrier_ok(dev)) {
3334 netif_carrier_off(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00003335 netdev_info(dev, "link down\n");
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003336 nv_txrx_gate(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003337 nv_stop_rx(dev);
3338 }
3339 }
3340}
3341
3342static void nv_link_irq(struct net_device *dev)
3343{
3344 u8 __iomem *base = get_hwbase(dev);
3345 u32 miistat;
3346
3347 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05003348 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
Joe Perchesf52dafc2010-11-29 07:41:55 +00003349 netdev_dbg(dev, "link change irq, status 0x%x\n", miistat);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003350
3351 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3352 nv_linkchange(dev);
Joe Perches6b808582010-11-29 07:41:53 +00003353 netdev_dbg(dev, "link change notification done\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003354}
3355
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003356static void nv_msi_workaround(struct fe_priv *np)
3357{
3358
3359 /* Need to toggle the msi irq mask within the ethernet device,
3360 * otherwise, future interrupts will not be detected.
3361 */
3362 if (np->msi_flags & NV_MSI_ENABLED) {
3363 u8 __iomem *base = np->base;
3364
3365 writel(0, base + NvRegMSIIrqMask);
3366 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3367 }
3368}
3369
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003370static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3371{
3372 struct fe_priv *np = netdev_priv(dev);
3373
3374 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3375 if (total_work > NV_DYNAMIC_THRESHOLD) {
3376 /* transition to poll based interrupts */
3377 np->quiet_count = 0;
3378 if (np->irqmask != NVREG_IRQMASK_CPU) {
3379 np->irqmask = NVREG_IRQMASK_CPU;
3380 return 1;
3381 }
3382 } else {
3383 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3384 np->quiet_count++;
3385 } else {
3386 /* reached a period of low activity, switch
3387 to per tx/rx packet interrupts */
3388 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3389 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3390 return 1;
3391 }
3392 }
3393 }
3394 }
3395 return 0;
3396}
3397
David Howells7d12e782006-10-05 14:55:46 +01003398static irqreturn_t nv_nic_irq(int foo, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003399{
3400 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003401 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003402 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003403
Joe Perches6b808582010-11-29 07:41:53 +00003404 netdev_dbg(dev, "%s\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003405
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003406 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3407 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003408 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003409 } else {
3410 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003411 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003412 }
Joe Perches6b808582010-11-29 07:41:53 +00003413 netdev_dbg(dev, "irq: %08x\n", np->events);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003414 if (!(np->events & np->irqmask))
3415 return IRQ_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003416
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003417 nv_msi_workaround(np);
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003418
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003419 if (napi_schedule_prep(&np->napi)) {
3420 /*
3421 * Disable further irq's (msix not enabled with napi)
3422 */
3423 writel(0, base + NvRegIrqMask);
3424 __napi_schedule(&np->napi);
3425 }
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003426
Joe Perches6b808582010-11-29 07:41:53 +00003427 netdev_dbg(dev, "%s: completed\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003428
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003429 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003430}
3431
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003432/**
3433 * All _optimized functions are used to help increase performance
3434 * (reduce CPU and increase throughput). They use descripter version 3,
3435 * compiler directives, and reduce memory accesses.
3436 */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003437static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3438{
3439 struct net_device *dev = (struct net_device *) data;
3440 struct fe_priv *np = netdev_priv(dev);
3441 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003442
Joe Perches6b808582010-11-29 07:41:53 +00003443 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003444
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003445 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3446 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003447 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003448 } else {
3449 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003450 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003451 }
Joe Perches6b808582010-11-29 07:41:53 +00003452 netdev_dbg(dev, "irq: %08x\n", np->events);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003453 if (!(np->events & np->irqmask))
3454 return IRQ_NONE;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003455
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003456 nv_msi_workaround(np);
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003457
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003458 if (napi_schedule_prep(&np->napi)) {
3459 /*
3460 * Disable further irq's (msix not enabled with napi)
3461 */
3462 writel(0, base + NvRegIrqMask);
3463 __napi_schedule(&np->napi);
3464 }
Joe Perches6b808582010-11-29 07:41:53 +00003465 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003466
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003467 return IRQ_HANDLED;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003468}
3469
David Howells7d12e782006-10-05 14:55:46 +01003470static irqreturn_t nv_nic_irq_tx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003471{
3472 struct net_device *dev = (struct net_device *) data;
3473 struct fe_priv *np = netdev_priv(dev);
3474 u8 __iomem *base = get_hwbase(dev);
3475 u32 events;
3476 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003477 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003478
Joe Perches6b808582010-11-29 07:41:53 +00003479 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003480
Szymon Janc78aea4f2010-11-27 08:39:43 +00003481 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003482 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3483 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
Joe Perches6b808582010-11-29 07:41:53 +00003484 netdev_dbg(dev, "tx irq: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003485 if (!(events & np->irqmask))
3486 break;
3487
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003488 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003489 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003490 spin_unlock_irqrestore(&np->lock, flags);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003491
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003492 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003493 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003494 /* disable interrupts on the nic */
3495 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3496 pci_push(base);
3497
3498 if (!np->in_shutdown) {
3499 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3500 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3501 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003502 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003503 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003504 break;
3505 }
3506
3507 }
Joe Perches6b808582010-11-29 07:41:53 +00003508 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003509
3510 return IRQ_RETVAL(i);
3511}
3512
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003513static int nv_napi_poll(struct napi_struct *napi, int budget)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003514{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003515 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3516 struct net_device *dev = np->dev;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003517 u8 __iomem *base = get_hwbase(dev);
Francois Romieud15e9c42006-12-17 23:03:15 +01003518 unsigned long flags;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003519 int retcode;
Szymon Janc78aea4f2010-11-27 08:39:43 +00003520 int rx_count, tx_work = 0, rx_work = 0;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003521
stephen hemminger81a2e362010-04-28 08:25:28 +00003522 do {
3523 if (!nv_optimized(np)) {
3524 spin_lock_irqsave(&np->lock, flags);
3525 tx_work += nv_tx_done(dev, np->tx_ring_size);
3526 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003527
Tom Herbertd951f722010-05-05 18:15:21 +00003528 rx_count = nv_rx_process(dev, budget - rx_work);
stephen hemminger81a2e362010-04-28 08:25:28 +00003529 retcode = nv_alloc_rx(dev);
3530 } else {
3531 spin_lock_irqsave(&np->lock, flags);
3532 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3533 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003534
Tom Herbertd951f722010-05-05 18:15:21 +00003535 rx_count = nv_rx_process_optimized(dev,
3536 budget - rx_work);
stephen hemminger81a2e362010-04-28 08:25:28 +00003537 retcode = nv_alloc_rx_optimized(dev);
3538 }
3539 } while (retcode == 0 &&
3540 rx_count > 0 && (rx_work += rx_count) < budget);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003541
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003542 if (retcode) {
Francois Romieud15e9c42006-12-17 23:03:15 +01003543 spin_lock_irqsave(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003544 if (!np->in_shutdown)
3545 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Francois Romieud15e9c42006-12-17 23:03:15 +01003546 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003547 }
3548
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003549 nv_change_interrupt_mode(dev, tx_work + rx_work);
3550
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003551 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3552 spin_lock_irqsave(&np->lock, flags);
3553 nv_link_irq(dev);
3554 spin_unlock_irqrestore(&np->lock, flags);
3555 }
3556 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3557 spin_lock_irqsave(&np->lock, flags);
3558 nv_linkchange(dev);
3559 spin_unlock_irqrestore(&np->lock, flags);
3560 np->link_timeout = jiffies + LINK_TIMEOUT;
3561 }
3562 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3563 spin_lock_irqsave(&np->lock, flags);
3564 if (!np->in_shutdown) {
3565 np->nic_poll_irq = np->irqmask;
3566 np->recover_error = 1;
3567 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3568 }
3569 spin_unlock_irqrestore(&np->lock, flags);
David S. Miller6c2da9c2009-04-09 01:09:33 -07003570 napi_complete(napi);
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003571 return rx_work;
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003572 }
3573
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003574 if (rx_work < budget) {
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003575 /* re-enable interrupts
3576 (msix not enabled in napi) */
David S. Miller6c2da9c2009-04-09 01:09:33 -07003577 napi_complete(napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003578
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003579 writel(np->irqmask, base + NvRegIrqMask);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003580 }
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003581 return rx_work;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003582}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003583
David Howells7d12e782006-10-05 14:55:46 +01003584static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003585{
3586 struct net_device *dev = (struct net_device *) data;
3587 struct fe_priv *np = netdev_priv(dev);
3588 u8 __iomem *base = get_hwbase(dev);
3589 u32 events;
3590 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003591 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003592
Joe Perches6b808582010-11-29 07:41:53 +00003593 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003594
Szymon Janc78aea4f2010-11-27 08:39:43 +00003595 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003596 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3597 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
Joe Perches6b808582010-11-29 07:41:53 +00003598 netdev_dbg(dev, "rx irq: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003599 if (!(events & np->irqmask))
3600 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003601
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003602 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003603 if (unlikely(nv_alloc_rx_optimized(dev))) {
3604 spin_lock_irqsave(&np->lock, flags);
3605 if (!np->in_shutdown)
3606 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3607 spin_unlock_irqrestore(&np->lock, flags);
3608 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003609 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003610
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003611 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003612 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003613 /* disable interrupts on the nic */
3614 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3615 pci_push(base);
3616
3617 if (!np->in_shutdown) {
3618 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3619 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3620 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003621 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003622 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003623 break;
3624 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003625 }
Joe Perches6b808582010-11-29 07:41:53 +00003626 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003627
3628 return IRQ_RETVAL(i);
3629}
3630
David Howells7d12e782006-10-05 14:55:46 +01003631static irqreturn_t nv_nic_irq_other(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003632{
3633 struct net_device *dev = (struct net_device *) data;
3634 struct fe_priv *np = netdev_priv(dev);
3635 u8 __iomem *base = get_hwbase(dev);
3636 u32 events;
3637 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003638 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003639
Joe Perches6b808582010-11-29 07:41:53 +00003640 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003641
Szymon Janc78aea4f2010-11-27 08:39:43 +00003642 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003643 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3644 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
Joe Perches6b808582010-11-29 07:41:53 +00003645 netdev_dbg(dev, "irq: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003646 if (!(events & np->irqmask))
3647 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003648
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003649 /* check tx in case we reached max loop limit in tx isr */
3650 spin_lock_irqsave(&np->lock, flags);
3651 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3652 spin_unlock_irqrestore(&np->lock, flags);
3653
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003654 if (events & NVREG_IRQ_LINK) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003655 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003656 nv_link_irq(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003657 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003658 }
3659 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003660 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003661 nv_linkchange(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003662 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003663 np->link_timeout = jiffies + LINK_TIMEOUT;
3664 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003665 if (events & NVREG_IRQ_RECOVER_ERROR) {
3666 spin_lock_irq(&np->lock);
3667 /* disable interrupts on the nic */
3668 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3669 pci_push(base);
3670
3671 if (!np->in_shutdown) {
3672 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3673 np->recover_error = 1;
3674 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3675 }
3676 spin_unlock_irq(&np->lock);
3677 break;
3678 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003679 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003680 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003681 /* disable interrupts on the nic */
3682 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3683 pci_push(base);
3684
3685 if (!np->in_shutdown) {
3686 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3687 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3688 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003689 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003690 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003691 break;
3692 }
3693
3694 }
Joe Perches6b808582010-11-29 07:41:53 +00003695 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003696
3697 return IRQ_RETVAL(i);
3698}
3699
David Howells7d12e782006-10-05 14:55:46 +01003700static irqreturn_t nv_nic_irq_test(int foo, void *data)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003701{
3702 struct net_device *dev = (struct net_device *) data;
3703 struct fe_priv *np = netdev_priv(dev);
3704 u8 __iomem *base = get_hwbase(dev);
3705 u32 events;
3706
Joe Perches6b808582010-11-29 07:41:53 +00003707 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003708
3709 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3710 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3711 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3712 } else {
3713 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3714 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3715 }
3716 pci_push(base);
Joe Perches6b808582010-11-29 07:41:53 +00003717 netdev_dbg(dev, "irq: %08x\n", events);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003718 if (!(events & NVREG_IRQ_TIMER))
3719 return IRQ_RETVAL(0);
3720
Ayaz Abdulla4db0ee172008-06-09 16:51:06 -07003721 nv_msi_workaround(np);
3722
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003723 spin_lock(&np->lock);
3724 np->intr_test = 1;
3725 spin_unlock(&np->lock);
3726
Joe Perches6b808582010-11-29 07:41:53 +00003727 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003728
3729 return IRQ_RETVAL(1);
3730}
3731
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003732static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3733{
3734 u8 __iomem *base = get_hwbase(dev);
3735 int i;
3736 u32 msixmap = 0;
3737
3738 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3739 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3740 * the remaining 8 interrupts.
3741 */
3742 for (i = 0; i < 8; i++) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003743 if ((irqmask >> i) & 0x1)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003744 msixmap |= vector << (i << 2);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003745 }
3746 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3747
3748 msixmap = 0;
3749 for (i = 0; i < 8; i++) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003750 if ((irqmask >> (i + 8)) & 0x1)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003751 msixmap |= vector << (i << 2);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003752 }
3753 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3754}
3755
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003756static int nv_request_irq(struct net_device *dev, int intr_test)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003757{
3758 struct fe_priv *np = get_nvpriv(dev);
3759 u8 __iomem *base = get_hwbase(dev);
3760 int ret = 1;
3761 int i;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003762 irqreturn_t (*handler)(int foo, void *data);
3763
3764 if (intr_test) {
3765 handler = nv_nic_irq_test;
3766 } else {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003767 if (nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003768 handler = nv_nic_irq_optimized;
3769 else
3770 handler = nv_nic_irq;
3771 }
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003772
3773 if (np->msi_flags & NV_MSI_X_CAPABLE) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003774 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003775 np->msi_x_entry[i].entry = i;
Szymon Janc34cf97e2010-11-27 08:39:46 +00003776 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3777 if (ret == 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003778 np->msi_flags |= NV_MSI_X_ENABLED;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003779 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003780 /* Request irq for rx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003781 sprintf(np->name_rx, "%s-rx", dev->name);
3782 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003783 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003784 netdev_info(dev,
3785 "request_irq failed for rx %d\n",
3786 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003787 pci_disable_msix(np->pci_dev);
3788 np->msi_flags &= ~NV_MSI_X_ENABLED;
3789 goto out_err;
3790 }
3791 /* Request irq for tx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003792 sprintf(np->name_tx, "%s-tx", dev->name);
3793 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003794 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003795 netdev_info(dev,
3796 "request_irq failed for tx %d\n",
3797 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003798 pci_disable_msix(np->pci_dev);
3799 np->msi_flags &= ~NV_MSI_X_ENABLED;
3800 goto out_free_rx;
3801 }
3802 /* Request irq for link and timer handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003803 sprintf(np->name_other, "%s-other", dev->name);
3804 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003805 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003806 netdev_info(dev,
3807 "request_irq failed for link %d\n",
3808 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003809 pci_disable_msix(np->pci_dev);
3810 np->msi_flags &= ~NV_MSI_X_ENABLED;
3811 goto out_free_tx;
3812 }
3813 /* map interrupts to their respective vector */
3814 writel(0, base + NvRegMSIXMap0);
3815 writel(0, base + NvRegMSIXMap1);
3816 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3817 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3818 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3819 } else {
3820 /* Request irq for all interrupts */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003821 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003822 netdev_info(dev,
3823 "request_irq failed %d\n",
3824 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003825 pci_disable_msix(np->pci_dev);
3826 np->msi_flags &= ~NV_MSI_X_ENABLED;
3827 goto out_err;
3828 }
3829
3830 /* map interrupts to vector 0 */
3831 writel(0, base + NvRegMSIXMap0);
3832 writel(0, base + NvRegMSIXMap1);
3833 }
3834 }
3835 }
3836 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
Szymon Janc34cf97e2010-11-27 08:39:46 +00003837 ret = pci_enable_msi(np->pci_dev);
3838 if (ret == 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003839 np->msi_flags |= NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003840 dev->irq = np->pci_dev->irq;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003841 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
Joe Perches1d397f32010-11-29 07:41:57 +00003842 netdev_info(dev, "request_irq failed %d\n",
3843 ret);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003844 pci_disable_msi(np->pci_dev);
3845 np->msi_flags &= ~NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003846 dev->irq = np->pci_dev->irq;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003847 goto out_err;
3848 }
3849
3850 /* map interrupts to vector 0 */
3851 writel(0, base + NvRegMSIMap0);
3852 writel(0, base + NvRegMSIMap1);
3853 /* enable msi vector 0 */
3854 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3855 }
3856 }
3857 if (ret != 0) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003858 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003859 goto out_err;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003860
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003861 }
3862
3863 return 0;
3864out_free_tx:
3865 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3866out_free_rx:
3867 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3868out_err:
3869 return 1;
3870}
3871
3872static void nv_free_irq(struct net_device *dev)
3873{
3874 struct fe_priv *np = get_nvpriv(dev);
3875 int i;
3876
3877 if (np->msi_flags & NV_MSI_X_ENABLED) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003878 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003879 free_irq(np->msi_x_entry[i].vector, dev);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003880 pci_disable_msix(np->pci_dev);
3881 np->msi_flags &= ~NV_MSI_X_ENABLED;
3882 } else {
3883 free_irq(np->pci_dev->irq, dev);
3884 if (np->msi_flags & NV_MSI_ENABLED) {
3885 pci_disable_msi(np->pci_dev);
3886 np->msi_flags &= ~NV_MSI_ENABLED;
3887 }
3888 }
3889}
3890
Linus Torvalds1da177e2005-04-16 15:20:36 -07003891static void nv_do_nic_poll(unsigned long data)
3892{
3893 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003894 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003895 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003896 u32 mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003897
Linus Torvalds1da177e2005-04-16 15:20:36 -07003898 /*
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003899 * First disable irq(s) and then
Linus Torvalds1da177e2005-04-16 15:20:36 -07003900 * reenable interrupts on the nic, we have to do this before calling
3901 * nv_nic_irq because that may decide to do otherwise
3902 */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003903
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003904 if (!using_multi_irqs(dev)) {
3905 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003906 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003907 else
Manfred Spraula7475902007-10-17 21:52:33 +02003908 disable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003909 mask = np->irqmask;
3910 } else {
3911 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003912 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003913 mask |= NVREG_IRQ_RX_ALL;
3914 }
3915 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003916 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003917 mask |= NVREG_IRQ_TX_ALL;
3918 }
3919 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003920 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003921 mask |= NVREG_IRQ_OTHER;
3922 }
3923 }
Manfred Spraula7475902007-10-17 21:52:33 +02003924 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3925
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003926 if (np->recover_error) {
3927 np->recover_error = 0;
Joe Perches1d397f32010-11-29 07:41:57 +00003928 netdev_info(dev, "MAC in recoverable error state\n");
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003929 if (netif_running(dev)) {
3930 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07003931 netif_addr_lock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003932 spin_lock(&np->lock);
3933 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003934 nv_stop_rxtx(dev);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08003935 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3936 nv_mac_reset(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003937 nv_txrx_reset(dev);
3938 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003939 nv_drain_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003940 /* reinit driver view of the rx queue */
3941 set_bufsize(dev);
3942 if (nv_init_ring(dev)) {
3943 if (!np->in_shutdown)
3944 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3945 }
3946 /* reinit nic view of the rx queue */
3947 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3948 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00003949 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003950 base + NvRegRingSizes);
3951 pci_push(base);
3952 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3953 pci_push(base);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08003954 /* clear interrupts */
3955 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3956 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3957 else
3958 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003959
3960 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003961 nv_start_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003962 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07003963 netif_addr_unlock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003964 netif_tx_unlock_bh(dev);
3965 }
3966 }
3967
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003968 writel(mask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003969 pci_push(base);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003970
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003971 if (!using_multi_irqs(dev)) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003972 np->nic_poll_irq = 0;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003973 if (nv_optimized(np))
Ayaz Abdullafcc5f262007-03-23 05:49:37 -05003974 nv_nic_irq_optimized(0, dev);
3975 else
3976 nv_nic_irq(0, dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003977 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003978 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003979 else
Manfred Spraula7475902007-10-17 21:52:33 +02003980 enable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003981 } else {
3982 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003983 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01003984 nv_nic_irq_rx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003985 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003986 }
3987 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003988 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01003989 nv_nic_irq_tx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003990 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003991 }
3992 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003993 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
David Howells7d12e782006-10-05 14:55:46 +01003994 nv_nic_irq_other(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003995 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003996 }
3997 }
Yinghai Lu79d30a52009-02-06 01:30:01 -08003998
Linus Torvalds1da177e2005-04-16 15:20:36 -07003999}
4000
Michal Schmidt2918c352005-05-12 19:42:06 -04004001#ifdef CONFIG_NET_POLL_CONTROLLER
4002static void nv_poll_controller(struct net_device *dev)
4003{
4004 nv_do_nic_poll((unsigned long) dev);
4005}
4006#endif
4007
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004008static void nv_do_stats_poll(unsigned long data)
4009{
4010 struct net_device *dev = (struct net_device *) data;
4011 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004012
Ayaz Abdulla57fff692007-01-23 12:27:00 -05004013 nv_get_hw_stats(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004014
4015 if (!np->in_shutdown)
Daniel Drakebfebbb82008-03-18 11:07:18 +00004016 mod_timer(&np->stats_poll,
4017 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004018}
4019
Linus Torvalds1da177e2005-04-16 15:20:36 -07004020static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4021{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004022 struct fe_priv *np = netdev_priv(dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04004023 strcpy(info->driver, DRV_NAME);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004024 strcpy(info->version, FORCEDETH_VERSION);
4025 strcpy(info->bus_info, pci_name(np->pci_dev));
4026}
4027
4028static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4029{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004030 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004031 wolinfo->supported = WAKE_MAGIC;
4032
4033 spin_lock_irq(&np->lock);
4034 if (np->wolenabled)
4035 wolinfo->wolopts = WAKE_MAGIC;
4036 spin_unlock_irq(&np->lock);
4037}
4038
4039static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4040{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004041 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004042 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004043 u32 flags = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004044
Linus Torvalds1da177e2005-04-16 15:20:36 -07004045 if (wolinfo->wolopts == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004046 np->wolenabled = 0;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004047 } else if (wolinfo->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004048 np->wolenabled = 1;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004049 flags = NVREG_WAKEUPFLAGS_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004050 }
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004051 if (netif_running(dev)) {
4052 spin_lock_irq(&np->lock);
4053 writel(flags, base + NvRegWakeUpFlags);
4054 spin_unlock_irq(&np->lock);
4055 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004056 return 0;
4057}
4058
4059static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4060{
4061 struct fe_priv *np = netdev_priv(dev);
4062 int adv;
4063
4064 spin_lock_irq(&np->lock);
4065 ecmd->port = PORT_MII;
4066 if (!netif_running(dev)) {
4067 /* We do not track link speed / duplex setting if the
4068 * interface is disabled. Force a link check */
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004069 if (nv_update_linkspeed(dev)) {
4070 if (!netif_carrier_ok(dev))
4071 netif_carrier_on(dev);
4072 } else {
4073 if (netif_carrier_ok(dev))
4074 netif_carrier_off(dev);
4075 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004076 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004077
4078 if (netif_carrier_ok(dev)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004079 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004080 case NVREG_LINKSPEED_10:
4081 ecmd->speed = SPEED_10;
4082 break;
4083 case NVREG_LINKSPEED_100:
4084 ecmd->speed = SPEED_100;
4085 break;
4086 case NVREG_LINKSPEED_1000:
4087 ecmd->speed = SPEED_1000;
4088 break;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004089 }
4090 ecmd->duplex = DUPLEX_HALF;
4091 if (np->duplex)
4092 ecmd->duplex = DUPLEX_FULL;
4093 } else {
4094 ecmd->speed = -1;
4095 ecmd->duplex = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004096 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004097
4098 ecmd->autoneg = np->autoneg;
4099
4100 ecmd->advertising = ADVERTISED_MII;
4101 if (np->autoneg) {
4102 ecmd->advertising |= ADVERTISED_Autoneg;
4103 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004104 if (adv & ADVERTISE_10HALF)
4105 ecmd->advertising |= ADVERTISED_10baseT_Half;
4106 if (adv & ADVERTISE_10FULL)
4107 ecmd->advertising |= ADVERTISED_10baseT_Full;
4108 if (adv & ADVERTISE_100HALF)
4109 ecmd->advertising |= ADVERTISED_100baseT_Half;
4110 if (adv & ADVERTISE_100FULL)
4111 ecmd->advertising |= ADVERTISED_100baseT_Full;
4112 if (np->gigabit == PHY_GIGABIT) {
4113 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4114 if (adv & ADVERTISE_1000FULL)
4115 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4116 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004117 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004118 ecmd->supported = (SUPPORTED_Autoneg |
4119 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4120 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4121 SUPPORTED_MII);
4122 if (np->gigabit == PHY_GIGABIT)
4123 ecmd->supported |= SUPPORTED_1000baseT_Full;
4124
4125 ecmd->phy_address = np->phyaddr;
4126 ecmd->transceiver = XCVR_EXTERNAL;
4127
4128 /* ignore maxtxpkt, maxrxpkt for now */
4129 spin_unlock_irq(&np->lock);
4130 return 0;
4131}
4132
4133static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4134{
4135 struct fe_priv *np = netdev_priv(dev);
4136
4137 if (ecmd->port != PORT_MII)
4138 return -EINVAL;
4139 if (ecmd->transceiver != XCVR_EXTERNAL)
4140 return -EINVAL;
4141 if (ecmd->phy_address != np->phyaddr) {
4142 /* TODO: support switching between multiple phys. Should be
4143 * trivial, but not enabled due to lack of test hardware. */
4144 return -EINVAL;
4145 }
4146 if (ecmd->autoneg == AUTONEG_ENABLE) {
4147 u32 mask;
4148
4149 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4150 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4151 if (np->gigabit == PHY_GIGABIT)
4152 mask |= ADVERTISED_1000baseT_Full;
4153
4154 if ((ecmd->advertising & mask) == 0)
4155 return -EINVAL;
4156
4157 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4158 /* Note: autonegotiation disable, speed 1000 intentionally
4159 * forbidden - noone should need that. */
4160
4161 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4162 return -EINVAL;
4163 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4164 return -EINVAL;
4165 } else {
4166 return -EINVAL;
4167 }
4168
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004169 netif_carrier_off(dev);
4170 if (netif_running(dev)) {
Tobias Diedrich97bff092008-07-03 23:54:56 -07004171 unsigned long flags;
4172
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004173 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004174 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004175 netif_addr_lock(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004176 /* with plain spinlock lockdep complains */
4177 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004178 /* stop engines */
Tobias Diedrich97bff092008-07-03 23:54:56 -07004179 /* FIXME:
4180 * this can take some time, and interrupts are disabled
4181 * due to spin_lock_irqsave, but let's hope no daemon
4182 * is going to change the settings very often...
4183 * Worst case:
4184 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4185 * + some minor delays, which is up to a second approximately
4186 */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004187 nv_stop_rxtx(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004188 spin_unlock_irqrestore(&np->lock, flags);
David S. Millere308a5d2008-07-15 00:13:44 -07004189 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004190 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004191 }
4192
Linus Torvalds1da177e2005-04-16 15:20:36 -07004193 if (ecmd->autoneg == AUTONEG_ENABLE) {
4194 int adv, bmcr;
4195
4196 np->autoneg = 1;
4197
4198 /* advertise only what has been requested */
4199 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004200 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004201 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4202 adv |= ADVERTISE_10HALF;
4203 if (ecmd->advertising & ADVERTISED_10baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004204 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004205 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4206 adv |= ADVERTISE_100HALF;
4207 if (ecmd->advertising & ADVERTISED_100baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004208 adv |= ADVERTISE_100FULL;
4209 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4210 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4211 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4212 adv |= ADVERTISE_PAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004213 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4214
4215 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004216 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004217 adv &= ~ADVERTISE_1000FULL;
4218 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4219 adv |= ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004220 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004221 }
4222
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004223 if (netif_running(dev))
Joe Perches1d397f32010-11-29 07:41:57 +00004224 netdev_info(dev, "link down\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07004225 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004226 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4227 bmcr |= BMCR_ANENABLE;
4228 /* reset the phy in order for settings to stick,
4229 * and cause autoneg to start */
4230 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004231 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004232 return -EINVAL;
4233 }
4234 } else {
4235 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4236 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4237 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004238 } else {
4239 int adv, bmcr;
4240
4241 np->autoneg = 0;
4242
4243 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004244 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004245 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4246 adv |= ADVERTISE_10HALF;
4247 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004248 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004249 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4250 adv |= ADVERTISE_100HALF;
4251 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004252 adv |= ADVERTISE_100FULL;
4253 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4254 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4255 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4256 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4257 }
4258 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4259 adv |= ADVERTISE_PAUSE_ASYM;
4260 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4261 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004262 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4263 np->fixed_mode = adv;
4264
4265 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004266 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004267 adv &= ~ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004268 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004269 }
4270
4271 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004272 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4273 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004274 bmcr |= BMCR_FULLDPLX;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004275 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004276 bmcr |= BMCR_SPEED100;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004277 if (np->phy_oui == PHY_OUI_MARVELL) {
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004278 /* reset the phy in order for forced mode settings to stick */
4279 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004280 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004281 return -EINVAL;
4282 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004283 } else {
4284 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4285 if (netif_running(dev)) {
4286 /* Wait a bit and then reconfigure the nic. */
4287 udelay(10);
4288 nv_linkchange(dev);
4289 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004290 }
4291 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004292
4293 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004294 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004295 nv_enable_irq(dev);
4296 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004297
4298 return 0;
4299}
4300
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004301#define FORCEDETH_REGS_VER 1
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004302
4303static int nv_get_regs_len(struct net_device *dev)
4304{
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004305 struct fe_priv *np = netdev_priv(dev);
4306 return np->register_size;
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004307}
4308
4309static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4310{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004311 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004312 u8 __iomem *base = get_hwbase(dev);
4313 u32 *rbuf = buf;
4314 int i;
4315
4316 regs->version = FORCEDETH_REGS_VER;
4317 spin_lock_irq(&np->lock);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004318 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004319 rbuf[i] = readl(base + i*sizeof(u32));
4320 spin_unlock_irq(&np->lock);
4321}
4322
4323static int nv_nway_reset(struct net_device *dev)
4324{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004325 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004326 int ret;
4327
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004328 if (np->autoneg) {
4329 int bmcr;
4330
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004331 netif_carrier_off(dev);
4332 if (netif_running(dev)) {
4333 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004334 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004335 netif_addr_lock(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004336 spin_lock(&np->lock);
4337 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004338 nv_stop_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004339 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004340 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004341 netif_tx_unlock_bh(dev);
Joe Perches1d397f32010-11-29 07:41:57 +00004342 netdev_info(dev, "link down\n");
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004343 }
4344
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004345 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004346 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4347 bmcr |= BMCR_ANENABLE;
4348 /* reset the phy in order for settings to stick*/
4349 if (phy_reset(dev, bmcr)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004350 netdev_info(dev, "phy reset failed\n");
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004351 return -EINVAL;
4352 }
4353 } else {
4354 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4355 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4356 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004357
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004358 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004359 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004360 nv_enable_irq(dev);
4361 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004362 ret = 0;
4363 } else {
4364 ret = -EINVAL;
4365 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004366
4367 return ret;
4368}
4369
Zachary Amsden0674d592006-06-04 02:51:38 -07004370static int nv_set_tso(struct net_device *dev, u32 value)
4371{
4372 struct fe_priv *np = netdev_priv(dev);
4373
4374 if ((np->driver_data & DEV_HAS_CHECKSUM))
4375 return ethtool_op_set_tso(dev, value);
4376 else
Ayaz Abdulla6a788142006-06-10 22:47:26 -04004377 return -EOPNOTSUPP;
Zachary Amsden0674d592006-06-04 02:51:38 -07004378}
Zachary Amsden0674d592006-06-04 02:51:38 -07004379
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004380static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4381{
4382 struct fe_priv *np = netdev_priv(dev);
4383
4384 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4385 ring->rx_mini_max_pending = 0;
4386 ring->rx_jumbo_max_pending = 0;
4387 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4388
4389 ring->rx_pending = np->rx_ring_size;
4390 ring->rx_mini_pending = 0;
4391 ring->rx_jumbo_pending = 0;
4392 ring->tx_pending = np->tx_ring_size;
4393}
4394
4395static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4396{
4397 struct fe_priv *np = netdev_priv(dev);
4398 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004399 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004400 dma_addr_t ring_addr;
4401
4402 if (ring->rx_pending < RX_RING_MIN ||
4403 ring->tx_pending < TX_RING_MIN ||
4404 ring->rx_mini_pending != 0 ||
4405 ring->rx_jumbo_pending != 0 ||
4406 (np->desc_ver == DESC_VER_1 &&
4407 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4408 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4409 (np->desc_ver != DESC_VER_1 &&
4410 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4411 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4412 return -EINVAL;
4413 }
4414
4415 /* allocate new rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004416 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004417 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4418 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4419 &ring_addr);
4420 } else {
4421 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4422 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4423 &ring_addr);
4424 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004425 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4426 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4427 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004428 /* fall back to old rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004429 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004430 if (rxtx_ring)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004431 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4432 rxtx_ring, ring_addr);
4433 } else {
4434 if (rxtx_ring)
4435 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4436 rxtx_ring, ring_addr);
4437 }
Szymon Janc9b03b062010-11-27 08:39:44 +00004438
4439 kfree(rx_skbuff);
4440 kfree(tx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004441 goto exit;
4442 }
4443
4444 if (netif_running(dev)) {
4445 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004446 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004447 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004448 netif_addr_lock(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004449 spin_lock(&np->lock);
4450 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004451 nv_stop_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004452 nv_txrx_reset(dev);
4453 /* drain queues */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004454 nv_drain_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004455 /* delete queues */
4456 free_rings(dev);
4457 }
4458
4459 /* set new values */
4460 np->rx_ring_size = ring->rx_pending;
4461 np->tx_ring_size = ring->tx_pending;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004462
4463 if (!nv_optimized(np)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004464 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004465 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4466 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004467 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004468 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4469 }
Szymon Janc78aea4f2010-11-27 08:39:43 +00004470 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4471 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004472 np->ring_addr = ring_addr;
4473
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004474 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4475 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004476
4477 if (netif_running(dev)) {
4478 /* reinit driver view of the queues */
4479 set_bufsize(dev);
4480 if (nv_init_ring(dev)) {
4481 if (!np->in_shutdown)
4482 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4483 }
4484
4485 /* reinit nic view of the queues */
4486 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4487 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004488 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004489 base + NvRegRingSizes);
4490 pci_push(base);
4491 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4492 pci_push(base);
4493
4494 /* restart engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004495 nv_start_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004496 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004497 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004498 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004499 nv_napi_enable(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004500 nv_enable_irq(dev);
4501 }
4502 return 0;
4503exit:
4504 return -ENOMEM;
4505}
4506
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004507static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4508{
4509 struct fe_priv *np = netdev_priv(dev);
4510
4511 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4512 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4513 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4514}
4515
4516static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4517{
4518 struct fe_priv *np = netdev_priv(dev);
4519 int adv, bmcr;
4520
4521 if ((!np->autoneg && np->duplex == 0) ||
4522 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004523 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004524 return -EINVAL;
4525 }
4526 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
Joe Perches1d397f32010-11-29 07:41:57 +00004527 netdev_info(dev, "hardware does not support tx pause frames\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004528 return -EINVAL;
4529 }
4530
4531 netif_carrier_off(dev);
4532 if (netif_running(dev)) {
4533 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004534 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004535 netif_addr_lock(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004536 spin_lock(&np->lock);
4537 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004538 nv_stop_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004539 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004540 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004541 netif_tx_unlock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004542 }
4543
4544 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4545 if (pause->rx_pause)
4546 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4547 if (pause->tx_pause)
4548 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4549
4550 if (np->autoneg && pause->autoneg) {
4551 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4552
4553 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4554 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4555 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4556 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4557 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4558 adv |= ADVERTISE_PAUSE_ASYM;
4559 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4560
4561 if (netif_running(dev))
Joe Perches1d397f32010-11-29 07:41:57 +00004562 netdev_info(dev, "link down\n");
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004563 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4564 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4565 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4566 } else {
4567 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4568 if (pause->rx_pause)
4569 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4570 if (pause->tx_pause)
4571 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4572
4573 if (!netif_running(dev))
4574 nv_update_linkspeed(dev);
4575 else
4576 nv_update_pause(dev, np->pause_flags);
4577 }
4578
4579 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004580 nv_start_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004581 nv_enable_irq(dev);
4582 }
4583 return 0;
4584}
4585
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004586static u32 nv_get_rx_csum(struct net_device *dev)
4587{
4588 struct fe_priv *np = netdev_priv(dev);
Eric Dumazet807540b2010-09-23 05:40:09 +00004589 return np->rx_csum != 0;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004590}
4591
4592static int nv_set_rx_csum(struct net_device *dev, u32 data)
4593{
4594 struct fe_priv *np = netdev_priv(dev);
4595 u8 __iomem *base = get_hwbase(dev);
4596 int retcode = 0;
4597
4598 if (np->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004599 if (data) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004600 np->rx_csum = 1;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004601 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004602 } else {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004603 np->rx_csum = 0;
4604 /* vlan is dependent on rx checksum offload */
4605 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4606 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004607 }
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004608 if (netif_running(dev)) {
4609 spin_lock_irq(&np->lock);
4610 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4611 spin_unlock_irq(&np->lock);
4612 }
4613 } else {
4614 return -EINVAL;
4615 }
4616
4617 return retcode;
4618}
4619
4620static int nv_set_tx_csum(struct net_device *dev, u32 data)
4621{
4622 struct fe_priv *np = netdev_priv(dev);
4623
4624 if (np->driver_data & DEV_HAS_CHECKSUM)
Ayaz Abdullac1086cd2009-02-07 00:24:39 -08004625 return ethtool_op_set_tx_csum(dev, data);
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004626 else
4627 return -EOPNOTSUPP;
4628}
4629
4630static int nv_set_sg(struct net_device *dev, u32 data)
4631{
4632 struct fe_priv *np = netdev_priv(dev);
4633
4634 if (np->driver_data & DEV_HAS_CHECKSUM)
4635 return ethtool_op_set_sg(dev, data);
4636 else
4637 return -EOPNOTSUPP;
4638}
4639
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004640static int nv_get_sset_count(struct net_device *dev, int sset)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004641{
4642 struct fe_priv *np = netdev_priv(dev);
4643
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004644 switch (sset) {
4645 case ETH_SS_TEST:
4646 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4647 return NV_TEST_COUNT_EXTENDED;
4648 else
4649 return NV_TEST_COUNT_BASE;
4650 case ETH_SS_STATS:
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004651 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4652 return NV_DEV_STATISTICS_V3_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004653 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4654 return NV_DEV_STATISTICS_V2_COUNT;
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004655 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4656 return NV_DEV_STATISTICS_V1_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004657 else
4658 return 0;
4659 default:
4660 return -EOPNOTSUPP;
4661 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004662}
4663
4664static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4665{
4666 struct fe_priv *np = netdev_priv(dev);
4667
4668 /* update stats */
4669 nv_do_stats_poll((unsigned long)dev);
4670
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004671 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004672}
4673
4674static int nv_link_test(struct net_device *dev)
4675{
4676 struct fe_priv *np = netdev_priv(dev);
4677 int mii_status;
4678
4679 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4680 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4681
4682 /* check phy link status */
4683 if (!(mii_status & BMSR_LSTATUS))
4684 return 0;
4685 else
4686 return 1;
4687}
4688
4689static int nv_register_test(struct net_device *dev)
4690{
4691 u8 __iomem *base = get_hwbase(dev);
4692 int i = 0;
4693 u32 orig_read, new_read;
4694
4695 do {
4696 orig_read = readl(base + nv_registers_test[i].reg);
4697
4698 /* xor with mask to toggle bits */
4699 orig_read ^= nv_registers_test[i].mask;
4700
4701 writel(orig_read, base + nv_registers_test[i].reg);
4702
4703 new_read = readl(base + nv_registers_test[i].reg);
4704
4705 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4706 return 0;
4707
4708 /* restore original value */
4709 orig_read ^= nv_registers_test[i].mask;
4710 writel(orig_read, base + nv_registers_test[i].reg);
4711
4712 } while (nv_registers_test[++i].reg != 0);
4713
4714 return 1;
4715}
4716
4717static int nv_interrupt_test(struct net_device *dev)
4718{
4719 struct fe_priv *np = netdev_priv(dev);
4720 u8 __iomem *base = get_hwbase(dev);
4721 int ret = 1;
4722 int testcnt;
4723 u32 save_msi_flags, save_poll_interval = 0;
4724
4725 if (netif_running(dev)) {
4726 /* free current irq */
4727 nv_free_irq(dev);
4728 save_poll_interval = readl(base+NvRegPollingInterval);
4729 }
4730
4731 /* flag to test interrupt handler */
4732 np->intr_test = 0;
4733
4734 /* setup test irq */
4735 save_msi_flags = np->msi_flags;
4736 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4737 np->msi_flags |= 0x001; /* setup 1 vector */
4738 if (nv_request_irq(dev, 1))
4739 return 0;
4740
4741 /* setup timer interrupt */
4742 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4743 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4744
4745 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4746
4747 /* wait for at least one interrupt */
4748 msleep(100);
4749
4750 spin_lock_irq(&np->lock);
4751
4752 /* flag should be set within ISR */
4753 testcnt = np->intr_test;
4754 if (!testcnt)
4755 ret = 2;
4756
4757 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4758 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4759 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4760 else
4761 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4762
4763 spin_unlock_irq(&np->lock);
4764
4765 nv_free_irq(dev);
4766
4767 np->msi_flags = save_msi_flags;
4768
4769 if (netif_running(dev)) {
4770 writel(save_poll_interval, base + NvRegPollingInterval);
4771 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4772 /* restore original irq */
4773 if (nv_request_irq(dev, 0))
4774 return 0;
4775 }
4776
4777 return ret;
4778}
4779
4780static int nv_loopback_test(struct net_device *dev)
4781{
4782 struct fe_priv *np = netdev_priv(dev);
4783 u8 __iomem *base = get_hwbase(dev);
4784 struct sk_buff *tx_skb, *rx_skb;
4785 dma_addr_t test_dma_addr;
4786 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004787 u32 flags;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004788 int len, i, pkt_len;
4789 u8 *pkt_data;
4790 u32 filter_flags = 0;
4791 u32 misc1_flags = 0;
4792 int ret = 1;
4793
4794 if (netif_running(dev)) {
4795 nv_disable_irq(dev);
4796 filter_flags = readl(base + NvRegPacketFilterFlags);
4797 misc1_flags = readl(base + NvRegMisc1);
4798 } else {
4799 nv_txrx_reset(dev);
4800 }
4801
4802 /* reinit driver view of the rx queue */
4803 set_bufsize(dev);
4804 nv_init_ring(dev);
4805
4806 /* setup hardware for loopback */
4807 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4808 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4809
4810 /* reinit nic view of the rx queue */
4811 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4812 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004813 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004814 base + NvRegRingSizes);
4815 pci_push(base);
4816
4817 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004818 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004819
4820 /* setup packet for tx */
4821 pkt_len = ETH_DATA_LEN;
4822 tx_skb = dev_alloc_skb(pkt_len);
Jesper Juhl46798c82006-09-25 16:39:24 -07004823 if (!tx_skb) {
Joe Perches1d397f32010-11-29 07:41:57 +00004824 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
Jesper Juhl46798c82006-09-25 16:39:24 -07004825 ret = 0;
4826 goto out;
4827 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03004828 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4829 skb_tailroom(tx_skb),
4830 PCI_DMA_FROMDEVICE);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004831 pkt_data = skb_put(tx_skb, pkt_len);
4832 for (i = 0; i < pkt_len; i++)
4833 pkt_data[i] = (u8)(i & 0xff);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004834
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004835 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004836 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4837 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004838 } else {
Al Viro5bb7ea22007-12-09 16:06:41 +00004839 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4840 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004841 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004842 }
4843 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4844 pci_push(get_hwbase(dev));
4845
4846 msleep(500);
4847
4848 /* check for rx of the packet */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004849 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004850 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004851 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4852
4853 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004854 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004855 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4856 }
4857
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004858 if (flags & NV_RX_AVAIL) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004859 ret = 0;
4860 } else if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004861 if (flags & NV_RX_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004862 ret = 0;
4863 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004864 if (flags & NV_RX2_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004865 ret = 0;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004866 }
4867
4868 if (ret) {
4869 if (len != pkt_len) {
4870 ret = 0;
Joe Perches6b808582010-11-29 07:41:53 +00004871 netdev_dbg(dev, "loopback len mismatch %d vs %d\n",
4872 len, pkt_len);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004873 } else {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004874 rx_skb = np->rx_skb[0].skb;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004875 for (i = 0; i < pkt_len; i++) {
4876 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4877 ret = 0;
Joe Perches6b808582010-11-29 07:41:53 +00004878 netdev_dbg(dev, "loopback pattern check failed on byte %d\n",
4879 i);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004880 break;
4881 }
4882 }
4883 }
4884 } else {
Joe Perches6b808582010-11-29 07:41:53 +00004885 netdev_dbg(dev, "loopback - did not receive test packet\n");
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004886 }
4887
Eric Dumazet73a37072009-06-17 21:17:59 +00004888 pci_unmap_single(np->pci_dev, test_dma_addr,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07004889 (skb_end_pointer(tx_skb) - tx_skb->data),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004890 PCI_DMA_TODEVICE);
4891 dev_kfree_skb_any(tx_skb);
Jesper Juhl46798c82006-09-25 16:39:24 -07004892 out:
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004893 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004894 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004895 nv_txrx_reset(dev);
4896 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004897 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004898
4899 if (netif_running(dev)) {
4900 writel(misc1_flags, base + NvRegMisc1);
4901 writel(filter_flags, base + NvRegPacketFilterFlags);
4902 nv_enable_irq(dev);
4903 }
4904
4905 return ret;
4906}
4907
4908static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4909{
4910 struct fe_priv *np = netdev_priv(dev);
4911 u8 __iomem *base = get_hwbase(dev);
4912 int result;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004913 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004914
4915 if (!nv_link_test(dev)) {
4916 test->flags |= ETH_TEST_FL_FAILED;
4917 buffer[0] = 1;
4918 }
4919
4920 if (test->flags & ETH_TEST_FL_OFFLINE) {
4921 if (netif_running(dev)) {
4922 netif_stop_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004923 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004924 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004925 netif_addr_lock(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004926 spin_lock_irq(&np->lock);
4927 nv_disable_hw_interrupts(dev, np->irqmask);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004928 if (!(np->msi_flags & NV_MSI_X_ENABLED))
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004929 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004930 else
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004931 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004932 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004933 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004934 nv_txrx_reset(dev);
4935 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004936 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004937 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004938 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004939 netif_tx_unlock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004940 }
4941
4942 if (!nv_register_test(dev)) {
4943 test->flags |= ETH_TEST_FL_FAILED;
4944 buffer[1] = 1;
4945 }
4946
4947 result = nv_interrupt_test(dev);
4948 if (result != 1) {
4949 test->flags |= ETH_TEST_FL_FAILED;
4950 buffer[2] = 1;
4951 }
4952 if (result == 0) {
4953 /* bail out */
4954 return;
4955 }
4956
4957 if (!nv_loopback_test(dev)) {
4958 test->flags |= ETH_TEST_FL_FAILED;
4959 buffer[3] = 1;
4960 }
4961
4962 if (netif_running(dev)) {
4963 /* reinit driver view of the rx queue */
4964 set_bufsize(dev);
4965 if (nv_init_ring(dev)) {
4966 if (!np->in_shutdown)
4967 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4968 }
4969 /* reinit nic view of the rx queue */
4970 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4971 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004972 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004973 base + NvRegRingSizes);
4974 pci_push(base);
4975 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4976 pci_push(base);
4977 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004978 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004979 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004980 nv_napi_enable(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004981 nv_enable_hw_interrupts(dev, np->irqmask);
4982 }
4983 }
4984}
4985
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004986static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4987{
4988 switch (stringset) {
4989 case ETH_SS_STATS:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004990 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004991 break;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004992 case ETH_SS_TEST:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004993 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004994 break;
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004995 }
4996}
4997
Jeff Garzik7282d492006-09-13 14:30:00 -04004998static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004999 .get_drvinfo = nv_get_drvinfo,
5000 .get_link = ethtool_op_get_link,
5001 .get_wol = nv_get_wol,
5002 .set_wol = nv_set_wol,
5003 .get_settings = nv_get_settings,
5004 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005005 .get_regs_len = nv_get_regs_len,
5006 .get_regs = nv_get_regs,
5007 .nway_reset = nv_nway_reset,
Ayaz Abdulla6a788142006-06-10 22:47:26 -04005008 .set_tso = nv_set_tso,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005009 .get_ringparam = nv_get_ringparam,
5010 .set_ringparam = nv_set_ringparam,
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005011 .get_pauseparam = nv_get_pauseparam,
5012 .set_pauseparam = nv_set_pauseparam,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005013 .get_rx_csum = nv_get_rx_csum,
5014 .set_rx_csum = nv_set_rx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005015 .set_tx_csum = nv_set_tx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005016 .set_sg = nv_set_sg,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005017 .get_strings = nv_get_strings,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005018 .get_ethtool_stats = nv_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005019 .get_sset_count = nv_get_sset_count,
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005020 .self_test = nv_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005021};
5022
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005023static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5024{
5025 struct fe_priv *np = get_nvpriv(dev);
5026
5027 spin_lock_irq(&np->lock);
5028
5029 /* save vlan group */
5030 np->vlangrp = grp;
5031
5032 if (grp) {
5033 /* enable vlan on MAC */
5034 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5035 } else {
5036 /* disable vlan on MAC */
5037 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5038 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5039 }
5040
5041 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5042
5043 spin_unlock_irq(&np->lock);
Stephen Hemminger25805dc2007-06-01 09:44:01 -07005044}
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005045
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005046/* The mgmt unit and driver use a semaphore to access the phy during init */
5047static int nv_mgmt_acquire_sema(struct net_device *dev)
5048{
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005049 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005050 u8 __iomem *base = get_hwbase(dev);
5051 int i;
5052 u32 tx_ctrl, mgmt_sema;
5053
5054 for (i = 0; i < 10; i++) {
5055 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5056 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5057 break;
5058 msleep(500);
5059 }
5060
5061 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5062 return 0;
5063
5064 for (i = 0; i < 2; i++) {
5065 tx_ctrl = readl(base + NvRegTransmitterControl);
5066 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5067 writel(tx_ctrl, base + NvRegTransmitterControl);
5068
5069 /* verify that semaphore was acquired */
5070 tx_ctrl = readl(base + NvRegTransmitterControl);
5071 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005072 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5073 np->mgmt_sema = 1;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005074 return 1;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005075 } else
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005076 udelay(50);
5077 }
5078
5079 return 0;
5080}
5081
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005082static void nv_mgmt_release_sema(struct net_device *dev)
5083{
5084 struct fe_priv *np = netdev_priv(dev);
5085 u8 __iomem *base = get_hwbase(dev);
5086 u32 tx_ctrl;
5087
5088 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5089 if (np->mgmt_sema) {
5090 tx_ctrl = readl(base + NvRegTransmitterControl);
5091 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5092 writel(tx_ctrl, base + NvRegTransmitterControl);
5093 }
5094 }
5095}
5096
5097
5098static int nv_mgmt_get_version(struct net_device *dev)
5099{
5100 struct fe_priv *np = netdev_priv(dev);
5101 u8 __iomem *base = get_hwbase(dev);
5102 u32 data_ready = readl(base + NvRegTransmitterControl);
5103 u32 data_ready2 = 0;
5104 unsigned long start;
5105 int ready = 0;
5106
5107 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5108 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5109 start = jiffies;
5110 while (time_before(jiffies, start + 5*HZ)) {
5111 data_ready2 = readl(base + NvRegTransmitterControl);
5112 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5113 ready = 1;
5114 break;
5115 }
5116 schedule_timeout_uninterruptible(1);
5117 }
5118
5119 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5120 return 0;
5121
5122 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5123
5124 return 1;
5125}
5126
Linus Torvalds1da177e2005-04-16 15:20:36 -07005127static int nv_open(struct net_device *dev)
5128{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005129 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005130 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005131 int ret = 1;
5132 int oom, i;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005133 u32 low;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005134
Joe Perches6b808582010-11-29 07:41:53 +00005135 netdev_dbg(dev, "%s\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005136
Ed Swierkcb52deb2008-12-01 12:24:43 +00005137 /* power up phy */
5138 mii_rw(dev, np->phyaddr, MII_BMCR,
5139 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5140
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005141 nv_txrx_gate(dev, false);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005142 /* erase previous misconfiguration */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005143 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5144 nv_mac_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005145 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5146 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005147 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5148 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005149 writel(0, base + NvRegPacketFilterFlags);
5150
5151 writel(0, base + NvRegTransmitterControl);
5152 writel(0, base + NvRegReceiverControl);
5153
5154 writel(0, base + NvRegAdapterControl);
5155
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005156 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5157 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5158
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005159 /* initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02005160 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005161 oom = nv_init_ring(dev);
5162
5163 writel(0, base + NvRegLinkSpeed);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005164 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005165 nv_txrx_reset(dev);
5166 writel(0, base + NvRegUnknownSetupReg6);
5167
5168 np->in_shutdown = 0;
5169
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005170 /* give hw rings */
Ayaz Abdulla0832b252006-02-04 13:13:26 -05005171 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005172 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07005173 base + NvRegRingSizes);
5174
Linus Torvalds1da177e2005-04-16 15:20:36 -07005175 writel(np->linkspeed, base + NvRegLinkSpeed);
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04005176 if (np->desc_ver == DESC_VER_1)
5177 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5178 else
5179 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005180 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005181 writel(np->vlanctl_bits, base + NvRegVlanControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005182 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005183 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00005184 if (reg_delay(dev, NvRegUnknownSetupReg5,
5185 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5186 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
Joe Perches1d397f32010-11-29 07:41:57 +00005187 netdev_info(dev,
5188 "%s: SetupReg5, Bit 31 remained off\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005189
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005190 writel(0, base + NvRegMIIMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005191 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005192 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005193
Linus Torvalds1da177e2005-04-16 15:20:36 -07005194 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5195 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5196 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02005197 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005198
5199 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005200
5201 get_random_bytes(&low, sizeof(low));
5202 low &= NVREG_SLOTTIME_MASK;
5203 if (np->desc_ver == DESC_VER_1) {
5204 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5205 } else {
5206 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5207 /* setup legacy backoff */
5208 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5209 } else {
5210 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5211 nv_gear_backoff_reseed(dev);
5212 }
5213 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04005214 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5215 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005216 if (poll_interval == -1) {
5217 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5218 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5219 else
5220 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005221 } else
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005222 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005223 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5224 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5225 base + NvRegAdapterControl);
5226 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005227 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04005228 if (np->wolenabled)
5229 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005230
5231 i = readl(base + NvRegPowerState);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005232 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005233 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5234
5235 pci_push(base);
5236 udelay(10);
5237 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5238
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005239 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005240 pci_push(base);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005241 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005242 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5243 pci_push(base);
5244
Szymon Janc78aea4f2010-11-27 08:39:43 +00005245 if (nv_request_irq(dev, 0))
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005246 goto out_drain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005247
5248 /* ask for interrupts */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005249 nv_enable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005250
5251 spin_lock_irq(&np->lock);
5252 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5253 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005254 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5255 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005256 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5257 /* One manual link speed update: Interrupts are enabled, future link
5258 * speed changes cause interrupts and are handled by nv_link_irq().
5259 */
5260 {
5261 u32 miistat;
5262 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005263 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Joe Perchesf52dafc2010-11-29 07:41:55 +00005264 netdev_dbg(dev, "startup: got 0x%08x\n", miistat);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005265 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02005266 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5267 * to init hw */
5268 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005269 ret = nv_update_linkspeed(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005270 nv_start_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005271 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005272 nv_napi_enable(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005273
Linus Torvalds1da177e2005-04-16 15:20:36 -07005274 if (ret) {
5275 netif_carrier_on(dev);
5276 } else {
Joe Perches1d397f32010-11-29 07:41:57 +00005277 netdev_info(dev, "no link during initialization\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005278 netif_carrier_off(dev);
5279 }
5280 if (oom)
5281 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005282
5283 /* start statistics timer */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005284 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Daniel Drakebfebbb82008-03-18 11:07:18 +00005285 mod_timer(&np->stats_poll,
5286 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005287
Linus Torvalds1da177e2005-04-16 15:20:36 -07005288 spin_unlock_irq(&np->lock);
5289
5290 return 0;
5291out_drain:
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005292 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005293 return ret;
5294}
5295
5296static int nv_close(struct net_device *dev)
5297{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005298 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005299 u8 __iomem *base;
5300
5301 spin_lock_irq(&np->lock);
5302 np->in_shutdown = 1;
5303 spin_unlock_irq(&np->lock);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005304 nv_napi_disable(dev);
Manfred Spraula7475902007-10-17 21:52:33 +02005305 synchronize_irq(np->pci_dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005306
5307 del_timer_sync(&np->oom_kick);
5308 del_timer_sync(&np->nic_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005309 del_timer_sync(&np->stats_poll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005310
5311 netif_stop_queue(dev);
5312 spin_lock_irq(&np->lock);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005313 nv_stop_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005314 nv_txrx_reset(dev);
5315
5316 /* disable interrupts on the nic or we will lock up */
5317 base = get_hwbase(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005318 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005319 pci_push(base);
Joe Perchesf52dafc2010-11-29 07:41:55 +00005320 netdev_dbg(dev, "Irqmask is zero again\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005321
5322 spin_unlock_irq(&np->lock);
5323
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005324 nv_free_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005325
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005326 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005327
Ed Swierk5a9a8e32009-06-02 00:19:52 -07005328 if (np->wolenabled || !phy_power_down) {
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005329 nv_txrx_gate(dev, false);
Tim Mann2cc49a52007-06-14 13:16:38 -07005330 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005331 nv_start_rx(dev);
Ed Swierkcb52deb2008-12-01 12:24:43 +00005332 } else {
5333 /* power down phy */
5334 mii_rw(dev, np->phyaddr, MII_BMCR,
5335 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005336 nv_txrx_gate(dev, true);
Tim Mann2cc49a52007-06-14 13:16:38 -07005337 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005338
5339 /* FIXME: power down nic */
5340
5341 return 0;
5342}
5343
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005344static const struct net_device_ops nv_netdev_ops = {
5345 .ndo_open = nv_open,
5346 .ndo_stop = nv_close,
5347 .ndo_get_stats = nv_get_stats,
Stephen Hemminger00829822008-11-20 20:14:53 -08005348 .ndo_start_xmit = nv_start_xmit,
5349 .ndo_tx_timeout = nv_tx_timeout,
5350 .ndo_change_mtu = nv_change_mtu,
5351 .ndo_validate_addr = eth_validate_addr,
5352 .ndo_set_mac_address = nv_set_mac_address,
5353 .ndo_set_multicast_list = nv_set_multicast,
5354 .ndo_vlan_rx_register = nv_vlan_rx_register,
5355#ifdef CONFIG_NET_POLL_CONTROLLER
5356 .ndo_poll_controller = nv_poll_controller,
5357#endif
5358};
5359
5360static const struct net_device_ops nv_netdev_ops_optimized = {
5361 .ndo_open = nv_open,
5362 .ndo_stop = nv_close,
5363 .ndo_get_stats = nv_get_stats,
5364 .ndo_start_xmit = nv_start_xmit_optimized,
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005365 .ndo_tx_timeout = nv_tx_timeout,
5366 .ndo_change_mtu = nv_change_mtu,
5367 .ndo_validate_addr = eth_validate_addr,
5368 .ndo_set_mac_address = nv_set_mac_address,
5369 .ndo_set_multicast_list = nv_set_multicast,
5370 .ndo_vlan_rx_register = nv_vlan_rx_register,
5371#ifdef CONFIG_NET_POLL_CONTROLLER
5372 .ndo_poll_controller = nv_poll_controller,
5373#endif
5374};
5375
Linus Torvalds1da177e2005-04-16 15:20:36 -07005376static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5377{
5378 struct net_device *dev;
5379 struct fe_priv *np;
5380 unsigned long addr;
5381 u8 __iomem *base;
5382 int err, i;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005383 u32 powerstate, txreg;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005384 u32 phystate_orig = 0, phystate;
5385 int phyinitialized = 0;
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005386 static int printed_version;
5387
5388 if (!printed_version++)
Joe Perches294a5542010-11-29 07:41:56 +00005389 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5390 FORCEDETH_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005391
5392 dev = alloc_etherdev(sizeof(struct fe_priv));
5393 err = -ENOMEM;
5394 if (!dev)
5395 goto out;
5396
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005397 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005398 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005399 np->pci_dev = pci_dev;
5400 spin_lock_init(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005401 SET_NETDEV_DEV(dev, &pci_dev->dev);
5402
5403 init_timer(&np->oom_kick);
5404 np->oom_kick.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005405 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005406 init_timer(&np->nic_poll);
5407 np->nic_poll.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005408 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005409 init_timer(&np->stats_poll);
5410 np->stats_poll.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005411 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005412
5413 err = pci_enable_device(pci_dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005414 if (err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005415 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005416
5417 pci_set_master(pci_dev);
5418
5419 err = pci_request_regions(pci_dev, DRV_NAME);
5420 if (err < 0)
5421 goto out_disable;
5422
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005423 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005424 np->register_size = NV_PCI_REGSZ_VER3;
5425 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005426 np->register_size = NV_PCI_REGSZ_VER2;
5427 else
5428 np->register_size = NV_PCI_REGSZ_VER1;
5429
Linus Torvalds1da177e2005-04-16 15:20:36 -07005430 err = -EINVAL;
5431 addr = 0;
5432 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
Joe Perches6b808582010-11-29 07:41:53 +00005433 netdev_dbg(dev, "%s: resource %d start %p len %lld flags 0x%08lx\n",
5434 pci_name(pci_dev), i,
5435 (void *)(unsigned long)pci_resource_start(pci_dev, i),
5436 (long long)pci_resource_len(pci_dev, i),
5437 pci_resource_flags(pci_dev, i));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005438 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005439 pci_resource_len(pci_dev, i) >= np->register_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005440 addr = pci_resource_start(pci_dev, i);
5441 break;
5442 }
5443 }
5444 if (i == DEVICE_COUNT_RESOURCE) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005445 dev_printk(KERN_INFO, &pci_dev->dev,
5446 "Couldn't find register window\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005447 goto out_relreg;
5448 }
5449
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005450 /* copy of driver data */
5451 np->driver_data = id->driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005452 /* copy of device id */
5453 np->device_id = id->device;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005454
Linus Torvalds1da177e2005-04-16 15:20:36 -07005455 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02005456 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5457 /* packet format 3: supports 40-bit addressing */
5458 np->desc_ver = DESC_VER_3;
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005459 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005460 if (dma_64bit) {
Yang Hongyang6afd1422009-04-06 19:01:15 -07005461 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005462 dev_printk(KERN_INFO, &pci_dev->dev,
5463 "64-bit DMA failed, using 32-bit addressing\n");
5464 else
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005465 dev->features |= NETIF_F_HIGHDMA;
Yang Hongyang6afd1422009-04-06 19:01:15 -07005466 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005467 dev_printk(KERN_INFO, &pci_dev->dev,
5468 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005469 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005470 }
Manfred Spraulee733622005-07-31 18:32:26 +02005471 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5472 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005473 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005474 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02005475 } else {
5476 /* original packet format */
5477 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005478 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02005479 }
Manfred Spraulee733622005-07-31 18:32:26 +02005480
5481 np->pkt_limit = NV_PKTLIMIT_1;
5482 if (id->driver_data & DEV_HAS_LARGEDESC)
5483 np->pkt_limit = NV_PKTLIMIT_2;
5484
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005485 if (id->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04005486 np->rx_csum = 1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005487 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdullaedcfe5f2008-08-20 16:34:37 -07005488 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Ayaz Abdullafa454592006-01-05 22:45:45 -08005489 dev->features |= NETIF_F_TSO;
Tom Herbert53f224c2010-05-03 19:08:45 +00005490 dev->features |= NETIF_F_GRO;
Ayaz Abdulla21828162007-01-23 12:27:21 -05005491 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005492
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005493 np->vlanctl_bits = 0;
5494 if (id->driver_data & DEV_HAS_VLAN) {
5495 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5496 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005497 }
5498
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005499 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005500 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5501 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5502 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005503 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005504 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005505
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005506
Linus Torvalds1da177e2005-04-16 15:20:36 -07005507 err = -ENOMEM;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005508 np->base = ioremap(addr, np->register_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005509 if (!np->base)
5510 goto out_relreg;
5511 dev->base_addr = (unsigned long)np->base;
Manfred Spraulee733622005-07-31 18:32:26 +02005512
Linus Torvalds1da177e2005-04-16 15:20:36 -07005513 dev->irq = pci_dev->irq;
Manfred Spraulee733622005-07-31 18:32:26 +02005514
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005515 np->rx_ring_size = RX_RING_DEFAULT;
5516 np->tx_ring_size = TX_RING_DEFAULT;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005517
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005518 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02005519 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005520 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005521 &np->ring_addr);
5522 if (!np->rx_ring.orig)
5523 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005524 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005525 } else {
5526 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005527 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005528 &np->ring_addr);
5529 if (!np->rx_ring.ex)
5530 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005531 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005532 }
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07005533 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5534 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005535 if (!np->rx_skb || !np->tx_skb)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005536 goto out_freering;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005537
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005538 if (!nv_optimized(np))
Stephen Hemminger00829822008-11-20 20:14:53 -08005539 dev->netdev_ops = &nv_netdev_ops;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05005540 else
Stephen Hemminger00829822008-11-20 20:14:53 -08005541 dev->netdev_ops = &nv_netdev_ops_optimized;
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005542
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005543 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005544 SET_ETHTOOL_OPS(dev, &ops);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005545 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5546
5547 pci_set_drvdata(pci_dev, dev);
5548
5549 /* read the mac address */
5550 base = get_hwbase(dev);
5551 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5552 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5553
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005554 /* check the workaround bit for correct mac address order */
5555 txreg = readl(base + NvRegTransmitPoll);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005556 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005557 /* mac address is already in correct order */
5558 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5559 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5560 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5561 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5562 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5563 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005564 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5565 /* mac address is already in correct order */
5566 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5567 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5568 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5569 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5570 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5571 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5572 /*
5573 * Set orig mac address back to the reversed version.
5574 * This flag will be cleared during low power transition.
5575 * Therefore, we should always put back the reversed address.
5576 */
5577 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5578 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5579 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005580 } else {
5581 /* need to reverse mac address to correct order */
5582 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5583 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5584 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5585 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5586 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5587 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005588 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005589 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005590 }
John W. Linvillec704b852005-09-12 10:48:56 -04005591 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005592
John W. Linvillec704b852005-09-12 10:48:56 -04005593 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005594 /*
5595 * Bad mac address. At least one bios sets the mac address
5596 * to 01:23:45:67:89:ab
5597 */
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005598 dev_printk(KERN_ERR, &pci_dev->dev,
Johannes Berge1749612008-10-27 15:59:26 -07005599 "Invalid Mac address detected: %pM\n",
Szymon Janc78aea4f2010-11-27 08:39:43 +00005600 dev->dev_addr);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005601 dev_printk(KERN_ERR, &pci_dev->dev,
5602 "Please complain to your hardware vendor. Switching to a random MAC.\n");
Stanislav O. Bezzubtsev655a6592009-11-15 21:17:02 -08005603 random_ether_addr(dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005604 }
5605
Joe Perches6b808582010-11-29 07:41:53 +00005606 netdev_dbg(dev, "%s: MAC Address %pM\n",
5607 pci_name(pci_dev), dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005608
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005609 /* set mac address */
5610 nv_copy_mac_to_hw(dev);
5611
Tobias Diedrich9a60a822008-06-01 00:54:42 +02005612 /* Workaround current PCI init glitch: wakeup bits aren't
5613 * being set from PCI PM capability.
5614 */
5615 device_init_wakeup(&pci_dev->dev, 1);
5616
Linus Torvalds1da177e2005-04-16 15:20:36 -07005617 /* disable WOL */
5618 writel(0, base + NvRegWakeUpFlags);
5619 np->wolenabled = 0;
5620
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005621 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005622
5623 /* take phy and nic out of low power mode */
5624 powerstate = readl(base + NvRegPowerState2);
5625 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005626 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
Auke Kok44c10132007-06-08 15:46:36 -07005627 pci_dev->revision >= 0xA3)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005628 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5629 writel(powerstate, base + NvRegPowerState2);
5630 }
5631
Szymon Janc78aea4f2010-11-27 08:39:43 +00005632 if (np->desc_ver == DESC_VER_1)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005633 np->tx_flags = NV_TX_VALID;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005634 else
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005635 np->tx_flags = NV_TX2_VALID;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005636
5637 np->msi_flags = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005638 if ((id->driver_data & DEV_HAS_MSI) && msi)
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005639 np->msi_flags |= NV_MSI_CAPABLE;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005640
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005641 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5642 /* msix has had reported issues when modifying irqmask
5643 as in the case of napi, therefore, disable for now
5644 */
David S. Miller0a127612010-05-03 23:33:05 -07005645#if 0
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005646 np->msi_flags |= NV_MSI_X_CAPABLE;
5647#endif
5648 }
5649
5650 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005651 np->irqmask = NVREG_IRQMASK_CPU;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005652 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5653 np->msi_flags |= 0x0001;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005654 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5655 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5656 /* start off in throughput mode */
5657 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5658 /* remove support for msix mode */
5659 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5660 } else {
5661 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5662 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5663 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5664 np->msi_flags |= 0x0003;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005665 }
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005666
Linus Torvalds1da177e2005-04-16 15:20:36 -07005667 if (id->driver_data & DEV_NEED_TIMERIRQ)
5668 np->irqmask |= NVREG_IRQ_TIMER;
5669 if (id->driver_data & DEV_NEED_LINKTIMER) {
Joe Perchesf52dafc2010-11-29 07:41:55 +00005670 netdev_dbg(dev, "%s: link timer on\n", pci_name(pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005671 np->need_linktimer = 1;
5672 np->link_timeout = jiffies + LINK_TIMEOUT;
5673 } else {
Joe Perchesf52dafc2010-11-29 07:41:55 +00005674 netdev_dbg(dev, "%s: link timer off\n", pci_name(pci_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005675 np->need_linktimer = 0;
5676 }
5677
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005678 /* Limit the number of tx's outstanding for hw bug */
5679 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5680 np->tx_limit = 1;
Ayaz Abdulla5c659322010-04-13 18:49:51 -07005681 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005682 pci_dev->revision >= 0xA2)
5683 np->tx_limit = 0;
5684 }
5685
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005686 /* clear phy state and temporarily halt phy interrupts */
5687 writel(0, base + NvRegMIIMask);
5688 phystate = readl(base + NvRegAdapterControl);
5689 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5690 phystate_orig = 1;
5691 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5692 writel(phystate, base + NvRegAdapterControl);
5693 }
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005694 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005695
5696 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005697 /* management unit running on the mac? */
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005698 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5699 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5700 nv_mgmt_acquire_sema(dev) &&
5701 nv_mgmt_get_version(dev)) {
5702 np->mac_in_use = 1;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005703 if (np->mgmt_version > 0)
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005704 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
Joe Perchesf52dafc2010-11-29 07:41:55 +00005705 netdev_dbg(dev, "%s: mgmt unit is running. mac in use %x\n",
5706 pci_name(pci_dev), np->mac_in_use);
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005707 /* management unit setup the phy already? */
5708 if (np->mac_in_use &&
5709 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5710 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5711 /* phy is inited by mgmt unit */
5712 phyinitialized = 1;
Joe Perchesf52dafc2010-11-29 07:41:55 +00005713 netdev_dbg(dev, "%s: Phy already initialized by mgmt unit\n",
5714 pci_name(pci_dev));
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005715 } else {
5716 /* we need to init the phy */
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005717 }
5718 }
5719 }
5720
Linus Torvalds1da177e2005-04-16 15:20:36 -07005721 /* find a suitable phy */
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005722 for (i = 1; i <= 32; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005723 int id1, id2;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005724 int phyaddr = i & 0x1F;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005725
5726 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005727 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005728 spin_unlock_irq(&np->lock);
5729 if (id1 < 0 || id1 == 0xffff)
5730 continue;
5731 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005732 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005733 spin_unlock_irq(&np->lock);
5734 if (id2 < 0 || id2 == 0xffff)
5735 continue;
5736
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04005737 np->phy_model = id2 & PHYID2_MODEL_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005738 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5739 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
Joe Perches6b808582010-11-29 07:41:53 +00005740 netdev_dbg(dev, "%s: %s: Found PHY %04x:%04x at address %d\n",
5741 pci_name(pci_dev), __func__, id1, id2, phyaddr);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005742 np->phyaddr = phyaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005743 np->phy_oui = id1 | id2;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005744
5745 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5746 if (np->phy_oui == PHY_OUI_REALTEK2)
5747 np->phy_oui = PHY_OUI_REALTEK;
5748 /* Setup phy revision for Realtek */
5749 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5750 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5751
Linus Torvalds1da177e2005-04-16 15:20:36 -07005752 break;
5753 }
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005754 if (i == 33) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005755 dev_printk(KERN_INFO, &pci_dev->dev,
5756 "open: Could not find a valid PHY.\n");
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005757 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005758 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005759
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005760 if (!phyinitialized) {
5761 /* reset it */
5762 phy_init(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005763 } else {
5764 /* see if it is a gigabit phy */
5765 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005766 if (mii_status & PHY_GIGABIT)
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005767 np->gigabit = PHY_GIGABIT;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005768 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005769
5770 /* set default link speed settings */
5771 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5772 np->duplex = 0;
5773 np->autoneg = 1;
5774
5775 err = register_netdev(dev);
5776 if (err) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005777 dev_printk(KERN_INFO, &pci_dev->dev,
5778 "unable to register netdev: %d\n", err);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005779 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005780 }
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005781
5782 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5783 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5784 dev->name,
5785 np->phy_oui,
5786 np->phyaddr,
5787 dev->dev_addr[0],
5788 dev->dev_addr[1],
5789 dev->dev_addr[2],
5790 dev->dev_addr[3],
5791 dev->dev_addr[4],
5792 dev->dev_addr[5]);
5793
5794 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
Szymon Janc78aea4f2010-11-27 08:39:43 +00005795 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5796 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5797 "csum " : "",
5798 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5799 "vlan " : "",
5800 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5801 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5802 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5803 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5804 np->need_linktimer ? "lnktim " : "",
5805 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5806 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5807 np->desc_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005808
5809 return 0;
5810
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005811out_error:
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005812 if (phystate_orig)
5813 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005814 pci_set_drvdata(pci_dev, NULL);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005815out_freering:
5816 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005817out_unmap:
5818 iounmap(get_hwbase(dev));
5819out_relreg:
5820 pci_release_regions(pci_dev);
5821out_disable:
5822 pci_disable_device(pci_dev);
5823out_free:
5824 free_netdev(dev);
5825out:
5826 return err;
5827}
5828
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005829static void nv_restore_phy(struct net_device *dev)
5830{
5831 struct fe_priv *np = netdev_priv(dev);
5832 u16 phy_reserved, mii_control;
5833
5834 if (np->phy_oui == PHY_OUI_REALTEK &&
5835 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5836 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5837 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5838 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5839 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5840 phy_reserved |= PHY_REALTEK_INIT8;
5841 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5842 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5843
5844 /* restart auto negotiation */
5845 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5846 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5847 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5848 }
5849}
5850
Yinghai Luf55c21f2008-09-13 13:10:31 -07005851static void nv_restore_mac_addr(struct pci_dev *pci_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005852{
5853 struct net_device *dev = pci_get_drvdata(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005854 struct fe_priv *np = netdev_priv(dev);
5855 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005856
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005857 /* special op: write back the misordered MAC address - otherwise
5858 * the next nv_probe would see a wrong address.
5859 */
5860 writel(np->orig_mac[0], base + NvRegMacAddrA);
5861 writel(np->orig_mac[1], base + NvRegMacAddrB);
Björn Steinbrink2e3884b2008-01-07 23:22:53 -08005862 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5863 base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005864}
5865
5866static void __devexit nv_remove(struct pci_dev *pci_dev)
5867{
5868 struct net_device *dev = pci_get_drvdata(pci_dev);
5869
5870 unregister_netdev(dev);
5871
5872 nv_restore_mac_addr(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005873
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005874 /* restore any phy related changes */
5875 nv_restore_phy(dev);
5876
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005877 nv_mgmt_release_sema(dev);
5878
Linus Torvalds1da177e2005-04-16 15:20:36 -07005879 /* free all structures */
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005880 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005881 iounmap(get_hwbase(dev));
5882 pci_release_regions(pci_dev);
5883 pci_disable_device(pci_dev);
5884 free_netdev(dev);
5885 pci_set_drvdata(pci_dev, NULL);
5886}
5887
Francois Romieua1893172006-10-10 14:33:27 -07005888#ifdef CONFIG_PM
5889static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5890{
5891 struct net_device *dev = pci_get_drvdata(pdev);
5892 struct fe_priv *np = netdev_priv(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005893 u8 __iomem *base = get_hwbase(dev);
5894 int i;
Francois Romieua1893172006-10-10 14:33:27 -07005895
Tobias Diedrich25d90812008-05-18 15:04:29 +02005896 if (netif_running(dev)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00005897 /* Gross. */
Tobias Diedrich25d90812008-05-18 15:04:29 +02005898 nv_close(dev);
5899 }
Francois Romieua1893172006-10-10 14:33:27 -07005900 netif_device_detach(dev);
5901
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005902 /* save non-pci configuration space */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005903 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005904 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5905
Francois Romieua1893172006-10-10 14:33:27 -07005906 pci_save_state(pdev);
5907 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
Tobias Diedrich25d90812008-05-18 15:04:29 +02005908 pci_disable_device(pdev);
Francois Romieua1893172006-10-10 14:33:27 -07005909 pci_set_power_state(pdev, pci_choose_state(pdev, state));
Francois Romieua1893172006-10-10 14:33:27 -07005910 return 0;
5911}
5912
5913static int nv_resume(struct pci_dev *pdev)
5914{
5915 struct net_device *dev = pci_get_drvdata(pdev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005916 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005917 u8 __iomem *base = get_hwbase(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005918 int i, rc = 0;
Francois Romieua1893172006-10-10 14:33:27 -07005919
Francois Romieua1893172006-10-10 14:33:27 -07005920 pci_set_power_state(pdev, PCI_D0);
5921 pci_restore_state(pdev);
Tobias Diedrich25d90812008-05-18 15:04:29 +02005922 /* ack any pending wake events, disable PME */
Francois Romieua1893172006-10-10 14:33:27 -07005923 pci_enable_wake(pdev, PCI_D0, 0);
5924
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005925 /* restore non-pci configuration space */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005926 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005927 writel(np->saved_config_space[i], base+i*sizeof(u32));
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005928
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005929 if (np->driver_data & DEV_NEED_MSI_FIX)
5930 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
Ayaz Abdullab6e44052009-02-07 00:24:15 -08005931
Ed Swierk35a74332009-04-06 17:49:12 -07005932 /* restore phy state, including autoneg */
5933 phy_init(dev);
5934
Tobias Diedrich25d90812008-05-18 15:04:29 +02005935 netif_device_attach(dev);
5936 if (netif_running(dev)) {
5937 rc = nv_open(dev);
5938 nv_set_multicast(dev);
5939 }
Francois Romieua1893172006-10-10 14:33:27 -07005940 return rc;
5941}
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005942
5943static void nv_shutdown(struct pci_dev *pdev)
5944{
5945 struct net_device *dev = pci_get_drvdata(pdev);
5946 struct fe_priv *np = netdev_priv(dev);
5947
5948 if (netif_running(dev))
5949 nv_close(dev);
5950
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005951 /*
5952 * Restore the MAC so a kernel started by kexec won't get confused.
5953 * If we really go for poweroff, we must not restore the MAC,
5954 * otherwise the MAC for WOL will be reversed at least on some boards.
5955 */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005956 if (system_state != SYSTEM_POWER_OFF)
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005957 nv_restore_mac_addr(pdev);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005958
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005959 pci_disable_device(pdev);
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005960 /*
5961 * Apparently it is not possible to reinitialise from D3 hot,
5962 * only put the device into D3 if we really go for poweroff.
5963 */
Rafael J. Wysocki3cb55992008-09-05 14:00:19 -07005964 if (system_state == SYSTEM_POWER_OFF) {
5965 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
5966 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
5967 pci_set_power_state(pdev, PCI_D3hot);
5968 }
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005969}
Francois Romieua1893172006-10-10 14:33:27 -07005970#else
5971#define nv_suspend NULL
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005972#define nv_shutdown NULL
Francois Romieua1893172006-10-10 14:33:27 -07005973#define nv_resume NULL
5974#endif /* CONFIG_PM */
5975
Alexey Dobriyana3aa1882010-01-07 11:58:11 +00005976static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005977 { /* nForce Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005978 PCI_DEVICE(0x10DE, 0x01C3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005979 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005980 },
5981 { /* nForce2 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005982 PCI_DEVICE(0x10DE, 0x0066),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005983 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005984 },
5985 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005986 PCI_DEVICE(0x10DE, 0x00D6),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005987 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005988 },
5989 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005990 PCI_DEVICE(0x10DE, 0x0086),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005991 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005992 },
5993 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005994 PCI_DEVICE(0x10DE, 0x008C),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005995 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005996 },
5997 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005998 PCI_DEVICE(0x10DE, 0x00E6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005999 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006000 },
6001 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006002 PCI_DEVICE(0x10DE, 0x00DF),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006003 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006004 },
6005 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006006 PCI_DEVICE(0x10DE, 0x0056),
Yinghai Lu033e97b2009-02-06 01:30:56 -08006007 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006008 },
6009 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006010 PCI_DEVICE(0x10DE, 0x0057),
Yinghai Lu033e97b2009-02-06 01:30:56 -08006011 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006012 },
6013 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006014 PCI_DEVICE(0x10DE, 0x0037),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006015 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006016 },
6017 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006018 PCI_DEVICE(0x10DE, 0x0038),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006019 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006020 },
6021 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006022 PCI_DEVICE(0x10DE, 0x0268),
6023 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006024 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006025 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006026 PCI_DEVICE(0x10DE, 0x0269),
6027 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006028 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006029 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006030 PCI_DEVICE(0x10DE, 0x0372),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006031 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006032 },
6033 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006034 PCI_DEVICE(0x10DE, 0x0373),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006035 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006036 },
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006037 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006038 PCI_DEVICE(0x10DE, 0x03E5),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006039 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006040 },
6041 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006042 PCI_DEVICE(0x10DE, 0x03E6),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006043 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006044 },
6045 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006046 PCI_DEVICE(0x10DE, 0x03EE),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006047 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006048 },
6049 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006050 PCI_DEVICE(0x10DE, 0x03EF),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006051 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006052 },
6053 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006054 PCI_DEVICE(0x10DE, 0x0450),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006055 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006056 },
6057 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006058 PCI_DEVICE(0x10DE, 0x0451),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006059 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006060 },
6061 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006062 PCI_DEVICE(0x10DE, 0x0452),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006063 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006064 },
6065 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006066 PCI_DEVICE(0x10DE, 0x0453),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006067 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006068 },
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006069 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006070 PCI_DEVICE(0x10DE, 0x054C),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006071 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006072 },
6073 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006074 PCI_DEVICE(0x10DE, 0x054D),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006075 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006076 },
6077 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006078 PCI_DEVICE(0x10DE, 0x054E),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006079 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006080 },
6081 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006082 PCI_DEVICE(0x10DE, 0x054F),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006083 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006084 },
Ayaz Abdulla13986612007-07-22 20:43:26 -04006085 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006086 PCI_DEVICE(0x10DE, 0x07DC),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006087 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006088 },
6089 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006090 PCI_DEVICE(0x10DE, 0x07DD),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006091 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006092 },
6093 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006094 PCI_DEVICE(0x10DE, 0x07DE),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006095 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006096 },
6097 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006098 PCI_DEVICE(0x10DE, 0x07DF),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006099 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006100 },
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006101 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006102 PCI_DEVICE(0x10DE, 0x0760),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006103 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006104 },
6105 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006106 PCI_DEVICE(0x10DE, 0x0761),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006107 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006108 },
6109 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006110 PCI_DEVICE(0x10DE, 0x0762),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006111 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006112 },
6113 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006114 PCI_DEVICE(0x10DE, 0x0763),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006115 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006116 },
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006117 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006118 PCI_DEVICE(0x10DE, 0x0AB0),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006119 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006120 },
6121 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006122 PCI_DEVICE(0x10DE, 0x0AB1),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006123 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006124 },
6125 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006126 PCI_DEVICE(0x10DE, 0x0AB2),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006127 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006128 },
6129 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006130 PCI_DEVICE(0x10DE, 0x0AB3),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006131 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006132 },
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00006133 { /* MCP89 Ethernet Controller */
6134 PCI_DEVICE(0x10DE, 0x0D7D),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006135 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00006136 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07006137 {0,},
6138};
6139
6140static struct pci_driver driver = {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006141 .name = DRV_NAME,
6142 .id_table = pci_tbl,
6143 .probe = nv_probe,
6144 .remove = __devexit_p(nv_remove),
6145 .suspend = nv_suspend,
6146 .resume = nv_resume,
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006147 .shutdown = nv_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006148};
6149
Linus Torvalds1da177e2005-04-16 15:20:36 -07006150static int __init init_nic(void)
6151{
Jeff Garzik29917622006-08-19 17:48:59 -04006152 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006153}
6154
6155static void __exit exit_nic(void)
6156{
6157 pci_unregister_driver(&driver);
6158}
6159
6160module_param(max_interrupt_work, int, 0);
6161MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006162module_param(optimization_mode, int, 0);
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006163MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006164module_param(poll_interval, int, 0);
6165MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04006166module_param(msi, int, 0);
6167MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6168module_param(msix, int, 0);
6169MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6170module_param(dma_64bit, int, 0);
6171MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006172module_param(phy_cross, int, 0);
6173MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
Ed Swierk5a9a8e32009-06-02 00:19:52 -07006174module_param(phy_power_down, int, 0);
6175MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
Linus Torvalds1da177e2005-04-16 15:20:36 -07006176
6177MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6178MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6179MODULE_LICENSE("GPL");
6180
6181MODULE_DEVICE_TABLE(pci, pci_tbl);
6182
6183module_init(init_nic);
6184module_exit(exit_nic);