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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/mtd/nand/rtc_from4.c
3 *
4 * Copyright (C) 2004 Red Hat, Inc.
Thomas Gleixner61b03bd2005-11-07 11:15:49 +00005 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * Derived from drivers/mtd/nand/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
8 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +00009 * $Id: rtc_from4.c,v 1.10 2005/11/07 11:14:31 gleixner Exp $
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * Overview:
16 * This is a device driver for the AG-AND flash device found on the
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000017 * Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4),
18 * which utilizes the Renesas HN29V1G91T-30 part.
Linus Torvalds1da177e2005-04-16 15:20:36 -070019 * This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device.
20 */
21
22#include <linux/delay.h>
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/slab.h>
26#include <linux/rslib.h>
27#include <linux/module.h>
28#include <linux/mtd/compatmac.h>
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/nand.h>
31#include <linux/mtd/partitions.h>
32#include <asm/io.h>
33
34/*
35 * MTD structure for Renesas board
36 */
37static struct mtd_info *rtc_from4_mtd = NULL;
38
39#define RTC_FROM4_MAX_CHIPS 2
40
41/* HS77x9 processor register defines */
42#define SH77X9_BCR1 ((volatile unsigned short *)(0xFFFFFF60))
43#define SH77X9_BCR2 ((volatile unsigned short *)(0xFFFFFF62))
44#define SH77X9_WCR1 ((volatile unsigned short *)(0xFFFFFF64))
45#define SH77X9_WCR2 ((volatile unsigned short *)(0xFFFFFF66))
46#define SH77X9_MCR ((volatile unsigned short *)(0xFFFFFF68))
47#define SH77X9_PCR ((volatile unsigned short *)(0xFFFFFF6C))
48#define SH77X9_FRQCR ((volatile unsigned short *)(0xFFFFFF80))
49
50/*
51 * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor)
52 */
53/* Address where flash is mapped */
54#define RTC_FROM4_FIO_BASE 0x14000000
55
56/* CLE and ALE are tied to address lines 5 & 4, respectively */
57#define RTC_FROM4_CLE (1 << 5)
58#define RTC_FROM4_ALE (1 << 4)
59
60/* address lines A24-A22 used for chip selection */
61#define RTC_FROM4_NAND_ADDR_SLOT3 (0x00800000)
62#define RTC_FROM4_NAND_ADDR_SLOT4 (0x00C00000)
63#define RTC_FROM4_NAND_ADDR_FPGA (0x01000000)
64/* mask address lines A24-A22 used for chip selection */
65#define RTC_FROM4_NAND_ADDR_MASK (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)
66
67/* FPGA status register for checking device ready (bit zero) */
68#define RTC_FROM4_FPGA_SR (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)
69#define RTC_FROM4_DEVICE_READY 0x0001
70
71/* FPGA Reed-Solomon ECC Control register */
72
73#define RTC_FROM4_RS_ECC_CTL (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)
74#define RTC_FROM4_RS_ECC_CTL_CLR (1 << 7)
75#define RTC_FROM4_RS_ECC_CTL_GEN (1 << 6)
76#define RTC_FROM4_RS_ECC_CTL_FD_E (1 << 5)
77
78/* FPGA Reed-Solomon ECC code base */
79#define RTC_FROM4_RS_ECC (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)
80#define RTC_FROM4_RS_ECCN (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)
81
82/* FPGA Reed-Solomon ECC check register */
83#define RTC_FROM4_RS_ECC_CHK (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
84#define RTC_FROM4_RS_ECC_CHK_ERROR (1 << 7)
85
David A. Marlined3786a2005-01-24 20:40:15 +000086#define ERR_STAT_ECC_AVAILABLE 0x20
87
Linus Torvalds1da177e2005-04-16 15:20:36 -070088/* Undefine for software ECC */
89#define RTC_FROM4_HWECC 1
90
David A. Marlined3786a2005-01-24 20:40:15 +000091/* Define as 1 for no virtual erase blocks (in JFFS2) */
92#define RTC_FROM4_NO_VIRTBLOCKS 0
93
Linus Torvalds1da177e2005-04-16 15:20:36 -070094/*
95 * Module stuff
96 */
David A. Marlin97f1a082005-01-17 19:44:39 +000097static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
Jesper Juhl3c6bee12006-01-09 20:54:01 -080099static const struct mtd_partition partition_info[] = {
David Woodhousee0c7d762006-05-13 18:07:53 +0100100 {
101 .name = "Renesas flash partition 1",
102 .offset = 0,
103 .size = MTDPART_SIZ_FULL},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104};
David Woodhousee0c7d762006-05-13 18:07:53 +0100105
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106#define NUM_PARTITIONS 1
107
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000108/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 * hardware specific flash bbt decriptors
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000110 * Note: this is to allow debugging by disabling
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 * NAND_BBT_CREATE and/or NAND_BBT_WRITE
112 *
113 */
David Woodhousee0c7d762006-05-13 18:07:53 +0100114static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
115static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116
117static struct nand_bbt_descr rtc_from4_bbt_main_descr = {
118 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
119 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
120 .offs = 40,
121 .len = 4,
122 .veroffs = 44,
123 .maxblocks = 4,
124 .pattern = bbt_pattern
125};
126
127static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {
128 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
129 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
130 .offs = 40,
131 .len = 4,
132 .veroffs = 44,
133 .maxblocks = 4,
134 .pattern = mirror_pattern
135};
136
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137#ifdef RTC_FROM4_HWECC
138
139/* the Reed Solomon control structure */
140static struct rs_control *rs_decoder;
141
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000142/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 * hardware specific Out Of Band information
144 */
145static struct nand_oobinfo rtc_from4_nand_oobinfo = {
146 .useecc = MTD_NANDECC_AUTOPLACE,
147 .eccbytes = 32,
148 .eccpos = {
David Woodhousee0c7d762006-05-13 18:07:53 +0100149 0, 1, 2, 3, 4, 5, 6, 7,
150 8, 9, 10, 11, 12, 13, 14, 15,
151 16, 17, 18, 19, 20, 21, 22, 23,
152 24, 25, 26, 27, 28, 29, 30, 31},
153 .oobfree = {{32, 32}}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154};
155
156/* Aargh. I missed the reversed bit order, when I
157 * was talking to Renesas about the FPGA.
158 *
159 * The table is used for bit reordering and inversion
160 * of the ecc byte which we get from the FPGA
161 */
162static uint8_t revbits[256] = {
David Woodhousee0c7d762006-05-13 18:07:53 +0100163 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
164 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
165 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
166 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
167 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
168 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
169 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
170 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
171 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
172 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
173 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
174 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
175 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
176 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
177 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
178 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
179 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
180 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
181 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
182 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
183 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
184 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
185 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
186 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
187 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
188 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
189 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
190 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
191 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
192 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
193 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
194 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195};
196
197#endif
198
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000199/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 * rtc_from4_hwcontrol - hardware specific access to control-lines
201 * @mtd: MTD device structure
202 * @cmd: hardware control command
203 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000204 * Address lines (A5 and A4) are used to control Command and Address Latch
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205 * Enable on this board, so set the read/write address appropriately.
206 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000207 * Chip Enable is also controlled by the Chip Select (CS5) and
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208 * Address lines (A24-A22), so no action is required here.
209 *
210 */
211static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd)
212{
David Woodhousee0c7d762006-05-13 18:07:53 +0100213 struct nand_chip *this = (struct nand_chip *)(mtd->priv);
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000214
David Woodhousee0c7d762006-05-13 18:07:53 +0100215 switch (cmd) {
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000216
217 case NAND_CTL_SETCLE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_CLE);
219 break;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000220 case NAND_CTL_CLRCLE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_CLE);
222 break;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000223
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 case NAND_CTL_SETALE:
225 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_ALE);
226 break;
227 case NAND_CTL_CLRALE:
228 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_ALE);
229 break;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000230
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 case NAND_CTL_SETNCE:
232 break;
233 case NAND_CTL_CLRNCE:
234 break;
235
236 }
237}
238
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239/*
240 * rtc_from4_nand_select_chip - hardware specific chip select
241 * @mtd: MTD device structure
242 * @chip: Chip to select (0 == slot 3, 1 == slot 4)
243 *
244 * The chip select is based on address lines A24-A22.
245 * This driver uses flash slots 3 and 4 (A23-A22).
246 *
247 */
248static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip)
249{
David Woodhousee0c7d762006-05-13 18:07:53 +0100250 struct nand_chip *this = mtd->priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251
252 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);
253 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);
254
David Woodhousee0c7d762006-05-13 18:07:53 +0100255 switch (chip) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256
David Woodhousee0c7d762006-05-13 18:07:53 +0100257 case 0: /* select slot 3 chip */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);
259 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);
David Woodhousee0c7d762006-05-13 18:07:53 +0100260 break;
261 case 1: /* select slot 4 chip */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);
263 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);
David Woodhousee0c7d762006-05-13 18:07:53 +0100264 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
David Woodhousee0c7d762006-05-13 18:07:53 +0100266 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267}
268
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269/*
270 * rtc_from4_nand_device_ready - hardware specific ready/busy check
271 * @mtd: MTD device structure
272 *
273 * This board provides the Ready/Busy state in the status register
274 * of the FPGA. Bit zero indicates the RDY(1)/BSY(0) signal.
275 *
276 */
277static int rtc_from4_nand_device_ready(struct mtd_info *mtd)
278{
279 unsigned short status;
280
281 status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));
282
283 return (status & RTC_FROM4_DEVICE_READY);
284
285}
286
David A. Marlin97f1a082005-01-17 19:44:39 +0000287/*
288 * deplete - code to perform device recovery in case there was a power loss
289 * @mtd: MTD device structure
290 * @chip: Chip to select (0 == slot 3, 1 == slot 4)
291 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000292 * If there was a sudden loss of power during an erase operation, a
David A. Marlin97f1a082005-01-17 19:44:39 +0000293 * "device recovery" operation must be performed when power is restored
294 * to ensure correct operation. This routine performs the required steps
295 * for the requested chip.
296 *
297 * See page 86 of the data sheet for details.
298 *
299 */
300static void deplete(struct mtd_info *mtd, int chip)
301{
David Woodhousee0c7d762006-05-13 18:07:53 +0100302 struct nand_chip *this = mtd->priv;
David A. Marlin97f1a082005-01-17 19:44:39 +0000303
David Woodhousee0c7d762006-05-13 18:07:53 +0100304 /* wait until device is ready */
305 while (!this->dev_ready(mtd)) ;
David A. Marlin97f1a082005-01-17 19:44:39 +0000306
307 this->select_chip(mtd, chip);
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000308
David A. Marlin97f1a082005-01-17 19:44:39 +0000309 /* Send the commands for device recovery, phase 1 */
David Woodhousee0c7d762006-05-13 18:07:53 +0100310 this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000);
311 this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
David A. Marlin97f1a082005-01-17 19:44:39 +0000312
313 /* Send the commands for device recovery, phase 2 */
David Woodhousee0c7d762006-05-13 18:07:53 +0100314 this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004);
315 this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
David A. Marlin97f1a082005-01-17 19:44:39 +0000316
317}
318
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319#ifdef RTC_FROM4_HWECC
320/*
321 * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function
322 * @mtd: MTD device structure
323 * @mode: I/O mode; read or write
324 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000325 * enable hardware ECC for data read or write
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 *
327 */
328static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode)
329{
David Woodhousee0c7d762006-05-13 18:07:53 +0100330 volatile unsigned short *rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331 unsigned short status;
332
333 switch (mode) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100334 case NAND_ECC_READ:
335 status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_FD_E;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336
337 *rs_ecc_ctl = status;
338 break;
339
David Woodhousee0c7d762006-05-13 18:07:53 +0100340 case NAND_ECC_READSYN:
341 status = 0x00;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342
343 *rs_ecc_ctl = status;
344 break;
345
David Woodhousee0c7d762006-05-13 18:07:53 +0100346 case NAND_ECC_WRITE:
347 status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_GEN | RTC_FROM4_RS_ECC_CTL_FD_E;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348
349 *rs_ecc_ctl = status;
350 break;
351
David Woodhousee0c7d762006-05-13 18:07:53 +0100352 default:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 BUG();
354 break;
355 }
356
357}
358
359/*
360 * rtc_from4_calculate_ecc - hardware specific code to read ECC code
361 * @mtd: MTD device structure
362 * @dat: buffer containing the data to generate ECC codes
363 * @ecc_code ECC codes calculated
364 *
365 * The ECC code is calculated by the FPGA. All we have to do is read the values
366 * from the FPGA registers.
367 *
368 * Note: We read from the inverted registers, since data is inverted before
369 * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code
370 *
371 */
372static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
373{
David Woodhousee0c7d762006-05-13 18:07:53 +0100374 volatile unsigned short *rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375 unsigned short value;
376 int i;
377
378 for (i = 0; i < 8; i++) {
379 value = *rs_eccn;
380 ecc_code[i] = (unsigned char)value;
381 rs_eccn++;
382 }
383 ecc_code[7] |= 0x0f; /* set the last four bits (not used) */
384}
385
386/*
387 * rtc_from4_correct_data - hardware specific code to correct data using ECC code
388 * @mtd: MTD device structure
389 * @buf: buffer containing the data to generate ECC codes
390 * @ecc1 ECC codes read
391 * @ecc2 ECC codes calculated
392 *
393 * The FPGA tells us fast, if there's an error or not. If no, we go back happy
394 * else we read the ecc results from the fpga and call the rs library to decode
David A. Marlined3786a2005-01-24 20:40:15 +0000395 * and hopefully correct the error.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397 */
398static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2)
399{
400 int i, j, res;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000401 unsigned short status;
David A. Marlin97f1a082005-01-17 19:44:39 +0000402 uint16_t par[6], syn[6];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 uint8_t ecc[8];
David Woodhousee0c7d762006-05-13 18:07:53 +0100404 volatile unsigned short *rs_ecc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405
406 status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));
407
408 if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) {
409 return 0;
410 }
411
412 /* Read the syndrom pattern from the FPGA and correct the bitorder */
413 rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
David Woodhousee0c7d762006-05-13 18:07:53 +0100414 for (i = 0; i < 8; i++) {
415 ecc[i] = revbits[(*rs_ecc) & 0xFF];
416 rs_ecc++;
417 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418
419 /* convert into 6 10bit syndrome fields */
David Woodhousee0c7d762006-05-13 18:07:53 +0100420 par[5] = rs_decoder->index_of[(((uint16_t) ecc[0] >> 0) & 0x0ff) | (((uint16_t) ecc[1] << 8) & 0x300)];
421 par[4] = rs_decoder->index_of[(((uint16_t) ecc[1] >> 2) & 0x03f) | (((uint16_t) ecc[2] << 6) & 0x3c0)];
422 par[3] = rs_decoder->index_of[(((uint16_t) ecc[2] >> 4) & 0x00f) | (((uint16_t) ecc[3] << 4) & 0x3f0)];
423 par[2] = rs_decoder->index_of[(((uint16_t) ecc[3] >> 6) & 0x003) | (((uint16_t) ecc[4] << 2) & 0x3fc)];
424 par[1] = rs_decoder->index_of[(((uint16_t) ecc[5] >> 0) & 0x0ff) | (((uint16_t) ecc[6] << 8) & 0x300)];
425 par[0] = (((uint16_t) ecc[6] >> 2) & 0x03f) | (((uint16_t) ecc[7] << 6) & 0x3c0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426
427 /* Convert to computable syndrome */
428 for (i = 0; i < 6; i++) {
429 syn[i] = par[0];
430 for (j = 1; j < 6; j++)
431 if (par[j] != rs_decoder->nn)
432 syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)];
433
434 /* Convert to index form */
435 syn[i] = rs_decoder->index_of[syn[i]];
436 }
437
David Woodhousee0c7d762006-05-13 18:07:53 +0100438 /* Let the library code do its magic. */
439 res = decode_rs8(rs_decoder, (uint8_t *) buf, par, 512, syn, 0, NULL, 0xff, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440 if (res > 0) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100441 DEBUG(MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: " "ECC corrected %d errors on read\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 }
443 return res;
444}
David A. Marlined3786a2005-01-24 20:40:15 +0000445
David A. Marlined3786a2005-01-24 20:40:15 +0000446/**
447 * rtc_from4_errstat - perform additional error status checks
448 * @mtd: MTD device structure
449 * @this: NAND chip structure
450 * @state: state or the operation
451 * @status: status code returned from read status
452 * @page: startpage inside the chip, must be called with (page & this->pagemask)
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000453 *
454 * Perform additional error status checks on erase and write failures
455 * to determine if errors are correctable. For this device, correctable
David A. Marlined3786a2005-01-24 20:40:15 +0000456 * 1-bit errors on erase and write are considered acceptable.
457 *
458 * note: see pages 34..37 of data sheet for details.
459 *
460 */
461static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page)
462{
David Woodhousee0c7d762006-05-13 18:07:53 +0100463 int er_stat = 0;
464 int rtn, retlen;
465 size_t len;
David A. Marlined3786a2005-01-24 20:40:15 +0000466 uint8_t *buf;
David Woodhousee0c7d762006-05-13 18:07:53 +0100467 int i;
David A. Marlined3786a2005-01-24 20:40:15 +0000468
David Woodhousee0c7d762006-05-13 18:07:53 +0100469 this->cmdfunc(mtd, NAND_CMD_STATUS_CLEAR, -1, -1);
David A. Marlined3786a2005-01-24 20:40:15 +0000470
David Woodhousee0c7d762006-05-13 18:07:53 +0100471 if (state == FL_ERASING) {
472 for (i = 0; i < 4; i++) {
473 if (status & 1 << (i + 1)) {
474 this->cmdfunc(mtd, (NAND_CMD_STATUS_ERROR + i + 1), -1, -1);
David A. Marlined3786a2005-01-24 20:40:15 +0000475 rtn = this->read_byte(mtd);
David Woodhousee0c7d762006-05-13 18:07:53 +0100476 this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
David A. Marlined3786a2005-01-24 20:40:15 +0000477 if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100478 er_stat |= 1 << (i + 1); /* err_ecc_not_avail */
David A. Marlined3786a2005-01-24 20:40:15 +0000479 }
480 }
481 }
482 } else if (state == FL_WRITING) {
483 /* single bank write logic */
David Woodhousee0c7d762006-05-13 18:07:53 +0100484 this->cmdfunc(mtd, NAND_CMD_STATUS_ERROR, -1, -1);
David A. Marlined3786a2005-01-24 20:40:15 +0000485 rtn = this->read_byte(mtd);
David Woodhousee0c7d762006-05-13 18:07:53 +0100486 this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
David A. Marlined3786a2005-01-24 20:40:15 +0000487 if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100488 er_stat |= 1 << 1; /* err_ecc_not_avail */
David A. Marlined3786a2005-01-24 20:40:15 +0000489 } else {
490 len = mtd->oobblock;
David Woodhousee0c7d762006-05-13 18:07:53 +0100491 buf = kmalloc(len, GFP_KERNEL);
David A. Marlined3786a2005-01-24 20:40:15 +0000492 if (!buf) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100493 printk(KERN_ERR "rtc_from4_errstat: Out of memory!\n");
494 er_stat = 1; /* if we can't check, assume failed */
David A. Marlined3786a2005-01-24 20:40:15 +0000495 } else {
496 /* recovery read */
497 /* page read */
David Woodhousee0c7d762006-05-13 18:07:53 +0100498 rtn = nand_do_read_ecc(mtd, page, len, &retlen, buf, NULL, this->autooob, 1);
David A. Marlined3786a2005-01-24 20:40:15 +0000499 if (rtn) { /* if read failed or > 1-bit error corrected */
David Woodhousee0c7d762006-05-13 18:07:53 +0100500 er_stat |= 1 << 1; /* ECC read failed */
David A. Marlined3786a2005-01-24 20:40:15 +0000501 }
502 kfree(buf);
503 }
504 }
505 }
506
507 rtn = status;
David Woodhousee0c7d762006-05-13 18:07:53 +0100508 if (er_stat == 0) { /* if ECC is available */
David A. Marlined3786a2005-01-24 20:40:15 +0000509 rtn = (status & ~NAND_STATUS_FAIL); /* clear the error bit */
510 }
511
512 return rtn;
513}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514#endif
515
516/*
517 * Main initialization routine
518 */
David Woodhousee0c7d762006-05-13 18:07:53 +0100519int __init rtc_from4_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520{
521 struct nand_chip *this;
522 unsigned short bcr1, bcr2, wcr2;
David A. Marlin97f1a082005-01-17 19:44:39 +0000523 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524
525 /* Allocate memory for MTD device structure and private data */
David Woodhousee0c7d762006-05-13 18:07:53 +0100526 rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 if (!rtc_from4_mtd) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100528 printk("Unable to allocate Renesas NAND MTD device structure.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529 return -ENOMEM;
530 }
531
532 /* Get pointer to private data */
David Woodhousee0c7d762006-05-13 18:07:53 +0100533 this = (struct nand_chip *)(&rtc_from4_mtd[1]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534
535 /* Initialize structures */
David Woodhousee0c7d762006-05-13 18:07:53 +0100536 memset(rtc_from4_mtd, 0, sizeof(struct mtd_info));
537 memset(this, 0, sizeof(struct nand_chip));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
539 /* Link the private data with the MTD structure */
540 rtc_from4_mtd->priv = this;
David Woodhouse552d9202006-05-14 01:20:46 +0100541 rtc_from4_mtd->owner = THIS_MODULE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542
543 /* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */
544 bcr1 = *SH77X9_BCR1 & ~0x0002;
545 bcr1 |= 0x0002;
546 *SH77X9_BCR1 = bcr1;
547
548 /* set */
549 bcr2 = *SH77X9_BCR2 & ~0x0c00;
550 bcr2 |= 0x0800;
551 *SH77X9_BCR2 = bcr2;
552
553 /* set area 5 wait states */
554 wcr2 = *SH77X9_WCR2 & ~0x1c00;
555 wcr2 |= 0x1c00;
556 *SH77X9_WCR2 = wcr2;
557
558 /* Set address of NAND IO lines */
559 this->IO_ADDR_R = rtc_from4_fio_base;
560 this->IO_ADDR_W = rtc_from4_fio_base;
561 /* Set address of hardware control function */
562 this->hwcontrol = rtc_from4_hwcontrol;
563 /* Set address of chip select function */
David Woodhousee0c7d762006-05-13 18:07:53 +0100564 this->select_chip = rtc_from4_nand_select_chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 /* command delay time (in us) */
566 this->chip_delay = 100;
567 /* return the status of the Ready/Busy line */
568 this->dev_ready = rtc_from4_nand_device_ready;
569
570#ifdef RTC_FROM4_HWECC
571 printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
572
David Woodhousee0c7d762006-05-13 18:07:53 +0100573 this->eccmode = NAND_ECC_HW8_512;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574 this->options |= NAND_HWECC_SYNDROME;
David A. Marlined3786a2005-01-24 20:40:15 +0000575 /* return the status of extra status and ECC checks */
576 this->errstat = rtc_from4_errstat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 /* set the nand_oobinfo to support FPGA H/W error detection */
578 this->autooob = &rtc_from4_nand_oobinfo;
579 this->enable_hwecc = rtc_from4_enable_hwecc;
580 this->calculate_ecc = rtc_from4_calculate_ecc;
581 this->correct_data = rtc_from4_correct_data;
582#else
583 printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
584
585 this->eccmode = NAND_ECC_SOFT;
586#endif
587
588 /* set the bad block tables to support debugging */
589 this->bbt_td = &rtc_from4_bbt_main_descr;
590 this->bbt_md = &rtc_from4_bbt_mirror_descr;
591
592 /* Scan to find existence of the device */
593 if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) {
594 kfree(rtc_from4_mtd);
595 return -ENXIO;
596 }
597
David A. Marlin97f1a082005-01-17 19:44:39 +0000598 /* Perform 'device recovery' for each chip in case there was a power loss. */
David Woodhousee0c7d762006-05-13 18:07:53 +0100599 for (i = 0; i < this->numchips; i++) {
David A. Marlin97f1a082005-01-17 19:44:39 +0000600 deplete(rtc_from4_mtd, i);
601 }
602
David A. Marlined3786a2005-01-24 20:40:15 +0000603#if RTC_FROM4_NO_VIRTBLOCKS
604 /* use a smaller erase block to minimize wasted space when a block is bad */
605 /* note: this uses eight times as much RAM as using the default and makes */
606 /* mounts take four times as long. */
607 rtc_from4_mtd->flags |= MTD_NO_VIRTBLOCKS;
608#endif
609
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610 /* Register the partitions */
611 add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS);
612
613#ifdef RTC_FROM4_HWECC
614 /* We could create the decoder on demand, if memory is a concern.
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000615 * This way we have it handy, if an error happens
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616 *
617 * Symbolsize is 10 (bits)
618 * Primitve polynomial is x^10+x^3+1
619 * first consecutive root is 0
620 * primitve element to generate roots = 1
621 * generator polinomial degree = 6
622 */
623 rs_decoder = init_rs(10, 0x409, 0, 1, 6);
624 if (!rs_decoder) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100625 printk(KERN_ERR "Could not create a RS decoder\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626 nand_release(rtc_from4_mtd);
627 kfree(rtc_from4_mtd);
628 return -ENOMEM;
629 }
630#endif
631 /* Return happy */
632 return 0;
633}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634
David Woodhousee0c7d762006-05-13 18:07:53 +0100635module_init(rtc_from4_init);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636
637/*
638 * Clean up routine
639 */
640#ifdef MODULE
David Woodhousee0c7d762006-05-13 18:07:53 +0100641static void __exit rtc_from4_cleanup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642{
643 /* Release resource, unregister partitions */
644 nand_release(rtc_from4_mtd);
645
646 /* Free the MTD device structure */
David Woodhousee0c7d762006-05-13 18:07:53 +0100647 kfree(rtc_from4_mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648
649#ifdef RTC_FROM4_HWECC
650 /* Free the reed solomon resources */
651 if (rs_decoder) {
652 free_rs(rs_decoder);
653 }
654#endif
655}
David Woodhousee0c7d762006-05-13 18:07:53 +0100656
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657module_exit(rtc_from4_cleanup);
658#endif
659
660MODULE_LICENSE("GPL");
661MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");
662MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4");