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gerrit-public.fairphone.software / kernel / msm-4.19 / d046f6118bb2a207870e35db1411b958199a3750 / . / arch / m68knommu / platform / 68360 / head-ram.S
blob: f497713a4ec7ea72dfbc2a1fc4736c66000d233a [file] [log] [blame]
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]1/* arch/m68knommu/platform/68360/head-ram.S
2 *
3 * Startup code for Motorola 68360
4 *
5 * Copyright 2001 (C) SED Systems, a Division of Calian Ltd.
6 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
7 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
8 * uClinux Kernel
9 * Copyright (C) Michael Leslie <mleslie@lineo.com>
10 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
11 * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>,
12 *
13 */
14#define ASSEMBLY
15#include <linux/config.h>
16
17.global _stext
18.global _start
19
20.global _rambase
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]21.global _ramvec
22.global _ramstart
23.global _ramend
24
25.global _quicc_base
26.global _periph_base
27
Greg Ungererd046f612006-06-27 13:27:08 +1000[diff] [blame^]28#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
29
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]30#define REGB 0x1000
31#define PEPAR (_dprbase + REGB + 0x0016)
32#define GMR (_dprbase + REGB + 0x0040)
33#define OR0 (_dprbase + REGB + 0x0054)
34#define BR0 (_dprbase + REGB + 0x0050)
35#define OR1 (_dprbase + REGB + 0x0064)
36#define BR1 (_dprbase + REGB + 0x0060)
37#define OR4 (_dprbase + REGB + 0x0094)
38#define BR4 (_dprbase + REGB + 0x0090)
39#define OR6 (_dprbase + REGB + 0x00b4)
40#define BR6 (_dprbase + REGB + 0x00b0)
41#define OR7 (_dprbase + REGB + 0x00c4)
42#define BR7 (_dprbase + REGB + 0x00c0)
43
44#define MCR (_dprbase + REGB + 0x0000)
45#define AVR (_dprbase + REGB + 0x0008)
46
47#define SYPCR (_dprbase + REGB + 0x0022)
48
49#define PLLCR (_dprbase + REGB + 0x0010)
50#define CLKOCR (_dprbase + REGB + 0x000C)
51#define CDVCR (_dprbase + REGB + 0x0014)
52
53#define BKAR (_dprbase + REGB + 0x0030)
54#define BKCR (_dprbase + REGB + 0x0034)
55#define SWIV (_dprbase + REGB + 0x0023)
56#define PICR (_dprbase + REGB + 0x0026)
57#define PITR (_dprbase + REGB + 0x002A)
58
59/* Define for all memory configuration */
60#define MCU_SIM_GMR 0x00000000
61#define SIM_OR_MASK 0x0fffffff
62
63/* Defines for chip select zero - the flash */
64#define SIM_OR0_MASK 0x20000002
65#define SIM_BR0_MASK 0x00000001
66
67
68/* Defines for chip select one - the RAM */
69#define SIM_OR1_MASK 0x10000000
70#define SIM_BR1_MASK 0x00000001
71
72#define MCU_SIM_MBAR_ADRS 0x0003ff00
73#define MCU_SIM_MBAR_BA_MASK 0xfffff000
74#define MCU_SIM_MBAR_AS_MASK 0x00000001
75
76#define MCU_SIM_PEPAR 0x00B4
77
78#define MCU_DISABLE_INTRPTS 0x2700
79#define MCU_SIM_AVR 0x00
80
81#define MCU_SIM_MCR 0x00005cff
82
83#define MCU_SIM_CLKOCR 0x00
84#define MCU_SIM_PLLCR 0x8000
85#define MCU_SIM_CDVCR 0x0000
86
87#define MCU_SIM_SYPCR 0x0000
88#define MCU_SIM_SWIV 0x00
89#define MCU_SIM_PICR 0x0000
90#define MCU_SIM_PITR 0x0000
91
92
93#include <asm/m68360_regs.h>
94
95
96/*
97 * By the time this RAM specific code begins to execute, DPRAM
98 * and DRAM should already be mapped and accessible.
99 */
100
101 .text
102_start:
103_stext:
104 nop
105 ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */
106 /* We should not need to setup the boot stack the reset should do it. */
Greg Ungererd046f612006-06-27 13:27:08 +1000[diff] [blame^]107 movea.l #RAMEND, %sp /*set up stack at the end of DRAM:*/
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]108
109set_mbar_register:
110 moveq.l #0x07, %d1 /* Setup MBAR */
111 movec %d1, %dfc
112
113 lea.l MCU_SIM_MBAR_ADRS, %a0
114 move.l #_dprbase, %d0
115 andi.l #MCU_SIM_MBAR_BA_MASK, %d0
116 ori.l #MCU_SIM_MBAR_AS_MASK, %d0
117 moves.l %d0, %a0@
118
119 moveq.l #0x05, %d1
120 movec.l %d1, %dfc
121
122 /* Now we can begin to access registers in DPRAM */
123
124set_sim_mcr:
125 /* Set Module Configuration Register */
126 move.l #MCU_SIM_MCR, MCR
127
128 /* to do: Determine cause of reset */
129
130 /*
131 * configure system clock MC68360 p. 6-40
132 * (value +1)*osc/128 = system clock
133 */
134set_sim_clock:
135 move.w #MCU_SIM_PLLCR, PLLCR
136 move.b #MCU_SIM_CLKOCR, CLKOCR
137 move.w #MCU_SIM_CDVCR, CDVCR
138
139 /* Wait for the PLL to settle */
140 move.w #16384, %d0
141pll_settle_wait:
142 subi.w #1, %d0
143 bne pll_settle_wait
144
145 /* Setup the system protection register, and watchdog timer register */
146 move.b #MCU_SIM_SWIV, SWIV
147 move.w #MCU_SIM_PICR, PICR
148 move.w #MCU_SIM_PITR, PITR
149 move.w #MCU_SIM_SYPCR, SYPCR
150
151 /* Clear DPRAM - system + parameter */
152 movea.l #_dprbase, %a0
153 movea.l #_dprbase+0x2000, %a1
154
155 /* Copy 0 to %a0 until %a0 == %a1 */
156clear_dpram:
157 movel #0, %a0@+
158 cmpal %a0, %a1
159 bhi clear_dpram
160
161configure_memory_controller:
162 /* Set up Global Memory Register (GMR) */
163 move.l #MCU_SIM_GMR, %d0
164 move.l %d0, GMR
165
166configure_chip_select_0:
Greg Ungererd046f612006-06-27 13:27:08 +1000[diff] [blame^]167 move.l #RAMEND, %d0
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]168 subi.l #__ramstart, %d0
169 subq.l #0x01, %d0
170 eori.l #SIM_OR_MASK, %d0
171 ori.l #SIM_OR0_MASK, %d0
172 move.l %d0, OR0
173
174 move.l #__ramstart, %d0
175 ori.l #SIM_BR0_MASK, %d0
176 move.l %d0, BR0
177
178configure_chip_select_1:
179 move.l #__rom_end, %d0
180 subi.l #__rom_start, %d0
181 subq.l #0x01, %d0
182 eori.l #SIM_OR_MASK, %d0
183 ori.l #SIM_OR1_MASK, %d0
184 move.l %d0, OR1
185
186 move.l #__rom_start, %d0
187 ori.l #SIM_BR1_MASK, %d0
188 move.l %d0, BR1
189
190 move.w #MCU_SIM_PEPAR, PEPAR
191
192 /* point to vector table: */
193 move.l #_romvec, %a0
194 move.l #_ramvec, %a1
195copy_vectors:
196 move.l %a0@, %d0
197 move.l %d0, %a1@
198 move.l %a0@, %a1@
199 addq.l #0x04, %a0
200 addq.l #0x04, %a1
201 cmp.l #_start, %a0
202 blt copy_vectors
203
204 move.l #_ramvec, %a1
205 movec %a1, %vbr
206
207
208 /* Copy data segment from ROM to RAM */
209 moveal #_stext, %a0
210 moveal #_sdata, %a1
211 moveal #_edata, %a2
212
213 /* Copy %a0 to %a1 until %a1 == %a2 */
214LD1:
215 move.l %a0@, %d0
216 addq.l #0x04, %a0
217 move.l %d0, %a1@
218 addq.l #0x04, %a1
219 cmp.l #_edata, %a1
220 blt LD1
221
222 moveal #_sbss, %a0
223 moveal #_ebss, %a1
224
225 /* Copy 0 to %a0 until %a0 == %a1 */
226L1:
227 movel #0, %a0@+
228 cmpal %a0, %a1
229 bhi L1
230
231load_quicc:
232 move.l #_dprbase, _quicc_base
233
234store_ram_size:
235 /* Set ram size information */
236 move.l #_sdata, _rambase
237 move.l #_ebss, _ramstart
Greg Ungererd046f612006-06-27 13:27:08 +1000[diff] [blame^]238 move.l #RAMEND, %d0
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]239 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/
Greg Ungererd046f612006-06-27 13:27:08 +1000[diff] [blame^]240 move.l %d0, _ramend /* Different from RAMEND.*/
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]241
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]242 pea 0
243 pea env
244 pea %sp@(4)
245 pea 0
246
247 lea init_thread_union, %a2
248 lea 0x2000(%a2), %sp
249
250lp:
251 jsr start_kernel
252
253_exit:
254 jmp _exit
255
256
257 .data
258 .align 4
259env:
260 .long 0
261_quicc_base:
262 .long 0
263_periph_base:
264 .long 0
265_ramvec:
266 .long 0
267_rambase:
268 .long 0
269_ramstart:
270 .long 0
271_ramend:
272 .long 0
273_dprbase:
274 .long 0xffffe000
275
276 .text
277
278 /*
279 * These are the exception vectors at boot up, they are copied into RAM
280 * and then overwritten as needed.
281 */
282
283.section ".data.initvect","awx"
Greg Ungererd046f612006-06-27 13:27:08 +1000[diff] [blame^]284 .long RAMEND /* Reset: Initial Stack Pointer - 0. */
Greg Ungerer81d49032005-09-12 11:18:10 +1000[diff] [blame]285 .long _start /* Reset: Initial Program Counter - 1. */
286 .long buserr /* Bus Error - 2. */
287 .long trap /* Address Error - 3. */
288 .long trap /* Illegal Instruction - 4. */
289 .long trap /* Divide by zero - 5. */
290 .long trap /* CHK, CHK2 Instructions - 6. */
291 .long trap /* TRAPcc, TRAPV Instructions - 7. */
292 .long trap /* Privilege Violation - 8. */
293 .long trap /* Trace - 9. */
294 .long trap /* Line 1010 Emulator - 10. */
295 .long trap /* Line 1111 Emualtor - 11. */
296 .long trap /* Harware Breakpoint - 12. */
297 .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */
298 .long trap /* Format Error - 14. */
299 .long trap /* Uninitialized Interrupt - 15. */
300 .long trap /* (Unassigned, Reserver) - 16. */
301 .long trap /* (Unassigned, Reserver) - 17. */
302 .long trap /* (Unassigned, Reserver) - 18. */
303 .long trap /* (Unassigned, Reserver) - 19. */
304 .long trap /* (Unassigned, Reserver) - 20. */
305 .long trap /* (Unassigned, Reserver) - 21. */
306 .long trap /* (Unassigned, Reserver) - 22. */
307 .long trap /* (Unassigned, Reserver) - 23. */
308 .long trap /* Spurious Interrupt - 24. */
309 .long trap /* Level 1 Interrupt Autovector - 25. */
310 .long trap /* Level 2 Interrupt Autovector - 26. */
311 .long trap /* Level 3 Interrupt Autovector - 27. */
312 .long trap /* Level 4 Interrupt Autovector - 28. */
313 .long trap /* Level 5 Interrupt Autovector - 29. */
314 .long trap /* Level 6 Interrupt Autovector - 30. */
315 .long trap /* Level 7 Interrupt Autovector - 31. */
316 .long system_call /* Trap Instruction Vectors 0 - 32. */
317 .long trap /* Trap Instruction Vectors 1 - 33. */
318 .long trap /* Trap Instruction Vectors 2 - 34. */
319 .long trap /* Trap Instruction Vectors 3 - 35. */
320 .long trap /* Trap Instruction Vectors 4 - 36. */
321 .long trap /* Trap Instruction Vectors 5 - 37. */
322 .long trap /* Trap Instruction Vectors 6 - 38. */
323 .long trap /* Trap Instruction Vectors 7 - 39. */
324 .long trap /* Trap Instruction Vectors 8 - 40. */
325 .long trap /* Trap Instruction Vectors 9 - 41. */
326 .long trap /* Trap Instruction Vectors 10 - 42. */
327 .long trap /* Trap Instruction Vectors 11 - 43. */
328 .long trap /* Trap Instruction Vectors 12 - 44. */
329 .long trap /* Trap Instruction Vectors 13 - 45. */
330 .long trap /* Trap Instruction Vectors 14 - 46. */
331 .long trap /* Trap Instruction Vectors 15 - 47. */
332 .long 0 /* (Reserved for Coprocessor) - 48. */
333 .long 0 /* (Reserved for Coprocessor) - 49. */
334 .long 0 /* (Reserved for Coprocessor) - 50. */
335 .long 0 /* (Reserved for Coprocessor) - 51. */
336 .long 0 /* (Reserved for Coprocessor) - 52. */
337 .long 0 /* (Reserved for Coprocessor) - 53. */
338 .long 0 /* (Reserved for Coprocessor) - 54. */
339 .long 0 /* (Reserved for Coprocessor) - 55. */
340 .long 0 /* (Reserved for Coprocessor) - 56. */
341 .long 0 /* (Reserved for Coprocessor) - 57. */
342 .long 0 /* (Reserved for Coprocessor) - 58. */
343 .long 0 /* (Unassigned, Reserved) - 59. */
344 .long 0 /* (Unassigned, Reserved) - 60. */
345 .long 0 /* (Unassigned, Reserved) - 61. */
346 .long 0 /* (Unassigned, Reserved) - 62. */
347 .long 0 /* (Unassigned, Reserved) - 63. */
348 /* The assignment of these vectors to the CPM is */
349 /* dependent on the configuration of the CPM vba */
350 /* fields. */
351 .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */
352 .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
353 .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
354 .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */
355 .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */
356 .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */
357 .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
358 .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */
359 .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */
360 .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
361 .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
362 .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
363 .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */
364 .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */
365 .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
366 .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
367 .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */
368 .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
369 .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */
370 .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */
371 .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */
372 .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */
373 .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */
374 .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
375 .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
376 .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */
377 .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
378 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
379 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
380 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
381 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
382 .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
383 /* I don't think anything uses the vectors after here. */
384 .long 0 /* (User-Defined Vectors 34) - 96. */
385 .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */
386 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */
387 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */
388 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */
389 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */
390 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */
391 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */
392 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */
393 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */
394 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */
395 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */
396 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */
397 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */
398 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */
399 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */
400 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */
401 .long 0,0,0 /* (User-Defined Vectors 190 - 192). */
402.text
403ignore: rte