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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 *
Takashi Iwaid01ce992007-07-27 16:52:19 +02003 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
Randy Dunlap362775e2005-11-07 14:43:23 +010040#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include <linux/module.h>
Andrew Morton24982c52008-03-04 10:08:58 +010042#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
Ingo Molnar62932df2006-01-16 16:34:20 +010047#include <linux/mutex.h>
Takashi Iwai0cbf0092008-10-29 16:18:25 +010048#include <linux/reboot.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
Takashi Iwai5aba4f82008-01-07 15:16:37 +010054static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +020059static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
Takashi Iwai5aba4f82008-01-07 15:16:37 +010060static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
Takashi Iwaid4d9cd032008-12-19 15:19:11 +010061static int probe_only[SNDRV_CARDS];
Takashi Iwai27346162006-01-12 18:28:44 +010062static int single_cmd;
Takashi Iwai716238552009-09-28 13:14:04 +020063static int enable_msi = -1;
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +020064#ifdef CONFIG_SND_HDA_PATCH_LOADER
65static char *patch[SNDRV_CARDS];
66#endif
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +010067#ifdef CONFIG_SND_HDA_INPUT_BEEP
68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Takashi Iwai5aba4f82008-01-07 15:16:37 +010072module_param_array(index, int, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070073MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010074module_param_array(id, charp, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070075MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010076module_param_array(enable, bool, NULL, 0444);
77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78module_param_array(model, charp, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070079MODULE_PARM_DESC(model, "Use the given board model.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010080module_param_array(position_fix, int, NULL, 0444);
David Henningsson4cb36312010-09-30 10:12:50 +020081MODULE_PARM_DESC(position_fix, "DMA pointer read method."
82 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
Takashi Iwai555e2192008-06-10 17:53:34 +020083module_param_array(bdl_pos_adj, int, NULL, 0644);
84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010085module_param_array(probe_mask, int, NULL, 0444);
Takashi Iwai606ad752005-11-24 16:03:40 +010086MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
Jaroslav Kysela079e6832010-03-26 11:16:59 +010087module_param_array(probe_only, int, NULL, 0444);
Takashi Iwaid4d9cd032008-12-19 15:19:11 +010088MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
Takashi Iwai27346162006-01-12 18:28:44 +010089module_param(single_cmd, bool, 0444);
Takashi Iwaid01ce992007-07-27 16:52:19 +020090MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010092module_param(enable_msi, int, 0444);
Takashi Iwai134a11f2006-11-10 12:08:37 +010093MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +020094#ifdef CONFIG_SND_HDA_PATCH_LOADER
95module_param_array(patch, charp, NULL, 0444);
96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97#endif
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +010098#ifdef CONFIG_SND_HDA_INPUT_BEEP
99module_param_array(beep_mode, int, NULL, 0444);
100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102#endif
Takashi Iwai606ad752005-11-24 16:03:40 +0100103
Takashi Iwaidee1b662007-08-13 16:10:30 +0200104#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwaifee2fba2008-11-27 12:43:28 +0100105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106module_param(power_save, int, 0644);
107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
Takashi Iwaidee1b662007-08-13 16:10:30 +0200110/* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114static int power_save_controller = 1;
115module_param(power_save_controller, bool, 0644);
116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117#endif
118
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
Jason Gaston2f1b3812005-05-01 08:58:50 -0700122 "{Intel, ICH7},"
Frederick Lif5d40b32005-05-12 14:55:20 +0200123 "{Intel, ESB2},"
Jason Gastond2981392006-01-10 11:07:37 +0100124 "{Intel, ICH8},"
Jason Gastonf9cc8a82006-11-22 11:53:52 +0100125 "{Intel, ICH9},"
Jason Gastonc34f5a02008-01-29 12:38:49 +0100126 "{Intel, ICH10},"
Seth Heasleyb29c2362008-08-08 15:56:39 -0700127 "{Intel, PCH},"
Seth Heasleyd2f2fcd2010-01-12 17:03:35 -0800128 "{Intel, CPT},"
Seth Heasleycea310e2010-09-10 16:29:56 -0700129 "{Intel, PBG},"
Tobin Davis4979bca2008-01-30 08:13:55 +0100130 "{Intel, SCH},"
Takashi Iwaifc20a562005-05-12 15:00:41 +0200131 "{ATI, SB450},"
Felix Kuehling89be83f2006-03-31 12:33:59 +0200132 "{ATI, SB600},"
Felix Kuehling778b6e12006-05-17 11:22:21 +0200133 "{ATI, RS600},"
Felix Kuehling5b15c952006-10-16 12:49:47 +0200134 "{ATI, RS690},"
Wolke Liue6db1112007-04-27 12:20:57 +0200135 "{ATI, RS780},"
136 "{ATI, R600},"
Herton Ronaldo Krzesinski2797f722007-11-05 18:21:56 +0100137 "{ATI, RV630},"
138 "{ATI, RV610},"
Wolke Liu27da1832007-11-16 11:06:30 +0100139 "{ATI, RV670},"
140 "{ATI, RV635},"
141 "{ATI, RV620},"
142 "{ATI, RV770},"
Takashi Iwaifc20a562005-05-12 15:00:41 +0200143 "{VIA, VT8251},"
Takashi Iwai47672312005-08-12 16:44:04 +0200144 "{VIA, VT8237A},"
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200145 "{SiS, SIS966},"
146 "{ULI, M5461}}");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147MODULE_DESCRIPTION("Intel HDA driver");
148
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200149#ifdef CONFIG_SND_VERBOSE_PRINTK
150#define SFX /* nop */
151#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152#define SFX "hda-intel: "
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200153#endif
Takashi Iwaicb53c622007-08-10 17:21:45 +0200154
155/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 * registers
157 */
158#define ICH6_REG_GCAP 0x00
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200159#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
160#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
161#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
162#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
163#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164#define ICH6_REG_VMIN 0x02
165#define ICH6_REG_VMAJ 0x03
166#define ICH6_REG_OUTPAY 0x04
167#define ICH6_REG_INPAY 0x06
168#define ICH6_REG_GCTL 0x08
Takashi Iwai8a933ec2009-05-31 09:28:12 +0200169#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200170#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
171#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172#define ICH6_REG_WAKEEN 0x0c
173#define ICH6_REG_STATESTS 0x0e
174#define ICH6_REG_GSTS 0x10
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200175#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176#define ICH6_REG_INTCTL 0x20
177#define ICH6_REG_INTSTS 0x24
Jaroslav Kyselae5463722010-05-11 10:21:46 +0200178#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179#define ICH6_REG_SYNC 0x34
180#define ICH6_REG_CORBLBASE 0x40
181#define ICH6_REG_CORBUBASE 0x44
182#define ICH6_REG_CORBWP 0x48
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200183#define ICH6_REG_CORBRP 0x4a
184#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185#define ICH6_REG_CORBCTL 0x4c
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200186#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
187#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188#define ICH6_REG_CORBSTS 0x4d
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200189#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190#define ICH6_REG_CORBSIZE 0x4e
191
192#define ICH6_REG_RIRBLBASE 0x50
193#define ICH6_REG_RIRBUBASE 0x54
194#define ICH6_REG_RIRBWP 0x58
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200195#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196#define ICH6_REG_RINTCNT 0x5a
197#define ICH6_REG_RIRBCTL 0x5c
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200198#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
199#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
200#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201#define ICH6_REG_RIRBSTS 0x5d
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200202#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
203#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204#define ICH6_REG_RIRBSIZE 0x5e
205
206#define ICH6_REG_IC 0x60
207#define ICH6_REG_IR 0x64
208#define ICH6_REG_IRS 0x68
209#define ICH6_IRS_VALID (1<<1)
210#define ICH6_IRS_BUSY (1<<0)
211
212#define ICH6_REG_DPLBASE 0x70
213#define ICH6_REG_DPUBASE 0x74
214#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
215
216/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
217enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
218
219/* stream register offsets from stream base */
220#define ICH6_REG_SD_CTL 0x00
221#define ICH6_REG_SD_STS 0x03
222#define ICH6_REG_SD_LPIB 0x04
223#define ICH6_REG_SD_CBL 0x08
224#define ICH6_REG_SD_LVI 0x0c
225#define ICH6_REG_SD_FIFOW 0x0e
226#define ICH6_REG_SD_FIFOSIZE 0x10
227#define ICH6_REG_SD_FORMAT 0x12
228#define ICH6_REG_SD_BDLPL 0x18
229#define ICH6_REG_SD_BDLPU 0x1c
230
231/* PCI space */
232#define ICH6_PCIREG_TCSEL 0x44
233
234/*
235 * other constants
236 */
237
238/* max number of SDs */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200239/* ICH, ATI and VIA have 4 playback and 4 capture */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200240#define ICH6_NUM_CAPTURE 4
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200241#define ICH6_NUM_PLAYBACK 4
242
243/* ULI has 6 playback and 5 capture */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200244#define ULI_NUM_CAPTURE 5
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200245#define ULI_NUM_PLAYBACK 6
246
Felix Kuehling778b6e12006-05-17 11:22:21 +0200247/* ATI HDMI has 1 playback and 0 capture */
Felix Kuehling778b6e12006-05-17 11:22:21 +0200248#define ATIHDMI_NUM_CAPTURE 0
Felix Kuehling778b6e12006-05-17 11:22:21 +0200249#define ATIHDMI_NUM_PLAYBACK 1
250
Kailang Yangf2690022008-05-27 11:44:55 +0200251/* TERA has 4 playback and 3 capture */
252#define TERA_NUM_CAPTURE 3
253#define TERA_NUM_PLAYBACK 4
254
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200255/* this number is statically defined for simplicity */
256#define MAX_AZX_DEV 16
257
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258/* max number of fragments - we may use more if allocating more pages for BDL */
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100259#define BDL_SIZE 4096
260#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
261#define AZX_MAX_FRAG 32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262/* max buffer size - no h/w limit, you can increase as you like */
263#define AZX_MAX_BUF_SIZE (1024*1024*1024)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
265/* RIRB int mask: overrun[2], response[0] */
266#define RIRB_INT_RESPONSE 0x01
267#define RIRB_INT_OVERRUN 0x04
268#define RIRB_INT_MASK 0x05
269
Takashi Iwai2f5983f2008-09-03 16:00:44 +0200270/* STATESTS int mask: S3,SD2,SD1,SD0 */
Wei Ni7445dfc2010-03-03 15:05:53 +0800271#define AZX_MAX_CODECS 8
272#define AZX_DEFAULT_CODECS 4
Wu Fengguangdeadff12009-08-01 18:45:16 +0800273#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274
275/* SD_CTL bits */
276#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
277#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
Takashi Iwai850f0e52008-03-18 17:11:05 +0100278#define SD_CTL_STRIPE (3 << 16) /* stripe control */
279#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
280#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
282#define SD_CTL_STREAM_TAG_SHIFT 20
283
284/* SD_CTL and SD_STS */
285#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
286#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
287#define SD_INT_COMPLETE 0x04 /* completion interrupt */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200288#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
289 SD_INT_COMPLETE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290
291/* SD_STS */
292#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
293
294/* INTCTL and INTSTS */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200295#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
296#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
297#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299/* below are so far hardcoded - should read registers in future */
300#define ICH6_MAX_CORB_ENTRIES 256
301#define ICH6_MAX_RIRB_ENTRIES 256
302
Takashi Iwaic74db862005-05-12 14:26:27 +0200303/* position fix mode */
304enum {
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200305 POS_FIX_AUTO,
Takashi Iwaid2e1c972008-06-10 17:53:34 +0200306 POS_FIX_LPIB,
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200307 POS_FIX_POSBUF,
David Henningsson4cb36312010-09-30 10:12:50 +0200308 POS_FIX_VIACOMBO,
Takashi Iwaic74db862005-05-12 14:26:27 +0200309};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310
Frederick Lif5d40b32005-05-12 14:55:20 +0200311/* Defines for ATI HD Audio support in SB450 south bridge */
Frederick Lif5d40b32005-05-12 14:55:20 +0200312#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
313#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
314
Vinod Gda3fca22005-09-13 18:49:12 +0200315/* Defines for Nvidia HDA support */
316#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
317#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
Peer Chen320dcc32008-08-20 16:43:24 -0700318#define NVIDIA_HDA_ISTRM_COH 0x4d
319#define NVIDIA_HDA_OSTRM_COH 0x4c
320#define NVIDIA_HDA_ENABLE_COHBIT 0x01
Frederick Lif5d40b32005-05-12 14:55:20 +0200321
Takashi Iwai90a5ad52008-02-22 18:36:22 +0100322/* Defines for Intel SCH HDA snoop control */
323#define INTEL_SCH_HDA_DEVC 0x78
324#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
325
Joseph Chan0e153472008-08-26 14:38:03 +0200326/* Define IN stream 0 FIFO size offset in VIA controller */
327#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
328/* Define VIA HD Audio Device ID*/
329#define VIA_HDAC_DEVICE_ID 0x3288
330
Yang, Libinc4da29c2008-11-13 11:07:07 +0100331/* HD Audio class code */
332#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
Takashi Iwai90a5ad52008-02-22 18:36:22 +0100333
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 */
336
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100337struct azx_dev {
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100338 struct snd_dma_buffer bdl; /* BDL buffer */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200339 u32 *posbuf; /* position buffer pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340
Takashi Iwaid01ce992007-07-27 16:52:19 +0200341 unsigned int bufsize; /* size of the play buffer in bytes */
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200342 unsigned int period_bytes; /* size of the period in bytes */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200343 unsigned int frags; /* number for period in the play buffer */
344 unsigned int fifo_size; /* FIFO size */
Jaroslav Kyselae5463722010-05-11 10:21:46 +0200345 unsigned long start_wallclk; /* start + minimum wallclk */
346 unsigned long period_wallclk; /* wallclk for period */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347
Takashi Iwaid01ce992007-07-27 16:52:19 +0200348 void __iomem *sd_addr; /* stream descriptor pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349
Takashi Iwaid01ce992007-07-27 16:52:19 +0200350 u32 sd_int_sta_mask; /* stream int status mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351
352 /* pcm support */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200353 struct snd_pcm_substream *substream; /* assigned substream,
354 * set in PCM open
355 */
356 unsigned int format_val; /* format value to be set in the
357 * controller and the codec
358 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 unsigned char stream_tag; /* assigned stream */
360 unsigned char index; /* stream index */
Wu Fengguangef18bed2009-12-25 13:14:27 +0800361 int device; /* last device number assigned to */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362
Pavel Machek927fc862006-08-31 17:03:43 +0200363 unsigned int opened :1;
364 unsigned int running :1;
Takashi Iwai675f25d2008-06-10 17:53:20 +0200365 unsigned int irq_pending :1;
Joseph Chan0e153472008-08-26 14:38:03 +0200366 /*
367 * For VIA:
368 * A flag to ensure DMA position is 0
369 * when link position is not greater than FIFO size
370 */
371 unsigned int insufficient :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372};
373
374/* CORB/RIRB */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100375struct azx_rb {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 u32 *buf; /* CORB/RIRB buffer
377 * Each CORB entry is 4byte, RIRB is 8byte
378 */
379 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
380 /* for RIRB */
381 unsigned short rp, wp; /* read/write pointers */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800382 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
383 u32 res[AZX_MAX_CODECS]; /* last read value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384};
385
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100386struct azx {
387 struct snd_card *card;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 struct pci_dev *pci;
Takashi Iwai555e2192008-06-10 17:53:34 +0200389 int dev_index;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200391 /* chip type specific */
392 int driver_type;
393 int playback_streams;
394 int playback_index_offset;
395 int capture_streams;
396 int capture_index_offset;
397 int num_streams;
398
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 /* pci resources */
400 unsigned long addr;
401 void __iomem *remap_addr;
402 int irq;
403
404 /* locks */
405 spinlock_t reg_lock;
Ingo Molnar62932df2006-01-16 16:34:20 +0100406 struct mutex open_mutex;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200408 /* streams (x num_streams) */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100409 struct azx_dev *azx_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
411 /* PCM */
Takashi Iwaic8936222010-01-28 17:08:53 +0100412 struct snd_pcm *pcm[HDA_MAX_PCMS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413
414 /* HD codec */
415 unsigned short codec_mask;
Takashi Iwaif1eaaee2009-02-13 08:16:55 +0100416 int codec_probe_mask; /* copied from probe_mask option */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 struct hda_bus *bus;
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +0100418 unsigned int beep_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419
420 /* CORB/RIRB */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100421 struct azx_rb corb;
422 struct azx_rb rirb;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100424 /* CORB/RIRB and position buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 struct snd_dma_buffer rb;
426 struct snd_dma_buffer posbuf;
Takashi Iwaic74db862005-05-12 14:26:27 +0200427
428 /* flags */
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +0200429 int position_fix[2]; /* for both playback/capture streams */
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200430 int poll_count;
Takashi Iwaicb53c622007-08-10 17:21:45 +0200431 unsigned int running :1;
Pavel Machek927fc862006-08-31 17:03:43 +0200432 unsigned int initialized :1;
433 unsigned int single_cmd :1;
434 unsigned int polling_mode :1;
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200435 unsigned int msi :1;
Takashi Iwaia6a950a2008-06-10 17:53:35 +0200436 unsigned int irq_pending_warned :1;
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +0100437 unsigned int probing :1; /* codec probing phase */
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200438
439 /* for debugging */
Wu Fengguangfeb27342009-08-01 19:17:14 +0800440 unsigned int last_cmd[AZX_MAX_CODECS];
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200441
442 /* for pending irqs */
443 struct work_struct irq_pending_work;
Takashi Iwai0cbf0092008-10-29 16:18:25 +0100444
445 /* reboot notifier (for mysterious hangup problem at power-down) */
446 struct notifier_block reboot_notifier;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447};
448
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200449/* driver types */
450enum {
451 AZX_DRIVER_ICH,
Seth Heasley32679f92010-02-22 17:31:09 -0800452 AZX_DRIVER_PCH,
Tobin Davis4979bca2008-01-30 08:13:55 +0100453 AZX_DRIVER_SCH,
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200454 AZX_DRIVER_ATI,
Felix Kuehling778b6e12006-05-17 11:22:21 +0200455 AZX_DRIVER_ATIHDMI,
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200456 AZX_DRIVER_VIA,
457 AZX_DRIVER_SIS,
458 AZX_DRIVER_ULI,
Vinod Gda3fca22005-09-13 18:49:12 +0200459 AZX_DRIVER_NVIDIA,
Kailang Yangf2690022008-05-27 11:44:55 +0200460 AZX_DRIVER_TERA,
Takashi Iwai14d34f12010-10-21 09:03:25 +0200461 AZX_DRIVER_CTX,
Yang, Libinc4da29c2008-11-13 11:07:07 +0100462 AZX_DRIVER_GENERIC,
Takashi Iwai2f5983f2008-09-03 16:00:44 +0200463 AZX_NUM_DRIVERS, /* keep this as last entry */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200464};
465
466static char *driver_short_names[] __devinitdata = {
467 [AZX_DRIVER_ICH] = "HDA Intel",
Seth Heasley32679f92010-02-22 17:31:09 -0800468 [AZX_DRIVER_PCH] = "HDA Intel PCH",
Tobin Davis4979bca2008-01-30 08:13:55 +0100469 [AZX_DRIVER_SCH] = "HDA Intel MID",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200470 [AZX_DRIVER_ATI] = "HDA ATI SB",
Felix Kuehling778b6e12006-05-17 11:22:21 +0200471 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200472 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
473 [AZX_DRIVER_SIS] = "HDA SIS966",
Vinod Gda3fca22005-09-13 18:49:12 +0200474 [AZX_DRIVER_ULI] = "HDA ULI M5461",
475 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
Kailang Yangf2690022008-05-27 11:44:55 +0200476 [AZX_DRIVER_TERA] = "HDA Teradici",
Takashi Iwai14d34f12010-10-21 09:03:25 +0200477 [AZX_DRIVER_CTX] = "HDA Creative",
Yang, Libinc4da29c2008-11-13 11:07:07 +0100478 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200479};
480
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481/*
482 * macros for easy use
483 */
484#define azx_writel(chip,reg,value) \
485 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
486#define azx_readl(chip,reg) \
487 readl((chip)->remap_addr + ICH6_REG_##reg)
488#define azx_writew(chip,reg,value) \
489 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
490#define azx_readw(chip,reg) \
491 readw((chip)->remap_addr + ICH6_REG_##reg)
492#define azx_writeb(chip,reg,value) \
493 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
494#define azx_readb(chip,reg) \
495 readb((chip)->remap_addr + ICH6_REG_##reg)
496
497#define azx_sd_writel(dev,reg,value) \
498 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
499#define azx_sd_readl(dev,reg) \
500 readl((dev)->sd_addr + ICH6_REG_##reg)
501#define azx_sd_writew(dev,reg,value) \
502 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
503#define azx_sd_readw(dev,reg) \
504 readw((dev)->sd_addr + ICH6_REG_##reg)
505#define azx_sd_writeb(dev,reg,value) \
506 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
507#define azx_sd_readb(dev,reg) \
508 readb((dev)->sd_addr + ICH6_REG_##reg)
509
510/* for pcm support */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100511#define get_azx_dev(substream) (substream->runtime->private_data)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200513static int azx_acquire_irq(struct azx *chip, int do_disconnect);
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200514static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515/*
516 * Interface for HD codec
517 */
518
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519/*
520 * CORB / RIRB interface
521 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100522static int azx_alloc_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523{
524 int err;
525
526 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200527 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
528 snd_dma_pci_data(chip->pci),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529 PAGE_SIZE, &chip->rb);
530 if (err < 0) {
531 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
532 return err;
533 }
534 return 0;
535}
536
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100537static void azx_init_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538{
Wu Fengguangcdb1fbf2009-08-01 18:47:41 +0800539 spin_lock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540 /* CORB set up */
541 chip->corb.addr = chip->rb.addr;
542 chip->corb.buf = (u32 *)chip->rb.area;
543 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +0200544 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200546 /* set the corb size to 256 entries (ULI requires explicitly) */
547 azx_writeb(chip, CORBSIZE, 0x02);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548 /* set the corb write pointer to 0 */
549 azx_writew(chip, CORBWP, 0);
550 /* reset the corb hw read pointer */
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200551 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552 /* enable corb dma */
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200553 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554
555 /* RIRB set up */
556 chip->rirb.addr = chip->rb.addr + 2048;
557 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
Wu Fengguangdeadff12009-08-01 18:45:16 +0800558 chip->rirb.wp = chip->rirb.rp = 0;
559 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +0200561 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200563 /* set the rirb size to 256 entries (ULI requires explicitly) */
564 azx_writeb(chip, RIRBSIZE, 0x02);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 /* reset the rirb hw write pointer */
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200566 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 /* set N=1, get RIRB response interrupt for new entry */
Takashi Iwai14d34f12010-10-21 09:03:25 +0200568 if (chip->driver_type == AZX_DRIVER_CTX)
569 azx_writew(chip, RINTCNT, 0xc0);
570 else
571 azx_writew(chip, RINTCNT, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572 /* enable rirb dma and response irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
Wu Fengguangcdb1fbf2009-08-01 18:47:41 +0800574 spin_unlock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575}
576
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100577static void azx_free_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578{
Wu Fengguangcdb1fbf2009-08-01 18:47:41 +0800579 spin_lock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580 /* disable ringbuffer DMAs */
581 azx_writeb(chip, RIRBCTL, 0);
582 azx_writeb(chip, CORBCTL, 0);
Wu Fengguangcdb1fbf2009-08-01 18:47:41 +0800583 spin_unlock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584}
585
Wu Fengguangdeadff12009-08-01 18:45:16 +0800586static unsigned int azx_command_addr(u32 cmd)
587{
588 unsigned int addr = cmd >> 28;
589
590 if (addr >= AZX_MAX_CODECS) {
591 snd_BUG();
592 addr = 0;
593 }
594
595 return addr;
596}
597
598static unsigned int azx_response_addr(u32 res)
599{
600 unsigned int addr = res & 0xf;
601
602 if (addr >= AZX_MAX_CODECS) {
603 snd_BUG();
604 addr = 0;
605 }
606
607 return addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608}
609
610/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100611static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100613 struct azx *chip = bus->private_data;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800614 unsigned int addr = azx_command_addr(val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 unsigned int wp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616
Wu Fengguangc32649f2009-08-01 18:48:12 +0800617 spin_lock_irq(&chip->reg_lock);
618
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619 /* add command to corb */
620 wp = azx_readb(chip, CORBWP);
621 wp++;
622 wp %= ICH6_MAX_CORB_ENTRIES;
623
Wu Fengguangdeadff12009-08-01 18:45:16 +0800624 chip->rirb.cmds[addr]++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 chip->corb.buf[wp] = cpu_to_le32(val);
626 azx_writel(chip, CORBWP, wp);
Wu Fengguangc32649f2009-08-01 18:48:12 +0800627
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628 spin_unlock_irq(&chip->reg_lock);
629
630 return 0;
631}
632
633#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
634
635/* retrieve RIRB entry - called from interrupt handler */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100636static void azx_update_rirb(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637{
638 unsigned int rp, wp;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800639 unsigned int addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640 u32 res, res_ex;
641
642 wp = azx_readb(chip, RIRBWP);
643 if (wp == chip->rirb.wp)
644 return;
645 chip->rirb.wp = wp;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800646
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647 while (chip->rirb.rp != wp) {
648 chip->rirb.rp++;
649 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
650
651 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
652 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
653 res = le32_to_cpu(chip->rirb.buf[rp]);
Wu Fengguangdeadff12009-08-01 18:45:16 +0800654 addr = azx_response_addr(res_ex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
656 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
Wu Fengguangdeadff12009-08-01 18:45:16 +0800657 else if (chip->rirb.cmds[addr]) {
658 chip->rirb.res[addr] = res;
Takashi Iwai2add9b92008-03-18 09:47:06 +0100659 smp_wmb();
Wu Fengguangdeadff12009-08-01 18:45:16 +0800660 chip->rirb.cmds[addr]--;
Wu Fengguange310bb02009-08-01 19:18:45 +0800661 } else
662 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
663 "last cmd=%#08x\n",
664 res, res_ex,
665 chip->last_cmd[addr]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 }
667}
668
669/* receive a response */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800670static unsigned int azx_rirb_get_response(struct hda_bus *bus,
671 unsigned int addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100673 struct azx *chip = bus->private_data;
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200674 unsigned long timeout;
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200675 int do_poll = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200677 again:
678 timeout = jiffies + msecs_to_jiffies(1000);
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100679 for (;;) {
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200680 if (chip->polling_mode || do_poll) {
Takashi Iwaie96224a2006-08-21 17:57:44 +0200681 spin_lock_irq(&chip->reg_lock);
682 azx_update_rirb(chip);
683 spin_unlock_irq(&chip->reg_lock);
684 }
Wu Fengguangdeadff12009-08-01 18:45:16 +0800685 if (!chip->rirb.cmds[addr]) {
Takashi Iwai2add9b92008-03-18 09:47:06 +0100686 smp_rmb();
Takashi Iwaib6132912009-03-24 07:36:09 +0100687 bus->rirb_error = 0;
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200688
689 if (!do_poll)
690 chip->poll_count = 0;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800691 return chip->rirb.res[addr]; /* the last value */
Takashi Iwai2add9b92008-03-18 09:47:06 +0100692 }
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100693 if (time_after(jiffies, timeout))
694 break;
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100695 if (bus->needs_damn_long_delay)
Takashi Iwai52987652008-01-16 16:09:47 +0100696 msleep(2); /* temporary workaround */
697 else {
698 udelay(10);
699 cond_resched();
700 }
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100701 }
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200702
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200703 if (!chip->polling_mode && chip->poll_count < 2) {
704 snd_printdd(SFX "azx_get_response timeout, "
705 "polling the codec once: last cmd=0x%08x\n",
706 chip->last_cmd[addr]);
707 do_poll = 1;
708 chip->poll_count++;
709 goto again;
710 }
711
712
Takashi Iwai23c4a882009-10-30 13:21:49 +0100713 if (!chip->polling_mode) {
714 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
715 "switching to polling mode: last cmd=0x%08x\n",
716 chip->last_cmd[addr]);
717 chip->polling_mode = 1;
718 goto again;
719 }
720
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200721 if (chip->msi) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200722 snd_printk(KERN_WARNING SFX "No response from codec, "
Wu Fengguangfeb27342009-08-01 19:17:14 +0800723 "disabling MSI: last cmd=0x%08x\n",
724 chip->last_cmd[addr]);
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200725 free_irq(chip->irq, chip);
726 chip->irq = -1;
727 pci_disable_msi(chip->pci);
728 chip->msi = 0;
Takashi Iwaib6132912009-03-24 07:36:09 +0100729 if (azx_acquire_irq(chip, 1) < 0) {
730 bus->rirb_error = 1;
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200731 return -1;
Takashi Iwaib6132912009-03-24 07:36:09 +0100732 }
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200733 goto again;
734 }
735
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +0100736 if (chip->probing) {
737 /* If this critical timeout happens during the codec probing
738 * phase, this is likely an access to a non-existing codec
739 * slot. Better to return an error and reset the system.
740 */
741 return -1;
742 }
743
Takashi Iwai8dd78332009-06-02 01:16:07 +0200744 /* a fatal communication error; need either to reset or to fallback
745 * to the single_cmd mode
746 */
Takashi Iwaib6132912009-03-24 07:36:09 +0100747 bus->rirb_error = 1;
Takashi Iwaib20f3b82009-06-02 01:20:22 +0200748 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
Takashi Iwai8dd78332009-06-02 01:16:07 +0200749 bus->response_reset = 1;
750 return -1; /* give a chance to retry */
751 }
752
753 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
754 "switching to single_cmd mode: last cmd=0x%08x\n",
Wu Fengguangfeb27342009-08-01 19:17:14 +0800755 chip->last_cmd[addr]);
Takashi Iwai8dd78332009-06-02 01:16:07 +0200756 chip->single_cmd = 1;
757 bus->response_reset = 0;
Takashi Iwai1a696972009-11-07 09:49:04 +0100758 /* release CORB/RIRB */
Takashi Iwai4fcd3922009-05-25 18:34:52 +0200759 azx_free_cmd_io(chip);
Takashi Iwai1a696972009-11-07 09:49:04 +0100760 /* disable unsolicited responses */
761 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200762 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763}
764
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765/*
766 * Use the single immediate command instead of CORB/RIRB for simplicity
767 *
768 * Note: according to Intel, this is not preferred use. The command was
769 * intended for the BIOS only, and may get confused with unsolicited
770 * responses. So, we shouldn't use it for normal operation from the
771 * driver.
772 * I left the codes, however, for debugging/testing purposes.
773 */
774
Takashi Iwaib05a7d42009-05-28 11:59:12 +0200775/* receive a response */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800776static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
Takashi Iwaib05a7d42009-05-28 11:59:12 +0200777{
778 int timeout = 50;
779
780 while (timeout--) {
781 /* check IRV busy bit */
782 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
783 /* reuse rirb.res as the response return value */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800784 chip->rirb.res[addr] = azx_readl(chip, IR);
Takashi Iwaib05a7d42009-05-28 11:59:12 +0200785 return 0;
786 }
787 udelay(1);
788 }
789 if (printk_ratelimit())
790 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
791 azx_readw(chip, IRS));
Wu Fengguangdeadff12009-08-01 18:45:16 +0800792 chip->rirb.res[addr] = -1;
Takashi Iwaib05a7d42009-05-28 11:59:12 +0200793 return -EIO;
794}
795
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100797static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100799 struct azx *chip = bus->private_data;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800800 unsigned int addr = azx_command_addr(val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 int timeout = 50;
802
Takashi Iwai8dd78332009-06-02 01:16:07 +0200803 bus->rirb_error = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 while (timeout--) {
805 /* check ICB busy bit */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200806 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 /* Clear IRV valid bit */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200808 azx_writew(chip, IRS, azx_readw(chip, IRS) |
809 ICH6_IRS_VALID);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 azx_writel(chip, IC, val);
Takashi Iwaid01ce992007-07-27 16:52:19 +0200811 azx_writew(chip, IRS, azx_readw(chip, IRS) |
812 ICH6_IRS_BUSY);
Wu Fengguangdeadff12009-08-01 18:45:16 +0800813 return azx_single_wait_for_response(chip, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 }
815 udelay(1);
816 }
Marc Boucher1cfd52b2008-01-22 15:29:26 +0100817 if (printk_ratelimit())
818 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
819 azx_readw(chip, IRS), val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820 return -EIO;
821}
822
823/* receive a response */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800824static unsigned int azx_single_get_response(struct hda_bus *bus,
825 unsigned int addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100827 struct azx *chip = bus->private_data;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800828 return chip->rirb.res[addr];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829}
830
Takashi Iwai111d3af2006-02-16 18:17:58 +0100831/*
832 * The below are the main callbacks from hda_codec.
833 *
834 * They are just the skeleton to call sub-callbacks according to the
835 * current setting of chip->single_cmd.
836 */
837
838/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100839static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
Takashi Iwai111d3af2006-02-16 18:17:58 +0100840{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100841 struct azx *chip = bus->private_data;
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200842
Wu Fengguangfeb27342009-08-01 19:17:14 +0800843 chip->last_cmd[azx_command_addr(val)] = val;
Takashi Iwai111d3af2006-02-16 18:17:58 +0100844 if (chip->single_cmd)
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100845 return azx_single_send_cmd(bus, val);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100846 else
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100847 return azx_corb_send_cmd(bus, val);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100848}
849
850/* get a response */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800851static unsigned int azx_get_response(struct hda_bus *bus,
852 unsigned int addr)
Takashi Iwai111d3af2006-02-16 18:17:58 +0100853{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100854 struct azx *chip = bus->private_data;
Takashi Iwai111d3af2006-02-16 18:17:58 +0100855 if (chip->single_cmd)
Wu Fengguangdeadff12009-08-01 18:45:16 +0800856 return azx_single_get_response(bus, addr);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100857 else
Wu Fengguangdeadff12009-08-01 18:45:16 +0800858 return azx_rirb_get_response(bus, addr);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100859}
860
Takashi Iwaicb53c622007-08-10 17:21:45 +0200861#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100862static void azx_power_notify(struct hda_bus *bus);
Takashi Iwaicb53c622007-08-10 17:21:45 +0200863#endif
Takashi Iwai111d3af2006-02-16 18:17:58 +0100864
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865/* reset codec link */
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +0100866static int azx_reset(struct azx *chip, int full_reset)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867{
868 int count;
869
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +0100870 if (!full_reset)
871 goto __skip;
872
Danny Tholene8a7f132007-09-11 21:41:56 +0200873 /* clear STATESTS */
874 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
875
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 /* reset controller */
877 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
878
879 count = 50;
880 while (azx_readb(chip, GCTL) && --count)
881 msleep(1);
882
883 /* delay for >= 100us for codec PLL to settle per spec
884 * Rev 0.9 section 5.5.1
885 */
886 msleep(1);
887
888 /* Bring controller out of reset */
889 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
890
891 count = 50;
Pavel Machek927fc862006-08-31 17:03:43 +0200892 while (!azx_readb(chip, GCTL) && --count)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893 msleep(1);
894
Pavel Machek927fc862006-08-31 17:03:43 +0200895 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 msleep(1);
897
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +0100898 __skip:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899 /* check to see if controller is ready */
Pavel Machek927fc862006-08-31 17:03:43 +0200900 if (!azx_readb(chip, GCTL)) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200901 snd_printd(SFX "azx_reset: controller not ready!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700902 return -EBUSY;
903 }
904
Matt41e2fce2005-07-04 17:49:55 +0200905 /* Accept unsolicited responses */
Takashi Iwai1a696972009-11-07 09:49:04 +0100906 if (!chip->single_cmd)
907 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
908 ICH6_GCTL_UNSOL);
Matt41e2fce2005-07-04 17:49:55 +0200909
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910 /* detect codecs */
Pavel Machek927fc862006-08-31 17:03:43 +0200911 if (!chip->codec_mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912 chip->codec_mask = azx_readw(chip, STATESTS);
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200913 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 }
915
916 return 0;
917}
918
919
920/*
921 * Lowlevel interface
922 */
923
924/* enable interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100925static void azx_int_enable(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926{
927 /* enable controller CIE and GIE */
928 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
929 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
930}
931
932/* disable interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100933static void azx_int_disable(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934{
935 int i;
936
937 /* disable interrupts in stream descriptor */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200938 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100939 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940 azx_sd_writeb(azx_dev, SD_CTL,
941 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
942 }
943
944 /* disable SIE for all streams */
945 azx_writeb(chip, INTCTL, 0);
946
947 /* disable controller CIE and GIE */
948 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
949 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
950}
951
952/* clear interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100953static void azx_int_clear(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954{
955 int i;
956
957 /* clear stream status */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200958 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100959 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
961 }
962
963 /* clear STATESTS */
964 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
965
966 /* clear rirb status */
967 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
968
969 /* clear int status */
970 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
971}
972
973/* start a stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100974static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975{
Joseph Chan0e153472008-08-26 14:38:03 +0200976 /*
977 * Before stream start, initialize parameter
978 */
979 azx_dev->insufficient = 1;
980
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 /* enable SIE */
Wei Niccc5df02010-01-26 15:59:33 +0800982 azx_writel(chip, INTCTL,
983 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984 /* set DMA start and interrupt mask */
985 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
986 SD_CTL_DMA_START | SD_INT_MASK);
987}
988
Takashi Iwai1dddab42009-03-18 15:15:37 +0100989/* stop DMA */
990static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
993 ~(SD_CTL_DMA_START | SD_INT_MASK));
994 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
Takashi Iwai1dddab42009-03-18 15:15:37 +0100995}
996
997/* stop a stream */
998static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
999{
1000 azx_stream_clear(chip, azx_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001 /* disable SIE */
Wei Niccc5df02010-01-26 15:59:33 +08001002 azx_writel(chip, INTCTL,
1003 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004}
1005
1006
1007/*
Takashi Iwaicb53c622007-08-10 17:21:45 +02001008 * reset and start the controller registers
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 */
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01001010static void azx_init_chip(struct azx *chip, int full_reset)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011{
Takashi Iwaicb53c622007-08-10 17:21:45 +02001012 if (chip->initialized)
1013 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014
1015 /* reset controller */
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01001016 azx_reset(chip, full_reset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017
1018 /* initialize interrupts */
1019 azx_int_clear(chip);
1020 azx_int_enable(chip);
1021
1022 /* initialize the codec command I/O */
Takashi Iwai1a696972009-11-07 09:49:04 +01001023 if (!chip->single_cmd)
1024 azx_init_cmd_io(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02001026 /* program the position buffer */
1027 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +02001028 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
Frederick Lif5d40b32005-05-12 14:55:20 +02001029
Takashi Iwaicb53c622007-08-10 17:21:45 +02001030 chip->initialized = 1;
1031}
1032
1033/*
1034 * initialize the PCI registers
1035 */
1036/* update bits in a PCI register byte */
1037static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1038 unsigned char mask, unsigned char val)
1039{
1040 unsigned char data;
1041
1042 pci_read_config_byte(pci, reg, &data);
1043 data &= ~mask;
1044 data |= (val & mask);
1045 pci_write_config_byte(pci, reg, data);
1046}
1047
1048static void azx_init_pci(struct azx *chip)
1049{
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001050 unsigned short snoop;
1051
Takashi Iwaicb53c622007-08-10 17:21:45 +02001052 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1053 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1054 * Ensuring these bits are 0 clears playback static on some HD Audio
1055 * codecs
1056 */
1057 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1058
Vinod Gda3fca22005-09-13 18:49:12 +02001059 switch (chip->driver_type) {
1060 case AZX_DRIVER_ATI:
1061 /* For ATI SB450 azalia HD audio, we need to enable snoop */
Takashi Iwaicb53c622007-08-10 17:21:45 +02001062 update_pci_byte(chip->pci,
1063 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1064 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
Vinod Gda3fca22005-09-13 18:49:12 +02001065 break;
1066 case AZX_DRIVER_NVIDIA:
1067 /* For NVIDIA HDA, enable snoop */
Takashi Iwaicb53c622007-08-10 17:21:45 +02001068 update_pci_byte(chip->pci,
1069 NVIDIA_HDA_TRANSREG_ADDR,
1070 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
Peer Chen320dcc32008-08-20 16:43:24 -07001071 update_pci_byte(chip->pci,
1072 NVIDIA_HDA_ISTRM_COH,
1073 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1074 update_pci_byte(chip->pci,
1075 NVIDIA_HDA_OSTRM_COH,
1076 0x01, NVIDIA_HDA_ENABLE_COHBIT);
Vinod Gda3fca22005-09-13 18:49:12 +02001077 break;
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001078 case AZX_DRIVER_SCH:
Seth Heasley32679f92010-02-22 17:31:09 -08001079 case AZX_DRIVER_PCH:
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001080 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1081 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001082 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001083 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1084 pci_read_config_word(chip->pci,
1085 INTEL_SCH_HDA_DEVC, &snoop);
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001086 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1087 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001088 ? "Failed" : "OK");
1089 }
1090 break;
1091
Vinod Gda3fca22005-09-13 18:49:12 +02001092 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093}
1094
1095
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001096static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1097
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098/*
1099 * interrupt handler
1100 */
David Howells7d12e782006-10-05 14:55:46 +01001101static irqreturn_t azx_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102{
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001103 struct azx *chip = dev_id;
1104 struct azx_dev *azx_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 u32 status;
Clemens Ladisch9ef04062010-05-25 09:03:40 +02001106 u8 sd_status;
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001107 int i, ok;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001108
1109 spin_lock(&chip->reg_lock);
1110
1111 status = azx_readl(chip, INTSTS);
1112 if (status == 0) {
1113 spin_unlock(&chip->reg_lock);
1114 return IRQ_NONE;
1115 }
1116
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001117 for (i = 0; i < chip->num_streams; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 azx_dev = &chip->azx_dev[i];
1119 if (status & azx_dev->sd_int_sta_mask) {
Clemens Ladisch9ef04062010-05-25 09:03:40 +02001120 sd_status = azx_sd_readb(azx_dev, SD_STS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
Clemens Ladisch9ef04062010-05-25 09:03:40 +02001122 if (!azx_dev->substream || !azx_dev->running ||
1123 !(sd_status & SD_INT_COMPLETE))
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001124 continue;
1125 /* check whether this IRQ is really acceptable */
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001126 ok = azx_position_ok(chip, azx_dev);
1127 if (ok == 1) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001128 azx_dev->irq_pending = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129 spin_unlock(&chip->reg_lock);
1130 snd_pcm_period_elapsed(azx_dev->substream);
1131 spin_lock(&chip->reg_lock);
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001132 } else if (ok == 0 && chip->bus && chip->bus->workq) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001133 /* bogus IRQ, process it later */
1134 azx_dev->irq_pending = 1;
Takashi Iwai6acaed32009-01-12 10:09:24 +01001135 queue_work(chip->bus->workq,
1136 &chip->irq_pending_work);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137 }
1138 }
1139 }
1140
1141 /* clear rirb int */
1142 status = azx_readb(chip, RIRBSTS);
1143 if (status & RIRB_INT_MASK) {
Takashi Iwai14d34f12010-10-21 09:03:25 +02001144 if (status & RIRB_INT_RESPONSE) {
1145 if (chip->driver_type == AZX_DRIVER_CTX)
1146 udelay(80);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147 azx_update_rirb(chip);
Takashi Iwai14d34f12010-10-21 09:03:25 +02001148 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1150 }
1151
1152#if 0
1153 /* clear state status int */
1154 if (azx_readb(chip, STATESTS) & 0x04)
1155 azx_writeb(chip, STATESTS, 0x04);
1156#endif
1157 spin_unlock(&chip->reg_lock);
1158
1159 return IRQ_HANDLED;
1160}
1161
1162
1163/*
Takashi Iwai675f25d2008-06-10 17:53:20 +02001164 * set up a BDL entry
1165 */
1166static int setup_bdle(struct snd_pcm_substream *substream,
1167 struct azx_dev *azx_dev, u32 **bdlp,
1168 int ofs, int size, int with_ioc)
1169{
Takashi Iwai675f25d2008-06-10 17:53:20 +02001170 u32 *bdl = *bdlp;
1171
1172 while (size > 0) {
1173 dma_addr_t addr;
1174 int chunk;
1175
1176 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1177 return -EINVAL;
1178
Takashi Iwai77a23f22008-08-21 13:00:13 +02001179 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001180 /* program the address field of the BDL entry */
1181 bdl[0] = cpu_to_le32((u32)addr);
Takashi Iwai766979e2008-06-13 20:53:56 +02001182 bdl[1] = cpu_to_le32(upper_32_bits(addr));
Takashi Iwai675f25d2008-06-10 17:53:20 +02001183 /* program the size field of the BDL entry */
Takashi Iwaifc4abee2008-07-30 15:13:34 +02001184 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001185 bdl[2] = cpu_to_le32(chunk);
1186 /* program the IOC to enable interrupt
1187 * only when the whole fragment is processed
1188 */
1189 size -= chunk;
1190 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1191 bdl += 4;
1192 azx_dev->frags++;
1193 ofs += chunk;
1194 }
1195 *bdlp = bdl;
1196 return ofs;
1197}
1198
1199/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200 * set up BDL entries
1201 */
Takashi Iwai555e2192008-06-10 17:53:34 +02001202static int azx_setup_periods(struct azx *chip,
1203 struct snd_pcm_substream *substream,
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001204 struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205{
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001206 u32 *bdl;
1207 int i, ofs, periods, period_bytes;
Takashi Iwai555e2192008-06-10 17:53:34 +02001208 int pos_adj;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209
1210 /* reset BDL address */
1211 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1212 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1213
Takashi Iwai97b71c92009-03-18 15:09:13 +01001214 period_bytes = azx_dev->period_bytes;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001215 periods = azx_dev->bufsize / period_bytes;
1216
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217 /* program the initial BDL entries */
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001218 bdl = (u32 *)azx_dev->bdl.area;
1219 ofs = 0;
1220 azx_dev->frags = 0;
Takashi Iwai555e2192008-06-10 17:53:34 +02001221 pos_adj = bdl_pos_adj[chip->dev_index];
1222 if (pos_adj > 0) {
Takashi Iwai675f25d2008-06-10 17:53:20 +02001223 struct snd_pcm_runtime *runtime = substream->runtime;
Takashi Iwaie785d3d2008-07-15 16:28:43 +02001224 int pos_align = pos_adj;
Takashi Iwai555e2192008-06-10 17:53:34 +02001225 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001226 if (!pos_adj)
Takashi Iwaie785d3d2008-07-15 16:28:43 +02001227 pos_adj = pos_align;
1228 else
1229 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1230 pos_align;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001231 pos_adj = frames_to_bytes(runtime, pos_adj);
1232 if (pos_adj >= period_bytes) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001233 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
Takashi Iwai555e2192008-06-10 17:53:34 +02001234 bdl_pos_adj[chip->dev_index]);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001235 pos_adj = 0;
1236 } else {
1237 ofs = setup_bdle(substream, azx_dev,
1238 &bdl, ofs, pos_adj, 1);
1239 if (ofs < 0)
1240 goto error;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001241 }
Takashi Iwai555e2192008-06-10 17:53:34 +02001242 } else
1243 pos_adj = 0;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001244 for (i = 0; i < periods; i++) {
1245 if (i == periods - 1 && pos_adj)
1246 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1247 period_bytes - pos_adj, 0);
1248 else
1249 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1250 period_bytes, 1);
1251 if (ofs < 0)
1252 goto error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253 }
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001254 return 0;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001255
1256 error:
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001257 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
Takashi Iwai675f25d2008-06-10 17:53:20 +02001258 azx_dev->bufsize, period_bytes);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001259 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260}
1261
Takashi Iwai1dddab42009-03-18 15:15:37 +01001262/* reset stream */
1263static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264{
1265 unsigned char val;
1266 int timeout;
1267
Takashi Iwai1dddab42009-03-18 15:15:37 +01001268 azx_stream_clear(chip, azx_dev);
1269
Takashi Iwaid01ce992007-07-27 16:52:19 +02001270 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1271 SD_CTL_STREAM_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001272 udelay(3);
1273 timeout = 300;
1274 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1275 --timeout)
1276 ;
1277 val &= ~SD_CTL_STREAM_RESET;
1278 azx_sd_writeb(azx_dev, SD_CTL, val);
1279 udelay(3);
1280
1281 timeout = 300;
1282 /* waiting for hardware to report that the stream is out of reset */
1283 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1284 --timeout)
1285 ;
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001286
1287 /* reset first position - may not be synced with hw at this time */
1288 *azx_dev->posbuf = 0;
Takashi Iwai1dddab42009-03-18 15:15:37 +01001289}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290
Takashi Iwai1dddab42009-03-18 15:15:37 +01001291/*
1292 * set up the SD for streaming
1293 */
1294static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1295{
1296 /* make sure the run bit is zero for SD */
1297 azx_stream_clear(chip, azx_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298 /* program the stream_tag */
1299 azx_sd_writel(azx_dev, SD_CTL,
Takashi Iwaid01ce992007-07-27 16:52:19 +02001300 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
Linus Torvalds1da177e2005-04-16 15:20:36 -07001301 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1302
1303 /* program the length of samples in cyclic buffer */
1304 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1305
1306 /* program the stream format */
1307 /* this value needs to be the same as the one programmed */
1308 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1309
1310 /* program the stream LVI (last valid index) of the BDL */
1311 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1312
1313 /* program the BDL address */
1314 /* lower BDL address */
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001315 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001316 /* upper BDL address */
Takashi Iwai766979e2008-06-13 20:53:56 +02001317 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001318
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02001319 /* enable the position buffer */
David Henningsson4cb36312010-09-30 10:12:50 +02001320 if (chip->position_fix[0] != POS_FIX_LPIB ||
1321 chip->position_fix[1] != POS_FIX_LPIB) {
Takashi Iwaiee9d6b92008-03-14 15:52:20 +01001322 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1323 azx_writel(chip, DPLBASE,
1324 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1325 }
Takashi Iwaic74db862005-05-12 14:26:27 +02001326
Linus Torvalds1da177e2005-04-16 15:20:36 -07001327 /* set the interrupt enable bits in the descriptor control register */
Takashi Iwaid01ce992007-07-27 16:52:19 +02001328 azx_sd_writel(azx_dev, SD_CTL,
1329 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330
1331 return 0;
1332}
1333
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001334/*
1335 * Probe the given codec address
1336 */
1337static int probe_codec(struct azx *chip, int addr)
1338{
1339 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1340 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1341 unsigned int res;
1342
Wu Fengguanga678cde2009-08-01 18:46:46 +08001343 mutex_lock(&chip->bus->cmd_mutex);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001344 chip->probing = 1;
1345 azx_send_cmd(chip->bus, cmd);
Wu Fengguangdeadff12009-08-01 18:45:16 +08001346 res = azx_get_response(chip->bus, addr);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001347 chip->probing = 0;
Wu Fengguanga678cde2009-08-01 18:46:46 +08001348 mutex_unlock(&chip->bus->cmd_mutex);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001349 if (res == -1)
1350 return -EIO;
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001351 snd_printdd(SFX "codec #%d probed OK\n", addr);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001352 return 0;
1353}
1354
Takashi Iwai33fa35e2008-11-06 16:50:40 +01001355static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1356 struct hda_pcm *cpcm);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001357static void azx_stop_chip(struct azx *chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358
Takashi Iwai8dd78332009-06-02 01:16:07 +02001359static void azx_bus_reset(struct hda_bus *bus)
1360{
1361 struct azx *chip = bus->private_data;
Takashi Iwai8dd78332009-06-02 01:16:07 +02001362
1363 bus->in_reset = 1;
1364 azx_stop_chip(chip);
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01001365 azx_init_chip(chip, 1);
Alexander Beregalov65f75982009-06-04 13:46:16 +04001366#ifdef CONFIG_PM
Takashi Iwai8dd78332009-06-02 01:16:07 +02001367 if (chip->initialized) {
Alexander Beregalov65f75982009-06-04 13:46:16 +04001368 int i;
1369
Takashi Iwaic8936222010-01-28 17:08:53 +01001370 for (i = 0; i < HDA_MAX_PCMS; i++)
Takashi Iwai8dd78332009-06-02 01:16:07 +02001371 snd_pcm_suspend_all(chip->pcm[i]);
1372 snd_hda_suspend(chip->bus);
1373 snd_hda_resume(chip->bus);
1374 }
Alexander Beregalov65f75982009-06-04 13:46:16 +04001375#endif
Takashi Iwai8dd78332009-06-02 01:16:07 +02001376 bus->in_reset = 0;
1377}
1378
Linus Torvalds1da177e2005-04-16 15:20:36 -07001379/*
1380 * Codec initialization
1381 */
1382
Takashi Iwai2f5983f2008-09-03 16:00:44 +02001383/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1384static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
Wei Ni7445dfc2010-03-03 15:05:53 +08001385 [AZX_DRIVER_NVIDIA] = 8,
Kailang Yangf2690022008-05-27 11:44:55 +02001386 [AZX_DRIVER_TERA] = 1,
Takashi Iwaia9995a32007-03-12 21:30:46 +01001387};
1388
Takashi Iwaia1e21c92009-06-17 09:33:52 +02001389static int __devinit azx_codec_create(struct azx *chip, const char *model)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390{
1391 struct hda_bus_template bus_temp;
Takashi Iwai34c25352008-10-28 11:38:58 +01001392 int c, codecs, err;
1393 int max_slots;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394
1395 memset(&bus_temp, 0, sizeof(bus_temp));
1396 bus_temp.private_data = chip;
1397 bus_temp.modelname = model;
1398 bus_temp.pci = chip->pci;
Takashi Iwai111d3af2006-02-16 18:17:58 +01001399 bus_temp.ops.command = azx_send_cmd;
1400 bus_temp.ops.get_response = azx_get_response;
Takashi Iwai176d5332008-07-30 15:01:44 +02001401 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
Takashi Iwai8dd78332009-06-02 01:16:07 +02001402 bus_temp.ops.bus_reset = azx_bus_reset;
Takashi Iwaicb53c622007-08-10 17:21:45 +02001403#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwai11cd41b2008-11-28 07:22:18 +01001404 bus_temp.power_save = &power_save;
Takashi Iwaicb53c622007-08-10 17:21:45 +02001405 bus_temp.ops.pm_notify = azx_power_notify;
1406#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407
Takashi Iwaid01ce992007-07-27 16:52:19 +02001408 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1409 if (err < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410 return err;
1411
Wei Nidc9c8e22008-09-26 13:55:56 +08001412 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1413 chip->bus->needs_damn_long_delay = 1;
1414
Takashi Iwai34c25352008-10-28 11:38:58 +01001415 codecs = 0;
Takashi Iwai2f5983f2008-09-03 16:00:44 +02001416 max_slots = azx_max_codecs[chip->driver_type];
1417 if (!max_slots)
Wei Ni7445dfc2010-03-03 15:05:53 +08001418 max_slots = AZX_DEFAULT_CODECS;
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001419
1420 /* First try to probe all given codec slots */
1421 for (c = 0; c < max_slots; c++) {
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01001422 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001423 if (probe_codec(chip, c) < 0) {
1424 /* Some BIOSen give you wrong codec addresses
1425 * that don't exist
1426 */
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001427 snd_printk(KERN_WARNING SFX
1428 "Codec #%d probe error; "
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001429 "disabling it...\n", c);
1430 chip->codec_mask &= ~(1 << c);
1431 /* More badly, accessing to a non-existing
1432 * codec often screws up the controller chip,
Paul Menzel24481582010-02-08 20:37:26 +01001433 * and disturbs the further communications.
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001434 * Thus if an error occurs during probing,
1435 * better to reset the controller chip to
1436 * get back to the sanity state.
1437 */
1438 azx_stop_chip(chip);
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01001439 azx_init_chip(chip, 1);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001440 }
1441 }
1442 }
1443
1444 /* Then create codec instances */
Takashi Iwai34c25352008-10-28 11:38:58 +01001445 for (c = 0; c < max_slots; c++) {
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01001446 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
Takashi Iwaibccad142007-04-24 12:23:53 +02001447 struct hda_codec *codec;
Takashi Iwaia1e21c92009-06-17 09:33:52 +02001448 err = snd_hda_codec_new(chip->bus, c, &codec);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449 if (err < 0)
1450 continue;
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +01001451 codec->beep_mode = chip->beep_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452 codecs++;
Takashi Iwai19a982b2007-03-21 15:14:35 +01001453 }
1454 }
1455 if (!codecs) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001456 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1457 return -ENXIO;
1458 }
Takashi Iwaia1e21c92009-06-17 09:33:52 +02001459 return 0;
1460}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461
Takashi Iwaia1e21c92009-06-17 09:33:52 +02001462/* configure each codec instance */
1463static int __devinit azx_codec_configure(struct azx *chip)
1464{
1465 struct hda_codec *codec;
1466 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1467 snd_hda_codec_configure(codec);
1468 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469 return 0;
1470}
1471
1472
1473/*
1474 * PCM support
1475 */
1476
1477/* assign a stream for the PCM */
Wu Fengguangef18bed2009-12-25 13:14:27 +08001478static inline struct azx_dev *
1479azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480{
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001481 int dev, i, nums;
Wu Fengguangef18bed2009-12-25 13:14:27 +08001482 struct azx_dev *res = NULL;
1483
1484 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001485 dev = chip->playback_index_offset;
1486 nums = chip->playback_streams;
1487 } else {
1488 dev = chip->capture_index_offset;
1489 nums = chip->capture_streams;
1490 }
1491 for (i = 0; i < nums; i++, dev++)
Takashi Iwaid01ce992007-07-27 16:52:19 +02001492 if (!chip->azx_dev[dev].opened) {
Wu Fengguangef18bed2009-12-25 13:14:27 +08001493 res = &chip->azx_dev[dev];
1494 if (res->device == substream->pcm->device)
1495 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496 }
Wu Fengguangef18bed2009-12-25 13:14:27 +08001497 if (res) {
1498 res->opened = 1;
1499 res->device = substream->pcm->device;
1500 }
1501 return res;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502}
1503
1504/* release the assigned stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001505static inline void azx_release_device(struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506{
1507 azx_dev->opened = 0;
1508}
1509
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001510static struct snd_pcm_hardware azx_pcm_hw = {
Takashi Iwaid01ce992007-07-27 16:52:19 +02001511 .info = (SNDRV_PCM_INFO_MMAP |
1512 SNDRV_PCM_INFO_INTERLEAVED |
Linus Torvalds1da177e2005-04-16 15:20:36 -07001513 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1514 SNDRV_PCM_INFO_MMAP_VALID |
Pavel Machek927fc862006-08-31 17:03:43 +02001515 /* No full-resume yet implemented */
1516 /* SNDRV_PCM_INFO_RESUME |*/
Takashi Iwai850f0e52008-03-18 17:11:05 +01001517 SNDRV_PCM_INFO_PAUSE |
1518 SNDRV_PCM_INFO_SYNC_START),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1520 .rates = SNDRV_PCM_RATE_48000,
1521 .rate_min = 48000,
1522 .rate_max = 48000,
1523 .channels_min = 2,
1524 .channels_max = 2,
1525 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1526 .period_bytes_min = 128,
1527 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1528 .periods_min = 2,
1529 .periods_max = AZX_MAX_FRAG,
1530 .fifo_size = 0,
1531};
1532
1533struct azx_pcm {
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001534 struct azx *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535 struct hda_codec *codec;
1536 struct hda_pcm_stream *hinfo[2];
1537};
1538
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001539static int azx_pcm_open(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540{
1541 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1542 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001543 struct azx *chip = apcm->chip;
1544 struct azx_dev *azx_dev;
1545 struct snd_pcm_runtime *runtime = substream->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001546 unsigned long flags;
1547 int err;
1548
Ingo Molnar62932df2006-01-16 16:34:20 +01001549 mutex_lock(&chip->open_mutex);
Wu Fengguangef18bed2009-12-25 13:14:27 +08001550 azx_dev = azx_assign_device(chip, substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 if (azx_dev == NULL) {
Ingo Molnar62932df2006-01-16 16:34:20 +01001552 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 return -EBUSY;
1554 }
1555 runtime->hw = azx_pcm_hw;
1556 runtime->hw.channels_min = hinfo->channels_min;
1557 runtime->hw.channels_max = hinfo->channels_max;
1558 runtime->hw.formats = hinfo->formats;
1559 runtime->hw.rates = hinfo->rates;
1560 snd_pcm_limit_hw_rates(runtime);
1561 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
Joachim Deguara5f1545b2007-03-16 15:01:36 +01001562 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1563 128);
1564 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1565 128);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001566 snd_hda_power_up(apcm->codec);
Takashi Iwaid01ce992007-07-27 16:52:19 +02001567 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1568 if (err < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569 azx_release_device(azx_dev);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001570 snd_hda_power_down(apcm->codec);
Ingo Molnar62932df2006-01-16 16:34:20 +01001571 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001572 return err;
1573 }
Takashi Iwai70d321e2009-07-03 23:06:45 +02001574 snd_pcm_limit_hw_rates(runtime);
Takashi Iwaiaba66532009-07-05 11:44:46 +02001575 /* sanity check */
1576 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1577 snd_BUG_ON(!runtime->hw.channels_max) ||
1578 snd_BUG_ON(!runtime->hw.formats) ||
1579 snd_BUG_ON(!runtime->hw.rates)) {
1580 azx_release_device(azx_dev);
1581 hinfo->ops.close(hinfo, apcm->codec, substream);
1582 snd_hda_power_down(apcm->codec);
1583 mutex_unlock(&chip->open_mutex);
1584 return -EINVAL;
1585 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001586 spin_lock_irqsave(&chip->reg_lock, flags);
1587 azx_dev->substream = substream;
1588 azx_dev->running = 0;
1589 spin_unlock_irqrestore(&chip->reg_lock, flags);
1590
1591 runtime->private_data = azx_dev;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001592 snd_pcm_set_sync(substream);
Ingo Molnar62932df2006-01-16 16:34:20 +01001593 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594 return 0;
1595}
1596
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001597static int azx_pcm_close(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598{
1599 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1600 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001601 struct azx *chip = apcm->chip;
1602 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603 unsigned long flags;
1604
Ingo Molnar62932df2006-01-16 16:34:20 +01001605 mutex_lock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606 spin_lock_irqsave(&chip->reg_lock, flags);
1607 azx_dev->substream = NULL;
1608 azx_dev->running = 0;
1609 spin_unlock_irqrestore(&chip->reg_lock, flags);
1610 azx_release_device(azx_dev);
1611 hinfo->ops.close(hinfo, apcm->codec, substream);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001612 snd_hda_power_down(apcm->codec);
Ingo Molnar62932df2006-01-16 16:34:20 +01001613 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614 return 0;
1615}
1616
Takashi Iwaid01ce992007-07-27 16:52:19 +02001617static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1618 struct snd_pcm_hw_params *hw_params)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001619{
Takashi Iwai97b71c92009-03-18 15:09:13 +01001620 struct azx_dev *azx_dev = get_azx_dev(substream);
1621
1622 azx_dev->bufsize = 0;
1623 azx_dev->period_bytes = 0;
1624 azx_dev->format_val = 0;
Takashi Iwaid01ce992007-07-27 16:52:19 +02001625 return snd_pcm_lib_malloc_pages(substream,
1626 params_buffer_bytes(hw_params));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627}
1628
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001629static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630{
1631 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001632 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001633 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1634
1635 /* reset BDL address */
1636 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1637 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1638 azx_sd_writel(azx_dev, SD_CTL, 0);
Takashi Iwai97b71c92009-03-18 15:09:13 +01001639 azx_dev->bufsize = 0;
1640 azx_dev->period_bytes = 0;
1641 azx_dev->format_val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001642
Takashi Iwaieb541332010-08-06 13:48:11 +02001643 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001644
1645 return snd_pcm_lib_free_pages(substream);
1646}
1647
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001648static int azx_pcm_prepare(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649{
1650 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001651 struct azx *chip = apcm->chip;
1652 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001653 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001654 struct snd_pcm_runtime *runtime = substream->runtime;
Takashi Iwai62b7e5e2010-10-22 17:15:47 +02001655 unsigned int bufsize, period_bytes, format_val, stream_tag;
Takashi Iwai97b71c92009-03-18 15:09:13 +01001656 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001657
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001658 azx_stream_reset(chip, azx_dev);
Takashi Iwai97b71c92009-03-18 15:09:13 +01001659 format_val = snd_hda_calc_stream_format(runtime->rate,
1660 runtime->channels,
1661 runtime->format,
Anssi Hannula32c168c2010-08-03 13:28:57 +03001662 hinfo->maxbps,
1663 apcm->codec->spdif_ctls);
Takashi Iwai97b71c92009-03-18 15:09:13 +01001664 if (!format_val) {
Takashi Iwaid01ce992007-07-27 16:52:19 +02001665 snd_printk(KERN_ERR SFX
1666 "invalid format_val, rate=%d, ch=%d, format=%d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667 runtime->rate, runtime->channels, runtime->format);
1668 return -EINVAL;
1669 }
1670
Takashi Iwai97b71c92009-03-18 15:09:13 +01001671 bufsize = snd_pcm_lib_buffer_bytes(substream);
1672 period_bytes = snd_pcm_lib_period_bytes(substream);
1673
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001674 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
Takashi Iwai97b71c92009-03-18 15:09:13 +01001675 bufsize, format_val);
1676
1677 if (bufsize != azx_dev->bufsize ||
1678 period_bytes != azx_dev->period_bytes ||
1679 format_val != azx_dev->format_val) {
1680 azx_dev->bufsize = bufsize;
1681 azx_dev->period_bytes = period_bytes;
1682 azx_dev->format_val = format_val;
1683 err = azx_setup_periods(chip, substream, azx_dev);
1684 if (err < 0)
1685 return err;
1686 }
1687
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001688 /* wallclk has 24Mhz clock source */
1689 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1690 runtime->rate) * 1000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691 azx_setup_controller(chip, azx_dev);
1692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1693 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1694 else
1695 azx_dev->fifo_size = 0;
1696
Takashi Iwai62b7e5e2010-10-22 17:15:47 +02001697 stream_tag = azx_dev->stream_tag;
1698 /* CA-IBG chips need the playback stream starting from 1 */
1699 if (chip->driver_type == AZX_DRIVER_CTX &&
1700 stream_tag > chip->capture_streams)
1701 stream_tag -= chip->capture_streams;
1702 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
Takashi Iwaieb541332010-08-06 13:48:11 +02001703 azx_dev->format_val, substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001704}
1705
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001706static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001707{
1708 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001709 struct azx *chip = apcm->chip;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001710 struct azx_dev *azx_dev;
1711 struct snd_pcm_substream *s;
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001712 int rstart = 0, start, nsync = 0, sbits = 0;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001713 int nwait, timeout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001714
Linus Torvalds1da177e2005-04-16 15:20:36 -07001715 switch (cmd) {
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001716 case SNDRV_PCM_TRIGGER_START:
1717 rstart = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1719 case SNDRV_PCM_TRIGGER_RESUME:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001720 start = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721 break;
1722 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Jaroslav Kysela47123192005-08-15 20:53:07 +02001723 case SNDRV_PCM_TRIGGER_SUSPEND:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724 case SNDRV_PCM_TRIGGER_STOP:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001725 start = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001726 break;
1727 default:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001728 return -EINVAL;
1729 }
1730
1731 snd_pcm_group_for_each_entry(s, substream) {
1732 if (s->pcm->card != substream->pcm->card)
1733 continue;
1734 azx_dev = get_azx_dev(s);
1735 sbits |= 1 << azx_dev->index;
1736 nsync++;
1737 snd_pcm_trigger_done(s, substream);
1738 }
1739
1740 spin_lock(&chip->reg_lock);
1741 if (nsync > 1) {
1742 /* first, set SYNC bits of corresponding streams */
1743 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1744 }
1745 snd_pcm_group_for_each_entry(s, substream) {
1746 if (s->pcm->card != substream->pcm->card)
1747 continue;
1748 azx_dev = get_azx_dev(s);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001749 if (start) {
1750 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1751 if (!rstart)
1752 azx_dev->start_wallclk -=
1753 azx_dev->period_wallclk;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001754 azx_stream_start(chip, azx_dev);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001755 } else {
Takashi Iwai850f0e52008-03-18 17:11:05 +01001756 azx_stream_stop(chip, azx_dev);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001757 }
Takashi Iwai850f0e52008-03-18 17:11:05 +01001758 azx_dev->running = start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759 }
1760 spin_unlock(&chip->reg_lock);
Takashi Iwai850f0e52008-03-18 17:11:05 +01001761 if (start) {
1762 if (nsync == 1)
1763 return 0;
1764 /* wait until all FIFOs get ready */
1765 for (timeout = 5000; timeout; timeout--) {
1766 nwait = 0;
1767 snd_pcm_group_for_each_entry(s, substream) {
1768 if (s->pcm->card != substream->pcm->card)
1769 continue;
1770 azx_dev = get_azx_dev(s);
1771 if (!(azx_sd_readb(azx_dev, SD_STS) &
1772 SD_STS_FIFO_READY))
1773 nwait++;
1774 }
1775 if (!nwait)
1776 break;
1777 cpu_relax();
1778 }
1779 } else {
1780 /* wait until all RUN bits are cleared */
1781 for (timeout = 5000; timeout; timeout--) {
1782 nwait = 0;
1783 snd_pcm_group_for_each_entry(s, substream) {
1784 if (s->pcm->card != substream->pcm->card)
1785 continue;
1786 azx_dev = get_azx_dev(s);
1787 if (azx_sd_readb(azx_dev, SD_CTL) &
1788 SD_CTL_DMA_START)
1789 nwait++;
1790 }
1791 if (!nwait)
1792 break;
1793 cpu_relax();
1794 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795 }
Takashi Iwai850f0e52008-03-18 17:11:05 +01001796 if (nsync > 1) {
1797 spin_lock(&chip->reg_lock);
1798 /* reset SYNC bits */
1799 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1800 spin_unlock(&chip->reg_lock);
1801 }
1802 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803}
1804
Joseph Chan0e153472008-08-26 14:38:03 +02001805/* get the current DMA position with correction on VIA chips */
1806static unsigned int azx_via_get_position(struct azx *chip,
1807 struct azx_dev *azx_dev)
1808{
1809 unsigned int link_pos, mini_pos, bound_pos;
1810 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1811 unsigned int fifo_size;
1812
1813 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1814 if (azx_dev->index >= 4) {
1815 /* Playback, no problem using link position */
1816 return link_pos;
1817 }
1818
1819 /* Capture */
1820 /* For new chipset,
1821 * use mod to get the DMA position just like old chipset
1822 */
1823 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1824 mod_dma_pos %= azx_dev->period_bytes;
1825
1826 /* azx_dev->fifo_size can't get FIFO size of in stream.
1827 * Get from base address + offset.
1828 */
1829 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1830
1831 if (azx_dev->insufficient) {
1832 /* Link position never gather than FIFO size */
1833 if (link_pos <= fifo_size)
1834 return 0;
1835
1836 azx_dev->insufficient = 0;
1837 }
1838
1839 if (link_pos <= fifo_size)
1840 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1841 else
1842 mini_pos = link_pos - fifo_size;
1843
1844 /* Find nearest previous boudary */
1845 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1846 mod_link_pos = link_pos % azx_dev->period_bytes;
1847 if (mod_link_pos >= fifo_size)
1848 bound_pos = link_pos - mod_link_pos;
1849 else if (mod_dma_pos >= mod_mini_pos)
1850 bound_pos = mini_pos - mod_mini_pos;
1851 else {
1852 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1853 if (bound_pos >= azx_dev->bufsize)
1854 bound_pos = 0;
1855 }
1856
1857 /* Calculate real DMA position we want */
1858 return bound_pos + mod_dma_pos;
1859}
1860
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001861static unsigned int azx_get_position(struct azx *chip,
1862 struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001863{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001864 unsigned int pos;
David Henningsson4cb36312010-09-30 10:12:50 +02001865 int stream = azx_dev->substream->stream;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866
David Henningsson4cb36312010-09-30 10:12:50 +02001867 switch (chip->position_fix[stream]) {
1868 case POS_FIX_LPIB:
1869 /* read LPIB */
1870 pos = azx_sd_readl(azx_dev, SD_LPIB);
1871 break;
1872 case POS_FIX_VIACOMBO:
Joseph Chan0e153472008-08-26 14:38:03 +02001873 pos = azx_via_get_position(chip, azx_dev);
David Henningsson4cb36312010-09-30 10:12:50 +02001874 break;
1875 default:
1876 /* use the position buffer */
1877 pos = le32_to_cpu(*azx_dev->posbuf);
Takashi Iwaic74db862005-05-12 14:26:27 +02001878 }
David Henningsson4cb36312010-09-30 10:12:50 +02001879
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880 if (pos >= azx_dev->bufsize)
1881 pos = 0;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001882 return pos;
1883}
1884
1885static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1886{
1887 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1888 struct azx *chip = apcm->chip;
1889 struct azx_dev *azx_dev = get_azx_dev(substream);
1890 return bytes_to_frames(substream->runtime,
1891 azx_get_position(chip, azx_dev));
1892}
1893
1894/*
1895 * Check whether the current DMA position is acceptable for updating
1896 * periods. Returns non-zero if it's OK.
1897 *
1898 * Many HD-audio controllers appear pretty inaccurate about
1899 * the update-IRQ timing. The IRQ is issued before actually the
1900 * data is processed. So, we need to process it afterwords in a
1901 * workqueue.
1902 */
1903static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1904{
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001905 u32 wallclk;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001906 unsigned int pos;
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02001907 int stream;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001908
Jaroslav Kyselaf48f6062010-05-11 12:10:47 +02001909 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1910 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001911 return -1; /* bogus (too early) interrupt */
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001912
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02001913 stream = azx_dev->substream->stream;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001914 pos = azx_get_position(chip, azx_dev);
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02001915 if (chip->position_fix[stream] == POS_FIX_AUTO) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001916 if (!pos) {
1917 printk(KERN_WARNING
1918 "hda-intel: Invalid position buffer, "
1919 "using LPIB read method instead.\n");
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02001920 chip->position_fix[stream] = POS_FIX_LPIB;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001921 pos = azx_get_position(chip, azx_dev);
1922 } else
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02001923 chip->position_fix[stream] = POS_FIX_POSBUF;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001924 }
1925
Takashi Iwaid6d8bf52010-02-12 18:17:06 +01001926 if (WARN_ONCE(!azx_dev->period_bytes,
1927 "hda-intel: zero azx_dev->period_bytes"))
Jaroslav Kyselaf48f6062010-05-11 12:10:47 +02001928 return -1; /* this shouldn't happen! */
Jaroslav Kyselaedb39932010-06-02 13:29:17 +02001929 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
Jaroslav Kyselaf48f6062010-05-11 12:10:47 +02001930 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1931 /* NG - it's below the first next period boundary */
1932 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
Jaroslav Kyselaedb39932010-06-02 13:29:17 +02001933 azx_dev->start_wallclk += wallclk;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001934 return 1; /* OK, it's fine */
1935}
1936
1937/*
1938 * The work for pending PCM period updates.
1939 */
1940static void azx_irq_pending_work(struct work_struct *work)
1941{
1942 struct azx *chip = container_of(work, struct azx, irq_pending_work);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001943 int i, pending, ok;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001944
Takashi Iwaia6a950a2008-06-10 17:53:35 +02001945 if (!chip->irq_pending_warned) {
1946 printk(KERN_WARNING
1947 "hda-intel: IRQ timing workaround is activated "
1948 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1949 chip->card->number);
1950 chip->irq_pending_warned = 1;
1951 }
1952
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001953 for (;;) {
1954 pending = 0;
1955 spin_lock_irq(&chip->reg_lock);
1956 for (i = 0; i < chip->num_streams; i++) {
1957 struct azx_dev *azx_dev = &chip->azx_dev[i];
1958 if (!azx_dev->irq_pending ||
1959 !azx_dev->substream ||
1960 !azx_dev->running)
1961 continue;
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001962 ok = azx_position_ok(chip, azx_dev);
1963 if (ok > 0) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001964 azx_dev->irq_pending = 0;
1965 spin_unlock(&chip->reg_lock);
1966 snd_pcm_period_elapsed(azx_dev->substream);
1967 spin_lock(&chip->reg_lock);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001968 } else if (ok < 0) {
1969 pending = 0; /* too early */
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001970 } else
1971 pending++;
1972 }
1973 spin_unlock_irq(&chip->reg_lock);
1974 if (!pending)
1975 return;
Takashi Iwai08af4952010-08-03 14:39:04 +02001976 msleep(1);
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001977 }
1978}
1979
1980/* clear irq_pending flags and assure no on-going workq */
1981static void azx_clear_irq_pending(struct azx *chip)
1982{
1983 int i;
1984
1985 spin_lock_irq(&chip->reg_lock);
1986 for (i = 0; i < chip->num_streams; i++)
1987 chip->azx_dev[i].irq_pending = 0;
1988 spin_unlock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989}
1990
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001991static struct snd_pcm_ops azx_pcm_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001992 .open = azx_pcm_open,
1993 .close = azx_pcm_close,
1994 .ioctl = snd_pcm_lib_ioctl,
1995 .hw_params = azx_pcm_hw_params,
1996 .hw_free = azx_pcm_hw_free,
1997 .prepare = azx_pcm_prepare,
1998 .trigger = azx_pcm_trigger,
1999 .pointer = azx_pcm_pointer,
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002000 .page = snd_pcm_sgbuf_ops_page,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002001};
2002
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002003static void azx_pcm_free(struct snd_pcm *pcm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002004{
Takashi Iwai176d5332008-07-30 15:01:44 +02002005 struct azx_pcm *apcm = pcm->private_data;
2006 if (apcm) {
2007 apcm->chip->pcm[pcm->device] = NULL;
2008 kfree(apcm);
2009 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002010}
2011
Takashi Iwai176d5332008-07-30 15:01:44 +02002012static int
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002013azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2014 struct hda_pcm *cpcm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002015{
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002016 struct azx *chip = bus->private_data;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002017 struct snd_pcm *pcm;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002018 struct azx_pcm *apcm;
Takashi Iwai176d5332008-07-30 15:01:44 +02002019 int pcm_dev = cpcm->device;
2020 int s, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002021
Takashi Iwaic8936222010-01-28 17:08:53 +01002022 if (pcm_dev >= HDA_MAX_PCMS) {
Takashi Iwai176d5332008-07-30 15:01:44 +02002023 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2024 pcm_dev);
Takashi Iwaida3cec32008-08-08 17:12:14 +02002025 return -EINVAL;
Takashi Iwai176d5332008-07-30 15:01:44 +02002026 }
2027 if (chip->pcm[pcm_dev]) {
2028 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2029 return -EBUSY;
2030 }
2031 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2032 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2033 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002034 &pcm);
2035 if (err < 0)
2036 return err;
Takashi Iwai18cb7102009-04-16 10:22:24 +02002037 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
Takashi Iwai176d5332008-07-30 15:01:44 +02002038 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002039 if (apcm == NULL)
2040 return -ENOMEM;
2041 apcm->chip = chip;
2042 apcm->codec = codec;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043 pcm->private_data = apcm;
2044 pcm->private_free = azx_pcm_free;
Takashi Iwai176d5332008-07-30 15:01:44 +02002045 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2046 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2047 chip->pcm[pcm_dev] = pcm;
2048 cpcm->pcm = pcm;
2049 for (s = 0; s < 2; s++) {
2050 apcm->hinfo[s] = &cpcm->stream[s];
2051 if (cpcm->stream[s].substreams)
2052 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2053 }
2054 /* buffer pre-allocation */
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002055 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002056 snd_dma_pci_data(chip->pci),
Takashi Iwaifc4abee2008-07-30 15:13:34 +02002057 1024 * 64, 32 * 1024 * 1024);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058 return 0;
2059}
2060
2061/*
2062 * mixer creation - all stuff is implemented in hda module
2063 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002064static int __devinit azx_mixer_create(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002065{
2066 return snd_hda_build_controls(chip->bus);
2067}
2068
2069
2070/*
2071 * initialize SD streams
2072 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002073static int __devinit azx_init_stream(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002074{
2075 int i;
2076
2077 /* initialize each stream (aka device)
Takashi Iwaid01ce992007-07-27 16:52:19 +02002078 * assign the starting bdl address to each stream (device)
2079 * and initialize
Linus Torvalds1da177e2005-04-16 15:20:36 -07002080 */
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002081 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002082 struct azx_dev *azx_dev = &chip->azx_dev[i];
Takashi Iwai929861c2006-08-31 16:55:40 +02002083 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002084 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2085 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2086 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2087 azx_dev->sd_int_sta_mask = 1 << i;
2088 /* stream tag: must be non-zero and unique */
2089 azx_dev->index = i;
2090 azx_dev->stream_tag = i + 1;
2091 }
2092
2093 return 0;
2094}
2095
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002096static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2097{
Takashi Iwai437a5a42006-11-21 12:14:23 +01002098 if (request_irq(chip->pci->irq, azx_interrupt,
2099 chip->msi ? 0 : IRQF_SHARED,
Maxim Levitsky94928372010-02-04 22:26:37 +02002100 "hda_intel", chip)) {
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002101 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2102 "disabling device\n", chip->pci->irq);
2103 if (do_disconnect)
2104 snd_card_disconnect(chip->card);
2105 return -1;
2106 }
2107 chip->irq = chip->pci->irq;
Takashi Iwai69e13412006-11-21 12:10:55 +01002108 pci_intx(chip->pci, !chip->msi);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002109 return 0;
2110}
2111
Linus Torvalds1da177e2005-04-16 15:20:36 -07002112
Takashi Iwaicb53c622007-08-10 17:21:45 +02002113static void azx_stop_chip(struct azx *chip)
2114{
Takashi Iwai95e99fd2007-08-13 15:29:04 +02002115 if (!chip->initialized)
Takashi Iwaicb53c622007-08-10 17:21:45 +02002116 return;
2117
2118 /* disable interrupts */
2119 azx_int_disable(chip);
2120 azx_int_clear(chip);
2121
2122 /* disable CORB/RIRB */
2123 azx_free_cmd_io(chip);
2124
2125 /* disable position buffer */
2126 azx_writel(chip, DPLBASE, 0);
2127 azx_writel(chip, DPUBASE, 0);
2128
2129 chip->initialized = 0;
2130}
2131
2132#ifdef CONFIG_SND_HDA_POWER_SAVE
2133/* power-up/down the controller */
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002134static void azx_power_notify(struct hda_bus *bus)
Takashi Iwaicb53c622007-08-10 17:21:45 +02002135{
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002136 struct azx *chip = bus->private_data;
Takashi Iwaicb53c622007-08-10 17:21:45 +02002137 struct hda_codec *c;
2138 int power_on = 0;
2139
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002140 list_for_each_entry(c, &bus->codec_list, list) {
Takashi Iwaicb53c622007-08-10 17:21:45 +02002141 if (c->power_on) {
2142 power_on = 1;
2143 break;
2144 }
2145 }
2146 if (power_on)
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01002147 azx_init_chip(chip, 1);
Wu Fengguang0287d972009-12-11 20:15:11 +08002148 else if (chip->running && power_save_controller &&
2149 !bus->power_keep_link_on)
Takashi Iwaicb53c622007-08-10 17:21:45 +02002150 azx_stop_chip(chip);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002151}
Takashi Iwai5c0b9be2008-12-11 11:47:17 +01002152#endif /* CONFIG_SND_HDA_POWER_SAVE */
2153
2154#ifdef CONFIG_PM
2155/*
2156 * power management
2157 */
Takashi Iwai986862bd2008-11-27 12:40:13 +01002158
2159static int snd_hda_codecs_inuse(struct hda_bus *bus)
2160{
2161 struct hda_codec *codec;
2162
2163 list_for_each_entry(codec, &bus->codec_list, list) {
2164 if (snd_hda_codec_needs_resume(codec))
2165 return 1;
2166 }
2167 return 0;
2168}
Takashi Iwaicb53c622007-08-10 17:21:45 +02002169
Takashi Iwai421a1252005-11-17 16:11:09 +01002170static int azx_suspend(struct pci_dev *pci, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002171{
Takashi Iwai421a1252005-11-17 16:11:09 +01002172 struct snd_card *card = pci_get_drvdata(pci);
2173 struct azx *chip = card->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002174 int i;
2175
Takashi Iwai421a1252005-11-17 16:11:09 +01002176 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002177 azx_clear_irq_pending(chip);
Takashi Iwaic8936222010-01-28 17:08:53 +01002178 for (i = 0; i < HDA_MAX_PCMS; i++)
Takashi Iwai421a1252005-11-17 16:11:09 +01002179 snd_pcm_suspend_all(chip->pcm[i]);
Takashi Iwai0b7a2e92007-08-14 15:18:26 +02002180 if (chip->initialized)
Takashi Iwai8dd78332009-06-02 01:16:07 +02002181 snd_hda_suspend(chip->bus);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002182 azx_stop_chip(chip);
Takashi Iwai30b35392006-10-11 18:52:53 +02002183 if (chip->irq >= 0) {
Takashi Iwai43001c92006-09-08 12:30:03 +02002184 free_irq(chip->irq, chip);
Takashi Iwai30b35392006-10-11 18:52:53 +02002185 chip->irq = -1;
2186 }
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002187 if (chip->msi)
Takashi Iwai43001c92006-09-08 12:30:03 +02002188 pci_disable_msi(chip->pci);
Takashi Iwai421a1252005-11-17 16:11:09 +01002189 pci_disable_device(pci);
2190 pci_save_state(pci);
Takashi Iwai30b35392006-10-11 18:52:53 +02002191 pci_set_power_state(pci, pci_choose_state(pci, state));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002192 return 0;
2193}
2194
Takashi Iwai421a1252005-11-17 16:11:09 +01002195static int azx_resume(struct pci_dev *pci)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002196{
Takashi Iwai421a1252005-11-17 16:11:09 +01002197 struct snd_card *card = pci_get_drvdata(pci);
2198 struct azx *chip = card->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002199
Takashi Iwaid14a7e02009-02-16 10:13:03 +01002200 pci_set_power_state(pci, PCI_D0);
2201 pci_restore_state(pci);
Takashi Iwai30b35392006-10-11 18:52:53 +02002202 if (pci_enable_device(pci) < 0) {
2203 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2204 "disabling device\n");
2205 snd_card_disconnect(card);
2206 return -EIO;
2207 }
2208 pci_set_master(pci);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002209 if (chip->msi)
2210 if (pci_enable_msi(pci) < 0)
2211 chip->msi = 0;
2212 if (azx_acquire_irq(chip, 1) < 0)
Takashi Iwai30b35392006-10-11 18:52:53 +02002213 return -EIO;
Takashi Iwaicb53c622007-08-10 17:21:45 +02002214 azx_init_pci(chip);
Maxim Levitskyd804ad92007-09-03 15:28:04 +02002215
2216 if (snd_hda_codecs_inuse(chip->bus))
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01002217 azx_init_chip(chip, 1);
Maxim Levitskyd804ad92007-09-03 15:28:04 +02002218
Linus Torvalds1da177e2005-04-16 15:20:36 -07002219 snd_hda_resume(chip->bus);
Takashi Iwai421a1252005-11-17 16:11:09 +01002220 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002221 return 0;
2222}
2223#endif /* CONFIG_PM */
2224
2225
2226/*
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002227 * reboot notifier for hang-up problem at power-down
2228 */
2229static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2230{
2231 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
Takashi Iwaifb8d1a32009-11-10 16:02:29 +01002232 snd_hda_bus_reboot_notify(chip->bus);
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002233 azx_stop_chip(chip);
2234 return NOTIFY_OK;
2235}
2236
2237static void azx_notifier_register(struct azx *chip)
2238{
2239 chip->reboot_notifier.notifier_call = azx_halt;
2240 register_reboot_notifier(&chip->reboot_notifier);
2241}
2242
2243static void azx_notifier_unregister(struct azx *chip)
2244{
2245 if (chip->reboot_notifier.notifier_call)
2246 unregister_reboot_notifier(&chip->reboot_notifier);
2247}
2248
2249/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002250 * destructor
2251 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002252static int azx_free(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002253{
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002254 int i;
2255
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002256 azx_notifier_unregister(chip);
2257
Takashi Iwaice43fba2005-05-30 20:33:44 +02002258 if (chip->initialized) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002259 azx_clear_irq_pending(chip);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002260 for (i = 0; i < chip->num_streams; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002261 azx_stream_stop(chip, &chip->azx_dev[i]);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002262 azx_stop_chip(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002263 }
2264
Jeff Garzikf000fd82008-04-22 13:50:34 +02002265 if (chip->irq >= 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002266 free_irq(chip->irq, (void*)chip);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002267 if (chip->msi)
Takashi Iwai30b35392006-10-11 18:52:53 +02002268 pci_disable_msi(chip->pci);
Takashi Iwaif079c252006-06-01 11:42:14 +02002269 if (chip->remap_addr)
2270 iounmap(chip->remap_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002271
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002272 if (chip->azx_dev) {
2273 for (i = 0; i < chip->num_streams; i++)
2274 if (chip->azx_dev[i].bdl.area)
2275 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2276 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002277 if (chip->rb.area)
2278 snd_dma_free_pages(&chip->rb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002279 if (chip->posbuf.area)
2280 snd_dma_free_pages(&chip->posbuf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002281 pci_release_regions(chip->pci);
2282 pci_disable_device(chip->pci);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002283 kfree(chip->azx_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002284 kfree(chip);
2285
2286 return 0;
2287}
2288
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002289static int azx_dev_free(struct snd_device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002290{
2291 return azx_free(device->device_data);
2292}
2293
2294/*
Takashi Iwai3372a152007-02-01 15:46:50 +01002295 * white/black-listing for position_fix
2296 */
Ralf Baechle623ec042007-03-13 15:29:47 +01002297static struct snd_pci_quirk position_fix_list[] __devinitdata = {
Daniel T Chen7a68be92010-05-22 12:05:41 -04002298 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
Daniel T Chendd5a0892010-12-05 08:43:14 -05002299 SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
Takashi Iwaid2e1c972008-06-10 17:53:34 +02002300 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2301 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
Daniel T Chen9919c762010-03-03 18:24:26 -05002302 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
Takashi Iwai2f703e72009-12-01 14:17:37 +01002303 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
Takashi Iwaid2e1c972008-06-10 17:53:34 +02002304 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
Daniel T Chendd37f8e2010-05-30 01:17:03 -04002305 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
Daniel T Chen9f75c1b2010-05-30 13:08:41 -04002306 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
Daniel T Chene96d3122010-05-27 18:32:18 -04002307 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
Daniel T Chen4e0938d2010-05-22 13:12:22 -04002308 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2309 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
Daniel T Chen61bb42c2010-05-29 11:04:11 -04002310 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
Daniel T Chen9ec8dda2010-03-28 02:34:40 -04002311 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
Takashi Iwai45d4ebf2009-11-30 11:58:30 +01002312 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
Daniel T Chen0321b692010-03-05 09:04:49 -05002313 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
Takashi Iwai8815cd02010-04-15 09:02:41 +02002314 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
Daniel T Chenb90c0762010-05-30 19:31:41 -04002315 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
Daniel T Chen0e0280d2010-04-21 19:55:43 -04002316 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
Daniel T Chen572c0e32010-03-14 23:44:03 -04002317 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
Takashi Iwai3372a152007-02-01 15:46:50 +01002318 {}
2319};
2320
2321static int __devinit check_position_fix(struct azx *chip, int fix)
2322{
2323 const struct snd_pci_quirk *q;
2324
Takashi Iwaic673ba12009-03-17 07:49:14 +01002325 switch (fix) {
2326 case POS_FIX_LPIB:
2327 case POS_FIX_POSBUF:
David Henningsson4cb36312010-09-30 10:12:50 +02002328 case POS_FIX_VIACOMBO:
Takashi Iwaic673ba12009-03-17 07:49:14 +01002329 return fix;
2330 }
2331
Takashi Iwaic673ba12009-03-17 07:49:14 +01002332 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2333 if (q) {
2334 printk(KERN_INFO
2335 "hda_intel: position_fix set to %d "
2336 "for device %04x:%04x\n",
2337 q->value, q->subvendor, q->subdevice);
2338 return q->value;
Takashi Iwai3372a152007-02-01 15:46:50 +01002339 }
David Henningssonbdd9ef22010-10-04 12:02:14 +02002340
2341 /* Check VIA/ATI HD Audio Controller exist */
2342 switch (chip->driver_type) {
2343 case AZX_DRIVER_VIA:
2344 case AZX_DRIVER_ATI:
2345 /* Use link position directly, avoid any transfer problem. */
2346 return POS_FIX_VIACOMBO;
2347 }
2348
Takashi Iwaic673ba12009-03-17 07:49:14 +01002349 return POS_FIX_AUTO;
Takashi Iwai3372a152007-02-01 15:46:50 +01002350}
2351
2352/*
Takashi Iwai669ba272007-08-17 09:17:36 +02002353 * black-lists for probe_mask
2354 */
2355static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2356 /* Thinkpad often breaks the controller communication when accessing
2357 * to the non-working (or non-existing) modem codec slot.
2358 */
2359 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2360 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2361 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
Takashi Iwai0edb9452008-11-07 14:53:09 +01002362 /* broken BIOS */
2363 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
Takashi Iwaief1681d2008-11-24 17:29:28 +01002364 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2365 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
Takashi Iwai20db7cb2009-02-13 08:18:48 +01002366 /* forced codec slots */
Ozan Çağlayan93574842009-05-23 15:00:04 +03002367 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
Takashi Iwai20db7cb2009-02-13 08:18:48 +01002368 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
Takashi Iwai669ba272007-08-17 09:17:36 +02002369 {}
2370};
2371
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01002372#define AZX_FORCE_CODEC_MASK 0x100
2373
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002374static void __devinit check_probe_mask(struct azx *chip, int dev)
Takashi Iwai669ba272007-08-17 09:17:36 +02002375{
2376 const struct snd_pci_quirk *q;
2377
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01002378 chip->codec_probe_mask = probe_mask[dev];
2379 if (chip->codec_probe_mask == -1) {
Takashi Iwai669ba272007-08-17 09:17:36 +02002380 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2381 if (q) {
2382 printk(KERN_INFO
2383 "hda_intel: probe_mask set to 0x%x "
2384 "for device %04x:%04x\n",
2385 q->value, q->subvendor, q->subdevice);
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01002386 chip->codec_probe_mask = q->value;
Takashi Iwai669ba272007-08-17 09:17:36 +02002387 }
2388 }
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01002389
2390 /* check forced option */
2391 if (chip->codec_probe_mask != -1 &&
2392 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2393 chip->codec_mask = chip->codec_probe_mask & 0xff;
2394 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2395 chip->codec_mask);
2396 }
Takashi Iwai669ba272007-08-17 09:17:36 +02002397}
2398
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002399/*
Takashi Iwai716238552009-09-28 13:14:04 +02002400 * white/black-list for enable_msi
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002401 */
Takashi Iwai716238552009-09-28 13:14:04 +02002402static struct snd_pci_quirk msi_black_list[] __devinitdata = {
Takashi Iwai9dc83982009-12-22 08:15:01 +01002403 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
Takashi Iwai0a27fcf2010-02-15 17:05:28 +01002404 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
Ralf Gerbigecd21622010-03-09 18:25:47 +01002405 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
Michele Ballabio4193d132010-03-06 21:06:46 +01002406 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
Takashi Iwai38155952010-04-04 12:14:03 +02002407 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002408 {}
2409};
2410
2411static void __devinit check_msi(struct azx *chip)
2412{
2413 const struct snd_pci_quirk *q;
2414
Takashi Iwai716238552009-09-28 13:14:04 +02002415 if (enable_msi >= 0) {
2416 chip->msi = !!enable_msi;
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002417 return;
Takashi Iwai716238552009-09-28 13:14:04 +02002418 }
2419 chip->msi = 1; /* enable MSI as default */
2420 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002421 if (q) {
2422 printk(KERN_INFO
2423 "hda_intel: msi for device %04x:%04x set to %d\n",
2424 q->subvendor, q->subdevice, q->value);
2425 chip->msi = q->value;
Takashi Iwai80c43ed2010-03-15 15:51:53 +01002426 return;
2427 }
2428
2429 /* NVidia chipsets seem to cause troubles with MSI */
2430 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2431 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2432 chip->msi = 0;
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002433 }
2434}
2435
Takashi Iwai669ba272007-08-17 09:17:36 +02002436
2437/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002438 * constructor
2439 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002440static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002441 int dev, int driver_type,
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002442 struct azx **rchip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002443{
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002444 struct azx *chip;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002445 int i, err;
Tobin Davisbcd72002008-01-15 11:23:55 +01002446 unsigned short gcap;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002447 static struct snd_device_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002448 .dev_free = azx_dev_free,
2449 };
2450
2451 *rchip = NULL;
Tobin Davisbcd72002008-01-15 11:23:55 +01002452
Pavel Machek927fc862006-08-31 17:03:43 +02002453 err = pci_enable_device(pci);
2454 if (err < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002455 return err;
2456
Takashi Iwaie560d8d2005-09-09 14:21:46 +02002457 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
Pavel Machek927fc862006-08-31 17:03:43 +02002458 if (!chip) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002459 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2460 pci_disable_device(pci);
2461 return -ENOMEM;
2462 }
2463
2464 spin_lock_init(&chip->reg_lock);
Ingo Molnar62932df2006-01-16 16:34:20 +01002465 mutex_init(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002466 chip->card = card;
2467 chip->pci = pci;
2468 chip->irq = -1;
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002469 chip->driver_type = driver_type;
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002470 check_msi(chip);
Takashi Iwai555e2192008-06-10 17:53:34 +02002471 chip->dev_index = dev;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002472 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02002474 chip->position_fix[0] = chip->position_fix[1] =
2475 check_position_fix(chip, position_fix[dev]);
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002476 check_probe_mask(chip, dev);
Takashi Iwai3372a152007-02-01 15:46:50 +01002477
Takashi Iwai27346162006-01-12 18:28:44 +01002478 chip->single_cmd = single_cmd;
Takashi Iwaic74db862005-05-12 14:26:27 +02002479
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002480 if (bdl_pos_adj[dev] < 0) {
2481 switch (chip->driver_type) {
Takashi Iwai0c6341a2008-06-13 20:50:27 +02002482 case AZX_DRIVER_ICH:
Seth Heasley32679f92010-02-22 17:31:09 -08002483 case AZX_DRIVER_PCH:
Takashi Iwai0c6341a2008-06-13 20:50:27 +02002484 bdl_pos_adj[dev] = 1;
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002485 break;
2486 default:
Takashi Iwai0c6341a2008-06-13 20:50:27 +02002487 bdl_pos_adj[dev] = 32;
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002488 break;
2489 }
2490 }
2491
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002492#if BITS_PER_LONG != 64
2493 /* Fix up base address on ULI M5461 */
2494 if (chip->driver_type == AZX_DRIVER_ULI) {
2495 u16 tmp3;
2496 pci_read_config_word(pci, 0x40, &tmp3);
2497 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2498 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2499 }
2500#endif
2501
Pavel Machek927fc862006-08-31 17:03:43 +02002502 err = pci_request_regions(pci, "ICH HD audio");
2503 if (err < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002504 kfree(chip);
2505 pci_disable_device(pci);
2506 return err;
2507 }
2508
Pavel Machek927fc862006-08-31 17:03:43 +02002509 chip->addr = pci_resource_start(pci, 0);
Arjan van de Ven2f5ad542008-09-28 16:20:09 -07002510 chip->remap_addr = pci_ioremap_bar(pci, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002511 if (chip->remap_addr == NULL) {
2512 snd_printk(KERN_ERR SFX "ioremap error\n");
2513 err = -ENXIO;
2514 goto errout;
2515 }
2516
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002517 if (chip->msi)
2518 if (pci_enable_msi(pci) < 0)
2519 chip->msi = 0;
Stephen Hemminger7376d012006-08-21 19:17:46 +02002520
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002521 if (azx_acquire_irq(chip, 0) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002522 err = -EBUSY;
2523 goto errout;
2524 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002525
2526 pci_set_master(pci);
2527 synchronize_irq(chip->irq);
2528
Tobin Davisbcd72002008-01-15 11:23:55 +01002529 gcap = azx_readw(chip, GCAP);
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02002530 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
Tobin Davisbcd72002008-01-15 11:23:55 +01002531
Andiry Brienzadc4c2e62009-07-08 13:55:31 +08002532 /* disable SB600 64bit support for safety */
2533 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2534 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2535 struct pci_dev *p_smbus;
2536 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2537 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2538 NULL);
2539 if (p_smbus) {
2540 if (p_smbus->revision < 0x30)
2541 gcap &= ~ICH6_GCAP_64OK;
2542 pci_dev_put(p_smbus);
2543 }
2544 }
Takashi Iwai09240cf2009-03-17 07:47:18 +01002545
Jaroslav Kysela396087e2009-12-09 10:44:47 +01002546 /* disable 64bit DMA address for Teradici */
2547 /* it does not work with device 6549:1200 subsys e4a2:040b */
2548 if (chip->driver_type == AZX_DRIVER_TERA)
2549 gcap &= ~ICH6_GCAP_64OK;
2550
Takashi Iwaicf7aaca2008-02-06 15:05:57 +01002551 /* allow 64bit DMA address if supported by H/W */
Takashi Iwaib21fadb2009-05-28 12:26:15 +02002552 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
Yang Hongyange9304382009-04-13 14:40:14 -07002553 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
Takashi Iwai09240cf2009-03-17 07:47:18 +01002554 else {
Yang Hongyange9304382009-04-13 14:40:14 -07002555 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2556 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
Takashi Iwai09240cf2009-03-17 07:47:18 +01002557 }
Takashi Iwaicf7aaca2008-02-06 15:05:57 +01002558
Takashi Iwai8b6ed8e2008-02-19 11:36:35 +01002559 /* read number of streams from GCAP register instead of using
2560 * hardcoded value
2561 */
2562 chip->capture_streams = (gcap >> 8) & 0x0f;
2563 chip->playback_streams = (gcap >> 12) & 0x0f;
2564 if (!chip->playback_streams && !chip->capture_streams) {
Tobin Davisbcd72002008-01-15 11:23:55 +01002565 /* gcap didn't give any info, switching to old method */
2566
2567 switch (chip->driver_type) {
2568 case AZX_DRIVER_ULI:
2569 chip->playback_streams = ULI_NUM_PLAYBACK;
2570 chip->capture_streams = ULI_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002571 break;
2572 case AZX_DRIVER_ATIHDMI:
2573 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2574 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002575 break;
Yang, Libinc4da29c2008-11-13 11:07:07 +01002576 case AZX_DRIVER_GENERIC:
Tobin Davisbcd72002008-01-15 11:23:55 +01002577 default:
2578 chip->playback_streams = ICH6_NUM_PLAYBACK;
2579 chip->capture_streams = ICH6_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002580 break;
2581 }
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002582 }
Takashi Iwai8b6ed8e2008-02-19 11:36:35 +01002583 chip->capture_index_offset = 0;
2584 chip->playback_index_offset = chip->capture_streams;
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002585 chip->num_streams = chip->playback_streams + chip->capture_streams;
Takashi Iwaid01ce992007-07-27 16:52:19 +02002586 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2587 GFP_KERNEL);
Pavel Machek927fc862006-08-31 17:03:43 +02002588 if (!chip->azx_dev) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02002589 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002590 goto errout;
2591 }
2592
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002593 for (i = 0; i < chip->num_streams; i++) {
2594 /* allocate memory for the BDL for each stream */
2595 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2596 snd_dma_pci_data(chip->pci),
2597 BDL_SIZE, &chip->azx_dev[i].bdl);
2598 if (err < 0) {
2599 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2600 goto errout;
2601 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002602 }
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02002603 /* allocate memory for the position buffer */
Takashi Iwaid01ce992007-07-27 16:52:19 +02002604 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2605 snd_dma_pci_data(chip->pci),
2606 chip->num_streams * 8, &chip->posbuf);
2607 if (err < 0) {
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02002608 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2609 goto errout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002610 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002611 /* allocate CORB/RIRB */
Takashi Iwai817408612009-05-26 15:22:00 +02002612 err = azx_alloc_cmd_io(chip);
2613 if (err < 0)
2614 goto errout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002615
2616 /* initialize streams */
2617 azx_init_stream(chip);
2618
2619 /* initialize chip */
Takashi Iwaicb53c622007-08-10 17:21:45 +02002620 azx_init_pci(chip);
Jaroslav Kysela10e77dd2010-03-26 11:04:38 +01002621 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002622
2623 /* codec detection */
Pavel Machek927fc862006-08-31 17:03:43 +02002624 if (!chip->codec_mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002625 snd_printk(KERN_ERR SFX "no codecs found!\n");
2626 err = -ENODEV;
2627 goto errout;
2628 }
2629
Takashi Iwaid01ce992007-07-27 16:52:19 +02002630 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2631 if (err <0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002632 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2633 goto errout;
2634 }
2635
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002636 strcpy(card->driver, "HDA-Intel");
Takashi Iwai18cb7102009-04-16 10:22:24 +02002637 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2638 sizeof(card->shortname));
2639 snprintf(card->longname, sizeof(card->longname),
2640 "%s at 0x%lx irq %i",
2641 card->shortname, chip->addr, chip->irq);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002642
Linus Torvalds1da177e2005-04-16 15:20:36 -07002643 *rchip = chip;
2644 return 0;
2645
2646 errout:
2647 azx_free(chip);
2648 return err;
2649}
2650
Takashi Iwaicb53c622007-08-10 17:21:45 +02002651static void power_down_all_codecs(struct azx *chip)
2652{
2653#ifdef CONFIG_SND_HDA_POWER_SAVE
2654 /* The codecs were powered up in snd_hda_codec_new().
2655 * Now all initialization done, so turn them down if possible
2656 */
2657 struct hda_codec *codec;
2658 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2659 snd_hda_power_down(codec);
2660 }
2661#endif
2662}
2663
Takashi Iwaid01ce992007-07-27 16:52:19 +02002664static int __devinit azx_probe(struct pci_dev *pci,
2665 const struct pci_device_id *pci_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002666{
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002667 static int dev;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002668 struct snd_card *card;
2669 struct azx *chip;
Pavel Machek927fc862006-08-31 17:03:43 +02002670 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002671
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002672 if (dev >= SNDRV_CARDS)
2673 return -ENODEV;
2674 if (!enable[dev]) {
2675 dev++;
2676 return -ENOENT;
2677 }
2678
Takashi Iwaie58de7b2008-12-28 16:44:30 +01002679 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2680 if (err < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002681 snd_printk(KERN_ERR SFX "Error creating card!\n");
Takashi Iwaie58de7b2008-12-28 16:44:30 +01002682 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002683 }
2684
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +02002685 /* set this here since it's referred in snd_hda_load_patch() */
2686 snd_card_set_dev(card, &pci->dev);
2687
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002688 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002689 if (err < 0)
2690 goto out_free;
Takashi Iwai421a1252005-11-17 16:11:09 +01002691 card->private_data = chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002692
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +01002693#ifdef CONFIG_SND_HDA_INPUT_BEEP
2694 chip->beep_mode = beep_mode[dev];
2695#endif
2696
Linus Torvalds1da177e2005-04-16 15:20:36 -07002697 /* create codec instances */
Takashi Iwaia1e21c92009-06-17 09:33:52 +02002698 err = azx_codec_create(chip, model[dev]);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002699 if (err < 0)
2700 goto out_free;
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +02002701#ifdef CONFIG_SND_HDA_PATCH_LOADER
2702 if (patch[dev]) {
2703 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2704 patch[dev]);
2705 err = snd_hda_load_patch(chip->bus, patch[dev]);
2706 if (err < 0)
2707 goto out_free;
2708 }
2709#endif
Jaroslav Kysela10e77dd2010-03-26 11:04:38 +01002710 if ((probe_only[dev] & 1) == 0) {
Takashi Iwaia1e21c92009-06-17 09:33:52 +02002711 err = azx_codec_configure(chip);
2712 if (err < 0)
2713 goto out_free;
2714 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002715
2716 /* create PCM streams */
Takashi Iwai176d5332008-07-30 15:01:44 +02002717 err = snd_hda_build_pcms(chip->bus);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002718 if (err < 0)
2719 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002720
2721 /* create mixer controls */
Takashi Iwaid01ce992007-07-27 16:52:19 +02002722 err = azx_mixer_create(chip);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002723 if (err < 0)
2724 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002725
Takashi Iwaid01ce992007-07-27 16:52:19 +02002726 err = snd_card_register(card);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002727 if (err < 0)
2728 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002729
2730 pci_set_drvdata(pci, card);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002731 chip->running = 1;
2732 power_down_all_codecs(chip);
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002733 azx_notifier_register(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002734
Andrew Paprockie25bcdb2008-01-13 11:57:17 +01002735 dev++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002736 return err;
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002737out_free:
2738 snd_card_free(card);
2739 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002740}
2741
2742static void __devexit azx_remove(struct pci_dev *pci)
2743{
2744 snd_card_free(pci_get_drvdata(pci));
2745 pci_set_drvdata(pci, NULL);
2746}
2747
2748/* PCI IDs */
Alexey Dobriyancebe41d2010-02-06 00:21:03 +02002749static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
Seth Heasleyd2f2fcd2010-01-12 17:03:35 -08002750 /* CPT */
Seth Heasley32679f92010-02-22 17:31:09 -08002751 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
Seth Heasleycea310e2010-09-10 16:29:56 -07002752 /* PBG */
2753 { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH },
Takashi Iwai87218e92008-02-21 08:13:11 +01002754 /* SCH */
2755 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
Takashi Iwaib6864532010-09-15 10:17:26 +02002756 /* Generic Intel */
2757 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2758 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2759 .class_mask = 0xffffff,
2760 .driver_data = AZX_DRIVER_ICH },
Takashi Iwai87218e92008-02-21 08:13:11 +01002761 /* ATI SB 450/600 */
2762 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2763 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2764 /* ATI HDMI */
2765 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2766 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2767 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
Libin Yang9e6dd472008-08-12 12:25:46 +02002768 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
Takashi Iwai87218e92008-02-21 08:13:11 +01002769 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2770 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2771 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2772 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2773 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2774 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2775 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2776 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2777 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2778 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2779 /* VIA VT8251/VT8237A */
2780 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2781 /* SIS966 */
2782 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2783 /* ULI M5461 */
2784 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2785 /* NVIDIA MCP */
Takashi Iwai0c2fd1bf42009-12-18 16:41:39 +01002786 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2787 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2788 .class_mask = 0xffffff,
2789 .driver_data = AZX_DRIVER_NVIDIA },
Kailang Yangf2690022008-05-27 11:44:55 +02002790 /* Teradici */
2791 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
Takashi Iwai4e01f542009-04-16 08:53:34 +02002792 /* Creative X-Fi (CA0110-IBG) */
Takashi Iwai313f6e22009-05-18 12:40:52 +02002793#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2794 /* the following entry conflicts with snd-ctxfi driver,
2795 * as ctxfi driver mutates from HD-audio to native mode with
2796 * a special command sequence.
2797 */
Takashi Iwai4e01f542009-04-16 08:53:34 +02002798 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2799 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2800 .class_mask = 0xffffff,
Takashi Iwai14d34f12010-10-21 09:03:25 +02002801 .driver_data = AZX_DRIVER_CTX },
Takashi Iwai313f6e22009-05-18 12:40:52 +02002802#else
2803 /* this entry seems still valid -- i.e. without emu20kx chip */
Takashi Iwai14d34f12010-10-21 09:03:25 +02002804 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX },
Takashi Iwai313f6e22009-05-18 12:40:52 +02002805#endif
Otavio Salvadore35d4b12010-09-26 23:35:06 -03002806 /* Vortex86MX */
2807 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
Andiry Brienza9176b672009-07-17 11:32:32 +08002808 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
Yang, Libinc4da29c2008-11-13 11:07:07 +01002809 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2810 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2811 .class_mask = 0xffffff,
2812 .driver_data = AZX_DRIVER_GENERIC },
Andiry Brienza9176b672009-07-17 11:32:32 +08002813 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2814 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2815 .class_mask = 0xffffff,
2816 .driver_data = AZX_DRIVER_GENERIC },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002817 { 0, }
2818};
2819MODULE_DEVICE_TABLE(pci, azx_ids);
2820
2821/* pci_driver definition */
2822static struct pci_driver driver = {
2823 .name = "HDA Intel",
2824 .id_table = azx_ids,
2825 .probe = azx_probe,
2826 .remove = __devexit_p(azx_remove),
Takashi Iwai421a1252005-11-17 16:11:09 +01002827#ifdef CONFIG_PM
2828 .suspend = azx_suspend,
2829 .resume = azx_resume,
2830#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002831};
2832
2833static int __init alsa_card_azx_init(void)
2834{
Takashi Iwai01d25d42005-04-11 16:58:24 +02002835 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002836}
2837
2838static void __exit alsa_card_azx_exit(void)
2839{
2840 pci_unregister_driver(&driver);
2841}
2842
2843module_init(alsa_card_azx_init)
2844module_exit(alsa_card_azx_exit)