blob: 406ffd06b6db2fb7bd1fb52dc0cc3dae84255e3f [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Paul Gortmaker9d9779e2011-07-03 15:21:01 -040019#include <linux/module.h>
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070020#include <asm/unaligned.h>
21
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -070022#include "hw.h"
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040023#include "hw-ops.h"
Luis R. Rodriguezcfe8cba2009-09-13 23:39:31 -070024#include "rc.h"
Luis R. Rodriguezb622a722010-04-15 17:39:28 -040025#include "ar9003_mac.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070026
Sujithcbe61d82009-02-09 13:27:12 +053027static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070028
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040029MODULE_AUTHOR("Atheros Communications");
30MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
31MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
32MODULE_LICENSE("Dual BSD/GPL");
33
34static int __init ath9k_init(void)
35{
36 return 0;
37}
38module_init(ath9k_init);
39
40static void __exit ath9k_exit(void)
41{
42 return;
43}
44module_exit(ath9k_exit);
45
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040046/* Private hardware callbacks */
47
48static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49{
50 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
51}
52
53static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54{
55 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
56}
57
Luis R. Rodriguez64773962010-04-15 17:38:17 -040058static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
59 struct ath9k_channel *chan)
60{
61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
62}
63
Luis R. Rodriguez991312d2010-04-15 17:39:05 -040064static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65{
66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
67 return;
68
69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
70}
71
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -040072static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73{
74 /* You will not have this callback if using the old ANI */
75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
76 return;
77
78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
79}
80
Sujithf1dc5602008-10-29 10:16:30 +053081/********************/
82/* Helper Functions */
83/********************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070084
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020085static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +053086{
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -070087 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020088 struct ath_common *common = ath9k_hw_common(ah);
89 unsigned int clockrate;
Sujithcbe61d82009-02-09 13:27:12 +053090
Felix Fietkau087b6ff2011-07-09 11:12:49 +070091 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
92 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
93 clockrate = 117;
94 else if (!ah->curchan) /* should really check for CCK instead */
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020095 clockrate = ATH9K_CLOCK_RATE_CCK;
96 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
97 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
98 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
99 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
Vasanthakumar Thiagarajane5553722010-04-26 15:04:33 -0400100 else
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200101 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
102
103 if (conf_is_ht40(conf))
104 clockrate *= 2;
105
Felix Fietkau906c7202011-07-09 11:12:48 +0700106 if (ah->curchan) {
107 if (IS_CHAN_HALF_RATE(ah->curchan))
108 clockrate /= 2;
109 if (IS_CHAN_QUARTER_RATE(ah->curchan))
110 clockrate /= 4;
111 }
112
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200113 common->clockrate = clockrate;
Sujithf1dc5602008-10-29 10:16:30 +0530114}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700115
Sujithcbe61d82009-02-09 13:27:12 +0530116static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Sujithf1dc5602008-10-29 10:16:30 +0530117{
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200118 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +0530119
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200120 return usecs * common->clockrate;
Sujithf1dc5602008-10-29 10:16:30 +0530121}
122
Sujith0caa7b12009-02-16 13:23:20 +0530123bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700124{
125 int i;
126
Sujith0caa7b12009-02-16 13:23:20 +0530127 BUG_ON(timeout < AH_TIME_QUANTUM);
128
129 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700130 if ((REG_READ(ah, reg) & mask) == val)
131 return true;
132
133 udelay(AH_TIME_QUANTUM);
134 }
Sujith04bd46382008-11-28 22:18:05 +0530135
Joe Perchesd2182b62011-12-15 14:55:53 -0800136 ath_dbg(ath9k_hw_common(ah), ANY,
Joe Perches226afe62010-12-02 19:12:37 -0800137 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
138 timeout, reg, REG_READ(ah, reg), mask, val);
Sujithf1dc5602008-10-29 10:16:30 +0530139
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700140 return false;
141}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400142EXPORT_SYMBOL(ath9k_hw_wait);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700143
Felix Fietkaua9b6b252011-03-23 20:57:27 +0100144void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
145 int column, unsigned int *writecnt)
146{
147 int r;
148
149 ENABLE_REGWRITE_BUFFER(ah);
150 for (r = 0; r < array->ia_rows; r++) {
151 REG_WRITE(ah, INI_RA(array, r, 0),
152 INI_RA(array, r, column));
153 DO_DELAY(*writecnt);
154 }
155 REGWRITE_BUFFER_FLUSH(ah);
156}
157
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700158u32 ath9k_hw_reverse_bits(u32 val, u32 n)
159{
160 u32 retval;
161 int i;
162
163 for (i = 0, retval = 0; i < n; i++) {
164 retval = (retval << 1) | (val & 1);
165 val >>= 1;
166 }
167 return retval;
168}
169
Sujithcbe61d82009-02-09 13:27:12 +0530170u16 ath9k_hw_computetxtime(struct ath_hw *ah,
Felix Fietkau545750d2009-11-23 22:21:01 +0100171 u8 phy, int kbps,
Sujithf1dc5602008-10-29 10:16:30 +0530172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
174{
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
Sujithf1dc5602008-10-29 10:16:30 +0530176
177 if (kbps == 0)
178 return 0;
179
Felix Fietkau545750d2009-11-23 22:21:01 +0100180 switch (phy) {
Sujith46d14a52008-11-18 09:08:13 +0530181 case WLAN_RC_PHY_CCK:
Sujithf1dc5602008-10-29 10:16:30 +0530182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
Felix Fietkau545750d2009-11-23 22:21:01 +0100183 if (shortPreamble)
Sujithf1dc5602008-10-29 10:16:30 +0530184 phyTime >>= 1;
185 numBits = frameLen << 3;
186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
187 break;
Sujith46d14a52008-11-18 09:08:13 +0530188 case WLAN_RC_PHY_OFDM:
Sujith2660b812009-02-09 13:27:26 +0530189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME_QUARTER
194 + OFDM_PREAMBLE_TIME_QUARTER
195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
Sujith2660b812009-02-09 13:27:26 +0530196 } else if (ah->curchan &&
197 IS_CHAN_HALF_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME_HALF +
202 OFDM_PREAMBLE_TIME_HALF
203 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
204 } else {
205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
206 numBits = OFDM_PLCP_BITS + (frameLen << 3);
207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
209 + (numSymbols * OFDM_SYMBOL_TIME);
210 }
211 break;
212 default:
Joe Perches38002762010-12-02 19:12:36 -0800213 ath_err(ath9k_hw_common(ah),
214 "Unknown phy %u (rate ix %u)\n", phy, rateix);
Sujithf1dc5602008-10-29 10:16:30 +0530215 txTime = 0;
216 break;
217 }
218
219 return txTime;
220}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400221EXPORT_SYMBOL(ath9k_hw_computetxtime);
Sujithf1dc5602008-10-29 10:16:30 +0530222
Sujithcbe61d82009-02-09 13:27:12 +0530223void ath9k_hw_get_channel_centers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530224 struct ath9k_channel *chan,
225 struct chan_centers *centers)
226{
227 int8_t extoff;
Sujithf1dc5602008-10-29 10:16:30 +0530228
229 if (!IS_CHAN_HT40(chan)) {
230 centers->ctl_center = centers->ext_center =
231 centers->synth_center = chan->channel;
232 return;
233 }
234
235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
236 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
237 centers->synth_center =
238 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
239 extoff = 1;
240 } else {
241 centers->synth_center =
242 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
243 extoff = -1;
244 }
245
246 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700248 /* 25 MHz spacing is supported by hw but not on upper layers */
Sujithf1dc5602008-10-29 10:16:30 +0530249 centers->ext_center =
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700250 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
Sujithf1dc5602008-10-29 10:16:30 +0530251}
252
253/******************/
254/* Chip Revisions */
255/******************/
256
Sujithcbe61d82009-02-09 13:27:12 +0530257static void ath9k_hw_read_revisions(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530258{
259 u32 val;
260
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530261 switch (ah->hw_version.devid) {
262 case AR5416_AR9100_DEVID:
263 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 break;
Gabor Juhos37625612011-06-21 11:23:23 +0200265 case AR9300_DEVID_AR9330:
266 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
267 if (ah->get_mac_revision) {
268 ah->hw_version.macRev = ah->get_mac_revision();
269 } else {
270 val = REG_READ(ah, AR_SREV);
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 }
273 return;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530274 case AR9300_DEVID_AR9340:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
276 val = REG_READ(ah, AR_SREV);
277 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
278 return;
279 }
280
Sujithf1dc5602008-10-29 10:16:30 +0530281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
282
283 if (val == 0xFF) {
284 val = REG_READ(ah, AR_SREV);
Sujithd535a422009-02-09 13:27:06 +0530285 ah->hw_version.macVersion =
286 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
287 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530288
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530289 if (AR_SREV_9462(ah))
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530290 ah->is_pciexpress = true;
291 else
292 ah->is_pciexpress = (val &
293 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
Sujithf1dc5602008-10-29 10:16:30 +0530294 } else {
295 if (!AR_SREV_9100(ah))
Sujithd535a422009-02-09 13:27:06 +0530296 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
Sujithf1dc5602008-10-29 10:16:30 +0530297
Sujithd535a422009-02-09 13:27:06 +0530298 ah->hw_version.macRev = val & AR_SREV_REVISION;
Sujithf1dc5602008-10-29 10:16:30 +0530299
Sujithd535a422009-02-09 13:27:06 +0530300 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
Sujith2660b812009-02-09 13:27:26 +0530301 ah->is_pciexpress = true;
Sujithf1dc5602008-10-29 10:16:30 +0530302 }
303}
304
Sujithf1dc5602008-10-29 10:16:30 +0530305/************************************/
306/* HW Attach, Detach, Init Routines */
307/************************************/
308
Sujithcbe61d82009-02-09 13:27:12 +0530309static void ath9k_hw_disablepcie(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530310{
Felix Fietkau040b74f2010-12-12 00:51:07 +0100311 if (!AR_SREV_5416(ah))
Sujithf1dc5602008-10-29 10:16:30 +0530312 return;
313
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
323
324 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
325}
326
Stanislaw Gruszkad4930082011-07-29 15:59:08 +0200327static void ath9k_hw_aspm_init(struct ath_hw *ah)
328{
329 struct ath_common *common = ath9k_hw_common(ah);
330
331 if (common->bus_ops->aspm_init)
332 common->bus_ops->aspm_init(common);
333}
334
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400335/* This should work for all families including legacy */
Sujithcbe61d82009-02-09 13:27:12 +0530336static bool ath9k_hw_chip_test(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530337{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700338 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400339 u32 regAddr[2] = { AR_STA_ID0 };
Sujithf1dc5602008-10-29 10:16:30 +0530340 u32 regHold[2];
Joe Perches07b2fa52010-11-20 18:38:53 -0800341 static const u32 patternData[4] = {
342 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
343 };
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400344 int i, j, loop_max;
Sujithf1dc5602008-10-29 10:16:30 +0530345
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400346 if (!AR_SREV_9300_20_OR_LATER(ah)) {
347 loop_max = 2;
348 regAddr[1] = AR_PHY_BASE + (8 << 2);
349 } else
350 loop_max = 1;
351
352 for (i = 0; i < loop_max; i++) {
Sujithf1dc5602008-10-29 10:16:30 +0530353 u32 addr = regAddr[i];
354 u32 wrData, rdData;
355
356 regHold[i] = REG_READ(ah, addr);
357 for (j = 0; j < 0x100; j++) {
358 wrData = (j << 16) | j;
359 REG_WRITE(ah, addr, wrData);
360 rdData = REG_READ(ah, addr);
361 if (rdData != wrData) {
Joe Perches38002762010-12-02 19:12:36 -0800362 ath_err(common,
363 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
364 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530365 return false;
366 }
367 }
368 for (j = 0; j < 4; j++) {
369 wrData = patternData[j];
370 REG_WRITE(ah, addr, wrData);
371 rdData = REG_READ(ah, addr);
372 if (wrData != rdData) {
Joe Perches38002762010-12-02 19:12:36 -0800373 ath_err(common,
374 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
375 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530376 return false;
377 }
378 }
379 REG_WRITE(ah, regAddr[i], regHold[i]);
380 }
381 udelay(100);
Sujithcbe61d82009-02-09 13:27:12 +0530382
Sujithf1dc5602008-10-29 10:16:30 +0530383 return true;
384}
385
Luis R. Rodriguezb8b0f372009-08-03 12:24:43 -0700386static void ath9k_hw_init_config(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700387{
388 int i;
389
Sujith2660b812009-02-09 13:27:26 +0530390 ah->config.dma_beacon_response_time = 2;
391 ah->config.sw_beacon_response_time = 10;
392 ah->config.additional_swba_backoff = 0;
393 ah->config.ack_6mb = 0x0;
394 ah->config.cwm_ignore_extcca = 0;
Sujith2660b812009-02-09 13:27:26 +0530395 ah->config.pcie_clock_req = 0;
Sujith2660b812009-02-09 13:27:26 +0530396 ah->config.pcie_waen = 0;
397 ah->config.analog_shiftreg = 1;
Luis R. Rodriguez03c72512010-06-12 00:33:46 -0400398 ah->config.enable_ani = true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700399
400 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530401 ah->config.spurchans[i][0] = AR_NO_SPUR;
402 ah->config.spurchans[i][1] = AR_NO_SPUR;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700403 }
404
Luis R. Rodriguez6f481012011-01-20 17:47:39 -0800405 /* PAPRD needs some more work to be enabled */
406 ah->config.paprd_disable = 1;
407
Sujith0ce024c2009-12-14 14:57:00 +0530408 ah->config.rx_intr_mitigation = true;
Luis R. Rodriguez6a0ec302010-06-21 18:38:49 -0400409 ah->config.pcieSerDesWrite = true;
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400410
411 /*
412 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
413 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
414 * This means we use it for all AR5416 devices, and the few
415 * minor PCI AR9280 devices out there.
416 *
417 * Serialization is required because these devices do not handle
418 * well the case of two concurrent reads/writes due to the latency
419 * involved. During one read/write another read/write can be issued
420 * on another CPU while the previous read/write may still be working
421 * on our hardware, if we hit this case the hardware poops in a loop.
422 * We prevent this by serializing reads and writes.
423 *
424 * This issue is not present on PCI-Express devices or pre-AR5416
425 * devices (legacy, 802.11abg).
426 */
427 if (num_possible_cpus() > 1)
David S. Miller2d6a5e92009-03-17 15:01:30 -0700428 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700429}
430
Luis R. Rodriguez50aca252009-08-03 12:24:42 -0700431static void ath9k_hw_init_defaults(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700432{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700433 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
434
435 regulatory->country_code = CTRY_DEFAULT;
436 regulatory->power_limit = MAX_RATE_POWER;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700437
Sujithd535a422009-02-09 13:27:06 +0530438 ah->hw_version.magic = AR5416_MAGIC;
Sujithd535a422009-02-09 13:27:06 +0530439 ah->hw_version.subvendorid = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700440
Sujith2660b812009-02-09 13:27:26 +0530441 ah->atim_window = 0;
Felix Fietkau16f24112010-06-12 17:22:32 +0200442 ah->sta_id1_defaults =
443 AR_STA_ID1_CRPT_MIC_ENABLE |
444 AR_STA_ID1_MCAST_KSRCH;
Felix Fietkauf1717602011-03-19 13:55:41 +0100445 if (AR_SREV_9100(ah))
446 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
Sujith2660b812009-02-09 13:27:26 +0530447 ah->enable_32kHz_clock = DONT_USE_32KHZ;
Rajkumar Manoharane3f2acc2011-08-27 11:22:59 +0530448 ah->slottime = ATH9K_SLOT_TIME_9;
Sujith2660b812009-02-09 13:27:26 +0530449 ah->globaltxtimeout = (u32) -1;
Gabor Juhoscbdec972009-07-24 17:27:22 +0200450 ah->power_mode = ATH9K_PM_UNDEFINED;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700451}
452
Sujithcbe61d82009-02-09 13:27:12 +0530453static int ath9k_hw_init_macaddr(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700454{
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700455 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530456 u32 sum;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700457 int i;
Sujithf1dc5602008-10-29 10:16:30 +0530458 u16 eeval;
Joe Perches07b2fa52010-11-20 18:38:53 -0800459 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700460
Sujithf1dc5602008-10-29 10:16:30 +0530461 sum = 0;
462 for (i = 0; i < 3; i++) {
Luis R. Rodriguez49101672010-04-15 17:39:13 -0400463 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530464 sum += eeval;
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700465 common->macaddr[2 * i] = eeval >> 8;
466 common->macaddr[2 * i + 1] = eeval & 0xff;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700467 }
Sujithd8baa932009-03-30 15:28:25 +0530468 if (sum == 0 || sum == 0xffff * 3)
Sujithf1dc5602008-10-29 10:16:30 +0530469 return -EADDRNOTAVAIL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700470
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700471 return 0;
472}
473
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700474static int ath9k_hw_post_init(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700475{
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530476 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700477 int ecode;
478
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530479 if (common->bus_ops->ath_bus_type != ATH_USB) {
Sujith527d4852010-03-17 14:25:16 +0530480 if (!ath9k_hw_chip_test(ah))
481 return -ENODEV;
482 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700483
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400484 if (!AR_SREV_9300_20_OR_LATER(ah)) {
485 ecode = ar9002_hw_rf_claim(ah);
486 if (ecode != 0)
487 return ecode;
488 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700489
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700490 ecode = ath9k_hw_eeprom_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700491 if (ecode != 0)
492 return ecode;
Sujith7d01b222009-03-13 08:55:55 +0530493
Joe Perchesd2182b62011-12-15 14:55:53 -0800494 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800495 ah->eep_ops->get_eeprom_ver(ah),
496 ah->eep_ops->get_eeprom_rev(ah));
Sujith7d01b222009-03-13 08:55:55 +0530497
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400498 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
499 if (ecode) {
Joe Perches38002762010-12-02 19:12:36 -0800500 ath_err(ath9k_hw_common(ah),
501 "Failed allocating banks for external radio\n");
Rajkumar Manoharan48a7c3d2010-11-08 20:40:53 +0530502 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400503 return ecode;
Luis R. Rodriguez574d6b12009-10-19 02:33:37 -0400504 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700505
Nikolay Martynov42794252011-12-02 22:39:16 -0500506 if (ah->config.enable_ani) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700507 ath9k_hw_ani_setup(ah);
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700508 ath9k_hw_ani_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700509 }
Sujithf1dc5602008-10-29 10:16:30 +0530510
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700511 return 0;
512}
513
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400514static void ath9k_hw_attach_ops(struct ath_hw *ah)
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700515{
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400516 if (AR_SREV_9300_20_OR_LATER(ah))
517 ar9003_hw_attach_ops(ah);
518 else
519 ar9002_hw_attach_ops(ah);
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700520}
521
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400522/* Called for all hardware families */
523static int __ath9k_hw_init(struct ath_hw *ah)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700524{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700525 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700526 int r = 0;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700527
Senthil Balasubramanianac45c122010-12-22 21:14:20 +0530528 ath9k_hw_read_revisions(ah);
529
Senthil Balasubramanian0a8d7cb2010-12-22 19:17:18 +0530530 /*
531 * Read back AR_WA into a permanent copy and set bits 14 and 17.
532 * We need to do this to avoid RMW of this register. We cannot
533 * read the reg when chip is asleep.
534 */
535 ah->WARegVal = REG_READ(ah, AR_WA);
536 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
537 AR_WA_ASPM_TIMER_BASED_DISABLE);
538
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700539 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Joe Perches38002762010-12-02 19:12:36 -0800540 ath_err(common, "Couldn't reset chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700541 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700542 }
543
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530544 if (AR_SREV_9462(ah))
Rajkumar Manoharaneec353c2011-10-13 10:49:13 +0530545 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
546
Luis R. Rodriguezbab1f622010-04-15 17:38:20 -0400547 ath9k_hw_init_defaults(ah);
548 ath9k_hw_init_config(ah);
549
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400550 ath9k_hw_attach_ops(ah);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400551
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700552 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
Joe Perches38002762010-12-02 19:12:36 -0800553 ath_err(common, "Couldn't wakeup chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700554 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700555 }
556
557 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
558 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
John W. Linville4c85ab12010-07-28 10:06:35 -0400559 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
560 !ah->is_pciexpress)) {
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700561 ah->config.serialize_regmode =
562 SER_REG_MODE_ON;
563 } else {
564 ah->config.serialize_regmode =
565 SER_REG_MODE_OFF;
566 }
567 }
568
Joe Perchesd2182b62011-12-15 14:55:53 -0800569 ath_dbg(common, RESET, "serialize_regmode is %d\n",
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700570 ah->config.serialize_regmode);
571
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500572 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
573 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
574 else
575 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
576
Felix Fietkau6da5a722010-12-12 00:51:12 +0100577 switch (ah->hw_version.macVersion) {
578 case AR_SREV_VERSION_5416_PCI:
579 case AR_SREV_VERSION_5416_PCIE:
580 case AR_SREV_VERSION_9160:
581 case AR_SREV_VERSION_9100:
582 case AR_SREV_VERSION_9280:
583 case AR_SREV_VERSION_9285:
584 case AR_SREV_VERSION_9287:
585 case AR_SREV_VERSION_9271:
586 case AR_SREV_VERSION_9300:
Gabor Juhos2c8e5932011-06-21 11:23:21 +0200587 case AR_SREV_VERSION_9330:
Felix Fietkau6da5a722010-12-12 00:51:12 +0100588 case AR_SREV_VERSION_9485:
Vasanthakumar Thiagarajanbca04682011-04-19 19:29:20 +0530589 case AR_SREV_VERSION_9340:
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530590 case AR_SREV_VERSION_9462:
Felix Fietkau6da5a722010-12-12 00:51:12 +0100591 break;
592 default:
Joe Perches38002762010-12-02 19:12:36 -0800593 ath_err(common,
594 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
595 ah->hw_version.macVersion, ah->hw_version.macRev);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700596 return -EOPNOTSUPP;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700597 }
598
Gabor Juhos2c8e5932011-06-21 11:23:21 +0200599 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
600 AR_SREV_9330(ah))
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400601 ah->is_pciexpress = false;
602
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700603 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700604 ath9k_hw_init_cal_settings(ah);
605
606 ah->ani_function = ATH9K_ANI_ALL;
Felix Fietkau7a370812010-09-22 12:34:52 +0200607 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700608 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -0400609 if (!AR_SREV_9300_20_OR_LATER(ah))
610 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700611
Nikolay Martynov4f17c482011-12-06 21:57:17 -0500612 /* disable ANI for 9340 */
613 if (AR_SREV_9340(ah))
Nikolay Martynov42794252011-12-02 22:39:16 -0500614 ah->config.enable_ani = false;
615
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700616 ath9k_hw_init_mode_regs(ah);
617
Stanislaw Gruszka69ce6742011-08-05 13:10:34 +0200618 if (!ah->is_pciexpress)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700619 ath9k_hw_disablepcie(ah);
620
Luis R. Rodriguezd8f492b2010-04-15 17:39:04 -0400621 if (!AR_SREV_9300_20_OR_LATER(ah))
622 ar9002_hw_cck_chan14_spread(ah);
Sujith193cd452009-09-18 15:04:07 +0530623
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700624 r = ath9k_hw_post_init(ah);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700625 if (r)
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700626 return r;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700627
628 ath9k_hw_init_mode_gain_regs(ah);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +0100629 r = ath9k_hw_fill_cap_info(ah);
630 if (r)
631 return r;
632
Stanislaw Gruszka69ce6742011-08-05 13:10:34 +0200633 if (ah->is_pciexpress)
634 ath9k_hw_aspm_init(ah);
635
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700636 r = ath9k_hw_init_macaddr(ah);
637 if (r) {
Joe Perches38002762010-12-02 19:12:36 -0800638 ath_err(common, "Failed to initialize MAC address\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700639 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700640 }
641
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400642 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Sujith2660b812009-02-09 13:27:26 +0530643 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700644 else
Sujith2660b812009-02-09 13:27:26 +0530645 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700646
Gabor Juhos88e641d2011-06-21 11:23:30 +0200647 if (AR_SREV_9330(ah))
648 ah->bb_watchdog_timeout_ms = 85;
649 else
650 ah->bb_watchdog_timeout_ms = 25;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700651
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400652 common->state = ATH_HW_INITIALIZED;
653
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700654 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700655}
656
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400657int ath9k_hw_init(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530658{
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400659 int ret;
660 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530661
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400662 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
663 switch (ah->hw_version.devid) {
664 case AR5416_DEVID_PCI:
665 case AR5416_DEVID_PCIE:
666 case AR5416_AR9100_DEVID:
667 case AR9160_DEVID_PCI:
668 case AR9280_DEVID_PCI:
669 case AR9280_DEVID_PCIE:
670 case AR9285_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400671 case AR9287_DEVID_PCI:
672 case AR9287_DEVID_PCIE:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400673 case AR2427_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400674 case AR9300_DEVID_PCIE:
Vasanthakumar Thiagarajan3050c912010-12-06 04:27:36 -0800675 case AR9300_DEVID_AR9485_PCIE:
Gabor Juhos999a7a82011-06-21 11:23:52 +0200676 case AR9300_DEVID_AR9330:
Vasanthakumar Thiagarajanbca04682011-04-19 19:29:20 +0530677 case AR9300_DEVID_AR9340:
Luis R. Rodriguez5a63ef02011-08-24 15:36:08 -0700678 case AR9300_DEVID_AR9580:
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530679 case AR9300_DEVID_AR9462:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400680 break;
681 default:
682 if (common->bus_ops->ath_bus_type == ATH_USB)
683 break;
Joe Perches38002762010-12-02 19:12:36 -0800684 ath_err(common, "Hardware device ID 0x%04x not supported\n",
685 ah->hw_version.devid);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400686 return -EOPNOTSUPP;
687 }
Sujithf1dc5602008-10-29 10:16:30 +0530688
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400689 ret = __ath9k_hw_init(ah);
690 if (ret) {
Joe Perches38002762010-12-02 19:12:36 -0800691 ath_err(common,
692 "Unable to initialize hardware; initialization status: %d\n",
693 ret);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400694 return ret;
695 }
Sujithf1dc5602008-10-29 10:16:30 +0530696
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400697 return 0;
Sujithf1dc5602008-10-29 10:16:30 +0530698}
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400699EXPORT_SYMBOL(ath9k_hw_init);
Sujithf1dc5602008-10-29 10:16:30 +0530700
Sujithcbe61d82009-02-09 13:27:12 +0530701static void ath9k_hw_init_qos(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530702{
Sujith7d0d0df2010-04-16 11:53:57 +0530703 ENABLE_REGWRITE_BUFFER(ah);
704
Sujithf1dc5602008-10-29 10:16:30 +0530705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
707
708 REG_WRITE(ah, AR_QOS_NO_ACK,
709 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
710 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
711 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
712
713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
Sujith7d0d0df2010-04-16 11:53:57 +0530718
719 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530720}
721
Senthil Balasubramanianb84628e2011-04-22 11:32:12 +0530722u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
Vivek Natarajanb1415812011-01-27 14:45:07 +0530723{
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100724 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
725 udelay(100);
726 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
727
728 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
Vivek Natarajanb1415812011-01-27 14:45:07 +0530729 udelay(100);
Vivek Natarajanb1415812011-01-27 14:45:07 +0530730
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100731 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
Vivek Natarajanb1415812011-01-27 14:45:07 +0530732}
733EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
734
Sujithcbe61d82009-02-09 13:27:12 +0530735static void ath9k_hw_init_pll(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530736 struct ath9k_channel *chan)
737{
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800738 u32 pll;
739
Vivek Natarajan22983c32011-01-27 14:45:09 +0530740 if (AR_SREV_9485(ah)) {
Vivek Natarajan22983c32011-01-27 14:45:09 +0530741
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530742 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
744 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
746 AR_CH0_DPLL2_KD, 0x40);
747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
748 AR_CH0_DPLL2_KI, 0x4);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530749
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
751 AR_CH0_BB_DPLL1_REFDIV, 0x5);
752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
753 AR_CH0_BB_DPLL1_NINI, 0x58);
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
755 AR_CH0_BB_DPLL1_NFRAC, 0x0);
756
757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
758 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
759 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
760 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
762 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
763
764 /* program BB PLL phase_shift to 0x6 */
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
766 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
767
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
769 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
Vivek Natarajan75e03512011-03-10 11:05:42 +0530770 udelay(1000);
Gabor Juhosa5415d62011-06-21 11:23:29 +0200771 } else if (AR_SREV_9330(ah)) {
772 u32 ddr_dpll2, pll_control2, kd;
773
774 if (ah->is_clk_25mhz) {
775 ddr_dpll2 = 0x18e82f01;
776 pll_control2 = 0xe04a3d;
777 kd = 0x1d;
778 } else {
779 ddr_dpll2 = 0x19e82f01;
780 pll_control2 = 0x886666;
781 kd = 0x3d;
782 }
783
784 /* program DDR PLL ki and kd value */
785 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
786
787 /* program DDR PLL phase_shift */
788 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
789 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
790
791 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
792 udelay(1000);
793
794 /* program refdiv, nint, frac to RTC register */
795 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
796
797 /* program BB PLL kd and ki value */
798 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
800
801 /* program BB PLL phase_shift */
802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
803 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530804 } else if (AR_SREV_9340(ah)) {
805 u32 regval, pll2_divint, pll2_divfrac, refdiv;
806
807 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
808 udelay(1000);
809
810 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
811 udelay(100);
812
813 if (ah->is_clk_25mhz) {
814 pll2_divint = 0x54;
815 pll2_divfrac = 0x1eb85;
816 refdiv = 3;
817 } else {
818 pll2_divint = 88;
819 pll2_divfrac = 0;
820 refdiv = 5;
821 }
822
823 regval = REG_READ(ah, AR_PHY_PLL_MODE);
824 regval |= (0x1 << 16);
825 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
826 udelay(100);
827
828 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
829 (pll2_divint << 18) | pll2_divfrac);
830 udelay(100);
831
832 regval = REG_READ(ah, AR_PHY_PLL_MODE);
833 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
834 (0x4 << 26) | (0x18 << 19);
835 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
836 REG_WRITE(ah, AR_PHY_PLL_MODE,
837 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
838 udelay(1000);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530839 }
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800840
841 pll = ath9k_hw_compute_pll_control(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +0530842
Gabor Juhosd03a66c2009-01-14 20:17:09 +0100843 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
Sujithf1dc5602008-10-29 10:16:30 +0530844
Gabor Juhosa5415d62011-06-21 11:23:29 +0200845 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530846 udelay(1000);
847
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400848 /* Switch the core clock for ar9271 to 117Mhz */
849 if (AR_SREV_9271(ah)) {
Sujith25e2ab12010-03-17 14:25:22 +0530850 udelay(500);
851 REG_WRITE(ah, 0x50040, 0x304);
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400852 }
853
Sujithf1dc5602008-10-29 10:16:30 +0530854 udelay(RTC_PLL_SETTLE_DELAY);
855
856 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530857
858 if (AR_SREV_9340(ah)) {
859 if (ah->is_clk_25mhz) {
860 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
861 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
862 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
863 } else {
864 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
865 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
866 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
867 }
868 udelay(100);
869 }
Sujithf1dc5602008-10-29 10:16:30 +0530870}
871
Sujithcbe61d82009-02-09 13:27:12 +0530872static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
Colin McCabed97809d2008-12-01 13:38:55 -0800873 enum nl80211_iftype opmode)
Sujithf1dc5602008-10-29 10:16:30 +0530874{
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530875 u32 sync_default = AR_INTR_SYNC_DEFAULT;
Pavel Roskin152d5302010-03-31 18:05:37 -0400876 u32 imr_reg = AR_IMR_TXERR |
Sujithf1dc5602008-10-29 10:16:30 +0530877 AR_IMR_TXURN |
878 AR_IMR_RXERR |
879 AR_IMR_RXORN |
880 AR_IMR_BCNMISC;
881
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530882 if (AR_SREV_9340(ah))
883 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
884
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400885 if (AR_SREV_9300_20_OR_LATER(ah)) {
886 imr_reg |= AR_IMR_RXOK_HP;
887 if (ah->config.rx_intr_mitigation)
888 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
889 else
890 imr_reg |= AR_IMR_RXOK_LP;
Sujithf1dc5602008-10-29 10:16:30 +0530891
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400892 } else {
893 if (ah->config.rx_intr_mitigation)
894 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
895 else
896 imr_reg |= AR_IMR_RXOK;
897 }
898
899 if (ah->config.tx_intr_mitigation)
900 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
901 else
902 imr_reg |= AR_IMR_TXOK;
Sujithf1dc5602008-10-29 10:16:30 +0530903
Colin McCabed97809d2008-12-01 13:38:55 -0800904 if (opmode == NL80211_IFTYPE_AP)
Pavel Roskin152d5302010-03-31 18:05:37 -0400905 imr_reg |= AR_IMR_MIB;
Sujithf1dc5602008-10-29 10:16:30 +0530906
Sujith7d0d0df2010-04-16 11:53:57 +0530907 ENABLE_REGWRITE_BUFFER(ah);
908
Pavel Roskin152d5302010-03-31 18:05:37 -0400909 REG_WRITE(ah, AR_IMR, imr_reg);
Pavel Roskin74bad5c2010-02-23 18:15:27 -0500910 ah->imrs2_reg |= AR_IMR_S2_GTT;
911 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujithf1dc5602008-10-29 10:16:30 +0530912
913 if (!AR_SREV_9100(ah)) {
914 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530915 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
Sujithf1dc5602008-10-29 10:16:30 +0530916 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
917 }
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400918
Sujith7d0d0df2010-04-16 11:53:57 +0530919 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530920
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400921 if (AR_SREV_9300_20_OR_LATER(ah)) {
922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
926 }
Sujithf1dc5602008-10-29 10:16:30 +0530927}
928
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700929static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
930{
931 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
932 val = min(val, (u32) 0xFFFF);
933 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
934}
935
Felix Fietkau0005baf2010-01-15 02:33:40 +0100936static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530937{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100938 u32 val = ath9k_hw_mac_to_clks(ah, us);
939 val = min(val, (u32) 0xFFFF);
940 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
Sujithf1dc5602008-10-29 10:16:30 +0530941}
942
Felix Fietkau0005baf2010-01-15 02:33:40 +0100943static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530944{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100945 u32 val = ath9k_hw_mac_to_clks(ah, us);
946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
948}
949
950static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
951{
952 u32 val = ath9k_hw_mac_to_clks(ah, us);
953 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
954 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
Sujithf1dc5602008-10-29 10:16:30 +0530955}
956
Sujithcbe61d82009-02-09 13:27:12 +0530957static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Sujithf1dc5602008-10-29 10:16:30 +0530958{
Sujithf1dc5602008-10-29 10:16:30 +0530959 if (tu > 0xFFFF) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800960 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
961 tu);
Sujith2660b812009-02-09 13:27:26 +0530962 ah->globaltxtimeout = (u32) -1;
Sujithf1dc5602008-10-29 10:16:30 +0530963 return false;
964 } else {
965 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
Sujith2660b812009-02-09 13:27:26 +0530966 ah->globaltxtimeout = tu;
Sujithf1dc5602008-10-29 10:16:30 +0530967 return true;
968 }
969}
970
Felix Fietkau0005baf2010-01-15 02:33:40 +0100971void ath9k_hw_init_global_settings(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530972{
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700973 struct ath_common *common = ath9k_hw_common(ah);
974 struct ieee80211_conf *conf = &common->hw->conf;
975 const struct ath9k_channel *chan = ah->curchan;
Felix Fietkauadb50662011-08-28 01:52:10 +0200976 int acktimeout, ctstimeout;
Felix Fietkaue239d852010-01-15 02:34:58 +0100977 int slottime;
Felix Fietkau0005baf2010-01-15 02:33:40 +0100978 int sifstime;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700979 int rx_lat = 0, tx_lat = 0, eifs = 0;
980 u32 reg;
Felix Fietkau0005baf2010-01-15 02:33:40 +0100981
Joe Perchesd2182b62011-12-15 14:55:53 -0800982 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
Joe Perches226afe62010-12-02 19:12:37 -0800983 ah->misc_mode);
Sujithf1dc5602008-10-29 10:16:30 +0530984
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700985 if (!chan)
986 return;
987
Sujith2660b812009-02-09 13:27:26 +0530988 if (ah->misc_mode != 0)
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100989 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
Felix Fietkau0005baf2010-01-15 02:33:40 +0100990
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +0530991 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
992 rx_lat = 41;
993 else
994 rx_lat = 37;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700995 tx_lat = 54;
996
997 if (IS_CHAN_HALF_RATE(chan)) {
998 eifs = 175;
999 rx_lat *= 2;
1000 tx_lat *= 2;
1001 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1002 tx_lat += 11;
1003
1004 slottime = 13;
1005 sifstime = 32;
1006 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1007 eifs = 340;
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +05301008 rx_lat = (rx_lat * 4) - 1;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001009 tx_lat *= 4;
1010 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1011 tx_lat += 22;
1012
1013 slottime = 21;
1014 sifstime = 64;
1015 } else {
Rajkumar Manoharana7be0392011-08-27 12:13:21 +05301016 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1017 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1018 reg = AR_USEC_ASYNC_FIFO;
1019 } else {
1020 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1021 common->clockrate;
1022 reg = REG_READ(ah, AR_USEC);
1023 }
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001024 rx_lat = MS(reg, AR_USEC_RX_LAT);
1025 tx_lat = MS(reg, AR_USEC_TX_LAT);
1026
1027 slottime = ah->slottime;
1028 if (IS_CHAN_5GHZ(chan))
1029 sifstime = 16;
1030 else
1031 sifstime = 10;
1032 }
Felix Fietkau0005baf2010-01-15 02:33:40 +01001033
Felix Fietkaue239d852010-01-15 02:34:58 +01001034 /* As defined by IEEE 802.11-2007 17.3.8.6 */
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001035 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
Felix Fietkauadb50662011-08-28 01:52:10 +02001036 ctstimeout = acktimeout;
Felix Fietkau42c45682010-02-11 18:07:19 +01001037
1038 /*
1039 * Workaround for early ACK timeouts, add an offset to match the
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001040 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
Felix Fietkau42c45682010-02-11 18:07:19 +01001041 * This was initially only meant to work around an issue with delayed
1042 * BA frames in some implementations, but it has been found to fix ACK
1043 * timeout issues in other cases as well.
1044 */
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001045 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) {
Felix Fietkau42c45682010-02-11 18:07:19 +01001046 acktimeout += 64 - sifstime - ah->slottime;
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001047 ctstimeout += 48 - sifstime - ah->slottime;
1048 }
1049
Felix Fietkau42c45682010-02-11 18:07:19 +01001050
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001051 ath9k_hw_set_sifs_time(ah, sifstime);
1052 ath9k_hw_setslottime(ah, slottime);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001053 ath9k_hw_set_ack_timeout(ah, acktimeout);
Felix Fietkauadb50662011-08-28 01:52:10 +02001054 ath9k_hw_set_cts_timeout(ah, ctstimeout);
Sujith2660b812009-02-09 13:27:26 +05301055 if (ah->globaltxtimeout != (u32) -1)
1056 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001057
1058 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1059 REG_RMW(ah, AR_USEC,
1060 (common->clockrate - 1) |
1061 SM(rx_lat, AR_USEC_RX_LAT) |
1062 SM(tx_lat, AR_USEC_TX_LAT),
1063 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1064
Sujithf1dc5602008-10-29 10:16:30 +05301065}
Felix Fietkau0005baf2010-01-15 02:33:40 +01001066EXPORT_SYMBOL(ath9k_hw_init_global_settings);
Sujithf1dc5602008-10-29 10:16:30 +05301067
Sujith285f2dd2010-01-08 10:36:07 +05301068void ath9k_hw_deinit(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001069{
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001070 struct ath_common *common = ath9k_hw_common(ah);
1071
Sujith736b3a22010-03-17 14:25:24 +05301072 if (common->state < ATH_HW_INITIALIZED)
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001073 goto free_hw;
1074
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001075 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001076
1077free_hw:
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001078 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001079}
Sujith285f2dd2010-01-08 10:36:07 +05301080EXPORT_SYMBOL(ath9k_hw_deinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001081
Sujithf1dc5602008-10-29 10:16:30 +05301082/*******/
1083/* INI */
1084/*******/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001085
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001086u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Bob Copeland3a702e42009-03-30 22:30:29 -04001087{
1088 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1089
1090 if (IS_CHAN_B(chan))
1091 ctl |= CTL_11B;
1092 else if (IS_CHAN_G(chan))
1093 ctl |= CTL_11G;
1094 else
1095 ctl |= CTL_11A;
1096
1097 return ctl;
1098}
1099
Sujithf1dc5602008-10-29 10:16:30 +05301100/****************************************/
1101/* Reset and Channel Switching Routines */
1102/****************************************/
1103
Sujithcbe61d82009-02-09 13:27:12 +05301104static inline void ath9k_hw_set_dma(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301105{
Felix Fietkau57b32222010-04-15 17:39:22 -04001106 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301107
Sujith7d0d0df2010-04-16 11:53:57 +05301108 ENABLE_REGWRITE_BUFFER(ah);
1109
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001110 /*
1111 * set AHB_MODE not to do cacheline prefetches
1112 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001113 if (!AR_SREV_9300_20_OR_LATER(ah))
1114 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
Sujithf1dc5602008-10-29 10:16:30 +05301115
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001116 /*
1117 * let mac dma reads be in 128 byte chunks
1118 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001119 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301120
Sujith7d0d0df2010-04-16 11:53:57 +05301121 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301122
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001123 /*
1124 * Restore TX Trigger Level to its pre-reset value.
1125 * The initial value depends on whether aggregation is enabled, and is
1126 * adjusted whenever underruns are detected.
1127 */
Felix Fietkau57b32222010-04-15 17:39:22 -04001128 if (!AR_SREV_9300_20_OR_LATER(ah))
1129 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
Sujithf1dc5602008-10-29 10:16:30 +05301130
Sujith7d0d0df2010-04-16 11:53:57 +05301131 ENABLE_REGWRITE_BUFFER(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301132
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001133 /*
1134 * let mac dma writes be in 128 byte chunks
1135 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001136 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301137
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001138 /*
1139 * Setup receive FIFO threshold to hold off TX activities
1140 */
Sujithf1dc5602008-10-29 10:16:30 +05301141 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1142
Felix Fietkau57b32222010-04-15 17:39:22 -04001143 if (AR_SREV_9300_20_OR_LATER(ah)) {
1144 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1145 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1146
1147 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1148 ah->caps.rx_status_len);
1149 }
1150
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001151 /*
1152 * reduce the number of usable entries in PCU TXBUF to avoid
1153 * wrap around issues.
1154 */
Sujithf1dc5602008-10-29 10:16:30 +05301155 if (AR_SREV_9285(ah)) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001156 /* For AR9285 the number of Fifos are reduced to half.
1157 * So set the usable tx buf size also to half to
1158 * avoid data/delimiter underruns
1159 */
Sujithf1dc5602008-10-29 10:16:30 +05301160 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1161 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001162 } else if (!AR_SREV_9271(ah)) {
Sujithf1dc5602008-10-29 10:16:30 +05301163 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1164 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1165 }
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001166
Sujith7d0d0df2010-04-16 11:53:57 +05301167 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301168
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001169 if (AR_SREV_9300_20_OR_LATER(ah))
1170 ath9k_hw_reset_txstatus_ring(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301171}
1172
Sujithcbe61d82009-02-09 13:27:12 +05301173static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
Sujithf1dc5602008-10-29 10:16:30 +05301174{
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001175 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1176 u32 set = AR_STA_ID1_KSRCH_MODE;
Sujithf1dc5602008-10-29 10:16:30 +05301177
Sujithf1dc5602008-10-29 10:16:30 +05301178 switch (opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08001179 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04001180 case NL80211_IFTYPE_MESH_POINT:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001181 set |= AR_STA_ID1_ADHOC;
Sujithf1dc5602008-10-29 10:16:30 +05301182 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1183 break;
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001184 case NL80211_IFTYPE_AP:
1185 set |= AR_STA_ID1_STA_AP;
1186 /* fall through */
Colin McCabed97809d2008-12-01 13:38:55 -08001187 case NL80211_IFTYPE_STATION:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001188 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
Sujithf1dc5602008-10-29 10:16:30 +05301189 break;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301190 default:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001191 if (!ah->is_monitoring)
1192 set = 0;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301193 break;
Sujithf1dc5602008-10-29 10:16:30 +05301194 }
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001195 REG_RMW(ah, AR_STA_ID1, set, mask);
Sujithf1dc5602008-10-29 10:16:30 +05301196}
1197
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001198void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1199 u32 *coef_mantissa, u32 *coef_exponent)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001200{
1201 u32 coef_exp, coef_man;
1202
1203 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1204 if ((coef_scaled >> coef_exp) & 0x1)
1205 break;
1206
1207 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1208
1209 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1210
1211 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1212 *coef_exponent = coef_exp - 16;
1213}
1214
Sujithcbe61d82009-02-09 13:27:12 +05301215static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
Sujithf1dc5602008-10-29 10:16:30 +05301216{
1217 u32 rst_flags;
1218 u32 tmpReg;
1219
Sujith70768492009-02-16 13:23:12 +05301220 if (AR_SREV_9100(ah)) {
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001221 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1222 AR_RTC_DERIVED_CLK_PERIOD, 1);
Sujith70768492009-02-16 13:23:12 +05301223 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1224 }
1225
Sujith7d0d0df2010-04-16 11:53:57 +05301226 ENABLE_REGWRITE_BUFFER(ah);
1227
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001228 if (AR_SREV_9300_20_OR_LATER(ah)) {
1229 REG_WRITE(ah, AR_WA, ah->WARegVal);
1230 udelay(10);
1231 }
1232
Sujithf1dc5602008-10-29 10:16:30 +05301233 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1234 AR_RTC_FORCE_WAKE_ON_INT);
1235
1236 if (AR_SREV_9100(ah)) {
1237 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1238 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1239 } else {
1240 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1241 if (tmpReg &
1242 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1243 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001244 u32 val;
Sujithf1dc5602008-10-29 10:16:30 +05301245 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001246
1247 val = AR_RC_HOSTIF;
1248 if (!AR_SREV_9300_20_OR_LATER(ah))
1249 val |= AR_RC_AHB;
1250 REG_WRITE(ah, AR_RC, val);
1251
1252 } else if (!AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301253 REG_WRITE(ah, AR_RC, AR_RC_AHB);
Sujithf1dc5602008-10-29 10:16:30 +05301254
1255 rst_flags = AR_RTC_RC_MAC_WARM;
1256 if (type == ATH9K_RESET_COLD)
1257 rst_flags |= AR_RTC_RC_MAC_COLD;
1258 }
1259
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001260 if (AR_SREV_9330(ah)) {
1261 int npend = 0;
1262 int i;
1263
1264 /* AR9330 WAR:
1265 * call external reset function to reset WMAC if:
1266 * - doing a cold reset
1267 * - we have pending frames in the TX queues
1268 */
1269
1270 for (i = 0; i < AR_NUM_QCU; i++) {
1271 npend = ath9k_hw_numtxpending(ah, i);
1272 if (npend)
1273 break;
1274 }
1275
1276 if (ah->external_reset &&
1277 (npend || type == ATH9K_RESET_COLD)) {
1278 int reset_err = 0;
1279
Joe Perchesd2182b62011-12-15 14:55:53 -08001280 ath_dbg(ath9k_hw_common(ah), RESET,
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001281 "reset MAC via external reset\n");
1282
1283 reset_err = ah->external_reset();
1284 if (reset_err) {
1285 ath_err(ath9k_hw_common(ah),
1286 "External reset failed, err=%d\n",
1287 reset_err);
1288 return false;
1289 }
1290
1291 REG_WRITE(ah, AR_RTC_RESET, 1);
1292 }
1293 }
1294
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001295 REG_WRITE(ah, AR_RTC_RC, rst_flags);
Sujith7d0d0df2010-04-16 11:53:57 +05301296
1297 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301298
Sujithf1dc5602008-10-29 10:16:30 +05301299 udelay(50);
1300
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001301 REG_WRITE(ah, AR_RTC_RC, 0);
Sujith0caa7b12009-02-16 13:23:20 +05301302 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001303 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
Sujithf1dc5602008-10-29 10:16:30 +05301304 return false;
1305 }
1306
1307 if (!AR_SREV_9100(ah))
1308 REG_WRITE(ah, AR_RC, 0);
1309
Sujithf1dc5602008-10-29 10:16:30 +05301310 if (AR_SREV_9100(ah))
1311 udelay(50);
1312
1313 return true;
1314}
1315
Sujithcbe61d82009-02-09 13:27:12 +05301316static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301317{
Sujith7d0d0df2010-04-16 11:53:57 +05301318 ENABLE_REGWRITE_BUFFER(ah);
1319
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001320 if (AR_SREV_9300_20_OR_LATER(ah)) {
1321 REG_WRITE(ah, AR_WA, ah->WARegVal);
1322 udelay(10);
1323 }
1324
Sujithf1dc5602008-10-29 10:16:30 +05301325 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1326 AR_RTC_FORCE_WAKE_ON_INT);
1327
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001328 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301329 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1330
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001331 REG_WRITE(ah, AR_RTC_RESET, 0);
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301332
Sujith7d0d0df2010-04-16 11:53:57 +05301333 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301334
Senthil Balasubramanian84e21692010-04-15 17:38:30 -04001335 if (!AR_SREV_9300_20_OR_LATER(ah))
1336 udelay(2);
1337
1338 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301339 REG_WRITE(ah, AR_RC, 0);
1340
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001341 REG_WRITE(ah, AR_RTC_RESET, 1);
Sujithf1dc5602008-10-29 10:16:30 +05301342
1343 if (!ath9k_hw_wait(ah,
1344 AR_RTC_STATUS,
1345 AR_RTC_STATUS_M,
Sujith0caa7b12009-02-16 13:23:20 +05301346 AR_RTC_STATUS_ON,
1347 AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001348 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
Sujithf1dc5602008-10-29 10:16:30 +05301349 return false;
1350 }
1351
Sujithf1dc5602008-10-29 10:16:30 +05301352 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1353}
1354
Sujithcbe61d82009-02-09 13:27:12 +05301355static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Sujithf1dc5602008-10-29 10:16:30 +05301356{
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301357 bool ret = false;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301358
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001359 if (AR_SREV_9300_20_OR_LATER(ah)) {
1360 REG_WRITE(ah, AR_WA, ah->WARegVal);
1361 udelay(10);
1362 }
1363
Sujithf1dc5602008-10-29 10:16:30 +05301364 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1365 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1366
1367 switch (type) {
1368 case ATH9K_RESET_POWER_ON:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301369 ret = ath9k_hw_set_reset_power_on(ah);
1370 break;
Sujithf1dc5602008-10-29 10:16:30 +05301371 case ATH9K_RESET_WARM:
1372 case ATH9K_RESET_COLD:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301373 ret = ath9k_hw_set_reset(ah, type);
1374 break;
Sujithf1dc5602008-10-29 10:16:30 +05301375 default:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301376 break;
Sujithf1dc5602008-10-29 10:16:30 +05301377 }
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301378
1379 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1380 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1381
1382 return ret;
Sujithf1dc5602008-10-29 10:16:30 +05301383}
1384
Sujithcbe61d82009-02-09 13:27:12 +05301385static bool ath9k_hw_chip_reset(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301386 struct ath9k_channel *chan)
1387{
Vivek Natarajan42abfbe2009-09-17 09:27:59 +05301388 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +05301389 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1390 return false;
1391 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
Sujithf1dc5602008-10-29 10:16:30 +05301392 return false;
1393
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001394 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05301395 return false;
1396
Sujith2660b812009-02-09 13:27:26 +05301397 ah->chip_fullsleep = false;
Sujithf1dc5602008-10-29 10:16:30 +05301398 ath9k_hw_init_pll(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301399 ath9k_hw_set_rfmode(ah, chan);
1400
1401 return true;
1402}
1403
Sujithcbe61d82009-02-09 13:27:12 +05301404static bool ath9k_hw_channel_change(struct ath_hw *ah,
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001405 struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301406{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001407 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001408 u32 qnum;
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001409 int r;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301410 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1411 bool band_switch, mode_diff;
1412 u8 ini_reloaded;
1413
1414 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1415 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1416 CHANNEL_5GHZ));
1417 mode_diff = (chan->chanmode != ah->curchan->chanmode);
Sujithf1dc5602008-10-29 10:16:30 +05301418
1419 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1420 if (ath9k_hw_numtxpending(ah, qnum)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001421 ath_dbg(common, QUEUE,
Joe Perches226afe62010-12-02 19:12:37 -08001422 "Transmit frames pending on queue %d\n", qnum);
Sujithf1dc5602008-10-29 10:16:30 +05301423 return false;
1424 }
1425 }
1426
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001427 if (!ath9k_hw_rfbus_req(ah)) {
Joe Perches38002762010-12-02 19:12:36 -08001428 ath_err(common, "Could not kill baseband RX\n");
Sujithf1dc5602008-10-29 10:16:30 +05301429 return false;
1430 }
1431
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301432 if (edma && (band_switch || mode_diff)) {
1433 ath9k_hw_mark_phy_inactive(ah);
1434 udelay(5);
1435
1436 ath9k_hw_init_pll(ah, NULL);
1437
1438 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1439 ath_err(common, "Failed to do fast channel change\n");
1440 return false;
1441 }
1442 }
1443
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001444 ath9k_hw_set_channel_regs(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301445
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001446 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001447 if (r) {
Joe Perches38002762010-12-02 19:12:36 -08001448 ath_err(common, "Failed to set channel\n");
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001449 return false;
Sujithf1dc5602008-10-29 10:16:30 +05301450 }
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001451 ath9k_hw_set_clockrate(ah);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02001452 ath9k_hw_apply_txpower(ah, chan);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001453 ath9k_hw_rfbus_done(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301454
1455 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1456 ath9k_hw_set_delta_slope(ah, chan);
1457
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001458 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301459
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301460 if (edma && (band_switch || mode_diff)) {
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301461 ah->ah_flags |= AH_FASTCC;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301462 if (band_switch || ini_reloaded)
1463 ah->eep_ops->set_board_values(ah, chan);
1464
1465 ath9k_hw_init_bb(ah, chan);
1466
1467 if (band_switch || ini_reloaded)
1468 ath9k_hw_init_cal(ah, chan);
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301469 ah->ah_flags &= ~AH_FASTCC;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301470 }
1471
Sujithf1dc5602008-10-29 10:16:30 +05301472 return true;
1473}
1474
Felix Fietkau691680b2011-03-19 13:55:38 +01001475static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1476{
1477 u32 gpio_mask = ah->gpio_mask;
1478 int i;
1479
1480 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1481 if (!(gpio_mask & 1))
1482 continue;
1483
1484 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1485 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1486 }
1487}
1488
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001489bool ath9k_hw_check_alive(struct ath_hw *ah)
Johannes Berg3b319aa2009-06-13 14:50:26 +05301490{
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001491 int count = 50;
1492 u32 reg;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301493
Felix Fietkaue17f83e2010-09-22 12:34:53 +02001494 if (AR_SREV_9285_12_OR_LATER(ah))
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001495 return true;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301496
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001497 do {
1498 reg = REG_READ(ah, AR_OBS_BUS_1);
1499
1500 if ((reg & 0x7E7FFFEF) == 0x00702400)
1501 continue;
1502
1503 switch (reg & 0x7E000B00) {
1504 case 0x1E000000:
1505 case 0x52000B00:
1506 case 0x18000B00:
1507 continue;
1508 default:
1509 return true;
1510 }
1511 } while (count-- > 0);
1512
1513 return false;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301514}
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001515EXPORT_SYMBOL(ath9k_hw_check_alive);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301516
Sujithcbe61d82009-02-09 13:27:12 +05301517int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001518 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001519{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001520 struct ath_common *common = ath9k_hw_common(ah);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301521 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001522 u32 saveLedState;
Sujith2660b812009-02-09 13:27:26 +05301523 struct ath9k_channel *curchan = ah->curchan;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001524 u32 saveDefAntenna;
1525 u32 macStaId1;
Sujith46fe7822009-09-17 09:25:25 +05301526 u64 tsf = 0;
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001527 int i, r;
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301528 bool allow_fbs = false;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301529 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1530 bool save_fullsleep = ah->chip_fullsleep;
1531
1532 if (mci) {
1533
1534 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan));
1535
1536 if (mci_hw->bt_state == MCI_BT_CAL_START) {
1537 u32 payload[4] = {0, 0, 0, 0};
1538
Joe Perchesd2182b62011-12-15 14:55:53 -08001539 ath_dbg(common, MCI, "MCI stop rx for BT CAL\n");
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301540
1541 mci_hw->bt_state = MCI_BT_CAL;
1542
1543 /*
1544 * MCI FIX: disable mci interrupt here. This is to avoid
1545 * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and
1546 * lead to mci_intr reentry.
1547 */
1548
1549 ar9003_mci_disable_interrupt(ah);
1550
Joe Perchesd2182b62011-12-15 14:55:53 -08001551 ath_dbg(common, MCI, "send WLAN_CAL_GRANT\n");
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301552 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT);
1553 ar9003_mci_send_message(ah, MCI_GPM, 0, payload,
1554 16, true, false);
1555
Joe Perchesd2182b62011-12-15 14:55:53 -08001556 ath_dbg(common, MCI, "\nMCI BT is calibrating\n");
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301557
1558 /* Wait BT calibration to be completed for 25ms */
1559
1560 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE,
1561 0, 25000))
Joe Perchesd2182b62011-12-15 14:55:53 -08001562 ath_dbg(common, MCI,
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301563 "MCI got BT_CAL_DONE\n");
1564 else
Joe Perchesd2182b62011-12-15 14:55:53 -08001565 ath_dbg(common, MCI,
1566 "MCI ### BT cal takes to long, force bt_state to be bt_awake\n");
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301567 mci_hw->bt_state = MCI_BT_AWAKE;
1568 /* MCI FIX: enable mci interrupt here */
1569 ar9003_mci_enable_interrupt(ah);
1570
1571 return true;
1572 }
1573 }
1574
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001575
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001576 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001577 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001578
Felix Fietkaud9891c72010-09-29 17:15:27 +02001579 if (curchan && !ah->chip_fullsleep)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001580 ath9k_hw_getnf(ah, curchan);
1581
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001582 ah->caldata = caldata;
1583 if (caldata &&
1584 (chan->channel != caldata->channel ||
1585 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1586 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1587 /* Operating channel changed, reset channel calibration data */
1588 memset(caldata, 0, sizeof(*caldata));
1589 ath9k_init_nfcal_hist_buffer(ah, chan);
1590 }
Felix Fietkauf23fba42011-07-28 14:08:56 +02001591 ah->noise = ath9k_hw_getchan_noise(ah, chan);
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001592
Rajkumar Manoharan19787b22011-10-13 11:00:39 +05301593 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
Rajkumar Manoharan7db062a2011-09-14 14:20:30 +05301594 bChannelChange = false;
1595
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301596 if (caldata &&
1597 caldata->done_txiqcal_once &&
1598 caldata->done_txclcal_once &&
1599 caldata->rtt_hist.num_readings)
1600 allow_fbs = true;
1601
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001602 if (bChannelChange &&
Sujith2660b812009-02-09 13:27:26 +05301603 (ah->chip_fullsleep != true) &&
1604 (ah->curchan != NULL) &&
1605 (chan->channel != ah->curchan->channel) &&
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301606 (allow_fbs ||
1607 ((chan->channelFlags & CHANNEL_ALL) ==
1608 (ah->curchan->channelFlags & CHANNEL_ALL)))) {
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001609 if (ath9k_hw_channel_change(ah, chan)) {
Sujith2660b812009-02-09 13:27:26 +05301610 ath9k_hw_loadnf(ah, ah->curchan);
Felix Fietkau00c86592010-07-30 21:02:09 +02001611 ath9k_hw_start_nfcal(ah, true);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301612 if (mci && mci_hw->ready)
1613 ar9003_mci_2g5g_switch(ah, true);
1614
Rajkumar Manoharanc2ba3342010-09-03 16:00:00 +05301615 if (AR_SREV_9271(ah))
1616 ar9002_hw_load_ani_reg(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001617 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001618 }
1619 }
1620
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301621 if (mci) {
1622 ar9003_mci_disable_interrupt(ah);
1623
1624 if (mci_hw->ready && !save_fullsleep) {
1625 ar9003_mci_mute_bt(ah);
1626 udelay(20);
1627 REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
1628 }
1629
1630 mci_hw->bt_state = MCI_BT_SLEEP;
1631 mci_hw->ready = false;
1632 }
1633
1634
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001635 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1636 if (saveDefAntenna == 0)
1637 saveDefAntenna = 1;
1638
1639 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1640
Sujith46fe7822009-09-17 09:25:25 +05301641 /* For chips on which RTC reset is done, save TSF before it gets cleared */
Felix Fietkauf860d522010-06-30 02:07:48 +02001642 if (AR_SREV_9100(ah) ||
1643 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
Sujith46fe7822009-09-17 09:25:25 +05301644 tsf = ath9k_hw_gettsf64(ah);
1645
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001646 saveLedState = REG_READ(ah, AR_CFG_LED) &
1647 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1648 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1649
1650 ath9k_hw_mark_phy_inactive(ah);
1651
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -08001652 ah->paprd_table_write_done = false;
1653
Sujith05020d22010-03-17 14:25:23 +05301654 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001655 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1656 REG_WRITE(ah,
1657 AR9271_RESET_POWER_DOWN_CONTROL,
1658 AR9271_RADIO_RF_RST);
1659 udelay(50);
1660 }
1661
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001662 if (!ath9k_hw_chip_reset(ah, chan)) {
Joe Perches38002762010-12-02 19:12:36 -08001663 ath_err(common, "Chip reset failed\n");
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001664 return -EINVAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001665 }
1666
Sujith05020d22010-03-17 14:25:23 +05301667 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001668 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1669 ah->htc_reset_init = false;
1670 REG_WRITE(ah,
1671 AR9271_RESET_POWER_DOWN_CONTROL,
1672 AR9271_GATE_MAC_CTL);
1673 udelay(50);
1674 }
1675
Sujith46fe7822009-09-17 09:25:25 +05301676 /* Restore TSF */
Felix Fietkauf860d522010-06-30 02:07:48 +02001677 if (tsf)
Sujith46fe7822009-09-17 09:25:25 +05301678 ath9k_hw_settsf64(ah, tsf);
1679
Felix Fietkau7a370812010-09-22 12:34:52 +02001680 if (AR_SREV_9280_20_OR_LATER(ah))
Vasanthakumar Thiagarajan369391d2009-01-21 19:24:13 +05301681 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001682
Sujithe9141f72010-06-01 15:14:10 +05301683 if (!AR_SREV_9300_20_OR_LATER(ah))
1684 ar9002_hw_enable_async_fifo(ah);
1685
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001686 r = ath9k_hw_process_ini(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001687 if (r)
1688 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001689
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301690 if (mci)
1691 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1692
Felix Fietkauf860d522010-06-30 02:07:48 +02001693 /*
1694 * Some AR91xx SoC devices frequently fail to accept TSF writes
1695 * right after the chip reset. When that happens, write a new
1696 * value after the initvals have been applied, with an offset
1697 * based on measured time difference
1698 */
1699 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1700 tsf += 1500;
1701 ath9k_hw_settsf64(ah, tsf);
1702 }
1703
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001704 /* Setup MFP options for CCMP */
1705 if (AR_SREV_9280_20_OR_LATER(ah)) {
1706 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1707 * frames when constructing CCMP AAD. */
1708 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1709 0xc7ff);
1710 ah->sw_mgmt_crypto = false;
1711 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1712 /* Disable hardware crypto for management frames */
1713 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1714 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1715 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1716 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1717 ah->sw_mgmt_crypto = true;
1718 } else
1719 ah->sw_mgmt_crypto = true;
1720
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001721 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1722 ath9k_hw_set_delta_slope(ah, chan);
1723
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001724 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithd6509152009-03-13 08:56:05 +05301725 ah->eep_ops->set_board_values(ah, chan);
Luis R. Rodrigueza7765822009-10-19 02:33:45 -04001726
Sujith7d0d0df2010-04-16 11:53:57 +05301727 ENABLE_REGWRITE_BUFFER(ah);
1728
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001729 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1730 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001731 | macStaId1
1732 | AR_STA_ID1_RTS_USE_DEF
Sujith2660b812009-02-09 13:27:26 +05301733 | (ah->config.
Sujith60b67f52008-08-07 10:52:38 +05301734 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
Sujith2660b812009-02-09 13:27:26 +05301735 | ah->sta_id1_defaults);
Luis R. Rodriguez13b81552009-09-10 17:52:45 -07001736 ath_hw_setbssidmask(common);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001737 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
Luis R. Rodriguez3453ad82009-09-10 08:57:00 -07001738 ath9k_hw_write_associd(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001739 REG_WRITE(ah, AR_ISR, ~0);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001740 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1741
Sujith7d0d0df2010-04-16 11:53:57 +05301742 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301743
Sujith Manoharan00e00032011-01-26 21:59:05 +05301744 ath9k_hw_set_operating_mode(ah, ah->opmode);
1745
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001746 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001747 if (r)
1748 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001749
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001750 ath9k_hw_set_clockrate(ah);
1751
Sujith7d0d0df2010-04-16 11:53:57 +05301752 ENABLE_REGWRITE_BUFFER(ah);
1753
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001754 for (i = 0; i < AR_NUM_DCU; i++)
1755 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1756
Sujith7d0d0df2010-04-16 11:53:57 +05301757 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301758
Sujith2660b812009-02-09 13:27:26 +05301759 ah->intr_txqs = 0;
Felix Fietkauf4c607d2011-03-23 20:57:28 +01001760 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001761 ath9k_hw_resettxqueue(ah, i);
1762
Sujith2660b812009-02-09 13:27:26 +05301763 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -04001764 ath9k_hw_ani_cache_ini_regs(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001765 ath9k_hw_init_qos(ah);
1766
Sujith2660b812009-02-09 13:27:26 +05301767 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Felix Fietkau55821322010-12-17 00:57:01 +01001768 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301769
Felix Fietkau0005baf2010-01-15 02:33:40 +01001770 ath9k_hw_init_global_settings(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001771
Felix Fietkaufe2b6af2011-07-09 11:12:51 +07001772 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1773 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1774 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1775 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1776 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1777 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1778 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301779 }
1780
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001781 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001782
1783 ath9k_hw_set_dma(ah);
1784
1785 REG_WRITE(ah, AR_OBS, 8);
1786
Sujith0ce024c2009-12-14 14:57:00 +05301787 if (ah->config.rx_intr_mitigation) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001788 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1789 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1790 }
1791
Vasanthakumar Thiagarajan7f62a132010-04-15 17:39:19 -04001792 if (ah->config.tx_intr_mitigation) {
1793 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1794 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1795 }
1796
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001797 ath9k_hw_init_bb(ah, chan);
1798
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301799 if (caldata) {
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301800 caldata->done_txiqcal_once = false;
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301801 caldata->done_txclcal_once = false;
Rajkumar Manoharan324c74a2011-10-13 11:00:41 +05301802 caldata->rtt_hist.num_readings = 0;
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301803 }
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001804 if (!ath9k_hw_init_cal(ah, chan))
Joe Perches6badaaf2009-06-28 09:26:32 -07001805 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001806
Rajkumar Manoharan93348922011-10-25 16:47:36 +05301807 ath9k_hw_loadnf(ah, chan);
1808 ath9k_hw_start_nfcal(ah, true);
1809
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301810 if (mci && mci_hw->ready) {
1811
1812 if (IS_CHAN_2GHZ(chan) &&
1813 (mci_hw->bt_state == MCI_BT_SLEEP)) {
1814
1815 if (ar9003_mci_check_int(ah,
1816 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
1817 ar9003_mci_check_int(ah,
1818 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) {
1819
1820 /*
1821 * BT is sleeping. Check if BT wakes up during
1822 * WLAN calibration. If BT wakes up during
1823 * WLAN calibration, need to go through all
1824 * message exchanges again and recal.
1825 */
1826
Joe Perchesd2182b62011-12-15 14:55:53 -08001827 ath_dbg(common, MCI,
1828 "MCI BT wakes up during WLAN calibration\n");
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301829
1830 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1831 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
1832 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE);
Joe Perchesd2182b62011-12-15 14:55:53 -08001833 ath_dbg(common, MCI, "MCI send REMOTE_RESET\n");
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301834 ar9003_mci_remote_reset(ah, true);
1835 ar9003_mci_send_sys_waking(ah, true);
1836 udelay(1);
1837 if (IS_CHAN_2GHZ(chan))
1838 ar9003_mci_send_lna_transfer(ah, true);
1839
1840 mci_hw->bt_state = MCI_BT_AWAKE;
1841
Joe Perchesd2182b62011-12-15 14:55:53 -08001842 ath_dbg(common, MCI, "MCI re-cal\n");
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301843
1844 if (caldata) {
1845 caldata->done_txiqcal_once = false;
1846 caldata->done_txclcal_once = false;
1847 caldata->rtt_hist.num_readings = 0;
1848 }
1849
1850 if (!ath9k_hw_init_cal(ah, chan))
1851 return -EIO;
1852
1853 }
1854 }
1855 ar9003_mci_enable_interrupt(ah);
1856 }
1857
Sujith7d0d0df2010-04-16 11:53:57 +05301858 ENABLE_REGWRITE_BUFFER(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001859
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001860 ath9k_hw_restore_chainmask(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001861 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1862
Sujith7d0d0df2010-04-16 11:53:57 +05301863 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301864
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001865 /*
1866 * For big endian systems turn on swapping for descriptors
1867 */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001868 if (AR_SREV_9100(ah)) {
1869 u32 mask;
1870 mask = REG_READ(ah, AR_CFG);
1871 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001872 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1873 mask);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001874 } else {
1875 mask =
1876 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1877 REG_WRITE(ah, AR_CFG, mask);
Joe Perchesd2182b62011-12-15 14:55:53 -08001878 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1879 REG_READ(ah, AR_CFG));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001880 }
1881 } else {
Sujithcbba8cd2010-06-02 15:53:31 +05301882 if (common->bus_ops->ath_bus_type == ATH_USB) {
1883 /* Configure AR9271 target WLAN */
1884 if (AR_SREV_9271(ah))
1885 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1886 else
1887 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1888 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001889#ifdef __BIG_ENDIAN
Gabor Juhos4033bda2011-06-21 11:23:35 +02001890 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
Vasanthakumar Thiagarajan2be7bfe2011-04-19 19:29:14 +05301891 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1892 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001893 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001894#endif
1895 }
1896
Felix Fietkau8a309302011-12-17 16:47:56 +01001897 if (ah->btcoex_hw.enabled &&
1898 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE)
Vasanthakumar Thiagarajan42cc41e2009-08-26 21:08:45 +05301899 ath9k_hw_btcoex_enable(ah);
1900
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301901 if (mci && mci_hw->ready) {
1902 /*
1903 * check BT state again to make
1904 * sure it's not changed.
1905 */
1906
1907 ar9003_mci_sync_bt_state(ah);
1908 ar9003_mci_2g5g_switch(ah, true);
1909
1910 if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
1911 (mci_hw->query_bt == true)) {
1912 mci_hw->need_flush_btinfo = true;
1913 }
1914 }
1915
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05301916 if (AR_SREV_9300_20_OR_LATER(ah)) {
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -04001917 ar9003_hw_bb_watchdog_config(ah);
Vasanthakumar Thiagarajand8903a52010-04-15 17:39:25 -04001918
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05301919 ar9003_hw_disable_phy_restart(ah);
1920 }
1921
Felix Fietkau691680b2011-03-19 13:55:38 +01001922 ath9k_hw_apply_gpio_override(ah);
1923
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001924 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001925}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001926EXPORT_SYMBOL(ath9k_hw_reset);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001927
Sujithf1dc5602008-10-29 10:16:30 +05301928/******************************/
1929/* Power Management (Chipset) */
1930/******************************/
1931
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001932/*
1933 * Notify Power Mgt is disabled in self-generated frames.
1934 * If requested, force chip to sleep.
1935 */
Sujithcbe61d82009-02-09 13:27:12 +05301936static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05301937{
1938 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1939 if (setChip) {
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05301940 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301941 REG_WRITE(ah, AR_TIMER_MODE,
1942 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1943 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1944 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1945 REG_WRITE(ah, AR_SLP32_INC,
1946 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1947 /* xxx Required for WLAN only case ? */
1948 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1949 udelay(100);
1950 }
1951
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001952 /*
1953 * Clear the RTC force wake bit to allow the
1954 * mac to go to sleep.
1955 */
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301956 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1957
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05301958 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301959 udelay(100);
1960
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001961 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301962 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1963
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001964 /* Shutdown chip. Active low */
Sujith Manoharanc91ec462012-02-22 12:40:03 +05301965 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301966 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1967 udelay(2);
1968 }
Sujithf1dc5602008-10-29 10:16:30 +05301969 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001970
1971 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
Rafael J. Wysockia7322812011-11-26 23:37:43 +01001972 if (AR_SREV_9300_20_OR_LATER(ah))
1973 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001974}
1975
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04001976/*
1977 * Notify Power Management is enabled in self-generating
1978 * frames. If request, set power mode of chip to
1979 * auto/normal. Duration in units of 128us (1/8 TU).
1980 */
Sujithcbe61d82009-02-09 13:27:12 +05301981static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001982{
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301983 u32 val;
1984
Sujithf1dc5602008-10-29 10:16:30 +05301985 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1986 if (setChip) {
Sujith2660b812009-02-09 13:27:26 +05301987 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001988
Sujithf1dc5602008-10-29 10:16:30 +05301989 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04001990 /* Set WakeOnInterrupt bit; clear ForceWake bit */
Sujithf1dc5602008-10-29 10:16:30 +05301991 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1992 AR_RTC_FORCE_WAKE_ON_INT);
1993 } else {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301994
1995 /* When chip goes into network sleep, it could be waken
1996 * up by MCI_INT interrupt caused by BT's HW messages
1997 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1998 * rate (~100us). This will cause chip to leave and
1999 * re-enter network sleep mode frequently, which in
2000 * consequence will have WLAN MCI HW to generate lots of
2001 * SYS_WAKING and SYS_SLEEPING messages which will make
2002 * BT CPU to busy to process.
2003 */
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302004 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302005 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2006 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2007 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2008 }
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04002009 /*
2010 * Clear the RTC force wake bit to allow the
2011 * mac to go to sleep.
2012 */
Sujithf1dc5602008-10-29 10:16:30 +05302013 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2014 AR_RTC_FORCE_WAKE_EN);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302015
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302016 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302017 udelay(30);
Sujithf1dc5602008-10-29 10:16:30 +05302018 }
2019 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002020
2021 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2022 if (AR_SREV_9300_20_OR_LATER(ah))
2023 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Sujithf1dc5602008-10-29 10:16:30 +05302024}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002025
Sujithcbe61d82009-02-09 13:27:12 +05302026static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05302027{
2028 u32 val;
2029 int i;
2030
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002031 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2032 if (AR_SREV_9300_20_OR_LATER(ah)) {
2033 REG_WRITE(ah, AR_WA, ah->WARegVal);
2034 udelay(10);
2035 }
2036
Sujithf1dc5602008-10-29 10:16:30 +05302037 if (setChip) {
2038 if ((REG_READ(ah, AR_RTC_STATUS) &
2039 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2040 if (ath9k_hw_set_reset_reg(ah,
2041 ATH9K_RESET_POWER_ON) != true) {
2042 return false;
2043 }
Luis R. Rodrigueze0412282010-04-15 17:38:15 -04002044 if (!AR_SREV_9300_20_OR_LATER(ah))
2045 ath9k_hw_init_pll(ah, NULL);
Sujithf1dc5602008-10-29 10:16:30 +05302046 }
2047 if (AR_SREV_9100(ah))
2048 REG_SET_BIT(ah, AR_RTC_RESET,
2049 AR_RTC_RESET_EN);
2050
2051 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2052 AR_RTC_FORCE_WAKE_EN);
2053 udelay(50);
2054
2055 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2056 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2057 if (val == AR_RTC_STATUS_ON)
2058 break;
2059 udelay(50);
2060 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2061 AR_RTC_FORCE_WAKE_EN);
2062 }
2063 if (i == 0) {
Joe Perches38002762010-12-02 19:12:36 -08002064 ath_err(ath9k_hw_common(ah),
2065 "Failed to wakeup in %uus\n",
2066 POWER_UP_TIME / 20);
Sujithf1dc5602008-10-29 10:16:30 +05302067 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002068 }
2069 }
2070
Sujithf1dc5602008-10-29 10:16:30 +05302071 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2072
2073 return true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002074}
2075
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002076bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Sujithf1dc5602008-10-29 10:16:30 +05302077{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002078 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +05302079 int status = true, setChip = true;
Sujithf1dc5602008-10-29 10:16:30 +05302080 static const char *modes[] = {
2081 "AWAKE",
2082 "FULL-SLEEP",
2083 "NETWORK SLEEP",
2084 "UNDEFINED"
2085 };
Sujithf1dc5602008-10-29 10:16:30 +05302086
Gabor Juhoscbdec972009-07-24 17:27:22 +02002087 if (ah->power_mode == mode)
2088 return status;
2089
Joe Perchesd2182b62011-12-15 14:55:53 -08002090 ath_dbg(common, RESET, "%s -> %s\n",
Joe Perches226afe62010-12-02 19:12:37 -08002091 modes[ah->power_mode], modes[mode]);
Sujithf1dc5602008-10-29 10:16:30 +05302092
2093 switch (mode) {
2094 case ATH9K_PM_AWAKE:
2095 status = ath9k_hw_set_power_awake(ah, setChip);
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302096
2097 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2098 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2099
Sujithf1dc5602008-10-29 10:16:30 +05302100 break;
2101 case ATH9K_PM_FULL_SLEEP:
Sujith Manoharand1ca8b82012-02-22 12:41:01 +05302102 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2103 ar9003_mci_set_full_sleep(ah);
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302104
Sujithf1dc5602008-10-29 10:16:30 +05302105 ath9k_set_power_sleep(ah, setChip);
Sujith2660b812009-02-09 13:27:26 +05302106 ah->chip_fullsleep = true;
Sujithf1dc5602008-10-29 10:16:30 +05302107 break;
2108 case ATH9K_PM_NETWORK_SLEEP:
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302109
2110 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2111 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2112
Sujithf1dc5602008-10-29 10:16:30 +05302113 ath9k_set_power_network_sleep(ah, setChip);
2114 break;
2115 default:
Joe Perches38002762010-12-02 19:12:36 -08002116 ath_err(common, "Unknown power mode %u\n", mode);
Sujithf1dc5602008-10-29 10:16:30 +05302117 return false;
2118 }
Sujith2660b812009-02-09 13:27:26 +05302119 ah->power_mode = mode;
Sujithf1dc5602008-10-29 10:16:30 +05302120
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002121 /*
2122 * XXX: If this warning never comes up after a while then
2123 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2124 * ath9k_hw_setpower() return type void.
2125 */
Sujith Manoharan97dcec52010-12-20 08:02:42 +05302126
2127 if (!(ah->ah_flags & AH_UNPLUGGED))
2128 ATH_DBG_WARN_ON_ONCE(!status);
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002129
Sujithf1dc5602008-10-29 10:16:30 +05302130 return status;
2131}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002132EXPORT_SYMBOL(ath9k_hw_setpower);
Sujithf1dc5602008-10-29 10:16:30 +05302133
Sujithf1dc5602008-10-29 10:16:30 +05302134/*******************/
2135/* Beacon Handling */
2136/*******************/
2137
Sujithcbe61d82009-02-09 13:27:12 +05302138void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002139{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002140 int flags = 0;
2141
Sujith7d0d0df2010-04-16 11:53:57 +05302142 ENABLE_REGWRITE_BUFFER(ah);
2143
Sujith2660b812009-02-09 13:27:26 +05302144 switch (ah->opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08002145 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04002146 case NL80211_IFTYPE_MESH_POINT:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002147 REG_SET_BIT(ah, AR_TXCFG,
2148 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
Felix Fietkaudd347f22011-03-22 21:54:17 +01002149 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2150 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002151 flags |= AR_NDP_TIMER_EN;
Colin McCabed97809d2008-12-01 13:38:55 -08002152 case NL80211_IFTYPE_AP:
Felix Fietkaudd347f22011-03-22 21:54:17 +01002153 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2154 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2155 TU_TO_USEC(ah->config.dma_beacon_response_time));
2156 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2157 TU_TO_USEC(ah->config.sw_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002158 flags |=
2159 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2160 break;
Colin McCabed97809d2008-12-01 13:38:55 -08002161 default:
Joe Perchesd2182b62011-12-15 14:55:53 -08002162 ath_dbg(ath9k_hw_common(ah), BEACON,
2163 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
Colin McCabed97809d2008-12-01 13:38:55 -08002164 return;
2165 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002166 }
2167
Felix Fietkaudd347f22011-03-22 21:54:17 +01002168 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2169 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2170 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2171 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002172
Sujith7d0d0df2010-04-16 11:53:57 +05302173 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302174
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002175 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2176}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002177EXPORT_SYMBOL(ath9k_hw_beaconinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002178
Sujithcbe61d82009-02-09 13:27:12 +05302179void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302180 const struct ath9k_beacon_state *bs)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002181{
2182 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
Sujith2660b812009-02-09 13:27:26 +05302183 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002184 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002185
Sujith7d0d0df2010-04-16 11:53:57 +05302186 ENABLE_REGWRITE_BUFFER(ah);
2187
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002188 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2189
2190 REG_WRITE(ah, AR_BEACON_PERIOD,
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302191 TU_TO_USEC(bs->bs_intval));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002192 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302193 TU_TO_USEC(bs->bs_intval));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002194
Sujith7d0d0df2010-04-16 11:53:57 +05302195 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302196
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002197 REG_RMW_FIELD(ah, AR_RSSI_THR,
2198 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2199
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302200 beaconintval = bs->bs_intval;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002201
2202 if (bs->bs_sleepduration > beaconintval)
2203 beaconintval = bs->bs_sleepduration;
2204
2205 dtimperiod = bs->bs_dtimperiod;
2206 if (bs->bs_sleepduration > dtimperiod)
2207 dtimperiod = bs->bs_sleepduration;
2208
2209 if (beaconintval == dtimperiod)
2210 nextTbtt = bs->bs_nextdtim;
2211 else
2212 nextTbtt = bs->bs_nexttbtt;
2213
Joe Perchesd2182b62011-12-15 14:55:53 -08002214 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2215 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2216 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2217 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002218
Sujith7d0d0df2010-04-16 11:53:57 +05302219 ENABLE_REGWRITE_BUFFER(ah);
2220
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002221 REG_WRITE(ah, AR_NEXT_DTIM,
2222 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2223 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2224
2225 REG_WRITE(ah, AR_SLEEP1,
2226 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2227 | AR_SLEEP1_ASSUME_DTIM);
2228
Sujith60b67f52008-08-07 10:52:38 +05302229 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002230 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2231 else
2232 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2233
2234 REG_WRITE(ah, AR_SLEEP2,
2235 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2236
2237 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2238 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2239
Sujith7d0d0df2010-04-16 11:53:57 +05302240 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302241
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002242 REG_SET_BIT(ah, AR_TIMER_MODE,
2243 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2244 AR_DTIM_TIMER_EN);
2245
Sujith4af9cf42009-02-12 10:06:47 +05302246 /* TSF Out of Range Threshold */
2247 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002248}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002249EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002250
Sujithf1dc5602008-10-29 10:16:30 +05302251/*******************/
2252/* HW Capabilities */
2253/*******************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002254
Felix Fietkau60540692011-07-19 08:46:44 +02002255static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2256{
2257 eeprom_chainmask &= chip_chainmask;
2258 if (eeprom_chainmask)
2259 return eeprom_chainmask;
2260 else
2261 return chip_chainmask;
2262}
2263
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002264/**
2265 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2266 * @ah: the atheros hardware data structure
2267 *
2268 * We enable DFS support upstream on chipsets which have passed a series
2269 * of tests. The testing requirements are going to be documented. Desired
2270 * test requirements are documented at:
2271 *
2272 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2273 *
2274 * Once a new chipset gets properly tested an individual commit can be used
2275 * to document the testing for DFS for that chipset.
2276 */
2277static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2278{
2279
2280 switch (ah->hw_version.macVersion) {
2281 /* AR9580 will likely be our first target to get testing on */
2282 case AR_SREV_VERSION_9580:
2283 default:
2284 return false;
2285 }
2286}
2287
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002288int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002289{
Sujith2660b812009-02-09 13:27:26 +05302290 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002291 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002292 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau60540692011-07-19 08:46:44 +02002293 unsigned int chip_chainmask;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002294
Sujith Manoharan0ff2b5c2011-04-20 11:00:34 +05302295 u16 eeval;
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002296 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002297
Sujithf74df6f2009-02-09 13:27:24 +05302298 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002299 regulatory->current_rd = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05302300
Sujith2660b812009-02-09 13:27:26 +05302301 if (ah->opmode != NL80211_IFTYPE_AP &&
Sujithd535a422009-02-09 13:27:06 +05302302 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002303 if (regulatory->current_rd == 0x64 ||
2304 regulatory->current_rd == 0x65)
2305 regulatory->current_rd += 5;
2306 else if (regulatory->current_rd == 0x41)
2307 regulatory->current_rd = 0x43;
Joe Perchesd2182b62011-12-15 14:55:53 -08002308 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2309 regulatory->current_rd);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002310 }
Sujithdc2222a2008-08-14 13:26:55 +05302311
Sujithf74df6f2009-02-09 13:27:24 +05302312 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002313 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
Joe Perches38002762010-12-02 19:12:36 -08002314 ath_err(common,
2315 "no band has been marked as supported in EEPROM\n");
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002316 return -EINVAL;
2317 }
2318
Felix Fietkaud4659912010-10-14 16:02:39 +02002319 if (eeval & AR5416_OPFLAGS_11A)
2320 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002321
Felix Fietkaud4659912010-10-14 16:02:39 +02002322 if (eeval & AR5416_OPFLAGS_11G)
2323 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
Sujithf1dc5602008-10-29 10:16:30 +05302324
Felix Fietkau60540692011-07-19 08:46:44 +02002325 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2326 chip_chainmask = 1;
Mohammed Shafi Shajakhanba5736a2011-11-30 21:10:52 +05302327 else if (AR_SREV_9462(ah))
2328 chip_chainmask = 3;
Felix Fietkau60540692011-07-19 08:46:44 +02002329 else if (!AR_SREV_9280_20_OR_LATER(ah))
2330 chip_chainmask = 7;
2331 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2332 chip_chainmask = 3;
2333 else
2334 chip_chainmask = 7;
2335
Sujithf74df6f2009-02-09 13:27:24 +05302336 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002337 /*
2338 * For AR9271 we will temporarilly uses the rx chainmax as read from
2339 * the EEPROM.
2340 */
Sujith8147f5d2009-02-20 15:13:23 +05302341 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002342 !(eeval & AR5416_OPFLAGS_11A) &&
2343 !(AR_SREV_9271(ah)))
2344 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
Sujith8147f5d2009-02-20 15:13:23 +05302345 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
Felix Fietkau598cdd52011-03-19 13:55:42 +01002346 else if (AR_SREV_9100(ah))
2347 pCap->rx_chainmask = 0x7;
Sujith8147f5d2009-02-20 15:13:23 +05302348 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002349 /* Use rx_chainmask from EEPROM. */
Sujith8147f5d2009-02-20 15:13:23 +05302350 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05302351
Felix Fietkau60540692011-07-19 08:46:44 +02002352 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2353 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
Felix Fietkau82b2d332011-09-03 01:40:23 +02002354 ah->txchainmask = pCap->tx_chainmask;
2355 ah->rxchainmask = pCap->rx_chainmask;
Felix Fietkau60540692011-07-19 08:46:44 +02002356
Felix Fietkau7a370812010-09-22 12:34:52 +02002357 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
Sujithf1dc5602008-10-29 10:16:30 +05302358
Felix Fietkau02d2ebb2010-11-22 15:39:39 +01002359 /* enable key search for every frame in an aggregate */
2360 if (AR_SREV_9300_20_OR_LATER(ah))
2361 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2362
Bruno Randolfce2220d2010-09-17 11:36:25 +09002363 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2364
Felix Fietkau0db156e2011-03-23 20:57:29 +01002365 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
Sujithf1dc5602008-10-29 10:16:30 +05302366 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2367 else
2368 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2369
Sujith5b5fa352010-03-17 14:25:15 +05302370 if (AR_SREV_9271(ah))
2371 pCap->num_gpio_pins = AR9271_NUM_GPIO;
Sujith88c1f4f2010-06-30 14:46:31 +05302372 else if (AR_DEVID_7010(ah))
2373 pCap->num_gpio_pins = AR7010_NUM_GPIO;
Mohammed Shafi Shajakhan6321eb02011-09-30 11:31:27 +05302374 else if (AR_SREV_9300_20_OR_LATER(ah))
2375 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2376 else if (AR_SREV_9287_11_OR_LATER(ah))
2377 pCap->num_gpio_pins = AR9287_NUM_GPIO;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002378 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302379 pCap->num_gpio_pins = AR9285_NUM_GPIO;
Felix Fietkau7a370812010-09-22 12:34:52 +02002380 else if (AR_SREV_9280_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302381 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2382 else
2383 pCap->num_gpio_pins = AR_NUM_GPIO;
2384
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302385 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302386 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302387 else
Sujithf1dc5602008-10-29 10:16:30 +05302388 pCap->rts_aggr_limit = (8 * 1024);
Sujithf1dc5602008-10-29 10:16:30 +05302389
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05302390#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith2660b812009-02-09 13:27:26 +05302391 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2392 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2393 ah->rfkill_gpio =
2394 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2395 ah->rfkill_polarity =
2396 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
Sujithf1dc5602008-10-29 10:16:30 +05302397
2398 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2399 }
2400#endif
Vasanthakumar Thiagarajand5d11542010-05-17 18:57:56 -07002401 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
Vivek Natarajanbde748a2010-04-05 14:48:05 +05302402 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2403 else
2404 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
Sujithf1dc5602008-10-29 10:16:30 +05302405
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05302406 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302407 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2408 else
2409 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2410
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002411 if (AR_SREV_9300_20_OR_LATER(ah)) {
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002412 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
Gabor Juhos0e707a92011-06-21 11:23:31 +02002413 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002414 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2415
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002416 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2417 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2418 pCap->rx_status_len = sizeof(struct ar9003_rxs);
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002419 pCap->tx_desc_len = sizeof(struct ar9003_txc);
Vasanthakumar Thiagarajan5088c2f2010-04-15 17:39:34 -04002420 pCap->txs_len = sizeof(struct ar9003_txs);
Luis R. Rodriguez6f481012011-01-20 17:47:39 -08002421 if (!ah->config.paprd_disable &&
2422 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
Felix Fietkau49352502010-06-12 00:33:59 -04002423 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002424 } else {
2425 pCap->tx_desc_len = sizeof(struct ath_desc);
Felix Fietkaua949b172011-07-09 11:12:47 +07002426 if (AR_SREV_9280_20(ah))
Felix Fietkau6b42e8d2010-04-26 15:04:35 -04002427 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002428 }
Vasanthakumar Thiagarajan1adf02f2010-04-15 17:38:24 -04002429
Vasanthakumar Thiagarajan6c84ce02010-04-15 17:39:16 -04002430 if (AR_SREV_9300_20_OR_LATER(ah))
2431 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2432
Senthil Balasubramanian6ee63f52010-11-10 05:03:16 -08002433 if (AR_SREV_9300_20_OR_LATER(ah))
2434 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2435
Felix Fietkaua42acef2010-09-22 12:34:54 +02002436 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
Vasanthakumar Thiagarajan6473d242010-05-13 18:42:38 -07002437 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2438
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002439 if (AR_SREV_9285(ah))
2440 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2441 ant_div_ctl1 =
2442 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2443 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2444 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2445 }
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +05302446 if (AR_SREV_9300_20_OR_LATER(ah)) {
2447 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2448 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2449 }
2450
2451
Gabor Juhos431da562011-06-21 11:23:41 +02002452 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302453 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2454 /*
2455 * enable the diversity-combining algorithm only when
2456 * both enable_lna_div and enable_fast_div are set
2457 * Table for Diversity
2458 * ant_div_alt_lnaconf bit 0-1
2459 * ant_div_main_lnaconf bit 2-3
2460 * ant_div_alt_gaintb bit 4
2461 * ant_div_main_gaintb bit 5
2462 * enable_ant_div_lnadiv bit 6
2463 * enable_ant_fast_div bit 7
2464 */
2465 if ((ant_div_ctl1 >> 0x6) == 0x3)
2466 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2467 }
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002468
Vasanthakumar Thiagarajan8060e162010-12-06 04:27:42 -08002469 if (AR_SREV_9485_10(ah)) {
2470 pCap->pcie_lcr_extsync_en = true;
2471 pCap->pcie_lcr_offset = 0x80;
2472 }
2473
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002474 if (ath9k_hw_dfs_tested(ah))
2475 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2476
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002477 tx_chainmask = pCap->tx_chainmask;
2478 rx_chainmask = pCap->rx_chainmask;
2479 while (tx_chainmask || rx_chainmask) {
2480 if (tx_chainmask & BIT(0))
2481 pCap->max_txchains++;
2482 if (rx_chainmask & BIT(0))
2483 pCap->max_rxchains++;
2484
2485 tx_chainmask >>= 1;
2486 rx_chainmask >>= 1;
2487 }
2488
Rajkumar Manoharan8ad74c42011-10-13 11:00:38 +05302489 if (AR_SREV_9300_20_OR_LATER(ah)) {
2490 ah->enabled_cals |= TX_IQ_CAL;
Mohammed Shafi Shajakhan6fea5932011-11-30 21:01:31 +05302491 if (AR_SREV_9485_OR_LATER(ah))
Rajkumar Manoharan8ad74c42011-10-13 11:00:38 +05302492 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2493 }
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302494 if (AR_SREV_9462(ah))
Rajkumar Manoharan7dc181c2011-10-24 18:19:49 +05302495 pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI;
Rajkumar Manoharan324c74a2011-10-13 11:00:41 +05302496
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002497 return 0;
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002498}
2499
Sujithf1dc5602008-10-29 10:16:30 +05302500/****************************/
2501/* GPIO / RFKILL / Antennae */
2502/****************************/
2503
Sujithcbe61d82009-02-09 13:27:12 +05302504static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302505 u32 gpio, u32 type)
2506{
2507 int addr;
2508 u32 gpio_shift, tmp;
2509
2510 if (gpio > 11)
2511 addr = AR_GPIO_OUTPUT_MUX3;
2512 else if (gpio > 5)
2513 addr = AR_GPIO_OUTPUT_MUX2;
2514 else
2515 addr = AR_GPIO_OUTPUT_MUX1;
2516
2517 gpio_shift = (gpio % 6) * 5;
2518
2519 if (AR_SREV_9280_20_OR_LATER(ah)
2520 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2521 REG_RMW(ah, addr, (type << gpio_shift),
2522 (0x1f << gpio_shift));
2523 } else {
2524 tmp = REG_READ(ah, addr);
2525 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2526 tmp &= ~(0x1f << gpio_shift);
2527 tmp |= (type << gpio_shift);
2528 REG_WRITE(ah, addr, tmp);
2529 }
2530}
2531
Sujithcbe61d82009-02-09 13:27:12 +05302532void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302533{
2534 u32 gpio_shift;
2535
Luis R. Rodriguez9680e8a2009-09-13 23:28:00 -07002536 BUG_ON(gpio >= ah->caps.num_gpio_pins);
Sujithf1dc5602008-10-29 10:16:30 +05302537
Sujith88c1f4f2010-06-30 14:46:31 +05302538 if (AR_DEVID_7010(ah)) {
2539 gpio_shift = gpio;
2540 REG_RMW(ah, AR7010_GPIO_OE,
2541 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2542 (AR7010_GPIO_OE_MASK << gpio_shift));
2543 return;
2544 }
Sujithf1dc5602008-10-29 10:16:30 +05302545
Sujith88c1f4f2010-06-30 14:46:31 +05302546 gpio_shift = gpio << 1;
Sujithf1dc5602008-10-29 10:16:30 +05302547 REG_RMW(ah,
2548 AR_GPIO_OE_OUT,
2549 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2550 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2551}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002552EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
Sujithf1dc5602008-10-29 10:16:30 +05302553
Sujithcbe61d82009-02-09 13:27:12 +05302554u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302555{
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302556#define MS_REG_READ(x, y) \
2557 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2558
Sujith2660b812009-02-09 13:27:26 +05302559 if (gpio >= ah->caps.num_gpio_pins)
Sujithf1dc5602008-10-29 10:16:30 +05302560 return 0xffffffff;
2561
Sujith88c1f4f2010-06-30 14:46:31 +05302562 if (AR_DEVID_7010(ah)) {
2563 u32 val;
2564 val = REG_READ(ah, AR7010_GPIO_IN);
2565 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2566 } else if (AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan93069902010-11-30 23:24:09 -08002567 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2568 AR_GPIO_BIT(gpio)) != 0;
Felix Fietkau783dfca2010-04-15 17:38:11 -04002569 else if (AR_SREV_9271(ah))
Sujith5b5fa352010-03-17 14:25:15 +05302570 return MS_REG_READ(AR9271, gpio) != 0;
Felix Fietkaua42acef2010-09-22 12:34:54 +02002571 else if (AR_SREV_9287_11_OR_LATER(ah))
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05302572 return MS_REG_READ(AR9287, gpio) != 0;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002573 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302574 return MS_REG_READ(AR9285, gpio) != 0;
Felix Fietkau7a370812010-09-22 12:34:52 +02002575 else if (AR_SREV_9280_20_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302576 return MS_REG_READ(AR928X, gpio) != 0;
2577 else
2578 return MS_REG_READ(AR, gpio) != 0;
Sujithf1dc5602008-10-29 10:16:30 +05302579}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002580EXPORT_SYMBOL(ath9k_hw_gpio_get);
Sujithf1dc5602008-10-29 10:16:30 +05302581
Sujithcbe61d82009-02-09 13:27:12 +05302582void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
Sujithf1dc5602008-10-29 10:16:30 +05302583 u32 ah_signal_type)
2584{
2585 u32 gpio_shift;
2586
Sujith88c1f4f2010-06-30 14:46:31 +05302587 if (AR_DEVID_7010(ah)) {
2588 gpio_shift = gpio;
2589 REG_RMW(ah, AR7010_GPIO_OE,
2590 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2591 (AR7010_GPIO_OE_MASK << gpio_shift));
2592 return;
2593 }
2594
Sujithf1dc5602008-10-29 10:16:30 +05302595 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
Sujithf1dc5602008-10-29 10:16:30 +05302596 gpio_shift = 2 * gpio;
Sujithf1dc5602008-10-29 10:16:30 +05302597 REG_RMW(ah,
2598 AR_GPIO_OE_OUT,
2599 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2600 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2601}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002602EXPORT_SYMBOL(ath9k_hw_cfg_output);
Sujithf1dc5602008-10-29 10:16:30 +05302603
Sujithcbe61d82009-02-09 13:27:12 +05302604void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Sujithf1dc5602008-10-29 10:16:30 +05302605{
Sujith88c1f4f2010-06-30 14:46:31 +05302606 if (AR_DEVID_7010(ah)) {
2607 val = val ? 0 : 1;
2608 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2609 AR_GPIO_BIT(gpio));
2610 return;
2611 }
2612
Sujith5b5fa352010-03-17 14:25:15 +05302613 if (AR_SREV_9271(ah))
2614 val = ~val;
2615
Sujithf1dc5602008-10-29 10:16:30 +05302616 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2617 AR_GPIO_BIT(gpio));
2618}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002619EXPORT_SYMBOL(ath9k_hw_set_gpio);
Sujithf1dc5602008-10-29 10:16:30 +05302620
Sujithcbe61d82009-02-09 13:27:12 +05302621u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302622{
2623 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2624}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002625EXPORT_SYMBOL(ath9k_hw_getdefantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302626
Sujithcbe61d82009-02-09 13:27:12 +05302627void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
Sujithf1dc5602008-10-29 10:16:30 +05302628{
2629 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2630}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002631EXPORT_SYMBOL(ath9k_hw_setantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302632
Sujithf1dc5602008-10-29 10:16:30 +05302633/*********************/
2634/* General Operation */
2635/*********************/
2636
Sujithcbe61d82009-02-09 13:27:12 +05302637u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302638{
2639 u32 bits = REG_READ(ah, AR_RX_FILTER);
2640 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2641
2642 if (phybits & AR_PHY_ERR_RADAR)
2643 bits |= ATH9K_RX_FILTER_PHYRADAR;
2644 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2645 bits |= ATH9K_RX_FILTER_PHYERR;
2646
2647 return bits;
2648}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002649EXPORT_SYMBOL(ath9k_hw_getrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302650
Sujithcbe61d82009-02-09 13:27:12 +05302651void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Sujithf1dc5602008-10-29 10:16:30 +05302652{
2653 u32 phybits;
2654
Sujith7d0d0df2010-04-16 11:53:57 +05302655 ENABLE_REGWRITE_BUFFER(ah);
2656
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302657 if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302658 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2659
Sujith7ea310b2009-09-03 12:08:43 +05302660 REG_WRITE(ah, AR_RX_FILTER, bits);
2661
Sujithf1dc5602008-10-29 10:16:30 +05302662 phybits = 0;
2663 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2664 phybits |= AR_PHY_ERR_RADAR;
2665 if (bits & ATH9K_RX_FILTER_PHYERR)
2666 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2667 REG_WRITE(ah, AR_PHY_ERR, phybits);
2668
2669 if (phybits)
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002670 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujithf1dc5602008-10-29 10:16:30 +05302671 else
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002672 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujith7d0d0df2010-04-16 11:53:57 +05302673
2674 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302675}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002676EXPORT_SYMBOL(ath9k_hw_setrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302677
Sujithcbe61d82009-02-09 13:27:12 +05302678bool ath9k_hw_phy_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302679{
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302680 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2681 return false;
2682
2683 ath9k_hw_init_pll(ah, NULL);
2684 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302685}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002686EXPORT_SYMBOL(ath9k_hw_phy_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302687
Sujithcbe61d82009-02-09 13:27:12 +05302688bool ath9k_hw_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302689{
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002690 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05302691 return false;
2692
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302693 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2694 return false;
2695
2696 ath9k_hw_init_pll(ah, NULL);
2697 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302698}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002699EXPORT_SYMBOL(ath9k_hw_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302700
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002701static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05302702{
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002703 enum eeprom_param gain_param;
Felix Fietkau9c204b42011-07-27 15:01:05 +02002704
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002705 if (IS_CHAN_2GHZ(chan))
2706 gain_param = EEP_ANTENNA_GAIN_2G;
2707 else
2708 gain_param = EEP_ANTENNA_GAIN_5G;
Sujithf1dc5602008-10-29 10:16:30 +05302709
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002710 return ah->eep_ops->get_eeprom(ah, gain_param);
2711}
2712
2713void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2714{
2715 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2716 struct ieee80211_channel *channel;
2717 int chan_pwr, new_pwr, max_gain;
2718 int ant_gain, ant_reduction = 0;
2719
2720 if (!chan)
2721 return;
2722
2723 channel = chan->chan;
2724 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2725 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2726 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2727
2728 ant_gain = get_antenna_gain(ah, chan);
2729 if (ant_gain > max_gain)
2730 ant_reduction = ant_gain - max_gain;
Sujithf1dc5602008-10-29 10:16:30 +05302731
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07002732 ah->eep_ops->set_txpower(ah, chan,
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002733 ath9k_regd_get_ctl(reg, chan),
2734 ant_reduction, new_pwr, false);
2735}
2736
2737void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2738{
2739 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2740 struct ath9k_channel *chan = ah->curchan;
2741 struct ieee80211_channel *channel = chan->chan;
2742
Dan Carpenter48ef5c42011-10-17 10:28:23 +03002743 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002744 if (test)
2745 channel->max_power = MAX_RATE_POWER / 2;
2746
2747 ath9k_hw_apply_txpower(ah, chan);
2748
2749 if (test)
2750 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
Sujithf1dc5602008-10-29 10:16:30 +05302751}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002752EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
Sujithf1dc5602008-10-29 10:16:30 +05302753
Sujithcbe61d82009-02-09 13:27:12 +05302754void ath9k_hw_setopmode(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302755{
Sujith2660b812009-02-09 13:27:26 +05302756 ath9k_hw_set_operating_mode(ah, ah->opmode);
Sujithf1dc5602008-10-29 10:16:30 +05302757}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002758EXPORT_SYMBOL(ath9k_hw_setopmode);
Sujithf1dc5602008-10-29 10:16:30 +05302759
Sujithcbe61d82009-02-09 13:27:12 +05302760void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
Sujithf1dc5602008-10-29 10:16:30 +05302761{
2762 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2763 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2764}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002765EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302766
Luis R. Rodriguezf2b21432009-09-10 08:50:20 -07002767void ath9k_hw_write_associd(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302768{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07002769 struct ath_common *common = ath9k_hw_common(ah);
2770
2771 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2772 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2773 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
Sujithf1dc5602008-10-29 10:16:30 +05302774}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002775EXPORT_SYMBOL(ath9k_hw_write_associd);
Sujithf1dc5602008-10-29 10:16:30 +05302776
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002777#define ATH9K_MAX_TSF_READ 10
2778
Sujithcbe61d82009-02-09 13:27:12 +05302779u64 ath9k_hw_gettsf64(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302780{
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002781 u32 tsf_lower, tsf_upper1, tsf_upper2;
2782 int i;
Sujithf1dc5602008-10-29 10:16:30 +05302783
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002784 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2785 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2786 tsf_lower = REG_READ(ah, AR_TSF_L32);
2787 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2788 if (tsf_upper2 == tsf_upper1)
2789 break;
2790 tsf_upper1 = tsf_upper2;
2791 }
Sujithf1dc5602008-10-29 10:16:30 +05302792
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002793 WARN_ON( i == ATH9K_MAX_TSF_READ );
2794
2795 return (((u64)tsf_upper1 << 32) | tsf_lower);
Sujithf1dc5602008-10-29 10:16:30 +05302796}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002797EXPORT_SYMBOL(ath9k_hw_gettsf64);
Sujithf1dc5602008-10-29 10:16:30 +05302798
Sujithcbe61d82009-02-09 13:27:12 +05302799void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002800{
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002801 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
Alina Friedrichsenb9a16192009-03-02 23:28:38 +01002802 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002803}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002804EXPORT_SYMBOL(ath9k_hw_settsf64);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002805
Sujithcbe61d82009-02-09 13:27:12 +05302806void ath9k_hw_reset_tsf(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302807{
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002808 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2809 AH_TSF_WRITE_TIMEOUT))
Joe Perchesd2182b62011-12-15 14:55:53 -08002810 ath_dbg(ath9k_hw_common(ah), RESET,
Joe Perches226afe62010-12-02 19:12:37 -08002811 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002812
Sujithf1dc5602008-10-29 10:16:30 +05302813 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002814}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002815EXPORT_SYMBOL(ath9k_hw_reset_tsf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002816
Sujith54e4cec2009-08-07 09:45:09 +05302817void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002818{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002819 if (setting)
Sujith2660b812009-02-09 13:27:26 +05302820 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002821 else
Sujith2660b812009-02-09 13:27:26 +05302822 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002823}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002824EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002825
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002826void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002827{
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002828 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithf1dc5602008-10-29 10:16:30 +05302829 u32 macmode;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002830
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002831 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
Sujithf1dc5602008-10-29 10:16:30 +05302832 macmode = AR_2040_JOINED_RX_CLEAR;
2833 else
2834 macmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002835
Sujithf1dc5602008-10-29 10:16:30 +05302836 REG_WRITE(ah, AR_2040_MODE, macmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002837}
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302838
2839/* HW Generic timers configuration */
2840
2841static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2842{
2843 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2844 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2845 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2846 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2847 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2848 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2849 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2850 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2851 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2852 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2853 AR_NDP2_TIMER_MODE, 0x0002},
2854 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2855 AR_NDP2_TIMER_MODE, 0x0004},
2856 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2857 AR_NDP2_TIMER_MODE, 0x0008},
2858 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2859 AR_NDP2_TIMER_MODE, 0x0010},
2860 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2861 AR_NDP2_TIMER_MODE, 0x0020},
2862 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2863 AR_NDP2_TIMER_MODE, 0x0040},
2864 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2865 AR_NDP2_TIMER_MODE, 0x0080}
2866};
2867
2868/* HW generic timer primitives */
2869
2870/* compute and clear index of rightmost 1 */
2871static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2872{
2873 u32 b;
2874
2875 b = *mask;
2876 b &= (0-b);
2877 *mask &= ~b;
2878 b *= debruijn32;
2879 b >>= 27;
2880
2881 return timer_table->gen_timer_index[b];
2882}
2883
Felix Fietkaudd347f22011-03-22 21:54:17 +01002884u32 ath9k_hw_gettsf32(struct ath_hw *ah)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302885{
2886 return REG_READ(ah, AR_TSF_L32);
2887}
Felix Fietkaudd347f22011-03-22 21:54:17 +01002888EXPORT_SYMBOL(ath9k_hw_gettsf32);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302889
2890struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2891 void (*trigger)(void *),
2892 void (*overflow)(void *),
2893 void *arg,
2894 u8 timer_index)
2895{
2896 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2897 struct ath_gen_timer *timer;
2898
2899 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2900
2901 if (timer == NULL) {
Joe Perches38002762010-12-02 19:12:36 -08002902 ath_err(ath9k_hw_common(ah),
2903 "Failed to allocate memory for hw timer[%d]\n",
2904 timer_index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302905 return NULL;
2906 }
2907
2908 /* allocate a hardware generic timer slot */
2909 timer_table->timers[timer_index] = timer;
2910 timer->index = timer_index;
2911 timer->trigger = trigger;
2912 timer->overflow = overflow;
2913 timer->arg = arg;
2914
2915 return timer;
2916}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002917EXPORT_SYMBOL(ath_gen_timer_alloc);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302918
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002919void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2920 struct ath_gen_timer *timer,
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05302921 u32 trig_timeout,
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002922 u32 timer_period)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302923{
2924 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05302925 u32 tsf, timer_next;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302926
2927 BUG_ON(!timer_period);
2928
2929 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2930
2931 tsf = ath9k_hw_gettsf32(ah);
2932
Vasanthakumar Thiagarajan788f6872011-04-21 18:33:27 +05302933 timer_next = tsf + trig_timeout;
2934
Joe Perchesd2182b62011-12-15 14:55:53 -08002935 ath_dbg(ath9k_hw_common(ah), HWTIMER,
Joe Perches226afe62010-12-02 19:12:37 -08002936 "current tsf %x period %x timer_next %x\n",
2937 tsf, timer_period, timer_next);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302938
2939 /*
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302940 * Program generic timer registers
2941 */
2942 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2943 timer_next);
2944 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2945 timer_period);
2946 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2947 gen_tmr_configuration[timer->index].mode_mask);
2948
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302949 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302950 /*
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302951 * Starting from AR9462, each generic timer can select which tsf
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302952 * to use. But we still follow the old rule, 0 - 7 use tsf and
2953 * 8 - 15 use tsf2.
2954 */
2955 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2956 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2957 (1 << timer->index));
2958 else
2959 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2960 (1 << timer->index));
2961 }
2962
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302963 /* Enable both trigger and thresh interrupt masks */
2964 REG_SET_BIT(ah, AR_IMR_S5,
2965 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2966 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302967}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002968EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302969
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002970void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302971{
2972 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2973
2974 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2975 (timer->index >= ATH_MAX_GEN_TIMER)) {
2976 return;
2977 }
2978
2979 /* Clear generic timer enable bits. */
2980 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2981 gen_tmr_configuration[timer->index].mode_mask);
2982
2983 /* Disable both trigger and thresh interrupt masks */
2984 REG_CLR_BIT(ah, AR_IMR_S5,
2985 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2986 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2987
2988 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302989}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002990EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302991
2992void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2993{
2994 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2995
2996 /* free the hardware generic timer slot */
2997 timer_table->timers[timer->index] = NULL;
2998 kfree(timer);
2999}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003000EXPORT_SYMBOL(ath_gen_timer_free);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303001
3002/*
3003 * Generic Timer Interrupts handling
3004 */
3005void ath_gen_timer_isr(struct ath_hw *ah)
3006{
3007 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3008 struct ath_gen_timer *timer;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003009 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303010 u32 trigger_mask, thresh_mask, index;
3011
3012 /* get hardware generic timer interrupt status */
3013 trigger_mask = ah->intr_gen_timer_trigger;
3014 thresh_mask = ah->intr_gen_timer_thresh;
3015 trigger_mask &= timer_table->timer_mask.val;
3016 thresh_mask &= timer_table->timer_mask.val;
3017
3018 trigger_mask &= ~thresh_mask;
3019
3020 while (thresh_mask) {
3021 index = rightmost_index(timer_table, &thresh_mask);
3022 timer = timer_table->timers[index];
3023 BUG_ON(!timer);
Joe Perchesd2182b62011-12-15 14:55:53 -08003024 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3025 index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303026 timer->overflow(timer->arg);
3027 }
3028
3029 while (trigger_mask) {
3030 index = rightmost_index(timer_table, &trigger_mask);
3031 timer = timer_table->timers[index];
3032 BUG_ON(!timer);
Joe Perchesd2182b62011-12-15 14:55:53 -08003033 ath_dbg(common, HWTIMER,
Joe Perches226afe62010-12-02 19:12:37 -08003034 "Gen timer[%d] trigger\n", index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303035 timer->trigger(timer->arg);
3036 }
3037}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003038EXPORT_SYMBOL(ath_gen_timer_isr);
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003039
Sujith05020d22010-03-17 14:25:23 +05303040/********/
3041/* HTC */
3042/********/
3043
3044void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3045{
3046 ah->htc_reset_init = true;
3047}
3048EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3049
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003050static struct {
3051 u32 version;
3052 const char * name;
3053} ath_mac_bb_names[] = {
3054 /* Devices with external radios */
3055 { AR_SREV_VERSION_5416_PCI, "5416" },
3056 { AR_SREV_VERSION_5416_PCIE, "5418" },
3057 { AR_SREV_VERSION_9100, "9100" },
3058 { AR_SREV_VERSION_9160, "9160" },
3059 /* Single-chip solutions */
3060 { AR_SREV_VERSION_9280, "9280" },
3061 { AR_SREV_VERSION_9285, "9285" },
Luis R. Rodriguez11158472009-10-27 12:59:35 -04003062 { AR_SREV_VERSION_9287, "9287" },
3063 { AR_SREV_VERSION_9271, "9271" },
Luis R. Rodriguezec839032010-04-15 17:39:20 -04003064 { AR_SREV_VERSION_9300, "9300" },
Gabor Juhos2c8e5932011-06-21 11:23:21 +02003065 { AR_SREV_VERSION_9330, "9330" },
Florian Fainelli397e5d52011-08-25 21:33:48 +02003066 { AR_SREV_VERSION_9340, "9340" },
Senthil Balasubramanian8f06ca22011-04-01 17:16:33 +05303067 { AR_SREV_VERSION_9485, "9485" },
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05303068 { AR_SREV_VERSION_9462, "9462" },
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003069};
3070
3071/* For devices with external radios */
3072static struct {
3073 u16 version;
3074 const char * name;
3075} ath_rf_names[] = {
3076 { 0, "5133" },
3077 { AR_RAD5133_SREV_MAJOR, "5133" },
3078 { AR_RAD5122_SREV_MAJOR, "5122" },
3079 { AR_RAD2133_SREV_MAJOR, "2133" },
3080 { AR_RAD2122_SREV_MAJOR, "2122" }
3081};
3082
3083/*
3084 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3085 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003086static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003087{
3088 int i;
3089
3090 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3091 if (ath_mac_bb_names[i].version == mac_bb_version) {
3092 return ath_mac_bb_names[i].name;
3093 }
3094 }
3095
3096 return "????";
3097}
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003098
3099/*
3100 * Return the RF name. "????" is returned if the RF is unknown.
3101 * Used for devices with external radios.
3102 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003103static const char *ath9k_hw_rf_name(u16 rf_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003104{
3105 int i;
3106
3107 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3108 if (ath_rf_names[i].version == rf_version) {
3109 return ath_rf_names[i].name;
3110 }
3111 }
3112
3113 return "????";
3114}
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003115
3116void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3117{
3118 int used;
3119
3120 /* chipsets >= AR9280 are single-chip */
Felix Fietkau7a370812010-09-22 12:34:52 +02003121 if (AR_SREV_9280_20_OR_LATER(ah)) {
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003122 used = snprintf(hw_name, len,
3123 "Atheros AR%s Rev:%x",
3124 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3125 ah->hw_version.macRev);
3126 }
3127 else {
3128 used = snprintf(hw_name, len,
3129 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3130 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3131 ah->hw_version.macRev,
3132 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3133 AR_RADIO_SREV_MAJOR)),
3134 ah->hw_version.phyRev);
3135 }
3136
3137 hw_name[used] = '\0';
3138}
3139EXPORT_SYMBOL(ath9k_hw_name);