Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / d27704d1ec2f9ba06247b402c58a6f2febecef78 / . / arch / arm / boot / dts / omap2420.dtsi
blob: ae89aad01595890511f241c5dd932505e24fa78e [file] [log] [blame]
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]1/*
2 * Device Tree Source for OMAP2420 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard98ef79572013-05-31 14:32:55 +0200[diff] [blame]11#include "omap2.dtsi"
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]12
13/ {
14 compatible = "ti,omap2420", "ti,omap2";
15
16 ocp {
Tero Kristobc797692014-02-21 17:05:02 +0200[diff] [blame]17 prcm: prcm@48008000 {
18 compatible = "ti,omap2-prcm";
19 reg = <0x48008000 0x1000>;
20
21 prcm_clocks: clocks {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 };
25
26 prcm_clockdomains: clockdomains {
27 };
28 };
29
30 scrm: scrm@48000000 {
31 compatible = "ti,omap2-scrm";
32 reg = <0x48000000 0x1000>;
33
34 scrm_clocks: clocks {
35 #address-cells = <1>;
36 #size-cells = <0>;
37 };
38
39 scrm_clockdomains: clockdomains {
40 };
41 };
42
Jon Hunter510c0ff2012-10-25 14:24:14 -0500[diff] [blame]43 counter32k: counter@48004000 {
44 compatible = "ti,omap-counter32k";
45 reg = <0x48004000 0x20>;
46 ti,hwmods = "counter_32k";
47 };
48
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]49 omap2420_pmx: pinmux@48000030 {
50 compatible = "ti,omap2420-padconf", "pinctrl-single";
51 reg = <0x48000030 0x0113>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 pinctrl-single,register-width = <8>;
55 pinctrl-single,function-mask = <0x3f>;
56 };
57
Jon Hunter423182e2013-02-28 15:32:00 -0600[diff] [blame]58 gpio1: gpio@48018000 {
59 compatible = "ti,omap2-gpio";
60 reg = <0x48018000 0x200>;
61 interrupts = <29>;
62 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]63 ti,gpio-always-on;
Jon Hunter423182e2013-02-28 15:32:00 -0600[diff] [blame]64 #gpio-cells = <2>;
65 gpio-controller;
66 #interrupt-cells = <2>;
67 interrupt-controller;
68 };
69
70 gpio2: gpio@4801a000 {
71 compatible = "ti,omap2-gpio";
72 reg = <0x4801a000 0x200>;
73 interrupts = <30>;
74 ti,hwmods = "gpio2";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]75 ti,gpio-always-on;
Jon Hunter423182e2013-02-28 15:32:00 -0600[diff] [blame]76 #gpio-cells = <2>;
77 gpio-controller;
78 #interrupt-cells = <2>;
79 interrupt-controller;
80 };
81
82 gpio3: gpio@4801c000 {
83 compatible = "ti,omap2-gpio";
84 reg = <0x4801c000 0x200>;
85 interrupts = <31>;
86 ti,hwmods = "gpio3";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]87 ti,gpio-always-on;
Jon Hunter423182e2013-02-28 15:32:00 -0600[diff] [blame]88 #gpio-cells = <2>;
89 gpio-controller;
90 #interrupt-cells = <2>;
91 interrupt-controller;
92 };
93
94 gpio4: gpio@4801e000 {
95 compatible = "ti,omap2-gpio";
96 reg = <0x4801e000 0x200>;
97 interrupts = <32>;
98 ti,hwmods = "gpio4";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]99 ti,gpio-always-on;
Jon Hunter423182e2013-02-28 15:32:00 -0600[diff] [blame]100 #gpio-cells = <2>;
101 gpio-controller;
102 #interrupt-cells = <2>;
103 interrupt-controller;
104 };
105
Jon Hunter1c7dbb52013-02-22 15:33:31 -0600[diff] [blame]106 gpmc: gpmc@6800a000 {
107 compatible = "ti,omap2420-gpmc";
108 reg = <0x6800a000 0x1000>;
109 #address-cells = <2>;
110 #size-cells = <1>;
111 interrupts = <20>;
112 gpmc,num-cs = <8>;
113 gpmc,num-waitpins = <4>;
114 ti,hwmods = "gpmc";
115 };
116
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]117 mcbsp1: mcbsp@48074000 {
118 compatible = "ti,omap2420-mcbsp";
119 reg = <0x48074000 0xff>;
120 reg-names = "mpu";
121 interrupts = <59>, /* TX interrupt */
122 <60>; /* RX interrupt */
123 interrupt-names = "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]124 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]125 dmas = <&sdma 31>,
126 <&sdma 32>;
127 dma-names = "tx", "rx";
Peter Ujfalusifaa00de2014-01-24 10:19:06 +0200[diff] [blame]128 status = "disabled";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]129 };
130
131 mcbsp2: mcbsp@48076000 {
132 compatible = "ti,omap2420-mcbsp";
133 reg = <0x48076000 0xff>;
134 reg-names = "mpu";
135 interrupts = <62>, /* TX interrupt */
136 <63>; /* RX interrupt */
137 interrupt-names = "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]138 ti,hwmods = "mcbsp2";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]139 dmas = <&sdma 33>,
140 <&sdma 34>;
141 dma-names = "tx", "rx";
Peter Ujfalusifaa00de2014-01-24 10:19:06 +0200[diff] [blame]142 status = "disabled";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]143 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]144
Tony Lindgren467f4bd2013-11-14 15:25:09 -0800[diff] [blame]145 msdi1: mmc@4809c000 {
146 compatible = "ti,omap2420-mmc";
147 ti,hwmods = "msdi1";
148 reg = <0x4809c000 0x80>;
149 interrupts = <83>;
150 dmas = <&sdma 61 &sdma 62>;
151 dma-names = "tx", "rx";
152 };
153
Suman Anna4fe5bd52014-04-22 17:23:36 -0500[diff] [blame]154 mailbox: mailbox@48094000 {
155 compatible = "ti,omap2-mailbox";
156 reg = <0x48094000 0x200>;
157 interrupts = <26>, <34>;
158 interrupt-names = "dsp", "iva";
159 ti,hwmods = "mailbox";
Suman Anna41ffada2014-07-11 16:44:34 -0500[diff] [blame]160 ti,mbox-num-users = <4>;
161 ti,mbox-num-fifos = <6>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame^]162 mbox_dsp: dsp {
163 ti,mbox-tx = <0 0 0>;
164 ti,mbox-rx = <1 0 0>;
165 };
166 mbox_iva: iva {
167 ti,mbox-tx = <2 1 3>;
168 ti,mbox-rx = <3 1 3>;
169 };
Suman Anna4fe5bd52014-04-22 17:23:36 -0500[diff] [blame]170 };
171
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]172 timer1: timer@48028000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]173 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]174 reg = <0x48028000 0x400>;
175 interrupts = <37>;
176 ti,hwmods = "timer1";
177 ti,timer-alwon;
178 };
Tony Lindgren467f4bd2013-11-14 15:25:09 -0800[diff] [blame]179
180 wd_timer2: wdt@48022000 {
181 compatible = "ti,omap2-wdt";
182 ti,hwmods = "wd_timer2";
183 reg = <0x48022000 0x80>;
184 };
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]185 };
186};
Tony Lindgren467f4bd2013-11-14 15:25:09 -0800[diff] [blame]187
188&i2c1 {
189 compatible = "ti,omap2420-i2c";
190};
191
192&i2c2 {
193 compatible = "ti,omap2420-i2c";
194};
Tero Kristo69a1e7a2014-02-24 18:51:05 +0200[diff] [blame]195
196/include/ "omap24xx-clocks.dtsi"
197/include/ "omap2420-clocks.dtsi"