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Paul Walmsleyad67ef62008-08-19 11:08:40 +03001/*
2 * OMAP2/3 powerdomain control
3 *
Paul Walmsley55ed9692010-01-26 20:12:59 -07004 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
Paul Walmsleyad67ef62008-08-19 11:08:40 +03006 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
16
17#include <linux/types.h>
18#include <linux/list.h>
19
20#include <asm/atomic.h>
21
Tony Lindgrence491cf2009-10-20 09:40:47 -070022#include <plat/cpu.h>
Paul Walmsleyad67ef62008-08-19 11:08:40 +030023
24
25/* Powerdomain basic power states */
26#define PWRDM_POWER_OFF 0x0
27#define PWRDM_POWER_RET 0x1
28#define PWRDM_POWER_INACTIVE 0x2
29#define PWRDM_POWER_ON 0x3
30
Paul Walmsley2354eb52009-12-08 16:33:12 -070031#define PWRDM_MAX_PWRSTS 4
32
Paul Walmsleyad67ef62008-08-19 11:08:40 +030033/* Powerdomain allowable state bitfields */
Rajendra Nayakd3353e12010-05-18 20:24:01 -060034#define PWRSTS_ON (1 << PWRDM_POWER_ON)
Paul Walmsleyad67ef62008-08-19 11:08:40 +030035#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_ON))
37
38#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
39 (1 << PWRDM_POWER_RET))
40
Abhijit Pagaref37c6df2010-01-26 20:12:52 -070041#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
42 (1 << PWRDM_POWER_ON))
43
Paul Walmsleyad67ef62008-08-19 11:08:40 +030044#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
45
46
Paul Walmsley0b7cbfb2008-06-25 18:09:37 -060047/* Powerdomain flags */
48#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
Thara Gopinath3863c742009-12-08 16:33:15 -070049#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
50 * in MEM bank 1 position. This is
51 * true for OMAP3430
52 */
Paul Walmsley0b7cbfb2008-06-25 18:09:37 -060053
Paul Walmsleyad67ef62008-08-19 11:08:40 +030054/*
Abhijit Pagare38900c22010-01-26 20:12:52 -070055 * Number of memory banks that are power-controllable. On OMAP4430, the
56 * maximum is 5.
Paul Walmsleyad67ef62008-08-19 11:08:40 +030057 */
Abhijit Pagare38900c22010-01-26 20:12:52 -070058#define PWRDM_MAX_MEM_BANKS 5
Paul Walmsleyad67ef62008-08-19 11:08:40 +030059
Paul Walmsley8420bb12008-08-19 11:08:44 +030060/*
61 * Maximum number of clockdomains that can be associated with a powerdomain.
Abhijit Pagare38900c22010-01-26 20:12:52 -070062 * CORE powerdomain on OMAP4 is the worst case
Paul Walmsley8420bb12008-08-19 11:08:44 +030063 */
Abhijit Pagare38900c22010-01-26 20:12:52 -070064#define PWRDM_MAX_CLKDMS 9
Paul Walmsley8420bb12008-08-19 11:08:44 +030065
Paul Walmsleyad67ef62008-08-19 11:08:40 +030066/* XXX A completely arbitrary number. What is reasonable here? */
67#define PWRDM_TRANSITION_BAILOUT 100000
68
Paul Walmsley8420bb12008-08-19 11:08:44 +030069struct clockdomain;
Paul Walmsleyad67ef62008-08-19 11:08:40 +030070struct powerdomain;
71
Paul Walmsleyf0271d62010-01-26 20:13:02 -070072/**
73 * struct powerdomain - OMAP powerdomain
74 * @name: Powerdomain name
75 * @omap_chip: represents the OMAP chip types containing this pwrdm
76 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
77 * @pwrsts: Possible powerdomain power states
78 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
79 * @flags: Powerdomain flags
80 * @banks: Number of software-controllable memory banks in this powerdomain
81 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
82 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
83 * @pwrdm_clkdms: Clockdomains in this powerdomain
84 * @node: list_head linking all powerdomains
85 * @state:
86 * @state_counter:
87 * @timer:
88 * @state_timer:
89 */
Paul Walmsleyad67ef62008-08-19 11:08:40 +030090struct powerdomain {
Paul Walmsleyad67ef62008-08-19 11:08:40 +030091 const char *name;
Paul Walmsleyad67ef62008-08-19 11:08:40 +030092 const struct omap_chip_id omap_chip;
Paul Walmsleye0594b42010-01-26 20:13:01 -070093 const s16 prcm_offs;
Paul Walmsleyad67ef62008-08-19 11:08:40 +030094 const u8 pwrsts;
Paul Walmsleyad67ef62008-08-19 11:08:40 +030095 const u8 pwrsts_logic_ret;
Paul Walmsley0b7cbfb2008-06-25 18:09:37 -060096 const u8 flags;
Paul Walmsleyad67ef62008-08-19 11:08:40 +030097 const u8 banks;
Paul Walmsleyad67ef62008-08-19 11:08:40 +030098 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
Paul Walmsleyad67ef62008-08-19 11:08:40 +030099 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
Paul Walmsley8420bb12008-08-19 11:08:44 +0300100 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300101 struct list_head node;
Peter 'p2' De Schrijverba20bb12008-10-15 17:48:43 +0300102 int state;
Paul Walmsley2354eb52009-12-08 16:33:12 -0700103 unsigned state_counter[PWRDM_MAX_PWRSTS];
Thara Gopinathcde08f82010-02-24 12:05:50 -0700104 unsigned ret_logic_off_counter;
105 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
Peter 'p2' De Schrijver331b93f2008-10-15 18:13:48 +0300106
107#ifdef CONFIG_PM_DEBUG
108 s64 timer;
Paul Walmsley2354eb52009-12-08 16:33:12 -0700109 s64 state_timer[PWRDM_MAX_PWRSTS];
Peter 'p2' De Schrijver331b93f2008-10-15 18:13:48 +0300110#endif
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300111};
112
113
114void pwrdm_init(struct powerdomain **pwrdm_list);
115
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300116struct powerdomain *pwrdm_lookup(const char *name);
117
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300118int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
119 void *user);
Artem Bityutskiyee894b12009-10-01 10:01:55 +0300120int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
121 void *user);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300122
Paul Walmsley8420bb12008-08-19 11:08:44 +0300123int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
124int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
125int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
126 int (*fn)(struct powerdomain *pwrdm,
127 struct clockdomain *clkdm));
128
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300129int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
130
131int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
132int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
Paul Walmsleyfecb4942009-01-27 19:12:50 -0700133int pwrdm_read_pwrst(struct powerdomain *pwrdm);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300134int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
135int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
136
137int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
138int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
139int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
140
141int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
142int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
Thara Gopinath1e3d0d22010-02-24 12:05:49 -0700143int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300144int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
145int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
Thara Gopinath1e3d0d22010-02-24 12:05:49 -0700146int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300147
Paul Walmsley0b7cbfb2008-06-25 18:09:37 -0600148int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
149int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
150bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
151
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300152int pwrdm_wait_transition(struct powerdomain *pwrdm);
153
Peter 'p2' De Schrijverba20bb12008-10-15 17:48:43 +0300154int pwrdm_state_switch(struct powerdomain *pwrdm);
155int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
156int pwrdm_pre_transition(void);
157int pwrdm_post_transition(void);
158
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300159#endif