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Kuninori Morimotof1407d52011-04-04 13:44:59 +09001/*
2 * Renesas USB driver
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
15 *
16 */
17#ifndef RENESAS_USB_DRIVER_H
18#define RENESAS_USB_DRIVER_H
19
20#include <linux/platform_device.h>
21#include <linux/usb/renesas_usbhs.h>
22
23struct usbhs_priv;
24
Paul Bollecc502bb2012-06-03 18:39:13 +020025#include "mod.h"
26#include "pipe.h"
Kuninori Morimotof1407d52011-04-04 13:44:59 +090027
28/*
29 *
30 * register define
31 *
32 */
33#define SYSCFG 0x0000
34#define BUSWAIT 0x0002
35#define DVSTCTR 0x0008
Kuninori Morimotodfbb7f42011-11-24 17:28:35 -080036#define TESTMODE 0x000C
Kuninori Morimotof1407d52011-04-04 13:44:59 +090037#define CFIFO 0x0014
38#define CFIFOSEL 0x0020
39#define CFIFOCTR 0x0022
Kuninori Morimotoe73a9892011-06-06 14:19:03 +090040#define D0FIFO 0x0100
41#define D0FIFOSEL 0x0028
42#define D0FIFOCTR 0x002A
43#define D1FIFO 0x0120
44#define D1FIFOSEL 0x002C
45#define D1FIFOCTR 0x002E
Kuninori Morimotof1407d52011-04-04 13:44:59 +090046#define INTENB0 0x0030
47#define INTENB1 0x0032
48#define BRDYENB 0x0036
49#define NRDYENB 0x0038
50#define BEMPENB 0x003A
51#define INTSTS0 0x0040
52#define INTSTS1 0x0042
53#define BRDYSTS 0x0046
54#define NRDYSTS 0x0048
55#define BEMPSTS 0x004A
56#define FRMNUM 0x004C
57#define USBREQ 0x0054 /* USB request type register */
58#define USBVAL 0x0056 /* USB request value register */
59#define USBINDX 0x0058 /* USB request index register */
60#define USBLENG 0x005A /* USB request length register */
61#define DCPCFG 0x005C
62#define DCPMAXP 0x005E
63#define DCPCTR 0x0060
64#define PIPESEL 0x0064
65#define PIPECFG 0x0068
66#define PIPEBUF 0x006A
67#define PIPEMAXP 0x006C
68#define PIPEPERI 0x006E
69#define PIPEnCTR 0x0070
Kuninori Morimotoe73a9892011-06-06 14:19:03 +090070#define PIPE1TRE 0x0090
71#define PIPE1TRN 0x0092
72#define PIPE2TRE 0x0094
73#define PIPE2TRN 0x0096
74#define PIPE3TRE 0x0098
75#define PIPE3TRN 0x009A
76#define PIPE4TRE 0x009C
77#define PIPE4TRN 0x009E
78#define PIPE5TRE 0x00A0
79#define PIPE5TRN 0x00A2
80#define PIPEBTRE 0x00A4
81#define PIPEBTRN 0x00A6
82#define PIPECTRE 0x00A8
83#define PIPECTRN 0x00AA
84#define PIPEDTRE 0x00AC
85#define PIPEDTRN 0x00AE
86#define PIPEETRE 0x00B0
87#define PIPEETRN 0x00B2
88#define PIPEFTRE 0x00B4
89#define PIPEFTRN 0x00B6
90#define PIPE9TRE 0x00B8
91#define PIPE9TRN 0x00BA
92#define PIPEATRE 0x00BC
93#define PIPEATRN 0x00BE
Kuninori Morimotoeb051912011-10-10 22:06:46 -070094#define DEVADD0 0x00D0 /* Device address n configuration */
95#define DEVADD1 0x00D2
96#define DEVADD2 0x00D4
97#define DEVADD3 0x00D6
98#define DEVADD4 0x00D8
99#define DEVADD5 0x00DA
100#define DEVADD6 0x00DC
101#define DEVADD7 0x00DE
102#define DEVADD8 0x00E0
103#define DEVADD9 0x00E2
104#define DEVADDA 0x00E4
Yoshihiro Shimodad3cf6a42014-11-10 20:02:47 +0900105#define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
106#define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
107#define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
108#define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900109
110/* SYSCFG */
111#define SCKE (1 << 10) /* USB Module Clock Enable */
112#define HSE (1 << 7) /* High-Speed Operation Enable */
113#define DCFM (1 << 6) /* Controller Function Select */
114#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
115#define DPRPU (1 << 4) /* D+ Line Resistance Control */
116#define USBE (1 << 0) /* USB Module Operation Enable */
117
118/* DVSTCTR */
119#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
120#define PWEN (1 << 9) /* Controls the PWEN pin output state */
Kuninori Morimoto258485d2011-10-10 22:01:40 -0700121#define USBRST (1 << 6) /* Bus Reset Output */
122#define UACT (1 << 4) /* USB Bus Enable */
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900123#define RHST (0x7) /* Reset Handshake */
124#define RHST_LOW_SPEED 1 /* Low-speed connection */
125#define RHST_FULL_SPEED 2 /* Full-speed connection */
126#define RHST_HIGH_SPEED 3 /* High-speed connection */
127
128/* CFIFOSEL */
Kuninori Morimotoe73a9892011-06-06 14:19:03 +0900129#define DREQE (1 << 12) /* DMA Transfer Request Enable */
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900130#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
131
132/* CFIFOCTR */
133#define BVAL (1 << 15) /* Buffer Memory Enable Flag */
134#define BCLR (1 << 14) /* CPU buffer clear */
135#define FRDY (1 << 13) /* FIFO Port Ready */
136#define DTLN_MASK (0x0FFF) /* Receive Data Length */
137
138/* INTENB0 */
139#define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
140#define RSME (1 << 14) /* Enable IRQ Resume */
141#define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
142#define DVSE (1 << 12) /* Enable IRQ Device State Transition */
143#define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
144#define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
145#define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
146#define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
147
148/* INTENB1 */
149#define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
150#define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
151#define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
152#define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
153#define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
154#define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
155
156/* INTSTS0 */
Kuninori Morimotob002ff62011-04-28 16:41:20 +0900157#define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900158#define DVST (1 << 12) /* Device State Transition Interrupt Status */
159#define CTRT (1 << 11) /* Control Stage Interrupt Status */
160#define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
161#define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
162#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
163#define VALID (1 << 3) /* USB Request Receive */
164
165#define DVSQ_MASK (0x3 << 4) /* Device State */
166#define POWER_STATE (0 << 4)
167#define DEFAULT_STATE (1 << 4)
168#define ADDRESS_STATE (2 << 4)
169#define CONFIGURATION_STATE (3 << 4)
170
171#define CTSQ_MASK (0x7) /* Control Transfer Stage */
172#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
173#define READ_DATA_STAGE 1 /* Control read data stage */
174#define READ_STATUS_STAGE 2 /* Control read status stage */
175#define WRITE_DATA_STAGE 3 /* Control write data stage */
176#define WRITE_STATUS_STAGE 4 /* Control write status stage */
177#define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
178#define SEQUENCE_ERROR 6 /* Control transfer sequence error */
179
Kuninori Morimoto89c1d2e2011-10-10 22:06:57 -0700180/* INTSTS1 */
181#define OVRCR (1 << 15) /* OVRCR Interrupt Status */
182#define BCHG (1 << 14) /* USB Bus Change Interrupt Status */
183#define DTCH (1 << 12) /* USB Disconnection Detect Interrupt Status */
184#define ATTCH (1 << 11) /* ATTCH Interrupt Status */
185#define EOFERR (1 << 6) /* EOF Error Detect Interrupt Status */
186#define SIGN (1 << 5) /* Setup Transaction Error Interrupt Status */
187#define SACK (1 << 4) /* Setup Transaction ACK Response Interrupt Status */
188
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900189/* PIPECFG */
190/* DCPCFG */
191#define TYPE_NONE (0 << 14) /* Transfer Type */
192#define TYPE_BULK (1 << 14)
193#define TYPE_INT (2 << 14)
194#define TYPE_ISO (3 << 14)
195#define DBLB (1 << 9) /* Double Buffer Mode */
196#define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */
197#define DIR_OUT (1 << 4) /* Transfer Direction */
198
199/* PIPEMAXP */
200/* DCPMAXP */
201#define DEVSEL_MASK (0xF << 12) /* Device Select */
202#define DCP_MAXP_MASK (0x7F)
203#define PIPE_MAXP_MASK (0x7FF)
204
205/* PIPEBUF */
206#define BUFSIZE_SHIFT 10
207#define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT)
208#define BUFNMB_MASK (0xFF)
209
210/* PIPEnCTR */
211/* DCPCTR */
212#define BSTS (1 << 15) /* Buffer Status */
Kuninori Morimotoef8bedb2011-10-10 22:02:33 -0700213#define SUREQ (1 << 14) /* Sending SETUP Token */
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900214#define CSSTS (1 << 12) /* CSSTS Status */
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900215#define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
Kuninori Morimoto6e6db822011-10-10 22:05:30 -0700216#define SQCLR (1 << 8) /* Toggle Bit Clear */
217#define SQSET (1 << 7) /* Toggle Bit Set */
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900218#define PBUSY (1 << 5) /* Pipe Busy */
219#define PID_MASK (0x3) /* Response PID */
220#define PID_NAK 0
221#define PID_BUF 1
222#define PID_STALL10 2
223#define PID_STALL11 3
224
225#define CCPL (1 << 2) /* Control Transfer End Enable */
226
Kuninori Morimotoe73a9892011-06-06 14:19:03 +0900227/* PIPEnTRE */
228#define TRENB (1 << 9) /* Transaction Counter Enable */
229#define TRCLR (1 << 8) /* Transaction Counter Clear */
230
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900231/* FRMNUM */
232#define FRNM_MASK (0x7FF)
233
Kuninori Morimotoeb051912011-10-10 22:06:46 -0700234/* DEVADDn */
235#define UPPHUB(x) (((x) & 0xF) << 11) /* HUB Register */
236#define HUBPORT(x) (((x) & 0x7) << 8) /* HUB Port for Target Device */
237#define USBSPD(x) (((x) & 0x3) << 6) /* Device Transfer Rate */
238#define USBSPD_SPEED_LOW 0x1
239#define USBSPD_SPEED_FULL 0x2
240#define USBSPD_SPEED_HIGH 0x3
241
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900242/*
243 * struct
244 */
245struct usbhs_priv {
246
247 void __iomem *base;
248 unsigned int irq;
Shimoda, Yoshihiro53069af2012-01-05 15:37:18 +0900249 unsigned long irqflags;
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900250
Kuninori Morimoto48298202011-10-12 21:02:22 -0700251 struct renesas_usbhs_platform_callback pfunc;
252 struct renesas_usbhs_driver_param dparam;
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900253
Kuninori Morimotobc573812011-04-28 16:41:14 +0900254 struct delayed_work notify_hotplug_work;
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900255 struct platform_device *pdev;
256
257 spinlock_t lock;
258
Kuninori Morimotob002ff62011-04-28 16:41:20 +0900259 u32 flags;
260
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900261 /*
262 * module control
263 */
264 struct usbhs_mod_info mod_info;
265
266 /*
267 * pipe control
268 */
269 struct usbhs_pipe_info pipe_info;
Kuninori Morimotod3af90a2011-06-06 14:18:44 +0900270
271 /*
272 * fifo control
273 */
274 struct usbhs_fifo_info fifo_info;
Ulrich Hecht8ecef002014-07-10 09:53:59 +0200275
Yoshihiro Shimodac042b852014-10-07 12:43:04 +0900276 struct usb_phy *usb_phy;
Yoshihiro Shimoda420974a2014-10-07 12:43:06 +0900277 struct phy *phy;
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900278};
279
280/*
281 * common
282 */
283u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
284void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
285void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
286
Kuninori Morimoto97664a22011-06-06 14:18:38 +0900287#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
288#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
289
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900290/*
291 * sysconfig
292 */
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900293void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
294void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
kuninori.morimoto.gx@renesas.com4cd2f592012-10-15 23:24:19 -0700295void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
Kuninori Morimotodfbb7f42011-11-24 17:28:35 -0800296void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900297
298/*
Kuninori Morimotoef8bedb2011-10-10 22:02:33 -0700299 * usb request
300 */
301void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
302void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
303
304/*
Kuninori Morimoto258485d2011-10-10 22:01:40 -0700305 * bus
306 */
307void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
308void usbhs_bus_send_reset(struct usbhs_priv *priv);
Kuninori Morimoto75587f52011-10-10 22:01:51 -0700309int usbhs_bus_get_speed(struct usbhs_priv *priv);
Kuninori Morimoto258485d2011-10-10 22:01:40 -0700310int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
311
312/*
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900313 * frame
314 */
315int usbhs_frame_get_num(struct usbhs_priv *priv);
316
317/*
Kuninori Morimotoeb051912011-10-10 22:06:46 -0700318 * device config
319 */
Kuninori Morimoto3dd49262011-10-31 00:47:13 -0700320int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
Kuninori Morimotoeb051912011-10-10 22:06:46 -0700321 u16 hubport, u16 speed);
322
323/*
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900324 * data
325 */
Kuninori Morimoto206dcc22011-04-28 16:40:54 +0900326struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
Kuninori Morimoto48298202011-10-12 21:02:22 -0700327#define usbhs_get_dparam(priv, param) (priv->dparam.param)
Kuninori Morimotof1407d52011-04-04 13:44:59 +0900328#define usbhs_priv_to_pdev(priv) (priv->pdev)
329#define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
330#define usbhs_priv_to_lock(priv) (&priv->lock)
331
332#endif /* RENESAS_USB_DRIVER_H */