Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Atmel AT91 AIC5 (Advanced Interrupt Controller) driver |
| 3 | * |
| 4 | * Copyright (C) 2004 SAN People |
| 5 | * Copyright (C) 2004 ATMEL |
| 6 | * Copyright (C) Rick Bronson |
| 7 | * Copyright (C) 2014 Free Electrons |
| 8 | * |
| 9 | * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> |
| 10 | * |
| 11 | * This file is licensed under the terms of the GNU General Public |
| 12 | * License version 2. This program is licensed "as is" without any |
| 13 | * warranty of any kind, whether express or implied. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/mm.h> |
| 19 | #include <linux/bitmap.h> |
| 20 | #include <linux/types.h> |
| 21 | #include <linux/irq.h> |
Joel Porquet | 41a83e0 | 2015-07-07 17:11:46 -0400 | [diff] [blame] | 22 | #include <linux/irqchip.h> |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 23 | #include <linux/of.h> |
| 24 | #include <linux/of_address.h> |
| 25 | #include <linux/of_irq.h> |
| 26 | #include <linux/irqdomain.h> |
| 27 | #include <linux/err.h> |
| 28 | #include <linux/slab.h> |
| 29 | #include <linux/io.h> |
| 30 | |
| 31 | #include <asm/exception.h> |
| 32 | #include <asm/mach/irq.h> |
| 33 | |
| 34 | #include "irq-atmel-aic-common.h" |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 35 | |
| 36 | /* Number of irq lines managed by AIC */ |
| 37 | #define NR_AIC5_IRQS 128 |
| 38 | |
| 39 | #define AT91_AIC5_SSR 0x0 |
| 40 | #define AT91_AIC5_INTSEL_MSK (0x7f << 0) |
| 41 | |
| 42 | #define AT91_AIC5_SMR 0x4 |
| 43 | |
| 44 | #define AT91_AIC5_SVR 0x8 |
| 45 | #define AT91_AIC5_IVR 0x10 |
| 46 | #define AT91_AIC5_FVR 0x14 |
| 47 | #define AT91_AIC5_ISR 0x18 |
| 48 | |
| 49 | #define AT91_AIC5_IPR0 0x20 |
| 50 | #define AT91_AIC5_IPR1 0x24 |
| 51 | #define AT91_AIC5_IPR2 0x28 |
| 52 | #define AT91_AIC5_IPR3 0x2c |
| 53 | #define AT91_AIC5_IMR 0x30 |
| 54 | #define AT91_AIC5_CISR 0x34 |
| 55 | |
| 56 | #define AT91_AIC5_IECR 0x40 |
| 57 | #define AT91_AIC5_IDCR 0x44 |
| 58 | #define AT91_AIC5_ICCR 0x48 |
| 59 | #define AT91_AIC5_ISCR 0x4c |
| 60 | #define AT91_AIC5_EOICR 0x38 |
| 61 | #define AT91_AIC5_SPU 0x3c |
| 62 | #define AT91_AIC5_DCR 0x6c |
| 63 | |
| 64 | #define AT91_AIC5_FFER 0x50 |
| 65 | #define AT91_AIC5_FFDR 0x54 |
| 66 | #define AT91_AIC5_FFSR 0x58 |
| 67 | |
| 68 | static struct irq_domain *aic5_domain; |
| 69 | |
| 70 | static asmlinkage void __exception_irq_entry |
| 71 | aic5_handle(struct pt_regs *regs) |
| 72 | { |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 73 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 74 | u32 irqnr; |
| 75 | u32 irqstat; |
| 76 | |
Ludovic Desroches | 414a431 | 2015-09-21 15:46:05 +0200 | [diff] [blame] | 77 | irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR); |
| 78 | irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 79 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 80 | if (!irqstat) |
Ludovic Desroches | 414a431 | 2015-09-21 15:46:05 +0200 | [diff] [blame] | 81 | irq_reg_writel(bgc, 0, AT91_AIC5_EOICR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 82 | else |
Marc Zyngier | 31b7b6a | 2014-08-26 11:03:35 +0100 | [diff] [blame] | 83 | handle_domain_irq(aic5_domain, irqnr, regs); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | static void aic5_mask(struct irq_data *d) |
| 87 | { |
| 88 | struct irq_domain *domain = d->domain; |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 89 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); |
Ludovic Desroches | d32dc9a | 2015-09-21 15:46:04 +0200 | [diff] [blame] | 90 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 91 | |
Ludovic Desroches | d32dc9a | 2015-09-21 15:46:04 +0200 | [diff] [blame] | 92 | /* |
| 93 | * Disable interrupt on AIC5. We always take the lock of the |
| 94 | * first irq chip as all chips share the same registers. |
| 95 | */ |
| 96 | irq_gc_lock(bgc); |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 97 | irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); |
| 98 | irq_reg_writel(gc, 1, AT91_AIC5_IDCR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 99 | gc->mask_cache &= ~d->mask; |
Ludovic Desroches | d32dc9a | 2015-09-21 15:46:04 +0200 | [diff] [blame] | 100 | irq_gc_unlock(bgc); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | static void aic5_unmask(struct irq_data *d) |
| 104 | { |
| 105 | struct irq_domain *domain = d->domain; |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 106 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); |
Ludovic Desroches | d32dc9a | 2015-09-21 15:46:04 +0200 | [diff] [blame] | 107 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 108 | |
Ludovic Desroches | d32dc9a | 2015-09-21 15:46:04 +0200 | [diff] [blame] | 109 | /* |
| 110 | * Enable interrupt on AIC5. We always take the lock of the |
| 111 | * first irq chip as all chips share the same registers. |
| 112 | */ |
| 113 | irq_gc_lock(bgc); |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 114 | irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); |
| 115 | irq_reg_writel(gc, 1, AT91_AIC5_IECR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 116 | gc->mask_cache |= d->mask; |
Ludovic Desroches | d32dc9a | 2015-09-21 15:46:04 +0200 | [diff] [blame] | 117 | irq_gc_unlock(bgc); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | static int aic5_retrigger(struct irq_data *d) |
| 121 | { |
| 122 | struct irq_domain *domain = d->domain; |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 123 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 124 | |
| 125 | /* Enable interrupt on AIC5 */ |
Ludovic Desroches | 414a431 | 2015-09-21 15:46:05 +0200 | [diff] [blame] | 126 | irq_gc_lock(bgc); |
| 127 | irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR); |
| 128 | irq_reg_writel(bgc, 1, AT91_AIC5_ISCR); |
| 129 | irq_gc_unlock(bgc); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 130 | |
| 131 | return 0; |
| 132 | } |
| 133 | |
| 134 | static int aic5_set_type(struct irq_data *d, unsigned type) |
| 135 | { |
| 136 | struct irq_domain *domain = d->domain; |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 137 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 138 | unsigned int smr; |
| 139 | int ret; |
| 140 | |
Ludovic Desroches | 414a431 | 2015-09-21 15:46:05 +0200 | [diff] [blame] | 141 | irq_gc_lock(bgc); |
| 142 | irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR); |
| 143 | smr = irq_reg_readl(bgc, AT91_AIC5_SMR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 144 | ret = aic_common_set_type(d, type, &smr); |
| 145 | if (!ret) |
Ludovic Desroches | 414a431 | 2015-09-21 15:46:05 +0200 | [diff] [blame] | 146 | irq_reg_writel(bgc, smr, AT91_AIC5_SMR); |
| 147 | irq_gc_unlock(bgc); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 148 | |
| 149 | return ret; |
| 150 | } |
| 151 | |
| 152 | #ifdef CONFIG_PM |
Alexandre Belloni | a50ac56 | 2017-04-10 16:50:11 +0200 | [diff] [blame] | 153 | static u32 *smr_cache; |
| 154 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 155 | static void aic5_suspend(struct irq_data *d) |
| 156 | { |
| 157 | struct irq_domain *domain = d->domain; |
| 158 | struct irq_domain_chip_generic *dgc = domain->gc; |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 159 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 160 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 161 | int i; |
| 162 | u32 mask; |
| 163 | |
Alexandre Belloni | a50ac56 | 2017-04-10 16:50:11 +0200 | [diff] [blame] | 164 | if (smr_cache) |
| 165 | for (i = 0; i < domain->revmap_size; i++) { |
| 166 | irq_reg_writel(bgc, i, AT91_AIC5_SSR); |
| 167 | smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR); |
| 168 | } |
| 169 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 170 | irq_gc_lock(bgc); |
| 171 | for (i = 0; i < dgc->irqs_per_chip; i++) { |
| 172 | mask = 1 << i; |
| 173 | if ((mask & gc->mask_cache) == (mask & gc->wake_active)) |
| 174 | continue; |
| 175 | |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 176 | irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 177 | if (mask & gc->wake_active) |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 178 | irq_reg_writel(bgc, 1, AT91_AIC5_IECR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 179 | else |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 180 | irq_reg_writel(bgc, 1, AT91_AIC5_IDCR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 181 | } |
| 182 | irq_gc_unlock(bgc); |
| 183 | } |
| 184 | |
| 185 | static void aic5_resume(struct irq_data *d) |
| 186 | { |
| 187 | struct irq_domain *domain = d->domain; |
| 188 | struct irq_domain_chip_generic *dgc = domain->gc; |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 189 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 190 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 191 | int i; |
| 192 | u32 mask; |
| 193 | |
| 194 | irq_gc_lock(bgc); |
Alexandre Belloni | a50ac56 | 2017-04-10 16:50:11 +0200 | [diff] [blame] | 195 | |
| 196 | if (smr_cache) { |
| 197 | irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU); |
| 198 | for (i = 0; i < domain->revmap_size; i++) { |
| 199 | irq_reg_writel(bgc, i, AT91_AIC5_SSR); |
| 200 | irq_reg_writel(bgc, i, AT91_AIC5_SVR); |
| 201 | irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR); |
| 202 | } |
| 203 | } |
| 204 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 205 | for (i = 0; i < dgc->irqs_per_chip; i++) { |
| 206 | mask = 1 << i; |
Alexandre Belloni | a50ac56 | 2017-04-10 16:50:11 +0200 | [diff] [blame] | 207 | |
| 208 | if (!smr_cache && |
| 209 | ((mask & gc->mask_cache) == (mask & gc->wake_active))) |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 210 | continue; |
| 211 | |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 212 | irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 213 | if (mask & gc->mask_cache) |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 214 | irq_reg_writel(bgc, 1, AT91_AIC5_IECR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 215 | else |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 216 | irq_reg_writel(bgc, 1, AT91_AIC5_IDCR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 217 | } |
| 218 | irq_gc_unlock(bgc); |
| 219 | } |
| 220 | |
| 221 | static void aic5_pm_shutdown(struct irq_data *d) |
| 222 | { |
| 223 | struct irq_domain *domain = d->domain; |
| 224 | struct irq_domain_chip_generic *dgc = domain->gc; |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 225 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 226 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 227 | int i; |
| 228 | |
| 229 | irq_gc_lock(bgc); |
| 230 | for (i = 0; i < dgc->irqs_per_chip; i++) { |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 231 | irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR); |
| 232 | irq_reg_writel(bgc, 1, AT91_AIC5_IDCR); |
| 233 | irq_reg_writel(bgc, 1, AT91_AIC5_ICCR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 234 | } |
| 235 | irq_gc_unlock(bgc); |
| 236 | } |
| 237 | #else |
| 238 | #define aic5_suspend NULL |
| 239 | #define aic5_resume NULL |
| 240 | #define aic5_pm_shutdown NULL |
| 241 | #endif /* CONFIG_PM */ |
| 242 | |
| 243 | static void __init aic5_hw_init(struct irq_domain *domain) |
| 244 | { |
| 245 | struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0); |
| 246 | int i; |
| 247 | |
| 248 | /* |
| 249 | * Perform 8 End Of Interrupt Command to make sure AIC |
| 250 | * will not Lock out nIRQ |
| 251 | */ |
| 252 | for (i = 0; i < 8; i++) |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 253 | irq_reg_writel(gc, 0, AT91_AIC5_EOICR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 254 | |
| 255 | /* |
| 256 | * Spurious Interrupt ID in Spurious Vector Register. |
| 257 | * When there is no current interrupt, the IRQ Vector Register |
| 258 | * reads the value stored in AIC_SPU |
| 259 | */ |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 260 | irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 261 | |
| 262 | /* No debugging in AIC: Debug (Protect) Control Register */ |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 263 | irq_reg_writel(gc, 0, AT91_AIC5_DCR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 264 | |
| 265 | /* Disable and clear all interrupts initially */ |
| 266 | for (i = 0; i < domain->revmap_size; i++) { |
Kevin Cernekee | 332fd7c | 2014-11-06 22:44:17 -0800 | [diff] [blame] | 267 | irq_reg_writel(gc, i, AT91_AIC5_SSR); |
| 268 | irq_reg_writel(gc, i, AT91_AIC5_SVR); |
| 269 | irq_reg_writel(gc, 1, AT91_AIC5_IDCR); |
| 270 | irq_reg_writel(gc, 1, AT91_AIC5_ICCR); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 271 | } |
| 272 | } |
| 273 | |
| 274 | static int aic5_irq_domain_xlate(struct irq_domain *d, |
| 275 | struct device_node *ctrlr, |
| 276 | const u32 *intspec, unsigned int intsize, |
| 277 | irq_hw_number_t *out_hwirq, |
| 278 | unsigned int *out_type) |
| 279 | { |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 280 | struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0); |
Boris Brezillon | 5eb0d6e | 2016-09-13 15:58:29 +0200 | [diff] [blame] | 281 | unsigned long flags; |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 282 | unsigned smr; |
| 283 | int ret; |
| 284 | |
Ludovic Desroches | b55a3bb | 2015-09-21 15:46:06 +0200 | [diff] [blame] | 285 | if (!bgc) |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 286 | return -EINVAL; |
| 287 | |
| 288 | ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, |
| 289 | out_hwirq, out_type); |
| 290 | if (ret) |
| 291 | return ret; |
| 292 | |
Boris Brezillon | 5eb0d6e | 2016-09-13 15:58:29 +0200 | [diff] [blame] | 293 | irq_gc_lock_irqsave(bgc, flags); |
Ludovic Desroches | 414a431 | 2015-09-21 15:46:05 +0200 | [diff] [blame] | 294 | irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR); |
| 295 | smr = irq_reg_readl(bgc, AT91_AIC5_SMR); |
Milo Kim | 5fd26a0 | 2016-01-13 16:19:51 +0900 | [diff] [blame] | 296 | aic_common_set_priority(intspec[2], &smr); |
Milo Kim | 4b5ce20 | 2016-01-13 16:19:52 +0900 | [diff] [blame] | 297 | irq_reg_writel(bgc, smr, AT91_AIC5_SMR); |
Boris Brezillon | 5eb0d6e | 2016-09-13 15:58:29 +0200 | [diff] [blame] | 298 | irq_gc_unlock_irqrestore(bgc, flags); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 299 | |
| 300 | return ret; |
| 301 | } |
| 302 | |
| 303 | static const struct irq_domain_ops aic5_irq_ops = { |
| 304 | .map = irq_map_generic_chip, |
| 305 | .xlate = aic5_irq_domain_xlate, |
| 306 | }; |
| 307 | |
Boris BREZILLON | 6704d12 | 2014-07-10 20:25:41 +0200 | [diff] [blame] | 308 | static void __init sama5d3_aic_irq_fixup(struct device_node *root) |
| 309 | { |
| 310 | aic_common_rtc_irq_fixup(root); |
| 311 | } |
| 312 | |
Nicolas Pitre | c376023 | 2015-07-24 15:24:45 -0400 | [diff] [blame] | 313 | static const struct of_device_id aic5_irq_fixups[] __initconst = { |
Boris BREZILLON | 6704d12 | 2014-07-10 20:25:41 +0200 | [diff] [blame] | 314 | { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup }, |
Alexandre Belloni | 20afdeb | 2014-09-12 17:43:00 +0200 | [diff] [blame] | 315 | { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup }, |
Boris BREZILLON | 6704d12 | 2014-07-10 20:25:41 +0200 | [diff] [blame] | 316 | { /* sentinel */ }, |
| 317 | }; |
| 318 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 319 | static int __init aic5_of_init(struct device_node *node, |
| 320 | struct device_node *parent, |
| 321 | int nirqs) |
| 322 | { |
| 323 | struct irq_chip_generic *gc; |
| 324 | struct irq_domain *domain; |
| 325 | int nchips; |
| 326 | int i; |
| 327 | |
| 328 | if (nirqs > NR_AIC5_IRQS) |
| 329 | return -EINVAL; |
| 330 | |
| 331 | if (aic5_domain) |
| 332 | return -EEXIST; |
| 333 | |
| 334 | domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5", |
Milo Kim | dd85c79 | 2016-01-13 16:19:49 +0900 | [diff] [blame] | 335 | nirqs, aic5_irq_fixups); |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 336 | if (IS_ERR(domain)) |
| 337 | return PTR_ERR(domain); |
| 338 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 339 | aic5_domain = domain; |
| 340 | nchips = aic5_domain->revmap_size / 32; |
| 341 | for (i = 0; i < nchips; i++) { |
| 342 | gc = irq_get_domain_generic_chip(domain, i * 32); |
| 343 | |
| 344 | gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR; |
| 345 | gc->chip_types[0].chip.irq_mask = aic5_mask; |
| 346 | gc->chip_types[0].chip.irq_unmask = aic5_unmask; |
| 347 | gc->chip_types[0].chip.irq_retrigger = aic5_retrigger; |
| 348 | gc->chip_types[0].chip.irq_set_type = aic5_set_type; |
| 349 | gc->chip_types[0].chip.irq_suspend = aic5_suspend; |
| 350 | gc->chip_types[0].chip.irq_resume = aic5_resume; |
| 351 | gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown; |
| 352 | } |
| 353 | |
| 354 | aic5_hw_init(domain); |
| 355 | set_handle_irq(aic5_handle); |
| 356 | |
| 357 | return 0; |
| 358 | } |
| 359 | |
Nicolas Ferre | 62a993d | 2015-06-18 15:07:35 +0200 | [diff] [blame] | 360 | #define NR_SAMA5D2_IRQS 77 |
| 361 | |
| 362 | static int __init sama5d2_aic5_of_init(struct device_node *node, |
| 363 | struct device_node *parent) |
| 364 | { |
Alexandre Belloni | a50ac56 | 2017-04-10 16:50:11 +0200 | [diff] [blame] | 365 | #ifdef CONFIG_PM |
| 366 | smr_cache = kcalloc(DIV_ROUND_UP(NR_SAMA5D2_IRQS, 32) * 32, |
| 367 | sizeof(*smr_cache), GFP_KERNEL); |
| 368 | if (!smr_cache) |
| 369 | return -ENOMEM; |
| 370 | #endif |
| 371 | |
Nicolas Ferre | 62a993d | 2015-06-18 15:07:35 +0200 | [diff] [blame] | 372 | return aic5_of_init(node, parent, NR_SAMA5D2_IRQS); |
| 373 | } |
| 374 | IRQCHIP_DECLARE(sama5d2_aic5, "atmel,sama5d2-aic", sama5d2_aic5_of_init); |
| 375 | |
Alexandre Belloni | 0cae165 | 2014-09-11 16:41:51 +0200 | [diff] [blame] | 376 | #define NR_SAMA5D3_IRQS 48 |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 377 | |
| 378 | static int __init sama5d3_aic5_of_init(struct device_node *node, |
| 379 | struct device_node *parent) |
| 380 | { |
| 381 | return aic5_of_init(node, parent, NR_SAMA5D3_IRQS); |
| 382 | } |
| 383 | IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init); |
Alexandre Belloni | 20afdeb | 2014-09-12 17:43:00 +0200 | [diff] [blame] | 384 | |
| 385 | #define NR_SAMA5D4_IRQS 68 |
| 386 | |
| 387 | static int __init sama5d4_aic5_of_init(struct device_node *node, |
| 388 | struct device_node *parent) |
| 389 | { |
| 390 | return aic5_of_init(node, parent, NR_SAMA5D4_IRQS); |
| 391 | } |
| 392 | IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init); |