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ZhengShunQian03a69562015-09-30 13:56:44 +01001/*
2 * Rockchip eFuse Driver
3 *
4 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
5 * Author: Caesar Wang <wxt@rock-chips.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
Caesar Wangc37ff3f2015-12-14 09:43:39 +000017#include <linux/clk.h>
18#include <linux/delay.h>
ZhengShunQian03a69562015-09-30 13:56:44 +010019#include <linux/device.h>
20#include <linux/io.h>
21#include <linux/module.h>
Caesar Wangc37ff3f2015-12-14 09:43:39 +000022#include <linux/nvmem-provider.h>
23#include <linux/slab.h>
ZhengShunQian03a69562015-09-30 13:56:44 +010024#include <linux/of.h>
Finley Xiao02baff32016-09-02 10:14:27 +010025#include <linux/of_platform.h>
Caesar Wangc37ff3f2015-12-14 09:43:39 +000026#include <linux/platform_device.h>
ZhengShunQian03a69562015-09-30 13:56:44 +010027
Finley Xiao02baff32016-09-02 10:14:27 +010028#define RK3288_A_SHIFT 6
29#define RK3288_A_MASK 0x3ff
30#define RK3288_PGENB BIT(3)
31#define RK3288_LOAD BIT(2)
32#define RK3288_STROBE BIT(1)
33#define RK3288_CSB BIT(0)
ZhengShunQian03a69562015-09-30 13:56:44 +010034
Finley Xiao02baff32016-09-02 10:14:27 +010035#define RK3399_A_SHIFT 16
36#define RK3399_A_MASK 0x3ff
37#define RK3399_NBYTES 4
38#define RK3399_STROBSFTSEL BIT(9)
39#define RK3399_RSB BIT(7)
40#define RK3399_PD BIT(5)
41#define RK3399_PGENB BIT(3)
42#define RK3399_LOAD BIT(2)
43#define RK3399_STROBE BIT(1)
44#define RK3399_CSB BIT(0)
45
46#define REG_EFUSE_CTRL 0x0000
47#define REG_EFUSE_DOUT 0x0004
ZhengShunQian03a69562015-09-30 13:56:44 +010048
Caesar Wangc37ff3f2015-12-14 09:43:39 +000049struct rockchip_efuse_chip {
ZhengShunQian03a69562015-09-30 13:56:44 +010050 struct device *dev;
51 void __iomem *base;
Caesar Wangc37ff3f2015-12-14 09:43:39 +000052 struct clk *clk;
ZhengShunQian03a69562015-09-30 13:56:44 +010053};
54
Finley Xiao02baff32016-09-02 10:14:27 +010055static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
56 void *val, size_t bytes)
ZhengShunQian03a69562015-09-30 13:56:44 +010057{
Caesar Wangc37ff3f2015-12-14 09:43:39 +000058 struct rockchip_efuse_chip *efuse = context;
ZhengShunQian03a69562015-09-30 13:56:44 +010059 u8 *buf = val;
60 int ret;
61
Caesar Wangc37ff3f2015-12-14 09:43:39 +000062 ret = clk_prepare_enable(efuse->clk);
ZhengShunQian03a69562015-09-30 13:56:44 +010063 if (ret < 0) {
Caesar Wangc37ff3f2015-12-14 09:43:39 +000064 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
ZhengShunQian03a69562015-09-30 13:56:44 +010065 return ret;
66 }
67
Finley Xiao02baff32016-09-02 10:14:27 +010068 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
ZhengShunQian03a69562015-09-30 13:56:44 +010069 udelay(1);
Srinivas Kandagatlacc907552016-04-24 20:28:11 +010070 while (bytes--) {
Caesar Wangc37ff3f2015-12-14 09:43:39 +000071 writel(readl(efuse->base + REG_EFUSE_CTRL) &
Finley Xiao02baff32016-09-02 10:14:27 +010072 (~(RK3288_A_MASK << RK3288_A_SHIFT)),
Caesar Wangc37ff3f2015-12-14 09:43:39 +000073 efuse->base + REG_EFUSE_CTRL);
74 writel(readl(efuse->base + REG_EFUSE_CTRL) |
Finley Xiao02baff32016-09-02 10:14:27 +010075 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
Caesar Wangc37ff3f2015-12-14 09:43:39 +000076 efuse->base + REG_EFUSE_CTRL);
ZhengShunQian03a69562015-09-30 13:56:44 +010077 udelay(1);
Caesar Wangc37ff3f2015-12-14 09:43:39 +000078 writel(readl(efuse->base + REG_EFUSE_CTRL) |
Finley Xiao02baff32016-09-02 10:14:27 +010079 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
ZhengShunQian03a69562015-09-30 13:56:44 +010080 udelay(1);
Caesar Wangc37ff3f2015-12-14 09:43:39 +000081 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
82 writel(readl(efuse->base + REG_EFUSE_CTRL) &
Finley Xiao02baff32016-09-02 10:14:27 +010083 (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
ZhengShunQian03a69562015-09-30 13:56:44 +010084 udelay(1);
ZhengShunQian03a69562015-09-30 13:56:44 +010085 }
86
87 /* Switch to standby mode */
Finley Xiao02baff32016-09-02 10:14:27 +010088 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
89
90 clk_disable_unprepare(efuse->clk);
91
92 return 0;
93}
94
95static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
96 void *val, size_t bytes)
97{
98 struct rockchip_efuse_chip *efuse = context;
99 unsigned int addr_start, addr_end, addr_offset, addr_len;
100 u32 out_value;
101 u8 *buf;
102 int ret, i = 0;
103
104 ret = clk_prepare_enable(efuse->clk);
105 if (ret < 0) {
106 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
107 return ret;
108 }
109
110 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
111 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
112 addr_offset = offset % RK3399_NBYTES;
113 addr_len = addr_end - addr_start;
114
115 buf = kzalloc(sizeof(*buf) * addr_len * RK3399_NBYTES, GFP_KERNEL);
116 if (!buf) {
117 clk_disable_unprepare(efuse->clk);
118 return -ENOMEM;
119 }
120
121 writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
122 efuse->base + REG_EFUSE_CTRL);
123 udelay(1);
124 while (addr_len--) {
125 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
126 ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
127 efuse->base + REG_EFUSE_CTRL);
128 udelay(1);
129 out_value = readl(efuse->base + REG_EFUSE_DOUT);
130 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
131 efuse->base + REG_EFUSE_CTRL);
132 udelay(1);
133
134 memcpy(&buf[i], &out_value, RK3399_NBYTES);
135 i += RK3399_NBYTES;
136 }
137
138 /* Switch to standby mode */
139 writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
140
141 memcpy(val, buf + addr_offset, bytes);
142
143 kfree(buf);
ZhengShunQian03a69562015-09-30 13:56:44 +0100144
Caesar Wangc37ff3f2015-12-14 09:43:39 +0000145 clk_disable_unprepare(efuse->clk);
ZhengShunQian03a69562015-09-30 13:56:44 +0100146
147 return 0;
148}
149
ZhengShunQian03a69562015-09-30 13:56:44 +0100150static struct nvmem_config econfig = {
151 .name = "rockchip-efuse",
Srinivas Kandagatlacc907552016-04-24 20:28:11 +0100152 .stride = 1,
153 .word_size = 1,
ZhengShunQian03a69562015-09-30 13:56:44 +0100154 .read_only = true,
155};
156
157static const struct of_device_id rockchip_efuse_match[] = {
Finley Xiao02baff32016-09-02 10:14:27 +0100158 /* deprecated but kept around for dts binding compatibility */
159 {
160 .compatible = "rockchip,rockchip-efuse",
161 .data = (void *)&rockchip_rk3288_efuse_read,
162 },
163 {
164 .compatible = "rockchip,rk3066a-efuse",
165 .data = (void *)&rockchip_rk3288_efuse_read,
166 },
167 {
168 .compatible = "rockchip,rk3188-efuse",
169 .data = (void *)&rockchip_rk3288_efuse_read,
170 },
171 {
Frank Wangd6e4bd12017-07-14 16:38:43 +0800172 .compatible = "rockchip,rk3228-efuse",
Finley Xiao820de1f2017-06-09 10:59:10 +0100173 .data = (void *)&rockchip_rk3288_efuse_read,
174 },
175 {
Finley Xiao02baff32016-09-02 10:14:27 +0100176 .compatible = "rockchip,rk3288-efuse",
177 .data = (void *)&rockchip_rk3288_efuse_read,
178 },
179 {
Romain Perier7a15cf22017-10-09 15:26:38 +0200180 .compatible = "rockchip,rk3368-efuse",
181 .data = (void *)&rockchip_rk3288_efuse_read,
182 },
183 {
Finley Xiao02baff32016-09-02 10:14:27 +0100184 .compatible = "rockchip,rk3399-efuse",
185 .data = (void *)&rockchip_rk3399_efuse_read,
186 },
ZhengShunQian03a69562015-09-30 13:56:44 +0100187 { /* sentinel */},
188};
189MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
190
kbuild test robot7e532f72015-09-30 21:46:06 +0800191static int rockchip_efuse_probe(struct platform_device *pdev)
ZhengShunQian03a69562015-09-30 13:56:44 +0100192{
ZhengShunQian03a69562015-09-30 13:56:44 +0100193 struct resource *res;
194 struct nvmem_device *nvmem;
Caesar Wangc37ff3f2015-12-14 09:43:39 +0000195 struct rockchip_efuse_chip *efuse;
Finley Xiao02baff32016-09-02 10:14:27 +0100196 const struct of_device_id *match;
197 struct device *dev = &pdev->dev;
198
199 match = of_match_device(dev->driver->of_match_table, dev);
200 if (!match || !match->data) {
201 dev_err(dev, "failed to get match data\n");
202 return -EINVAL;
203 }
Caesar Wangc37ff3f2015-12-14 09:43:39 +0000204
205 efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip),
206 GFP_KERNEL);
207 if (!efuse)
208 return -ENOMEM;
ZhengShunQian03a69562015-09-30 13:56:44 +0100209
210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Caesar Wangc37ff3f2015-12-14 09:43:39 +0000211 efuse->base = devm_ioremap_resource(&pdev->dev, res);
212 if (IS_ERR(efuse->base))
213 return PTR_ERR(efuse->base);
ZhengShunQian03a69562015-09-30 13:56:44 +0100214
Caesar Wangc37ff3f2015-12-14 09:43:39 +0000215 efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse");
216 if (IS_ERR(efuse->clk))
217 return PTR_ERR(efuse->clk);
ZhengShunQian03a69562015-09-30 13:56:44 +0100218
Caesar Wangc37ff3f2015-12-14 09:43:39 +0000219 efuse->dev = &pdev->dev;
Srinivas Kandagatlacc907552016-04-24 20:28:11 +0100220 econfig.size = resource_size(res);
Finley Xiao02baff32016-09-02 10:14:27 +0100221 econfig.reg_read = match->data;
Srinivas Kandagatlacc907552016-04-24 20:28:11 +0100222 econfig.priv = efuse;
Caesar Wangc37ff3f2015-12-14 09:43:39 +0000223 econfig.dev = efuse->dev;
ZhengShunQian03a69562015-09-30 13:56:44 +0100224 nvmem = nvmem_register(&econfig);
225 if (IS_ERR(nvmem))
226 return PTR_ERR(nvmem);
227
228 platform_set_drvdata(pdev, nvmem);
229
230 return 0;
231}
232
kbuild test robot7e532f72015-09-30 21:46:06 +0800233static int rockchip_efuse_remove(struct platform_device *pdev)
ZhengShunQian03a69562015-09-30 13:56:44 +0100234{
235 struct nvmem_device *nvmem = platform_get_drvdata(pdev);
236
237 return nvmem_unregister(nvmem);
238}
239
240static struct platform_driver rockchip_efuse_driver = {
241 .probe = rockchip_efuse_probe,
242 .remove = rockchip_efuse_remove,
243 .driver = {
244 .name = "rockchip-efuse",
245 .of_match_table = rockchip_efuse_match,
246 },
247};
248
249module_platform_driver(rockchip_efuse_driver);
250MODULE_DESCRIPTION("rockchip_efuse driver");
251MODULE_LICENSE("GPL v2");