Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * NAND Flash Controller Device Driver |
| 3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 17 | * |
| 18 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/delay.h> |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 21 | #include <linux/dma-mapping.h> |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 22 | #include <linux/wait.h> |
| 23 | #include <linux/mutex.h> |
David Miller | b8664b3 | 2010-08-04 22:57:51 -0700 | [diff] [blame] | 24 | #include <linux/slab.h> |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 25 | #include <linux/mtd/mtd.h> |
| 26 | #include <linux/module.h> |
| 27 | |
| 28 | #include "denali.h" |
| 29 | |
| 30 | MODULE_LICENSE("GPL"); |
| 31 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 32 | /* |
| 33 | * We define a module parameter that allows the user to override |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 34 | * the hardware and decide what timing mode should be used. |
| 35 | */ |
| 36 | #define NAND_DEFAULT_TIMINGS -1 |
| 37 | |
| 38 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; |
| 39 | module_param(onfi_timing_mode, int, S_IRUGO); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 40 | MODULE_PARM_DESC(onfi_timing_mode, |
| 41 | "Overrides default ONFI setting. -1 indicates use default timings"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 42 | |
| 43 | #define DENALI_NAND_NAME "denali-nand" |
| 44 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 45 | /* |
| 46 | * We define a macro here that combines all interrupts this driver uses into |
| 47 | * a single constant value, for convenience. |
| 48 | */ |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 49 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
| 50 | INTR_STATUS__ECC_TRANSACTION_DONE | \ |
| 51 | INTR_STATUS__ECC_ERR | \ |
| 52 | INTR_STATUS__PROGRAM_FAIL | \ |
| 53 | INTR_STATUS__LOAD_COMP | \ |
| 54 | INTR_STATUS__PROGRAM_COMP | \ |
| 55 | INTR_STATUS__TIME_OUT | \ |
| 56 | INTR_STATUS__ERASE_FAIL | \ |
| 57 | INTR_STATUS__RST_COMP | \ |
| 58 | INTR_STATUS__ERASE_COMP) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 59 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 60 | /* |
| 61 | * indicates whether or not the internal value for the flash bank is |
| 62 | * valid or not |
| 63 | */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 64 | #define CHIP_SELECT_INVALID -1 |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 65 | |
| 66 | #define SUPPORT_8BITECC 1 |
| 67 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 68 | /* |
| 69 | * This macro divides two integers and rounds fractional values up |
| 70 | * to the nearest integer value. |
| 71 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 72 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
| 73 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 74 | /* |
| 75 | * this macro allows us to convert from an MTD structure to our own |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 76 | * device context (denali) structure. |
| 77 | */ |
| 78 | #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd) |
| 79 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 80 | /* |
| 81 | * These constants are defined by the driver to enable common driver |
| 82 | * configuration options. |
| 83 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 84 | #define SPARE_ACCESS 0x41 |
| 85 | #define MAIN_ACCESS 0x42 |
| 86 | #define MAIN_SPARE_ACCESS 0x43 |
Masahiro Yamada | 2902330 | 2014-07-11 11:14:05 +0900 | [diff] [blame] | 87 | #define PIPELINE_ACCESS 0x2000 |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 88 | |
| 89 | #define DENALI_READ 0 |
| 90 | #define DENALI_WRITE 0x100 |
| 91 | |
| 92 | /* types of device accesses. We can issue commands and get status */ |
| 93 | #define COMMAND_CYCLE 0 |
| 94 | #define ADDR_CYCLE 1 |
| 95 | #define STATUS_CYCLE 2 |
| 96 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 97 | /* |
| 98 | * this is a helper macro that allows us to |
| 99 | * format the bank into the proper bits for the controller |
| 100 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 101 | #define BANK(x) ((x) << 24) |
| 102 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 103 | /* forward declarations */ |
| 104 | static void clear_interrupts(struct denali_nand_info *denali); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 105 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
| 106 | uint32_t irq_mask); |
| 107 | static void denali_irq_enable(struct denali_nand_info *denali, |
| 108 | uint32_t int_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 109 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
| 110 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 111 | /* |
| 112 | * Certain operations for the denali NAND controller use an indexed mode to |
| 113 | * read/write data. The operation is performed by writing the address value |
| 114 | * of the command to the device memory followed by the data. This function |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 115 | * abstracts this common operation. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 116 | */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 117 | static void index_addr(struct denali_nand_info *denali, |
| 118 | uint32_t address, uint32_t data) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 119 | { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 120 | iowrite32(address, denali->flash_mem); |
| 121 | iowrite32(data, denali->flash_mem + 0x10); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | /* Perform an indexed read of the device */ |
| 125 | static void index_addr_read_data(struct denali_nand_info *denali, |
| 126 | uint32_t address, uint32_t *pdata) |
| 127 | { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 128 | iowrite32(address, denali->flash_mem); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 129 | *pdata = ioread32(denali->flash_mem + 0x10); |
| 130 | } |
| 131 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 132 | /* |
| 133 | * We need to buffer some data for some of the NAND core routines. |
| 134 | * The operations manage buffering that data. |
| 135 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 136 | static void reset_buf(struct denali_nand_info *denali) |
| 137 | { |
| 138 | denali->buf.head = denali->buf.tail = 0; |
| 139 | } |
| 140 | |
| 141 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) |
| 142 | { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 143 | denali->buf.buf[denali->buf.tail++] = byte; |
| 144 | } |
| 145 | |
| 146 | /* reads the status of the device */ |
| 147 | static void read_status(struct denali_nand_info *denali) |
| 148 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 149 | uint32_t cmd; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 150 | |
| 151 | /* initialize the data buffer to store status */ |
| 152 | reset_buf(denali); |
| 153 | |
Chuanxiao Dong | f0bc0c7 | 2010-08-11 17:14:59 +0800 | [diff] [blame] | 154 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
| 155 | if (cmd) |
| 156 | write_byte_to_buf(denali, NAND_STATUS_WP); |
| 157 | else |
| 158 | write_byte_to_buf(denali, 0); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | /* resets a specific device connected to the core */ |
| 162 | static void reset_bank(struct denali_nand_info *denali) |
| 163 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 164 | uint32_t irq_status; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 165 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 166 | |
| 167 | clear_interrupts(denali); |
| 168 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 169 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 170 | |
| 171 | irq_status = wait_for_irq(denali, irq_mask); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 172 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 173 | if (irq_status & INTR_STATUS__TIME_OUT) |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 174 | dev_err(denali->dev, "reset bank failed.\n"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | /* Reset the flash controller */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 178 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 179 | { |
Masahiro Yamada | 93e3c8a | 2014-09-09 11:01:54 +0900 | [diff] [blame] | 180 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 181 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 182 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 183 | __FILE__, __LINE__, __func__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 184 | |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 185 | for (i = 0; i < denali->max_banks; i++) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 186 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
| 187 | denali->flash_reg + INTR_STATUS(i)); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 188 | |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 189 | for (i = 0; i < denali->max_banks; i++) { |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 190 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 191 | while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 192 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) |
Chuanxiao Dong | 628bfd41 | 2010-08-11 17:53:29 +0800 | [diff] [blame] | 193 | cpu_relax(); |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 194 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
| 195 | INTR_STATUS__TIME_OUT) |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 196 | dev_dbg(denali->dev, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 197 | "NAND Reset operation timed out on bank %d\n", i); |
| 198 | } |
| 199 | |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 200 | for (i = 0; i < denali->max_banks; i++) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 201 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 202 | denali->flash_reg + INTR_STATUS(i)); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 203 | |
| 204 | return PASS; |
| 205 | } |
| 206 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 207 | /* |
| 208 | * this routine calculates the ONFI timing values for a given mode and |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 209 | * programs the clocking register accordingly. The mode is determined by |
| 210 | * the get_onfi_nand_para routine. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 211 | */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 212 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 213 | uint16_t mode) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 214 | { |
| 215 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; |
| 216 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; |
| 217 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; |
| 218 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; |
| 219 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; |
| 220 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; |
| 221 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; |
| 222 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; |
| 223 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; |
| 224 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; |
| 225 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; |
| 226 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; |
| 227 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 228 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
| 229 | uint16_t dv_window = 0; |
| 230 | uint16_t en_lo, en_hi; |
| 231 | uint16_t acc_clks; |
| 232 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; |
| 233 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 234 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 235 | __FILE__, __LINE__, __func__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 236 | |
| 237 | en_lo = CEIL_DIV(Trp[mode], CLK_X); |
| 238 | en_hi = CEIL_DIV(Treh[mode], CLK_X); |
| 239 | #if ONFI_BLOOM_TIME |
| 240 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) |
| 241 | en_hi++; |
| 242 | #endif |
| 243 | |
| 244 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) |
| 245 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); |
| 246 | |
| 247 | if ((en_lo + en_hi) < CLK_MULTI) |
| 248 | en_lo += CLK_MULTI - en_lo - en_hi; |
| 249 | |
| 250 | while (dv_window < 8) { |
| 251 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; |
| 252 | |
| 253 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; |
| 254 | |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 255 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
| 256 | data_invalid_rhoh : data_invalid_rloh; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 257 | |
| 258 | dv_window = data_invalid - Trea[mode]; |
| 259 | |
| 260 | if (dv_window < 8) |
| 261 | en_lo++; |
| 262 | } |
| 263 | |
| 264 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); |
| 265 | |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 266 | while (acc_clks * CLK_X - Trea[mode] < 3) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 267 | acc_clks++; |
| 268 | |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 269 | if (data_invalid - acc_clks * CLK_X < 2) |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 270 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 271 | __FILE__, __LINE__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 272 | |
| 273 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); |
| 274 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); |
| 275 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); |
| 276 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); |
| 277 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 278 | if (cs_cnt == 0) |
| 279 | cs_cnt = 1; |
| 280 | |
| 281 | if (Tcea[mode]) { |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 282 | while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode]) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 283 | cs_cnt++; |
| 284 | } |
| 285 | |
| 286 | #if MODE5_WORKAROUND |
| 287 | if (mode == 5) |
| 288 | acc_clks = 5; |
| 289 | #endif |
| 290 | |
| 291 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 292 | if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && |
| 293 | ioread32(denali->flash_reg + DEVICE_ID) == 0x88) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 294 | acc_clks = 6; |
| 295 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 296 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
| 297 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); |
| 298 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); |
| 299 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); |
| 300 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); |
| 301 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); |
| 302 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); |
| 303 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 304 | } |
| 305 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 306 | /* queries the NAND device to see what ONFI modes it supports. */ |
| 307 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) |
| 308 | { |
| 309 | int i; |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 310 | |
| 311 | /* |
| 312 | * we needn't to do a reset here because driver has already |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 313 | * reset all the banks before |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 314 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 315 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
| 316 | ONFI_TIMING_MODE__VALUE)) |
| 317 | return FAIL; |
| 318 | |
| 319 | for (i = 5; i > 0; i--) { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 320 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
| 321 | (0x01 << i)) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 322 | break; |
| 323 | } |
| 324 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 325 | nand_onfi_timing_set(denali, i); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 326 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 327 | /* |
| 328 | * By now, all the ONFI devices we know support the page cache |
| 329 | * rw feature. So here we enable the pipeline_rw_ahead feature |
| 330 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 331 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
| 332 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ |
| 333 | |
| 334 | return PASS; |
| 335 | } |
| 336 | |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 337 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
| 338 | uint8_t device_id) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 339 | { |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 340 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 341 | /* Set timing register values according to datasheet */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 342 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
| 343 | iowrite32(20, denali->flash_reg + RE_2_WE); |
| 344 | iowrite32(12, denali->flash_reg + WE_2_RE); |
| 345 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); |
| 346 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); |
| 347 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); |
| 348 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 349 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | static void get_toshiba_nand_para(struct denali_nand_info *denali) |
| 353 | { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 354 | uint32_t tmp; |
| 355 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 356 | /* |
| 357 | * Workaround to fix a controller bug which reports a wrong |
| 358 | * spare area size for some kind of Toshiba NAND device |
| 359 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 360 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
| 361 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 362 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 363 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
| 364 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 365 | iowrite32(tmp, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 366 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 367 | #if SUPPORT_15BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 368 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 369 | #elif SUPPORT_8BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 370 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 371 | #endif |
| 372 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 373 | } |
| 374 | |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 375 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
| 376 | uint8_t device_id) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 377 | { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 378 | uint32_t main_size, spare_size; |
| 379 | |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 380 | switch (device_id) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 381 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
| 382 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 383 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
| 384 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); |
| 385 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 386 | main_size = 4096 * |
| 387 | ioread32(denali->flash_reg + DEVICES_CONNECTED); |
| 388 | spare_size = 224 * |
| 389 | ioread32(denali->flash_reg + DEVICES_CONNECTED); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 390 | iowrite32(main_size, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 391 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 392 | iowrite32(spare_size, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 393 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 394 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 395 | #if SUPPORT_15BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 396 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 397 | #elif SUPPORT_8BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 398 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 399 | #endif |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 400 | break; |
| 401 | default: |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 402 | dev_warn(denali->dev, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 403 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n" |
| 404 | "Will use default parameter values instead.\n", |
| 405 | device_id); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 406 | } |
| 407 | } |
| 408 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 409 | /* |
| 410 | * determines how many NAND chips are connected to the controller. Note for |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 411 | * Intel CE4100 devices we don't support more than one device. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 412 | */ |
| 413 | static void find_valid_banks(struct denali_nand_info *denali) |
| 414 | { |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 415 | uint32_t id[denali->max_banks]; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 416 | int i; |
| 417 | |
| 418 | denali->total_used_banks = 1; |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 419 | for (i = 0; i < denali->max_banks; i++) { |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 420 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
| 421 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 422 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 423 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 424 | dev_dbg(denali->dev, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 425 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
| 426 | |
| 427 | if (i == 0) { |
| 428 | if (!(id[i] & 0x0ff)) |
| 429 | break; /* WTF? */ |
| 430 | } else { |
| 431 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) |
| 432 | denali->total_used_banks++; |
| 433 | else |
| 434 | break; |
| 435 | } |
| 436 | } |
| 437 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 438 | if (denali->platform == INTEL_CE4100) { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 439 | /* |
| 440 | * Platform limitations of the CE4100 device limit |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 441 | * users to a single chip solution for NAND. |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 442 | * Multichip support is not enabled. |
| 443 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 444 | if (denali->total_used_banks != 1) { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 445 | dev_err(denali->dev, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 446 | "Sorry, Intel CE4100 only supports a single NAND device.\n"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 447 | BUG(); |
| 448 | } |
| 449 | } |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 450 | dev_dbg(denali->dev, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 451 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
| 452 | } |
| 453 | |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 454 | /* |
| 455 | * Use the configuration feature register to determine the maximum number of |
| 456 | * banks that the hardware supports. |
| 457 | */ |
| 458 | static void detect_max_banks(struct denali_nand_info *denali) |
| 459 | { |
| 460 | uint32_t features = ioread32(denali->flash_reg + FEATURES); |
| 461 | |
| 462 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); |
| 463 | } |
| 464 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 465 | static void detect_partition_feature(struct denali_nand_info *denali) |
| 466 | { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 467 | /* |
| 468 | * For MRST platform, denali->fwblks represent the |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 469 | * number of blocks firmware is taken, |
| 470 | * FW is in protect partition and MTD driver has no |
| 471 | * permission to access it. So let driver know how many |
| 472 | * blocks it can't touch. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 473 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 474 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 475 | if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & |
| 476 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 477 | denali->fwblks = |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 478 | ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) & |
| 479 | MIN_MAX_BANK__MIN_VALUE) * |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 480 | denali->blksperchip) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 481 | + |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 482 | (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & |
| 483 | MIN_BLK_ADDR__VALUE); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 484 | } else { |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 485 | denali->fwblks = SPECTRA_START_BLOCK; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 486 | } |
| 487 | } else { |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 488 | denali->fwblks = SPECTRA_START_BLOCK; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 489 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 490 | } |
| 491 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 492 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 493 | { |
| 494 | uint16_t status = PASS; |
grmoore@altera.com | d68a5c3 | 2014-06-23 14:21:10 -0500 | [diff] [blame] | 495 | uint32_t id_bytes[8], addr; |
Masahiro Yamada | 93e3c8a | 2014-09-09 11:01:54 +0900 | [diff] [blame] | 496 | uint8_t maf_id, device_id; |
| 497 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 498 | |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 499 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 500 | __FILE__, __LINE__, __func__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 501 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 502 | /* |
| 503 | * Use read id method to get device ID and other params. |
| 504 | * For some NAND chips, controller can't report the correct |
| 505 | * device ID by reading from DEVICE_ID register |
| 506 | */ |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 507 | addr = MODE_11 | BANK(denali->flash_bank); |
| 508 | index_addr(denali, addr | 0, 0x90); |
| 509 | index_addr(denali, addr | 1, 0); |
grmoore@altera.com | d68a5c3 | 2014-06-23 14:21:10 -0500 | [diff] [blame] | 510 | for (i = 0; i < 8; i++) |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 511 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
| 512 | maf_id = id_bytes[0]; |
| 513 | device_id = id_bytes[1]; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 514 | |
| 515 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & |
| 516 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ |
| 517 | if (FAIL == get_onfi_nand_para(denali)) |
| 518 | return FAIL; |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 519 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 520 | get_samsung_nand_para(denali, device_id); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 521 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 522 | get_toshiba_nand_para(denali); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 523 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
| 524 | get_hynix_nand_para(denali, device_id); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 525 | } |
| 526 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 527 | dev_info(denali->dev, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 528 | "Dump timing register values:\n" |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 529 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
| 530 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 531 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
| 532 | ioread32(denali->flash_reg + ACC_CLKS), |
| 533 | ioread32(denali->flash_reg + RE_2_WE), |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 534 | ioread32(denali->flash_reg + RE_2_RE), |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 535 | ioread32(denali->flash_reg + WE_2_RE), |
| 536 | ioread32(denali->flash_reg + ADDR_2_DATA), |
| 537 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), |
| 538 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), |
| 539 | ioread32(denali->flash_reg + CS_SETUP_CNT)); |
| 540 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 541 | find_valid_banks(denali); |
| 542 | |
| 543 | detect_partition_feature(denali); |
| 544 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 545 | /* |
| 546 | * If the user specified to override the default timings |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 547 | * with a specific ONFI mode, we apply those changes here. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 548 | */ |
| 549 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 550 | nand_onfi_timing_set(denali, onfi_timing_mode); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 551 | |
| 552 | return status; |
| 553 | } |
| 554 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 555 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 556 | uint16_t INT_ENABLE) |
| 557 | { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 558 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 559 | __FILE__, __LINE__, __func__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 560 | |
| 561 | if (INT_ENABLE) |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 562 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 563 | else |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 564 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 565 | } |
| 566 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 567 | /* |
| 568 | * validation function to verify that the controlling software is making |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 569 | * a valid request |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 570 | */ |
| 571 | static inline bool is_flash_bank_valid(int flash_bank) |
| 572 | { |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 573 | return flash_bank >= 0 && flash_bank < 4; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 574 | } |
| 575 | |
| 576 | static void denali_irq_init(struct denali_nand_info *denali) |
| 577 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 578 | uint32_t int_mask; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 579 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 580 | |
| 581 | /* Disable global interrupts */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 582 | denali_set_intr_modes(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 583 | |
| 584 | int_mask = DENALI_IRQ_ALL; |
| 585 | |
| 586 | /* Clear all status bits */ |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 587 | for (i = 0; i < denali->max_banks; ++i) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 588 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 589 | |
| 590 | denali_irq_enable(denali, int_mask); |
| 591 | } |
| 592 | |
| 593 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) |
| 594 | { |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 595 | denali_set_intr_modes(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 596 | free_irq(irqnum, denali); |
| 597 | } |
| 598 | |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 599 | static void denali_irq_enable(struct denali_nand_info *denali, |
| 600 | uint32_t int_mask) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 601 | { |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 602 | int i; |
| 603 | |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 604 | for (i = 0; i < denali->max_banks; ++i) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 605 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 606 | } |
| 607 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 608 | /* |
| 609 | * This function only returns when an interrupt that this driver cares about |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 610 | * occurs. This is to reduce the overhead of servicing interrupts |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 611 | */ |
| 612 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) |
| 613 | { |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 614 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 615 | } |
| 616 | |
| 617 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 618 | static inline void clear_interrupt(struct denali_nand_info *denali, |
| 619 | uint32_t irq_mask) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 620 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 621 | uint32_t intr_status_reg; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 622 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 623 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 624 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 625 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 626 | } |
| 627 | |
| 628 | static void clear_interrupts(struct denali_nand_info *denali) |
| 629 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 630 | uint32_t status; |
| 631 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 632 | spin_lock_irq(&denali->irq_lock); |
| 633 | |
| 634 | status = read_interrupt_status(denali); |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 635 | clear_interrupt(denali, status); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 636 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 637 | denali->irq_status = 0x0; |
| 638 | spin_unlock_irq(&denali->irq_lock); |
| 639 | } |
| 640 | |
| 641 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) |
| 642 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 643 | uint32_t intr_status_reg; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 644 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 645 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 646 | |
| 647 | return ioread32(denali->flash_reg + intr_status_reg); |
| 648 | } |
| 649 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 650 | /* |
| 651 | * This is the interrupt service routine. It handles all interrupts |
| 652 | * sent to this device. Note that on CE4100, this is a shared interrupt. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 653 | */ |
| 654 | static irqreturn_t denali_isr(int irq, void *dev_id) |
| 655 | { |
| 656 | struct denali_nand_info *denali = dev_id; |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 657 | uint32_t irq_status; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 658 | irqreturn_t result = IRQ_NONE; |
| 659 | |
| 660 | spin_lock(&denali->irq_lock); |
| 661 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 662 | /* check to see if a valid NAND chip has been selected. */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 663 | if (is_flash_bank_valid(denali->flash_bank)) { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 664 | /* |
| 665 | * check to see if controller generated the interrupt, |
| 666 | * since this is a shared interrupt |
| 667 | */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 668 | irq_status = denali_irq_detected(denali); |
| 669 | if (irq_status != 0) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 670 | /* handle interrupt */ |
| 671 | /* first acknowledge it */ |
| 672 | clear_interrupt(denali, irq_status); |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 673 | /* |
| 674 | * store the status in the device context for someone |
| 675 | * to read |
| 676 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 677 | denali->irq_status |= irq_status; |
| 678 | /* notify anyone who cares that it happened */ |
| 679 | complete(&denali->complete); |
| 680 | /* tell the OS that we've handled this */ |
| 681 | result = IRQ_HANDLED; |
| 682 | } |
| 683 | } |
| 684 | spin_unlock(&denali->irq_lock); |
| 685 | return result; |
| 686 | } |
| 687 | #define BANK(x) ((x) << 24) |
| 688 | |
| 689 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) |
| 690 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 691 | unsigned long comp_res; |
| 692 | uint32_t intr_status; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 693 | unsigned long timeout = msecs_to_jiffies(1000); |
| 694 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 695 | do { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 696 | comp_res = |
| 697 | wait_for_completion_timeout(&denali->complete, timeout); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 698 | spin_lock_irq(&denali->irq_lock); |
| 699 | intr_status = denali->irq_status; |
| 700 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 701 | if (intr_status & irq_mask) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 702 | denali->irq_status &= ~irq_mask; |
| 703 | spin_unlock_irq(&denali->irq_lock); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 704 | /* our interrupt was detected */ |
| 705 | break; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 706 | } |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 707 | |
| 708 | /* |
| 709 | * these are not the interrupts you are looking for - |
| 710 | * need to wait again |
| 711 | */ |
| 712 | spin_unlock_irq(&denali->irq_lock); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 713 | } while (comp_res != 0); |
| 714 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 715 | if (comp_res == 0) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 716 | /* timeout */ |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 717 | pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n", |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 718 | intr_status, irq_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 719 | |
| 720 | intr_status = 0; |
| 721 | } |
| 722 | return intr_status; |
| 723 | } |
| 724 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 725 | /* |
| 726 | * This helper function setups the registers for ECC and whether or not |
| 727 | * the spare area will be transferred. |
| 728 | */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 729 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 730 | bool transfer_spare) |
| 731 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 732 | int ecc_en_flag, transfer_spare_flag; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 733 | |
| 734 | /* set ECC, transfer spare bits if needed */ |
| 735 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; |
| 736 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; |
| 737 | |
| 738 | /* Enable spare area/ECC per user's request. */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 739 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 740 | iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 741 | } |
| 742 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 743 | /* |
| 744 | * sends a pipeline command operation to the controller. See the Denali NAND |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 745 | * controller's user guide for more information (section 4.2.3.6). |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 746 | */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 747 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 748 | bool ecc_en, bool transfer_spare, |
| 749 | int access_type, int op) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 750 | { |
| 751 | int status = PASS; |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 752 | uint32_t page_count = 1; |
| 753 | uint32_t addr, cmd, irq_status, irq_mask; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 754 | |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 755 | if (op == DENALI_READ) |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 756 | irq_mask = INTR_STATUS__LOAD_COMP; |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 757 | else if (op == DENALI_WRITE) |
| 758 | irq_mask = 0; |
| 759 | else |
| 760 | BUG(); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 761 | |
| 762 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); |
| 763 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 764 | clear_interrupts(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 765 | |
| 766 | addr = BANK(denali->flash_bank) | denali->page; |
| 767 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 768 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 769 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 770 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 771 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 772 | /* read spare area */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 773 | cmd = MODE_10 | addr; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 774 | index_addr(denali, cmd, access_type); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 775 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 776 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 777 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 778 | } else if (op == DENALI_READ) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 779 | /* setup page read request for access type */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 780 | cmd = MODE_10 | addr; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 781 | index_addr(denali, cmd, access_type); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 782 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 783 | /* |
| 784 | * page 33 of the NAND controller spec indicates we should not |
| 785 | * use the pipeline commands in Spare area only mode. |
| 786 | * So we don't. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 787 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 788 | if (access_type == SPARE_ACCESS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 789 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 790 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 791 | } else { |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 792 | index_addr(denali, cmd, |
Masahiro Yamada | 2902330 | 2014-07-11 11:14:05 +0900 | [diff] [blame] | 793 | PIPELINE_ACCESS | op | page_count); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 794 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 795 | /* |
| 796 | * wait for command to be accepted |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 797 | * can always use status0 bit as the |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 798 | * mask is identical for each bank. |
| 799 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 800 | irq_status = wait_for_irq(denali, irq_mask); |
| 801 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 802 | if (irq_status == 0) { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 803 | dev_err(denali->dev, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 804 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", |
| 805 | cmd, denali->page, addr); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 806 | status = FAIL; |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 807 | } else { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 808 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 809 | iowrite32(cmd, denali->flash_mem); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 810 | } |
| 811 | } |
| 812 | } |
| 813 | return status; |
| 814 | } |
| 815 | |
| 816 | /* helper function that simply writes a buffer to the flash */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 817 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 818 | const uint8_t *buf, int len) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 819 | { |
Masahiro Yamada | 93e3c8a | 2014-09-09 11:01:54 +0900 | [diff] [blame] | 820 | uint32_t *buf32; |
| 821 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 822 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 823 | /* |
| 824 | * verify that the len is a multiple of 4. |
| 825 | * see comment in read_data_from_flash_mem() |
| 826 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 827 | BUG_ON((len % 4) != 0); |
| 828 | |
| 829 | /* write the data to the flash memory */ |
| 830 | buf32 = (uint32_t *)buf; |
| 831 | for (i = 0; i < len / 4; i++) |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 832 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 833 | return i * 4; /* intent is to return the number of bytes read */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 834 | } |
| 835 | |
| 836 | /* helper function that simply reads a buffer from the flash */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 837 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 838 | uint8_t *buf, int len) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 839 | { |
Masahiro Yamada | 93e3c8a | 2014-09-09 11:01:54 +0900 | [diff] [blame] | 840 | uint32_t *buf32; |
| 841 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 842 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 843 | /* |
| 844 | * we assume that len will be a multiple of 4, if not it would be nice |
| 845 | * to know about it ASAP rather than have random failures... |
| 846 | * This assumption is based on the fact that this function is designed |
| 847 | * to be used to read flash pages, which are typically multiples of 4. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 848 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 849 | BUG_ON((len % 4) != 0); |
| 850 | |
| 851 | /* transfer the data from the flash */ |
| 852 | buf32 = (uint32_t *)buf; |
| 853 | for (i = 0; i < len / 4; i++) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 854 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 855 | return i * 4; /* intent is to return the number of bytes read */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 856 | } |
| 857 | |
| 858 | /* writes OOB data to the device */ |
| 859 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
| 860 | { |
| 861 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 862 | uint32_t irq_status; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 863 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
| 864 | INTR_STATUS__PROGRAM_FAIL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 865 | int status = 0; |
| 866 | |
| 867 | denali->page = page; |
| 868 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 869 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 870 | DENALI_WRITE) == PASS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 871 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
| 872 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 873 | /* wait for operation to complete */ |
| 874 | irq_status = wait_for_irq(denali, irq_mask); |
| 875 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 876 | if (irq_status == 0) { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 877 | dev_err(denali->dev, "OOB write failed\n"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 878 | status = -EIO; |
| 879 | } |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 880 | } else { |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 881 | dev_err(denali->dev, "unable to send pipeline command\n"); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 882 | status = -EIO; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 883 | } |
| 884 | return status; |
| 885 | } |
| 886 | |
| 887 | /* reads OOB data from the device */ |
| 888 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
| 889 | { |
| 890 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 891 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
| 892 | uint32_t irq_status, addr, cmd; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 893 | |
| 894 | denali->page = page; |
| 895 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 896 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 897 | DENALI_READ) == PASS) { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 898 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 899 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 900 | /* |
| 901 | * wait for command to be accepted |
| 902 | * can always use status0 bit as the |
| 903 | * mask is identical for each bank. |
| 904 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 905 | irq_status = wait_for_irq(denali, irq_mask); |
| 906 | |
| 907 | if (irq_status == 0) |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 908 | dev_err(denali->dev, "page on OOB timeout %d\n", |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 909 | denali->page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 910 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 911 | /* |
| 912 | * We set the device back to MAIN_ACCESS here as I observed |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 913 | * instability with the controller if you do a block erase |
| 914 | * and the last transaction was a SPARE_ACCESS. Block erase |
| 915 | * is reliable (according to the MTD test infrastructure) |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 916 | * if you are in MAIN_ACCESS. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 917 | */ |
| 918 | addr = BANK(denali->flash_bank) | denali->page; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 919 | cmd = MODE_10 | addr; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 920 | index_addr(denali, cmd, MAIN_ACCESS); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 921 | } |
| 922 | } |
| 923 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 924 | /* |
| 925 | * this function examines buffers to see if they contain data that |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 926 | * indicate that the buffer is part of an erased region of flash. |
| 927 | */ |
Rashika Kheria | 919193c | 2013-12-13 12:46:04 +0530 | [diff] [blame] | 928 | static bool is_erased(uint8_t *buf, int len) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 929 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 930 | int i; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 931 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 932 | for (i = 0; i < len; i++) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 933 | if (buf[i] != 0xFF) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 934 | return false; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 935 | return true; |
| 936 | } |
| 937 | #define ECC_SECTOR_SIZE 512 |
| 938 | |
| 939 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) |
| 940 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) |
| 941 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 942 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
| 943 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 944 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
| 945 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 946 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 947 | uint32_t irq_status, unsigned int *max_bitflips) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 948 | { |
| 949 | bool check_erased_page = false; |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 950 | unsigned int bitflips = 0; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 951 | |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 952 | if (irq_status & INTR_STATUS__ECC_ERR) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 953 | /* read the ECC errors. we'll ignore them for now */ |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 954 | uint32_t err_address, err_correction_info, err_byte, |
| 955 | err_sector, err_device, err_correction_value; |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 956 | denali_set_intr_modes(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 957 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 958 | do { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 959 | err_address = ioread32(denali->flash_reg + |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 960 | ECC_ERROR_ADDRESS); |
| 961 | err_sector = ECC_SECTOR(err_address); |
| 962 | err_byte = ECC_BYTE(err_address); |
| 963 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 964 | err_correction_info = ioread32(denali->flash_reg + |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 965 | ERR_CORRECTION_INFO); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 966 | err_correction_value = |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 967 | ECC_CORRECTION_VALUE(err_correction_info); |
| 968 | err_device = ECC_ERR_DEVICE(err_correction_info); |
| 969 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 970 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 971 | /* |
| 972 | * If err_byte is larger than ECC_SECTOR_SIZE, |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 973 | * means error happened in OOB, so we ignore |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 974 | * it. It's no need for us to correct it |
| 975 | * err_device is represented the NAND error |
| 976 | * bits are happened in if there are more |
| 977 | * than one NAND connected. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 978 | */ |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 979 | if (err_byte < ECC_SECTOR_SIZE) { |
| 980 | int offset; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 981 | |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 982 | offset = (err_sector * |
| 983 | ECC_SECTOR_SIZE + |
| 984 | err_byte) * |
| 985 | denali->devnum + |
| 986 | err_device; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 987 | /* correct the ECC error */ |
| 988 | buf[offset] ^= err_correction_value; |
| 989 | denali->mtd.ecc_stats.corrected++; |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 990 | bitflips++; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 991 | } |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 992 | } else { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 993 | /* |
| 994 | * if the error is not correctable, need to |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 995 | * look at the page to see if it is an erased |
| 996 | * page. if so, then it's not a real ECC error |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 997 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 998 | check_erased_page = true; |
| 999 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1000 | } while (!ECC_LAST_ERR(err_correction_info)); |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1001 | /* |
| 1002 | * Once handle all ecc errors, controller will triger |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 1003 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
| 1004 | * for a while for this interrupt |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1005 | */ |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 1006 | while (!(read_interrupt_status(denali) & |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1007 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
Chuanxiao Dong | 8ae61eb | 2010-08-10 00:07:01 +0800 | [diff] [blame] | 1008 | cpu_relax(); |
| 1009 | clear_interrupts(denali); |
| 1010 | denali_set_intr_modes(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1011 | } |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 1012 | *max_bitflips = bitflips; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1013 | return check_erased_page; |
| 1014 | } |
| 1015 | |
| 1016 | /* programs the controller to either enable/disable DMA transfers */ |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1017 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1018 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1019 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1020 | ioread32(denali->flash_reg + DMA_ENABLE); |
| 1021 | } |
| 1022 | |
| 1023 | /* setups the HW to perform the data DMA */ |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1024 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1025 | { |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1026 | uint32_t mode; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1027 | const int page_count = 1; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 1028 | uint32_t addr = denali->buf.dma_buf; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1029 | |
| 1030 | mode = MODE_10 | BANK(denali->flash_bank); |
| 1031 | |
| 1032 | /* DMA is a four step process */ |
| 1033 | |
| 1034 | /* 1. setup transfer type and # of pages */ |
| 1035 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); |
| 1036 | |
| 1037 | /* 2. set memory high address bits 23:8 */ |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 1038 | index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1039 | |
| 1040 | /* 3. set memory low address bits 23:8 */ |
Graham Moore | 7c272ac | 2015-01-09 09:32:35 -0600 | [diff] [blame] | 1041 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1042 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1043 | /* 4. interrupt when complete, burst len = 64 bytes */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1044 | index_addr(denali, mode | 0x14000, 0x2400); |
| 1045 | } |
| 1046 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1047 | /* |
| 1048 | * writes a page. user specifies type, and this function handles the |
| 1049 | * configuration details. |
| 1050 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1051 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1052 | const uint8_t *buf, bool raw_xfer) |
| 1053 | { |
| 1054 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1055 | dma_addr_t addr = denali->buf.dma_buf; |
| 1056 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1057 | uint32_t irq_status; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1058 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
| 1059 | INTR_STATUS__PROGRAM_FAIL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1060 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1061 | /* |
| 1062 | * if it is a raw xfer, we want to disable ecc and send the spare area. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1063 | * !raw_xfer - enable ecc |
| 1064 | * raw_xfer - transfer spare |
| 1065 | */ |
| 1066 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); |
| 1067 | |
| 1068 | /* copy buffer into DMA buffer */ |
| 1069 | memcpy(denali->buf.buf, buf, mtd->writesize); |
| 1070 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1071 | if (raw_xfer) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1072 | /* transfer the data to the spare area */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1073 | memcpy(denali->buf.buf + mtd->writesize, |
| 1074 | chip->oob_poi, |
| 1075 | mtd->oobsize); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1076 | } |
| 1077 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1078 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1079 | |
| 1080 | clear_interrupts(denali); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1081 | denali_enable_dma(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1082 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1083 | denali_setup_dma(denali, DENALI_WRITE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1084 | |
| 1085 | /* wait for operation to complete */ |
| 1086 | irq_status = wait_for_irq(denali, irq_mask); |
| 1087 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1088 | if (irq_status == 0) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1089 | dev_err(denali->dev, "timeout on write_page (type = %d)\n", |
| 1090 | raw_xfer); |
Brian Norris | c115add | 2014-07-21 19:07:31 -0700 | [diff] [blame] | 1091 | denali->status = NAND_STATUS_FAIL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1092 | } |
| 1093 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1094 | denali_enable_dma(denali, false); |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1095 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1096 | |
| 1097 | return 0; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1098 | } |
| 1099 | |
| 1100 | /* NAND core entry points */ |
| 1101 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1102 | /* |
| 1103 | * this is the callback that the NAND core calls to write a page. Since |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 1104 | * writing a page with ECC or without is similar, all the work is done |
| 1105 | * by write_page above. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1106 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1107 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
Brian Norris | 1fbb938 | 2012-05-02 10:14:55 -0700 | [diff] [blame] | 1108 | const uint8_t *buf, int oob_required) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1109 | { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1110 | /* |
| 1111 | * for regular page writes, we let HW handle all the ECC |
| 1112 | * data written to the device. |
| 1113 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1114 | return write_page(mtd, chip, buf, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1115 | } |
| 1116 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1117 | /* |
| 1118 | * This is the callback that the NAND core calls to write a page without ECC. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1119 | * raw access is similar to ECC page writes, so all the work is done in the |
Chuanxiao Dong | b292c34 | 2010-08-11 17:46:00 +0800 | [diff] [blame] | 1120 | * write_page() function above. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1121 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1122 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
Brian Norris | 1fbb938 | 2012-05-02 10:14:55 -0700 | [diff] [blame] | 1123 | const uint8_t *buf, int oob_required) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1124 | { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1125 | /* |
| 1126 | * for raw page writes, we want to disable ECC and simply write |
| 1127 | * whatever data is in the buffer. |
| 1128 | */ |
Josh Wu | fdbad98d | 2012-06-25 18:07:45 +0800 | [diff] [blame] | 1129 | return write_page(mtd, chip, buf, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1130 | } |
| 1131 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1132 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1133 | int page) |
| 1134 | { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1135 | return write_oob_data(mtd, chip->oob_poi, page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1136 | } |
| 1137 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1138 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
Shmulik Ladkani | 5c2ffb1 | 2012-05-09 13:06:35 +0300 | [diff] [blame] | 1139 | int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1140 | { |
| 1141 | read_oob_data(mtd, chip->oob_poi, page); |
| 1142 | |
Shmulik Ladkani | 5c2ffb1 | 2012-05-09 13:06:35 +0300 | [diff] [blame] | 1143 | return 0; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1144 | } |
| 1145 | |
| 1146 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
Brian Norris | 1fbb938 | 2012-05-02 10:14:55 -0700 | [diff] [blame] | 1147 | uint8_t *buf, int oob_required, int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1148 | { |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 1149 | unsigned int max_bitflips; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1150 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1151 | |
| 1152 | dma_addr_t addr = denali->buf.dma_buf; |
| 1153 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
| 1154 | |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1155 | uint32_t irq_status; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1156 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
| 1157 | INTR_STATUS__ECC_ERR; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1158 | bool check_erased_page = false; |
| 1159 | |
Chuanxiao Dong | 7d8a26f | 2010-08-11 18:19:23 +0800 | [diff] [blame] | 1160 | if (page != denali->page) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1161 | dev_err(denali->dev, |
| 1162 | "IN %s: page %d is not equal to denali->page %d", |
| 1163 | __func__, page, denali->page); |
Chuanxiao Dong | 7d8a26f | 2010-08-11 18:19:23 +0800 | [diff] [blame] | 1164 | BUG(); |
| 1165 | } |
| 1166 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1167 | setup_ecc_for_xfer(denali, true, false); |
| 1168 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1169 | denali_enable_dma(denali, true); |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1170 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1171 | |
| 1172 | clear_interrupts(denali); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1173 | denali_setup_dma(denali, DENALI_READ); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1174 | |
| 1175 | /* wait for operation to complete */ |
| 1176 | irq_status = wait_for_irq(denali, irq_mask); |
| 1177 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1178 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1179 | |
| 1180 | memcpy(buf, denali->buf.buf, mtd->writesize); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1181 | |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 1182 | check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1183 | denali_enable_dma(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1184 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1185 | if (check_erased_page) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1186 | read_oob_data(&denali->mtd, chip->oob_poi, denali->page); |
| 1187 | |
| 1188 | /* check ECC failures that may have occurred on erased pages */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1189 | if (check_erased_page) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1190 | if (!is_erased(buf, denali->mtd.writesize)) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1191 | denali->mtd.ecc_stats.failed++; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1192 | if (!is_erased(buf, denali->mtd.oobsize)) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1193 | denali->mtd.ecc_stats.failed++; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1194 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1195 | } |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 1196 | return max_bitflips; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1197 | } |
| 1198 | |
| 1199 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
Brian Norris | 1fbb938 | 2012-05-02 10:14:55 -0700 | [diff] [blame] | 1200 | uint8_t *buf, int oob_required, int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1201 | { |
| 1202 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1203 | dma_addr_t addr = denali->buf.dma_buf; |
| 1204 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1205 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1206 | |
Chuanxiao Dong | 7d8a26f | 2010-08-11 18:19:23 +0800 | [diff] [blame] | 1207 | if (page != denali->page) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1208 | dev_err(denali->dev, |
| 1209 | "IN %s: page %d is not equal to denali->page %d", |
| 1210 | __func__, page, denali->page); |
Chuanxiao Dong | 7d8a26f | 2010-08-11 18:19:23 +0800 | [diff] [blame] | 1211 | BUG(); |
| 1212 | } |
| 1213 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1214 | setup_ecc_for_xfer(denali, false, true); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1215 | denali_enable_dma(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1216 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1217 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1218 | |
| 1219 | clear_interrupts(denali); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1220 | denali_setup_dma(denali, DENALI_READ); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1221 | |
| 1222 | /* wait for operation to complete */ |
Brian Norris | ba5f2bc | 2014-09-19 09:37:19 -0700 | [diff] [blame] | 1223 | wait_for_irq(denali, irq_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1224 | |
Jamie Iles | 8445794 | 2011-05-06 15:28:55 +0100 | [diff] [blame] | 1225 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1226 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1227 | denali_enable_dma(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1228 | |
| 1229 | memcpy(buf, denali->buf.buf, mtd->writesize); |
| 1230 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); |
| 1231 | |
| 1232 | return 0; |
| 1233 | } |
| 1234 | |
| 1235 | static uint8_t denali_read_byte(struct mtd_info *mtd) |
| 1236 | { |
| 1237 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1238 | uint8_t result = 0xff; |
| 1239 | |
| 1240 | if (denali->buf.head < denali->buf.tail) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1241 | result = denali->buf.buf[denali->buf.head++]; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1242 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1243 | return result; |
| 1244 | } |
| 1245 | |
| 1246 | static void denali_select_chip(struct mtd_info *mtd, int chip) |
| 1247 | { |
| 1248 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 1249 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1250 | spin_lock_irq(&denali->irq_lock); |
| 1251 | denali->flash_bank = chip; |
| 1252 | spin_unlock_irq(&denali->irq_lock); |
| 1253 | } |
| 1254 | |
| 1255 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) |
| 1256 | { |
| 1257 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1258 | int status = denali->status; |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1259 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1260 | denali->status = 0; |
| 1261 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1262 | return status; |
| 1263 | } |
| 1264 | |
Brian Norris | 49c50b9 | 2014-05-06 16:02:19 -0700 | [diff] [blame] | 1265 | static int denali_erase(struct mtd_info *mtd, int page) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1266 | { |
| 1267 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1268 | |
Masahiro Yamada | 5637b69 | 2014-09-09 11:01:52 +0900 | [diff] [blame] | 1269 | uint32_t cmd, irq_status; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1270 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1271 | clear_interrupts(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1272 | |
| 1273 | /* setup page read request for access type */ |
| 1274 | cmd = MODE_10 | BANK(denali->flash_bank) | page; |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 1275 | index_addr(denali, cmd, 0x1); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1276 | |
| 1277 | /* wait for erase to complete or failure to occur */ |
Jamie Iles | 9589bf5 | 2011-05-06 15:28:56 +0100 | [diff] [blame] | 1278 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
| 1279 | INTR_STATUS__ERASE_FAIL); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1280 | |
Masahiro Yamada | 7d14ecd | 2014-09-16 20:04:24 +0900 | [diff] [blame] | 1281 | return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1282 | } |
| 1283 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1284 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1285 | int page) |
| 1286 | { |
| 1287 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 1288 | uint32_t addr, id; |
| 1289 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1290 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1291 | switch (cmd) { |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1292 | case NAND_CMD_PAGEPROG: |
| 1293 | break; |
| 1294 | case NAND_CMD_STATUS: |
| 1295 | read_status(denali); |
| 1296 | break; |
| 1297 | case NAND_CMD_READID: |
Florian Fainelli | 42af8b5 | 2010-08-30 18:32:20 +0200 | [diff] [blame] | 1298 | case NAND_CMD_PARAM: |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1299 | reset_buf(denali); |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1300 | /* |
| 1301 | * sometimes ManufactureId read from register is not right |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 1302 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
| 1303 | * So here we send READID cmd to NAND insteand |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1304 | */ |
Masahiro Yamada | 3157d1e | 2014-09-09 11:01:53 +0900 | [diff] [blame] | 1305 | addr = MODE_11 | BANK(denali->flash_bank); |
| 1306 | index_addr(denali, addr | 0, 0x90); |
| 1307 | index_addr(denali, addr | 1, 0); |
grmoore@altera.com | d68a5c3 | 2014-06-23 14:21:10 -0500 | [diff] [blame] | 1308 | for (i = 0; i < 8; i++) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1309 | index_addr_read_data(denali, addr | 2, &id); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 1310 | write_byte_to_buf(denali, id); |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1311 | } |
| 1312 | break; |
| 1313 | case NAND_CMD_READ0: |
| 1314 | case NAND_CMD_SEQIN: |
| 1315 | denali->page = page; |
| 1316 | break; |
| 1317 | case NAND_CMD_RESET: |
| 1318 | reset_bank(denali); |
| 1319 | break; |
| 1320 | case NAND_CMD_READOOB: |
| 1321 | /* TODO: Read OOB data */ |
| 1322 | break; |
| 1323 | default: |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1324 | pr_err(": unsupported command received 0x%x\n", cmd); |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1325 | break; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1326 | } |
| 1327 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1328 | /* end NAND core entry points */ |
| 1329 | |
| 1330 | /* Initialization code to bring the device up to a known good state */ |
| 1331 | static void denali_hw_init(struct denali_nand_info *denali) |
| 1332 | { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1333 | /* |
| 1334 | * tell driver how many bit controller will skip before |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1335 | * writing ECC code in OOB, this register may be already |
| 1336 | * set by firmware. So we read this value out. |
| 1337 | * if this value is 0, just let it be. |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1338 | */ |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1339 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
| 1340 | SPARE_AREA_SKIP_BYTES); |
Jamie Iles | bc27ede | 2011-06-06 17:11:34 +0100 | [diff] [blame] | 1341 | detect_max_banks(denali); |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 1342 | denali_nand_reset(denali); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1343 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
| 1344 | iowrite32(CHIP_EN_DONT_CARE__FLAG, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1345 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1346 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1347 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1348 | |
| 1349 | /* Should set value for these registers when init */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1350 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
| 1351 | iowrite32(1, denali->flash_reg + ECC_ENABLE); |
Chuanxiao Dong | 5eab6aaa | 2010-08-12 10:07:18 +0800 | [diff] [blame] | 1352 | denali_nand_timing_set(denali); |
| 1353 | denali_irq_init(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1354 | } |
| 1355 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1356 | /* |
| 1357 | * Althogh controller spec said SLC ECC is forceb to be 4bit, |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1358 | * but denali controller in MRST only support 15bit and 8bit ECC |
| 1359 | * correction |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1360 | */ |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1361 | #define ECC_8BITS 14 |
| 1362 | static struct nand_ecclayout nand_8bit_oob = { |
| 1363 | .eccbytes = 14, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1364 | }; |
| 1365 | |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1366 | #define ECC_15BITS 26 |
| 1367 | static struct nand_ecclayout nand_15bit_oob = { |
| 1368 | .eccbytes = 26, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1369 | }; |
| 1370 | |
| 1371 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; |
| 1372 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; |
| 1373 | |
| 1374 | static struct nand_bbt_descr bbt_main_descr = { |
| 1375 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
| 1376 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 1377 | .offs = 8, |
| 1378 | .len = 4, |
| 1379 | .veroffs = 12, |
| 1380 | .maxblocks = 4, |
| 1381 | .pattern = bbt_pattern, |
| 1382 | }; |
| 1383 | |
| 1384 | static struct nand_bbt_descr bbt_mirror_descr = { |
| 1385 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
| 1386 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 1387 | .offs = 8, |
| 1388 | .len = 4, |
| 1389 | .veroffs = 12, |
| 1390 | .maxblocks = 4, |
| 1391 | .pattern = mirror_pattern, |
| 1392 | }; |
| 1393 | |
Uwe Kleine-König | 421f91d | 2010-06-11 12:17:00 +0200 | [diff] [blame] | 1394 | /* initialize driver data structures */ |
Brian Norris | 8c51943 | 2013-08-10 22:57:30 -0700 | [diff] [blame] | 1395 | static void denali_drv_init(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1396 | { |
| 1397 | denali->idx = 0; |
| 1398 | |
| 1399 | /* setup interrupt handler */ |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1400 | /* |
| 1401 | * the completion object will be used to notify |
| 1402 | * the callee that the interrupt is done |
| 1403 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1404 | init_completion(&denali->complete); |
| 1405 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1406 | /* |
| 1407 | * the spinlock will be used to synchronize the ISR with any |
| 1408 | * element that might be access shared data (interrupt status) |
| 1409 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1410 | spin_lock_init(&denali->irq_lock); |
| 1411 | |
| 1412 | /* indicate that MTD has not selected a valid bank yet */ |
| 1413 | denali->flash_bank = CHIP_SELECT_INVALID; |
| 1414 | |
| 1415 | /* initialize our irq_status variable to indicate no interrupts */ |
| 1416 | denali->irq_status = 0; |
| 1417 | } |
| 1418 | |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1419 | int denali_init(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1420 | { |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1421 | int ret; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1422 | |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1423 | if (denali->platform == INTEL_CE4100) { |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1424 | /* |
| 1425 | * Due to a silicon limitation, we can only support |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1426 | * ONFI timing mode 1 and below. |
| 1427 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1428 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1429 | pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); |
| 1430 | return -EINVAL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1431 | } |
| 1432 | } |
| 1433 | |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1434 | /* allocate a temporary buffer for nand_scan_ident() */ |
| 1435 | denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, |
| 1436 | GFP_DMA | GFP_KERNEL); |
| 1437 | if (!denali->buf.buf) |
| 1438 | return -ENOMEM; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1439 | |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1440 | denali->mtd.dev.parent = denali->dev; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1441 | denali_hw_init(denali); |
| 1442 | denali_drv_init(denali); |
| 1443 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1444 | /* |
| 1445 | * denali_isr register is done after all the hardware |
| 1446 | * initilization is finished |
| 1447 | */ |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1448 | if (request_irq(denali->irq, denali_isr, IRQF_SHARED, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1449 | DENALI_NAND_NAME, denali)) { |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1450 | pr_err("Spectra: Unable to allocate IRQ\n"); |
| 1451 | return -ENODEV; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1452 | } |
| 1453 | |
| 1454 | /* now that our ISR is registered, we can enable interrupts */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 1455 | denali_set_intr_modes(denali, true); |
Chuanxiao Dong | 5eab6aaa | 2010-08-12 10:07:18 +0800 | [diff] [blame] | 1456 | denali->mtd.name = "denali-nand"; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1457 | denali->mtd.owner = THIS_MODULE; |
| 1458 | denali->mtd.priv = &denali->nand; |
| 1459 | |
| 1460 | /* register the driver with the NAND core subsystem */ |
| 1461 | denali->nand.select_chip = denali_select_chip; |
| 1462 | denali->nand.cmdfunc = denali_cmdfunc; |
| 1463 | denali->nand.read_byte = denali_read_byte; |
| 1464 | denali->nand.waitfunc = denali_waitfunc; |
| 1465 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1466 | /* |
| 1467 | * scan for NAND devices attached to the controller |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1468 | * this is the first stage in a two step process to register |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1469 | * with the nand subsystem |
| 1470 | */ |
Jamie Iles | c89eeda | 2011-05-06 15:28:57 +0100 | [diff] [blame] | 1471 | if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1472 | ret = -ENXIO; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1473 | goto failed_req_irq; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1474 | } |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1475 | |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1476 | /* allocate the right size buffer now */ |
| 1477 | devm_kfree(denali->dev, denali->buf.buf); |
| 1478 | denali->buf.buf = devm_kzalloc(denali->dev, |
| 1479 | denali->mtd.writesize + denali->mtd.oobsize, |
| 1480 | GFP_KERNEL); |
| 1481 | if (!denali->buf.buf) { |
| 1482 | ret = -ENOMEM; |
| 1483 | goto failed_req_irq; |
| 1484 | } |
| 1485 | |
| 1486 | /* Is 32-bit DMA supported? */ |
| 1487 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); |
| 1488 | if (ret) { |
| 1489 | pr_err("Spectra: no usable DMA configuration\n"); |
| 1490 | goto failed_req_irq; |
| 1491 | } |
| 1492 | |
| 1493 | denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, |
| 1494 | denali->mtd.writesize + denali->mtd.oobsize, |
| 1495 | DMA_BIDIRECTIONAL); |
| 1496 | if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { |
| 1497 | dev_err(denali->dev, "Spectra: failed to map DMA buffer\n"); |
| 1498 | ret = -EIO; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1499 | goto failed_req_irq; |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 1500 | } |
| 1501 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1502 | /* |
| 1503 | * support for multi nand |
| 1504 | * MTD known nothing about multi nand, so we should tell it |
| 1505 | * the real pagesize and anything necessery |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1506 | */ |
| 1507 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); |
| 1508 | denali->nand.chipsize <<= (denali->devnum - 1); |
| 1509 | denali->nand.page_shift += (denali->devnum - 1); |
| 1510 | denali->nand.pagemask = (denali->nand.chipsize >> |
| 1511 | denali->nand.page_shift) - 1; |
| 1512 | denali->nand.bbt_erase_shift += (denali->devnum - 1); |
| 1513 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; |
| 1514 | denali->nand.chip_shift += (denali->devnum - 1); |
| 1515 | denali->mtd.writesize <<= (denali->devnum - 1); |
| 1516 | denali->mtd.oobsize <<= (denali->devnum - 1); |
| 1517 | denali->mtd.erasesize <<= (denali->devnum - 1); |
| 1518 | denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; |
| 1519 | denali->bbtskipbytes *= denali->devnum; |
| 1520 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1521 | /* |
| 1522 | * second stage of the NAND scan |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1523 | * this stage requires information regarding ECC and |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1524 | * bad block management. |
| 1525 | */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1526 | |
| 1527 | /* Bad block management */ |
| 1528 | denali->nand.bbt_td = &bbt_main_descr; |
| 1529 | denali->nand.bbt_md = &bbt_mirror_descr; |
| 1530 | |
| 1531 | /* skip the scan for now until we have OOB read and write support */ |
Brian Norris | bb9ebd4 | 2011-05-31 16:31:23 -0700 | [diff] [blame] | 1532 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
Brian Norris | a40f734 | 2011-05-31 16:31:22 -0700 | [diff] [blame] | 1533 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1534 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
| 1535 | |
Graham Moore | d99d728 | 2015-01-14 09:38:50 -0600 | [diff] [blame^] | 1536 | /* no subpage writes on denali */ |
| 1537 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; |
| 1538 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1539 | /* |
| 1540 | * Denali Controller only support 15bit and 8bit ECC in MRST, |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1541 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
| 1542 | * SLC if possible. |
| 1543 | * */ |
Huang Shijie | 1d0ed69 | 2013-09-25 14:58:10 +0800 | [diff] [blame] | 1544 | if (!nand_is_slc(&denali->nand) && |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1545 | (denali->mtd.oobsize > (denali->bbtskipbytes + |
| 1546 | ECC_15BITS * (denali->mtd.writesize / |
| 1547 | ECC_SECTOR_SIZE)))) { |
| 1548 | /* if MLC OOB size is large enough, use 15bit ECC*/ |
Mike Dunn | 6a918ba | 2012-03-11 14:21:11 -0700 | [diff] [blame] | 1549 | denali->nand.ecc.strength = 15; |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1550 | denali->nand.ecc.layout = &nand_15bit_oob; |
| 1551 | denali->nand.ecc.bytes = ECC_15BITS; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1552 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1553 | } else if (denali->mtd.oobsize < (denali->bbtskipbytes + |
| 1554 | ECC_8BITS * (denali->mtd.writesize / |
| 1555 | ECC_SECTOR_SIZE))) { |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1556 | pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1557 | goto failed_req_irq; |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1558 | } else { |
Mike Dunn | 6a918ba | 2012-03-11 14:21:11 -0700 | [diff] [blame] | 1559 | denali->nand.ecc.strength = 8; |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1560 | denali->nand.ecc.layout = &nand_8bit_oob; |
| 1561 | denali->nand.ecc.bytes = ECC_8BITS; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame] | 1562 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1563 | } |
| 1564 | |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1565 | denali->nand.ecc.bytes *= denali->devnum; |
Mike Dunn | 6a918ba | 2012-03-11 14:21:11 -0700 | [diff] [blame] | 1566 | denali->nand.ecc.strength *= denali->devnum; |
Chuanxiao Dong | db9a3210 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1567 | denali->nand.ecc.layout->eccbytes *= |
| 1568 | denali->mtd.writesize / ECC_SECTOR_SIZE; |
| 1569 | denali->nand.ecc.layout->oobfree[0].offset = |
| 1570 | denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; |
| 1571 | denali->nand.ecc.layout->oobfree[0].length = |
| 1572 | denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - |
| 1573 | denali->bbtskipbytes; |
| 1574 | |
Masahiro Yamada | 43914a2 | 2014-09-09 11:01:51 +0900 | [diff] [blame] | 1575 | /* |
| 1576 | * Let driver know the total blocks number and how many blocks |
| 1577 | * contained by each nand chip. blksperchip will help driver to |
| 1578 | * know how many blocks is taken by FW. |
| 1579 | */ |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1580 | denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift; |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 1581 | denali->blksperchip = denali->totalblks / denali->nand.numchips; |
| 1582 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1583 | /* override the default read operations */ |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1584 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1585 | denali->nand.ecc.read_page = denali_read_page; |
| 1586 | denali->nand.ecc.read_page_raw = denali_read_page_raw; |
| 1587 | denali->nand.ecc.write_page = denali_write_page; |
| 1588 | denali->nand.ecc.write_page_raw = denali_write_page_raw; |
| 1589 | denali->nand.ecc.read_oob = denali_read_oob; |
| 1590 | denali->nand.ecc.write_oob = denali_write_oob; |
Brian Norris | 49c50b9 | 2014-05-06 16:02:19 -0700 | [diff] [blame] | 1591 | denali->nand.erase = denali_erase; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1592 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1593 | if (nand_scan_tail(&denali->mtd)) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1594 | ret = -ENXIO; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1595 | goto failed_req_irq; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1596 | } |
| 1597 | |
Jamie Iles | ee0e87b | 2011-05-23 10:23:40 +0100 | [diff] [blame] | 1598 | ret = mtd_device_register(&denali->mtd, NULL, 0); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1599 | if (ret) { |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1600 | dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n", |
Chuanxiao Dong | 7cfffac | 2010-08-10 00:16:51 +0800 | [diff] [blame] | 1601 | ret); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1602 | goto failed_req_irq; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1603 | } |
| 1604 | return 0; |
| 1605 | |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1606 | failed_req_irq: |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1607 | denali_irq_cleanup(denali->irq, denali); |
| 1608 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1609 | return ret; |
| 1610 | } |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1611 | EXPORT_SYMBOL(denali_init); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1612 | |
| 1613 | /* driver exit point */ |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1614 | void denali_remove(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1615 | { |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1616 | denali_irq_cleanup(denali->irq, denali); |
Huang Shijie | e07caa3 | 2013-12-21 00:02:28 +0800 | [diff] [blame] | 1617 | dma_unmap_single(denali->dev, denali->buf.dma_buf, |
Masahiro Yamada | 8125450 | 2014-09-16 20:04:25 +0900 | [diff] [blame] | 1618 | denali->mtd.writesize + denali->mtd.oobsize, |
| 1619 | DMA_BIDIRECTIONAL); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1620 | } |
Dinh Nguyen | 2a0a288 | 2012-09-27 10:58:05 -0600 | [diff] [blame] | 1621 | EXPORT_SYMBOL(denali_remove); |