blob: 870c7fc0f759dc515539c170f2befeae2d2be872 [file] [log] [blame]
Jason Robertsce082592010-05-13 15:57:33 +01001/*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
Jason Robertsce082592010-05-13 15:57:33 +010019#include <linux/interrupt.h>
20#include <linux/delay.h>
Jamie Iles84457942011-05-06 15:28:55 +010021#include <linux/dma-mapping.h>
Jason Robertsce082592010-05-13 15:57:33 +010022#include <linux/wait.h>
23#include <linux/mutex.h>
David Millerb8664b32010-08-04 22:57:51 -070024#include <linux/slab.h>
Jason Robertsce082592010-05-13 15:57:33 +010025#include <linux/mtd/mtd.h>
26#include <linux/module.h>
27
28#include "denali.h"
29
30MODULE_LICENSE("GPL");
31
Masahiro Yamada43914a22014-09-09 11:01:51 +090032/*
33 * We define a module parameter that allows the user to override
Jason Robertsce082592010-05-13 15:57:33 +010034 * the hardware and decide what timing mode should be used.
35 */
36#define NAND_DEFAULT_TIMINGS -1
37
38static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39module_param(onfi_timing_mode, int, S_IRUGO);
Masahiro Yamada81254502014-09-16 20:04:25 +090040MODULE_PARM_DESC(onfi_timing_mode,
41 "Overrides default ONFI setting. -1 indicates use default timings");
Jason Robertsce082592010-05-13 15:57:33 +010042
43#define DENALI_NAND_NAME "denali-nand"
44
Masahiro Yamada43914a22014-09-09 11:01:51 +090045/*
46 * We define a macro here that combines all interrupts this driver uses into
47 * a single constant value, for convenience.
48 */
Jamie Iles9589bf52011-05-06 15:28:56 +010049#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
50 INTR_STATUS__ECC_TRANSACTION_DONE | \
51 INTR_STATUS__ECC_ERR | \
52 INTR_STATUS__PROGRAM_FAIL | \
53 INTR_STATUS__LOAD_COMP | \
54 INTR_STATUS__PROGRAM_COMP | \
55 INTR_STATUS__TIME_OUT | \
56 INTR_STATUS__ERASE_FAIL | \
57 INTR_STATUS__RST_COMP | \
58 INTR_STATUS__ERASE_COMP)
Jason Robertsce082592010-05-13 15:57:33 +010059
Masahiro Yamada43914a22014-09-09 11:01:51 +090060/*
61 * indicates whether or not the internal value for the flash bank is
62 * valid or not
63 */
Chuanxiao5bac3ac2010-08-05 23:06:04 +080064#define CHIP_SELECT_INVALID -1
Jason Robertsce082592010-05-13 15:57:33 +010065
66#define SUPPORT_8BITECC 1
67
Masahiro Yamada43914a22014-09-09 11:01:51 +090068/*
69 * This macro divides two integers and rounds fractional values up
70 * to the nearest integer value.
71 */
Jason Robertsce082592010-05-13 15:57:33 +010072#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
73
Masahiro Yamada43914a22014-09-09 11:01:51 +090074/*
75 * this macro allows us to convert from an MTD structure to our own
Jason Robertsce082592010-05-13 15:57:33 +010076 * device context (denali) structure.
77 */
78#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
79
Masahiro Yamada43914a22014-09-09 11:01:51 +090080/*
81 * These constants are defined by the driver to enable common driver
82 * configuration options.
83 */
Jason Robertsce082592010-05-13 15:57:33 +010084#define SPARE_ACCESS 0x41
85#define MAIN_ACCESS 0x42
86#define MAIN_SPARE_ACCESS 0x43
Masahiro Yamada29023302014-07-11 11:14:05 +090087#define PIPELINE_ACCESS 0x2000
Jason Robertsce082592010-05-13 15:57:33 +010088
89#define DENALI_READ 0
90#define DENALI_WRITE 0x100
91
92/* types of device accesses. We can issue commands and get status */
93#define COMMAND_CYCLE 0
94#define ADDR_CYCLE 1
95#define STATUS_CYCLE 2
96
Masahiro Yamada43914a22014-09-09 11:01:51 +090097/*
98 * this is a helper macro that allows us to
99 * format the bank into the proper bits for the controller
100 */
Jason Robertsce082592010-05-13 15:57:33 +0100101#define BANK(x) ((x) << 24)
102
Jason Robertsce082592010-05-13 15:57:33 +0100103/* forward declarations */
104static void clear_interrupts(struct denali_nand_info *denali);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800105static uint32_t wait_for_irq(struct denali_nand_info *denali,
106 uint32_t irq_mask);
107static void denali_irq_enable(struct denali_nand_info *denali,
108 uint32_t int_mask);
Jason Robertsce082592010-05-13 15:57:33 +0100109static uint32_t read_interrupt_status(struct denali_nand_info *denali);
110
Masahiro Yamada43914a22014-09-09 11:01:51 +0900111/*
112 * Certain operations for the denali NAND controller use an indexed mode to
113 * read/write data. The operation is performed by writing the address value
114 * of the command to the device memory followed by the data. This function
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800115 * abstracts this common operation.
Masahiro Yamada43914a22014-09-09 11:01:51 +0900116 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800117static void index_addr(struct denali_nand_info *denali,
118 uint32_t address, uint32_t data)
Jason Robertsce082592010-05-13 15:57:33 +0100119{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800120 iowrite32(address, denali->flash_mem);
121 iowrite32(data, denali->flash_mem + 0x10);
Jason Robertsce082592010-05-13 15:57:33 +0100122}
123
124/* Perform an indexed read of the device */
125static void index_addr_read_data(struct denali_nand_info *denali,
126 uint32_t address, uint32_t *pdata)
127{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800128 iowrite32(address, denali->flash_mem);
Jason Robertsce082592010-05-13 15:57:33 +0100129 *pdata = ioread32(denali->flash_mem + 0x10);
130}
131
Masahiro Yamada43914a22014-09-09 11:01:51 +0900132/*
133 * We need to buffer some data for some of the NAND core routines.
134 * The operations manage buffering that data.
135 */
Jason Robertsce082592010-05-13 15:57:33 +0100136static void reset_buf(struct denali_nand_info *denali)
137{
138 denali->buf.head = denali->buf.tail = 0;
139}
140
141static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
142{
Jason Robertsce082592010-05-13 15:57:33 +0100143 denali->buf.buf[denali->buf.tail++] = byte;
144}
145
146/* reads the status of the device */
147static void read_status(struct denali_nand_info *denali)
148{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900149 uint32_t cmd;
Jason Robertsce082592010-05-13 15:57:33 +0100150
151 /* initialize the data buffer to store status */
152 reset_buf(denali);
153
Chuanxiao Dongf0bc0c72010-08-11 17:14:59 +0800154 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
155 if (cmd)
156 write_byte_to_buf(denali, NAND_STATUS_WP);
157 else
158 write_byte_to_buf(denali, 0);
Jason Robertsce082592010-05-13 15:57:33 +0100159}
160
161/* resets a specific device connected to the core */
162static void reset_bank(struct denali_nand_info *denali)
163{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900164 uint32_t irq_status;
Masahiro Yamada81254502014-09-16 20:04:25 +0900165 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
Jason Robertsce082592010-05-13 15:57:33 +0100166
167 clear_interrupts(denali);
168
Jamie Iles9589bf52011-05-06 15:28:56 +0100169 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
Jason Robertsce082592010-05-13 15:57:33 +0100170
171 irq_status = wait_for_irq(denali, irq_mask);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800172
Jamie Iles9589bf52011-05-06 15:28:56 +0100173 if (irq_status & INTR_STATUS__TIME_OUT)
Jamie Iles84457942011-05-06 15:28:55 +0100174 dev_err(denali->dev, "reset bank failed.\n");
Jason Robertsce082592010-05-13 15:57:33 +0100175}
176
177/* Reset the flash controller */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800178static uint16_t denali_nand_reset(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +0100179{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900180 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100181
Jamie Iles84457942011-05-06 15:28:55 +0100182 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900183 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100184
Masahiro Yamada81254502014-09-16 20:04:25 +0900185 for (i = 0; i < denali->max_banks; i++)
Jamie Iles9589bf52011-05-06 15:28:56 +0100186 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
187 denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100188
Masahiro Yamada81254502014-09-16 20:04:25 +0900189 for (i = 0; i < denali->max_banks; i++) {
Jamie Iles9589bf52011-05-06 15:28:56 +0100190 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
Masahiro Yamada81254502014-09-16 20:04:25 +0900191 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
Jamie Iles9589bf52011-05-06 15:28:56 +0100192 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
Chuanxiao Dong628bfd412010-08-11 17:53:29 +0800193 cpu_relax();
Jamie Iles9589bf52011-05-06 15:28:56 +0100194 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
195 INTR_STATUS__TIME_OUT)
Jamie Iles84457942011-05-06 15:28:55 +0100196 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100197 "NAND Reset operation timed out on bank %d\n", i);
198 }
199
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100200 for (i = 0; i < denali->max_banks; i++)
Jamie Iles9589bf52011-05-06 15:28:56 +0100201 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
Masahiro Yamada81254502014-09-16 20:04:25 +0900202 denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100203
204 return PASS;
205}
206
Masahiro Yamada43914a22014-09-09 11:01:51 +0900207/*
208 * this routine calculates the ONFI timing values for a given mode and
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800209 * programs the clocking register accordingly. The mode is determined by
210 * the get_onfi_nand_para routine.
Jason Robertsce082592010-05-13 15:57:33 +0100211 */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800212static void nand_onfi_timing_set(struct denali_nand_info *denali,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800213 uint16_t mode)
Jason Robertsce082592010-05-13 15:57:33 +0100214{
215 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
216 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
217 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
218 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
219 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
220 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
221 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
222 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
223 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
224 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
225 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
226 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
227
Jason Robertsce082592010-05-13 15:57:33 +0100228 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
229 uint16_t dv_window = 0;
230 uint16_t en_lo, en_hi;
231 uint16_t acc_clks;
232 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
233
Jamie Iles84457942011-05-06 15:28:55 +0100234 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900235 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100236
237 en_lo = CEIL_DIV(Trp[mode], CLK_X);
238 en_hi = CEIL_DIV(Treh[mode], CLK_X);
239#if ONFI_BLOOM_TIME
240 if ((en_hi * CLK_X) < (Treh[mode] + 2))
241 en_hi++;
242#endif
243
244 if ((en_lo + en_hi) * CLK_X < Trc[mode])
245 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
246
247 if ((en_lo + en_hi) < CLK_MULTI)
248 en_lo += CLK_MULTI - en_lo - en_hi;
249
250 while (dv_window < 8) {
251 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
252
253 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
254
Masahiro Yamada81254502014-09-16 20:04:25 +0900255 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
256 data_invalid_rhoh : data_invalid_rloh;
Jason Robertsce082592010-05-13 15:57:33 +0100257
258 dv_window = data_invalid - Trea[mode];
259
260 if (dv_window < 8)
261 en_lo++;
262 }
263
264 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
265
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900266 while (acc_clks * CLK_X - Trea[mode] < 3)
Jason Robertsce082592010-05-13 15:57:33 +0100267 acc_clks++;
268
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900269 if (data_invalid - acc_clks * CLK_X < 2)
Jamie Iles84457942011-05-06 15:28:55 +0100270 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900271 __FILE__, __LINE__);
Jason Robertsce082592010-05-13 15:57:33 +0100272
273 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
274 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
275 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
276 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
277 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
Jason Robertsce082592010-05-13 15:57:33 +0100278 if (cs_cnt == 0)
279 cs_cnt = 1;
280
281 if (Tcea[mode]) {
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900282 while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
Jason Robertsce082592010-05-13 15:57:33 +0100283 cs_cnt++;
284 }
285
286#if MODE5_WORKAROUND
287 if (mode == 5)
288 acc_clks = 5;
289#endif
290
291 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900292 if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
293 ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
Jason Robertsce082592010-05-13 15:57:33 +0100294 acc_clks = 6;
295
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800296 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
297 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
298 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
299 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
300 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
301 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
302 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
303 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
Jason Robertsce082592010-05-13 15:57:33 +0100304}
305
Jason Robertsce082592010-05-13 15:57:33 +0100306/* queries the NAND device to see what ONFI modes it supports. */
307static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
308{
309 int i;
Masahiro Yamada43914a22014-09-09 11:01:51 +0900310
311 /*
312 * we needn't to do a reset here because driver has already
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800313 * reset all the banks before
Masahiro Yamada43914a22014-09-09 11:01:51 +0900314 */
Jason Robertsce082592010-05-13 15:57:33 +0100315 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
316 ONFI_TIMING_MODE__VALUE))
317 return FAIL;
318
319 for (i = 5; i > 0; i--) {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800320 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
321 (0x01 << i))
Jason Robertsce082592010-05-13 15:57:33 +0100322 break;
323 }
324
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800325 nand_onfi_timing_set(denali, i);
Jason Robertsce082592010-05-13 15:57:33 +0100326
Masahiro Yamada43914a22014-09-09 11:01:51 +0900327 /*
328 * By now, all the ONFI devices we know support the page cache
329 * rw feature. So here we enable the pipeline_rw_ahead feature
330 */
Jason Robertsce082592010-05-13 15:57:33 +0100331 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
332 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
333
334 return PASS;
335}
336
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800337static void get_samsung_nand_para(struct denali_nand_info *denali,
338 uint8_t device_id)
Jason Robertsce082592010-05-13 15:57:33 +0100339{
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800340 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
Jason Robertsce082592010-05-13 15:57:33 +0100341 /* Set timing register values according to datasheet */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800342 iowrite32(5, denali->flash_reg + ACC_CLKS);
343 iowrite32(20, denali->flash_reg + RE_2_WE);
344 iowrite32(12, denali->flash_reg + WE_2_RE);
345 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
346 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
347 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
348 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
Jason Robertsce082592010-05-13 15:57:33 +0100349 }
Jason Robertsce082592010-05-13 15:57:33 +0100350}
351
352static void get_toshiba_nand_para(struct denali_nand_info *denali)
353{
Jason Robertsce082592010-05-13 15:57:33 +0100354 uint32_t tmp;
355
Masahiro Yamada43914a22014-09-09 11:01:51 +0900356 /*
357 * Workaround to fix a controller bug which reports a wrong
358 * spare area size for some kind of Toshiba NAND device
359 */
Jason Robertsce082592010-05-13 15:57:33 +0100360 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
361 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800362 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Jason Robertsce082592010-05-13 15:57:33 +0100363 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
364 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800365 iowrite32(tmp,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800366 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
Jason Robertsce082592010-05-13 15:57:33 +0100367#if SUPPORT_15BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800368 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100369#elif SUPPORT_8BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800370 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100371#endif
372 }
Jason Robertsce082592010-05-13 15:57:33 +0100373}
374
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800375static void get_hynix_nand_para(struct denali_nand_info *denali,
376 uint8_t device_id)
Jason Robertsce082592010-05-13 15:57:33 +0100377{
Jason Robertsce082592010-05-13 15:57:33 +0100378 uint32_t main_size, spare_size;
379
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800380 switch (device_id) {
Jason Robertsce082592010-05-13 15:57:33 +0100381 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
382 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800383 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
384 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
385 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800386 main_size = 4096 *
387 ioread32(denali->flash_reg + DEVICES_CONNECTED);
388 spare_size = 224 *
389 ioread32(denali->flash_reg + DEVICES_CONNECTED);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800390 iowrite32(main_size,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800391 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800392 iowrite32(spare_size,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800393 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800394 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
Jason Robertsce082592010-05-13 15:57:33 +0100395#if SUPPORT_15BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800396 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100397#elif SUPPORT_8BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800398 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100399#endif
Jason Robertsce082592010-05-13 15:57:33 +0100400 break;
401 default:
Jamie Iles84457942011-05-06 15:28:55 +0100402 dev_warn(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900403 "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
404 "Will use default parameter values instead.\n",
405 device_id);
Jason Robertsce082592010-05-13 15:57:33 +0100406 }
407}
408
Masahiro Yamada43914a22014-09-09 11:01:51 +0900409/*
410 * determines how many NAND chips are connected to the controller. Note for
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800411 * Intel CE4100 devices we don't support more than one device.
Jason Robertsce082592010-05-13 15:57:33 +0100412 */
413static void find_valid_banks(struct denali_nand_info *denali)
414{
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100415 uint32_t id[denali->max_banks];
Jason Robertsce082592010-05-13 15:57:33 +0100416 int i;
417
418 denali->total_used_banks = 1;
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100419 for (i = 0; i < denali->max_banks; i++) {
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900420 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
421 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
Masahiro Yamada81254502014-09-16 20:04:25 +0900422 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
Jason Robertsce082592010-05-13 15:57:33 +0100423
Jamie Iles84457942011-05-06 15:28:55 +0100424 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100425 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
426
427 if (i == 0) {
428 if (!(id[i] & 0x0ff))
429 break; /* WTF? */
430 } else {
431 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
432 denali->total_used_banks++;
433 else
434 break;
435 }
436 }
437
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800438 if (denali->platform == INTEL_CE4100) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900439 /*
440 * Platform limitations of the CE4100 device limit
Jason Robertsce082592010-05-13 15:57:33 +0100441 * users to a single chip solution for NAND.
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800442 * Multichip support is not enabled.
443 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800444 if (denali->total_used_banks != 1) {
Jamie Iles84457942011-05-06 15:28:55 +0100445 dev_err(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900446 "Sorry, Intel CE4100 only supports a single NAND device.\n");
Jason Robertsce082592010-05-13 15:57:33 +0100447 BUG();
448 }
449 }
Jamie Iles84457942011-05-06 15:28:55 +0100450 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100451 "denali->total_used_banks: %d\n", denali->total_used_banks);
452}
453
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100454/*
455 * Use the configuration feature register to determine the maximum number of
456 * banks that the hardware supports.
457 */
458static void detect_max_banks(struct denali_nand_info *denali)
459{
460 uint32_t features = ioread32(denali->flash_reg + FEATURES);
461
462 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
463}
464
Jason Robertsce082592010-05-13 15:57:33 +0100465static void detect_partition_feature(struct denali_nand_info *denali)
466{
Masahiro Yamada43914a22014-09-09 11:01:51 +0900467 /*
468 * For MRST platform, denali->fwblks represent the
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800469 * number of blocks firmware is taken,
470 * FW is in protect partition and MTD driver has no
471 * permission to access it. So let driver know how many
472 * blocks it can't touch.
Masahiro Yamada43914a22014-09-09 11:01:51 +0900473 */
Jason Robertsce082592010-05-13 15:57:33 +0100474 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
Jamie Iles9589bf52011-05-06 15:28:56 +0100475 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
476 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800477 denali->fwblks =
Jamie Iles9589bf52011-05-06 15:28:56 +0100478 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
479 MIN_MAX_BANK__MIN_VALUE) *
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800480 denali->blksperchip)
Jason Robertsce082592010-05-13 15:57:33 +0100481 +
Jamie Iles9589bf52011-05-06 15:28:56 +0100482 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
483 MIN_BLK_ADDR__VALUE);
Masahiro Yamada81254502014-09-16 20:04:25 +0900484 } else {
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800485 denali->fwblks = SPECTRA_START_BLOCK;
Masahiro Yamada81254502014-09-16 20:04:25 +0900486 }
487 } else {
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800488 denali->fwblks = SPECTRA_START_BLOCK;
Masahiro Yamada81254502014-09-16 20:04:25 +0900489 }
Jason Robertsce082592010-05-13 15:57:33 +0100490}
491
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800492static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +0100493{
494 uint16_t status = PASS;
grmoore@altera.comd68a5c32014-06-23 14:21:10 -0500495 uint32_t id_bytes[8], addr;
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900496 uint8_t maf_id, device_id;
497 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100498
Masahiro Yamada81254502014-09-16 20:04:25 +0900499 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800500 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100501
Masahiro Yamada43914a22014-09-09 11:01:51 +0900502 /*
503 * Use read id method to get device ID and other params.
504 * For some NAND chips, controller can't report the correct
505 * device ID by reading from DEVICE_ID register
506 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900507 addr = MODE_11 | BANK(denali->flash_bank);
508 index_addr(denali, addr | 0, 0x90);
509 index_addr(denali, addr | 1, 0);
grmoore@altera.comd68a5c32014-06-23 14:21:10 -0500510 for (i = 0; i < 8; i++)
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800511 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
512 maf_id = id_bytes[0];
513 device_id = id_bytes[1];
Jason Robertsce082592010-05-13 15:57:33 +0100514
515 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
516 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
517 if (FAIL == get_onfi_nand_para(denali))
518 return FAIL;
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800519 } else if (maf_id == 0xEC) { /* Samsung NAND */
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800520 get_samsung_nand_para(denali, device_id);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800521 } else if (maf_id == 0x98) { /* Toshiba NAND */
Jason Robertsce082592010-05-13 15:57:33 +0100522 get_toshiba_nand_para(denali);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800523 } else if (maf_id == 0xAD) { /* Hynix NAND */
524 get_hynix_nand_para(denali, device_id);
Jason Robertsce082592010-05-13 15:57:33 +0100525 }
526
Jamie Iles84457942011-05-06 15:28:55 +0100527 dev_info(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900528 "Dump timing register values:\n"
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800529 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
530 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
Jason Robertsce082592010-05-13 15:57:33 +0100531 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
532 ioread32(denali->flash_reg + ACC_CLKS),
533 ioread32(denali->flash_reg + RE_2_WE),
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800534 ioread32(denali->flash_reg + RE_2_RE),
Jason Robertsce082592010-05-13 15:57:33 +0100535 ioread32(denali->flash_reg + WE_2_RE),
536 ioread32(denali->flash_reg + ADDR_2_DATA),
537 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
538 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
539 ioread32(denali->flash_reg + CS_SETUP_CNT));
540
Jason Robertsce082592010-05-13 15:57:33 +0100541 find_valid_banks(denali);
542
543 detect_partition_feature(denali);
544
Masahiro Yamada43914a22014-09-09 11:01:51 +0900545 /*
546 * If the user specified to override the default timings
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800547 * with a specific ONFI mode, we apply those changes here.
Jason Robertsce082592010-05-13 15:57:33 +0100548 */
549 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800550 nand_onfi_timing_set(denali, onfi_timing_mode);
Jason Robertsce082592010-05-13 15:57:33 +0100551
552 return status;
553}
554
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800555static void denali_set_intr_modes(struct denali_nand_info *denali,
Jason Robertsce082592010-05-13 15:57:33 +0100556 uint16_t INT_ENABLE)
557{
Jamie Iles84457942011-05-06 15:28:55 +0100558 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900559 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100560
561 if (INT_ENABLE)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800562 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +0100563 else
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800564 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +0100565}
566
Masahiro Yamada43914a22014-09-09 11:01:51 +0900567/*
568 * validation function to verify that the controlling software is making
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800569 * a valid request
Jason Robertsce082592010-05-13 15:57:33 +0100570 */
571static inline bool is_flash_bank_valid(int flash_bank)
572{
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900573 return flash_bank >= 0 && flash_bank < 4;
Jason Robertsce082592010-05-13 15:57:33 +0100574}
575
576static void denali_irq_init(struct denali_nand_info *denali)
577{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900578 uint32_t int_mask;
Jamie Iles9589bf52011-05-06 15:28:56 +0100579 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100580
581 /* Disable global interrupts */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800582 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100583
584 int_mask = DENALI_IRQ_ALL;
585
586 /* Clear all status bits */
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100587 for (i = 0; i < denali->max_banks; ++i)
Jamie Iles9589bf52011-05-06 15:28:56 +0100588 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100589
590 denali_irq_enable(denali, int_mask);
591}
592
593static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
594{
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800595 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100596 free_irq(irqnum, denali);
597}
598
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800599static void denali_irq_enable(struct denali_nand_info *denali,
600 uint32_t int_mask)
Jason Robertsce082592010-05-13 15:57:33 +0100601{
Jamie Iles9589bf52011-05-06 15:28:56 +0100602 int i;
603
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100604 for (i = 0; i < denali->max_banks; ++i)
Jamie Iles9589bf52011-05-06 15:28:56 +0100605 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
Jason Robertsce082592010-05-13 15:57:33 +0100606}
607
Masahiro Yamada43914a22014-09-09 11:01:51 +0900608/*
609 * This function only returns when an interrupt that this driver cares about
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800610 * occurs. This is to reduce the overhead of servicing interrupts
Jason Robertsce082592010-05-13 15:57:33 +0100611 */
612static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
613{
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800614 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
Jason Robertsce082592010-05-13 15:57:33 +0100615}
616
617/* Interrupts are cleared by writing a 1 to the appropriate status bit */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800618static inline void clear_interrupt(struct denali_nand_info *denali,
619 uint32_t irq_mask)
Jason Robertsce082592010-05-13 15:57:33 +0100620{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900621 uint32_t intr_status_reg;
Jason Robertsce082592010-05-13 15:57:33 +0100622
Jamie Iles9589bf52011-05-06 15:28:56 +0100623 intr_status_reg = INTR_STATUS(denali->flash_bank);
Jason Robertsce082592010-05-13 15:57:33 +0100624
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800625 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
Jason Robertsce082592010-05-13 15:57:33 +0100626}
627
628static void clear_interrupts(struct denali_nand_info *denali)
629{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900630 uint32_t status;
631
Jason Robertsce082592010-05-13 15:57:33 +0100632 spin_lock_irq(&denali->irq_lock);
633
634 status = read_interrupt_status(denali);
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800635 clear_interrupt(denali, status);
Jason Robertsce082592010-05-13 15:57:33 +0100636
Jason Robertsce082592010-05-13 15:57:33 +0100637 denali->irq_status = 0x0;
638 spin_unlock_irq(&denali->irq_lock);
639}
640
641static uint32_t read_interrupt_status(struct denali_nand_info *denali)
642{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900643 uint32_t intr_status_reg;
Jason Robertsce082592010-05-13 15:57:33 +0100644
Jamie Iles9589bf52011-05-06 15:28:56 +0100645 intr_status_reg = INTR_STATUS(denali->flash_bank);
Jason Robertsce082592010-05-13 15:57:33 +0100646
647 return ioread32(denali->flash_reg + intr_status_reg);
648}
649
Masahiro Yamada43914a22014-09-09 11:01:51 +0900650/*
651 * This is the interrupt service routine. It handles all interrupts
652 * sent to this device. Note that on CE4100, this is a shared interrupt.
Jason Robertsce082592010-05-13 15:57:33 +0100653 */
654static irqreturn_t denali_isr(int irq, void *dev_id)
655{
656 struct denali_nand_info *denali = dev_id;
Masahiro Yamada5637b692014-09-09 11:01:52 +0900657 uint32_t irq_status;
Jason Robertsce082592010-05-13 15:57:33 +0100658 irqreturn_t result = IRQ_NONE;
659
660 spin_lock(&denali->irq_lock);
661
Masahiro Yamada43914a22014-09-09 11:01:51 +0900662 /* check to see if a valid NAND chip has been selected. */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800663 if (is_flash_bank_valid(denali->flash_bank)) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900664 /*
665 * check to see if controller generated the interrupt,
666 * since this is a shared interrupt
667 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800668 irq_status = denali_irq_detected(denali);
669 if (irq_status != 0) {
Jason Robertsce082592010-05-13 15:57:33 +0100670 /* handle interrupt */
671 /* first acknowledge it */
672 clear_interrupt(denali, irq_status);
Masahiro Yamada43914a22014-09-09 11:01:51 +0900673 /*
674 * store the status in the device context for someone
675 * to read
676 */
Jason Robertsce082592010-05-13 15:57:33 +0100677 denali->irq_status |= irq_status;
678 /* notify anyone who cares that it happened */
679 complete(&denali->complete);
680 /* tell the OS that we've handled this */
681 result = IRQ_HANDLED;
682 }
683 }
684 spin_unlock(&denali->irq_lock);
685 return result;
686}
687#define BANK(x) ((x) << 24)
688
689static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
690{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900691 unsigned long comp_res;
692 uint32_t intr_status;
Jason Robertsce082592010-05-13 15:57:33 +0100693 unsigned long timeout = msecs_to_jiffies(1000);
694
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800695 do {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800696 comp_res =
697 wait_for_completion_timeout(&denali->complete, timeout);
Jason Robertsce082592010-05-13 15:57:33 +0100698 spin_lock_irq(&denali->irq_lock);
699 intr_status = denali->irq_status;
700
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800701 if (intr_status & irq_mask) {
Jason Robertsce082592010-05-13 15:57:33 +0100702 denali->irq_status &= ~irq_mask;
703 spin_unlock_irq(&denali->irq_lock);
Jason Robertsce082592010-05-13 15:57:33 +0100704 /* our interrupt was detected */
705 break;
Jason Robertsce082592010-05-13 15:57:33 +0100706 }
Masahiro Yamada81254502014-09-16 20:04:25 +0900707
708 /*
709 * these are not the interrupts you are looking for -
710 * need to wait again
711 */
712 spin_unlock_irq(&denali->irq_lock);
Jason Robertsce082592010-05-13 15:57:33 +0100713 } while (comp_res != 0);
714
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800715 if (comp_res == 0) {
Jason Robertsce082592010-05-13 15:57:33 +0100716 /* timeout */
Dinh Nguyen2a0a2882012-09-27 10:58:05 -0600717 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800718 intr_status, irq_mask);
Jason Robertsce082592010-05-13 15:57:33 +0100719
720 intr_status = 0;
721 }
722 return intr_status;
723}
724
Masahiro Yamada43914a22014-09-09 11:01:51 +0900725/*
726 * This helper function setups the registers for ECC and whether or not
727 * the spare area will be transferred.
728 */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800729static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
Jason Robertsce082592010-05-13 15:57:33 +0100730 bool transfer_spare)
731{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900732 int ecc_en_flag, transfer_spare_flag;
Jason Robertsce082592010-05-13 15:57:33 +0100733
734 /* set ECC, transfer spare bits if needed */
735 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
736 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
737
738 /* Enable spare area/ECC per user's request. */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800739 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
Masahiro Yamada81254502014-09-16 20:04:25 +0900740 iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
Jason Robertsce082592010-05-13 15:57:33 +0100741}
742
Masahiro Yamada43914a22014-09-09 11:01:51 +0900743/*
744 * sends a pipeline command operation to the controller. See the Denali NAND
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800745 * controller's user guide for more information (section 4.2.3.6).
Jason Robertsce082592010-05-13 15:57:33 +0100746 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800747static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900748 bool ecc_en, bool transfer_spare,
749 int access_type, int op)
Jason Robertsce082592010-05-13 15:57:33 +0100750{
751 int status = PASS;
Masahiro Yamada5637b692014-09-09 11:01:52 +0900752 uint32_t page_count = 1;
753 uint32_t addr, cmd, irq_status, irq_mask;
Jason Robertsce082592010-05-13 15:57:33 +0100754
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800755 if (op == DENALI_READ)
Jamie Iles9589bf52011-05-06 15:28:56 +0100756 irq_mask = INTR_STATUS__LOAD_COMP;
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800757 else if (op == DENALI_WRITE)
758 irq_mask = 0;
759 else
760 BUG();
Jason Robertsce082592010-05-13 15:57:33 +0100761
762 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
763
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800764 clear_interrupts(denali);
Jason Robertsce082592010-05-13 15:57:33 +0100765
766 addr = BANK(denali->flash_bank) | denali->page;
767
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800768 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800769 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800770 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800771 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
Jason Robertsce082592010-05-13 15:57:33 +0100772 /* read spare area */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800773 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900774 index_addr(denali, cmd, access_type);
Jason Robertsce082592010-05-13 15:57:33 +0100775
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800776 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800777 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800778 } else if (op == DENALI_READ) {
Jason Robertsce082592010-05-13 15:57:33 +0100779 /* setup page read request for access type */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800780 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900781 index_addr(denali, cmd, access_type);
Jason Robertsce082592010-05-13 15:57:33 +0100782
Masahiro Yamada43914a22014-09-09 11:01:51 +0900783 /*
784 * page 33 of the NAND controller spec indicates we should not
785 * use the pipeline commands in Spare area only mode.
786 * So we don't.
Jason Robertsce082592010-05-13 15:57:33 +0100787 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800788 if (access_type == SPARE_ACCESS) {
Jason Robertsce082592010-05-13 15:57:33 +0100789 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800790 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800791 } else {
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900792 index_addr(denali, cmd,
Masahiro Yamada29023302014-07-11 11:14:05 +0900793 PIPELINE_ACCESS | op | page_count);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800794
Masahiro Yamada43914a22014-09-09 11:01:51 +0900795 /*
796 * wait for command to be accepted
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800797 * can always use status0 bit as the
Masahiro Yamada43914a22014-09-09 11:01:51 +0900798 * mask is identical for each bank.
799 */
Jason Robertsce082592010-05-13 15:57:33 +0100800 irq_status = wait_for_irq(denali, irq_mask);
801
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800802 if (irq_status == 0) {
Jamie Iles84457942011-05-06 15:28:55 +0100803 dev_err(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900804 "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n",
805 cmd, denali->page, addr);
Jason Robertsce082592010-05-13 15:57:33 +0100806 status = FAIL;
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800807 } else {
Jason Robertsce082592010-05-13 15:57:33 +0100808 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800809 iowrite32(cmd, denali->flash_mem);
Jason Robertsce082592010-05-13 15:57:33 +0100810 }
811 }
812 }
813 return status;
814}
815
816/* helper function that simply writes a buffer to the flash */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800817static int write_data_to_flash_mem(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900818 const uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100819{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900820 uint32_t *buf32;
821 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100822
Masahiro Yamada43914a22014-09-09 11:01:51 +0900823 /*
824 * verify that the len is a multiple of 4.
825 * see comment in read_data_from_flash_mem()
826 */
Jason Robertsce082592010-05-13 15:57:33 +0100827 BUG_ON((len % 4) != 0);
828
829 /* write the data to the flash memory */
830 buf32 = (uint32_t *)buf;
831 for (i = 0; i < len / 4; i++)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800832 iowrite32(*buf32++, denali->flash_mem + 0x10);
Masahiro Yamada81254502014-09-16 20:04:25 +0900833 return i * 4; /* intent is to return the number of bytes read */
Jason Robertsce082592010-05-13 15:57:33 +0100834}
835
836/* helper function that simply reads a buffer from the flash */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800837static int read_data_from_flash_mem(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900838 uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100839{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900840 uint32_t *buf32;
841 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100842
Masahiro Yamada43914a22014-09-09 11:01:51 +0900843 /*
844 * we assume that len will be a multiple of 4, if not it would be nice
845 * to know about it ASAP rather than have random failures...
846 * This assumption is based on the fact that this function is designed
847 * to be used to read flash pages, which are typically multiples of 4.
Jason Robertsce082592010-05-13 15:57:33 +0100848 */
Jason Robertsce082592010-05-13 15:57:33 +0100849 BUG_ON((len % 4) != 0);
850
851 /* transfer the data from the flash */
852 buf32 = (uint32_t *)buf;
853 for (i = 0; i < len / 4; i++)
Jason Robertsce082592010-05-13 15:57:33 +0100854 *buf32++ = ioread32(denali->flash_mem + 0x10);
Masahiro Yamada81254502014-09-16 20:04:25 +0900855 return i * 4; /* intent is to return the number of bytes read */
Jason Robertsce082592010-05-13 15:57:33 +0100856}
857
858/* writes OOB data to the device */
859static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
860{
861 struct denali_nand_info *denali = mtd_to_denali(mtd);
Masahiro Yamada5637b692014-09-09 11:01:52 +0900862 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +0100863 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
864 INTR_STATUS__PROGRAM_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +0100865 int status = 0;
866
867 denali->page = page;
868
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800869 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800870 DENALI_WRITE) == PASS) {
Jason Robertsce082592010-05-13 15:57:33 +0100871 write_data_to_flash_mem(denali, buf, mtd->oobsize);
872
Jason Robertsce082592010-05-13 15:57:33 +0100873 /* wait for operation to complete */
874 irq_status = wait_for_irq(denali, irq_mask);
875
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800876 if (irq_status == 0) {
Jamie Iles84457942011-05-06 15:28:55 +0100877 dev_err(denali->dev, "OOB write failed\n");
Jason Robertsce082592010-05-13 15:57:33 +0100878 status = -EIO;
879 }
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800880 } else {
Jamie Iles84457942011-05-06 15:28:55 +0100881 dev_err(denali->dev, "unable to send pipeline command\n");
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800882 status = -EIO;
Jason Robertsce082592010-05-13 15:57:33 +0100883 }
884 return status;
885}
886
887/* reads OOB data from the device */
888static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
889{
890 struct denali_nand_info *denali = mtd_to_denali(mtd);
Masahiro Yamada5637b692014-09-09 11:01:52 +0900891 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
892 uint32_t irq_status, addr, cmd;
Jason Robertsce082592010-05-13 15:57:33 +0100893
894 denali->page = page;
895
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800896 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800897 DENALI_READ) == PASS) {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800898 read_data_from_flash_mem(denali, buf, mtd->oobsize);
Jason Robertsce082592010-05-13 15:57:33 +0100899
Masahiro Yamada43914a22014-09-09 11:01:51 +0900900 /*
901 * wait for command to be accepted
902 * can always use status0 bit as the
903 * mask is identical for each bank.
904 */
Jason Robertsce082592010-05-13 15:57:33 +0100905 irq_status = wait_for_irq(denali, irq_mask);
906
907 if (irq_status == 0)
Jamie Iles84457942011-05-06 15:28:55 +0100908 dev_err(denali->dev, "page on OOB timeout %d\n",
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800909 denali->page);
Jason Robertsce082592010-05-13 15:57:33 +0100910
Masahiro Yamada43914a22014-09-09 11:01:51 +0900911 /*
912 * We set the device back to MAIN_ACCESS here as I observed
Jason Robertsce082592010-05-13 15:57:33 +0100913 * instability with the controller if you do a block erase
914 * and the last transaction was a SPARE_ACCESS. Block erase
915 * is reliable (according to the MTD test infrastructure)
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800916 * if you are in MAIN_ACCESS.
Jason Robertsce082592010-05-13 15:57:33 +0100917 */
918 addr = BANK(denali->flash_bank) | denali->page;
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800919 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900920 index_addr(denali, cmd, MAIN_ACCESS);
Jason Robertsce082592010-05-13 15:57:33 +0100921 }
922}
923
Masahiro Yamada43914a22014-09-09 11:01:51 +0900924/*
925 * this function examines buffers to see if they contain data that
Jason Robertsce082592010-05-13 15:57:33 +0100926 * indicate that the buffer is part of an erased region of flash.
927 */
Rashika Kheria919193c2013-12-13 12:46:04 +0530928static bool is_erased(uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100929{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900930 int i;
Masahiro Yamada81254502014-09-16 20:04:25 +0900931
Jason Robertsce082592010-05-13 15:57:33 +0100932 for (i = 0; i < len; i++)
Jason Robertsce082592010-05-13 15:57:33 +0100933 if (buf[i] != 0xFF)
Jason Robertsce082592010-05-13 15:57:33 +0100934 return false;
Jason Robertsce082592010-05-13 15:57:33 +0100935 return true;
936}
937#define ECC_SECTOR_SIZE 512
938
939#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
940#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
941#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800942#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
943#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
Jason Robertsce082592010-05-13 15:57:33 +0100944#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
945
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800946static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
Mike Dunn3f91e942012-04-25 12:06:09 -0700947 uint32_t irq_status, unsigned int *max_bitflips)
Jason Robertsce082592010-05-13 15:57:33 +0100948{
949 bool check_erased_page = false;
Mike Dunn3f91e942012-04-25 12:06:09 -0700950 unsigned int bitflips = 0;
Jason Robertsce082592010-05-13 15:57:33 +0100951
Jamie Iles9589bf52011-05-06 15:28:56 +0100952 if (irq_status & INTR_STATUS__ECC_ERR) {
Jason Robertsce082592010-05-13 15:57:33 +0100953 /* read the ECC errors. we'll ignore them for now */
Masahiro Yamada5637b692014-09-09 11:01:52 +0900954 uint32_t err_address, err_correction_info, err_byte,
955 err_sector, err_device, err_correction_value;
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800956 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100957
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800958 do {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800959 err_address = ioread32(denali->flash_reg +
Jason Robertsce082592010-05-13 15:57:33 +0100960 ECC_ERROR_ADDRESS);
961 err_sector = ECC_SECTOR(err_address);
962 err_byte = ECC_BYTE(err_address);
963
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800964 err_correction_info = ioread32(denali->flash_reg +
Jason Robertsce082592010-05-13 15:57:33 +0100965 ERR_CORRECTION_INFO);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800966 err_correction_value =
Jason Robertsce082592010-05-13 15:57:33 +0100967 ECC_CORRECTION_VALUE(err_correction_info);
968 err_device = ECC_ERR_DEVICE(err_correction_info);
969
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800970 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900971 /*
972 * If err_byte is larger than ECC_SECTOR_SIZE,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300973 * means error happened in OOB, so we ignore
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800974 * it. It's no need for us to correct it
975 * err_device is represented the NAND error
976 * bits are happened in if there are more
977 * than one NAND connected.
Masahiro Yamada43914a22014-09-09 11:01:51 +0900978 */
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800979 if (err_byte < ECC_SECTOR_SIZE) {
980 int offset;
Masahiro Yamada81254502014-09-16 20:04:25 +0900981
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800982 offset = (err_sector *
983 ECC_SECTOR_SIZE +
984 err_byte) *
985 denali->devnum +
986 err_device;
Jason Robertsce082592010-05-13 15:57:33 +0100987 /* correct the ECC error */
988 buf[offset] ^= err_correction_value;
989 denali->mtd.ecc_stats.corrected++;
Mike Dunn3f91e942012-04-25 12:06:09 -0700990 bitflips++;
Jason Robertsce082592010-05-13 15:57:33 +0100991 }
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800992 } else {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900993 /*
994 * if the error is not correctable, need to
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800995 * look at the page to see if it is an erased
996 * page. if so, then it's not a real ECC error
Masahiro Yamada43914a22014-09-09 11:01:51 +0900997 */
Jason Robertsce082592010-05-13 15:57:33 +0100998 check_erased_page = true;
999 }
Jason Robertsce082592010-05-13 15:57:33 +01001000 } while (!ECC_LAST_ERR(err_correction_info));
Masahiro Yamada43914a22014-09-09 11:01:51 +09001001 /*
1002 * Once handle all ecc errors, controller will triger
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +08001003 * a ECC_TRANSACTION_DONE interrupt, so here just wait
1004 * for a while for this interrupt
Masahiro Yamada43914a22014-09-09 11:01:51 +09001005 */
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +08001006 while (!(read_interrupt_status(denali) &
Jamie Iles9589bf52011-05-06 15:28:56 +01001007 INTR_STATUS__ECC_TRANSACTION_DONE))
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +08001008 cpu_relax();
1009 clear_interrupts(denali);
1010 denali_set_intr_modes(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001011 }
Mike Dunn3f91e942012-04-25 12:06:09 -07001012 *max_bitflips = bitflips;
Jason Robertsce082592010-05-13 15:57:33 +01001013 return check_erased_page;
1014}
1015
1016/* programs the controller to either enable/disable DMA transfers */
David Woodhouseaadff492010-05-13 16:12:43 +01001017static void denali_enable_dma(struct denali_nand_info *denali, bool en)
Jason Robertsce082592010-05-13 15:57:33 +01001018{
Masahiro Yamada5637b692014-09-09 11:01:52 +09001019 iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +01001020 ioread32(denali->flash_reg + DMA_ENABLE);
1021}
1022
1023/* setups the HW to perform the data DMA */
David Woodhouseaadff492010-05-13 16:12:43 +01001024static void denali_setup_dma(struct denali_nand_info *denali, int op)
Jason Robertsce082592010-05-13 15:57:33 +01001025{
Masahiro Yamada5637b692014-09-09 11:01:52 +09001026 uint32_t mode;
Jason Robertsce082592010-05-13 15:57:33 +01001027 const int page_count = 1;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001028 uint32_t addr = denali->buf.dma_buf;
Jason Robertsce082592010-05-13 15:57:33 +01001029
1030 mode = MODE_10 | BANK(denali->flash_bank);
1031
1032 /* DMA is a four step process */
1033
1034 /* 1. setup transfer type and # of pages */
1035 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1036
1037 /* 2. set memory high address bits 23:8 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001038 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
Jason Robertsce082592010-05-13 15:57:33 +01001039
1040 /* 3. set memory low address bits 23:8 */
Graham Moore7c272ac2015-01-09 09:32:35 -06001041 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
Jason Robertsce082592010-05-13 15:57:33 +01001042
Masahiro Yamada43914a22014-09-09 11:01:51 +09001043 /* 4. interrupt when complete, burst len = 64 bytes */
Jason Robertsce082592010-05-13 15:57:33 +01001044 index_addr(denali, mode | 0x14000, 0x2400);
1045}
1046
Masahiro Yamada43914a22014-09-09 11:01:51 +09001047/*
1048 * writes a page. user specifies type, and this function handles the
1049 * configuration details.
1050 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001051static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001052 const uint8_t *buf, bool raw_xfer)
1053{
1054 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001055 dma_addr_t addr = denali->buf.dma_buf;
1056 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
Masahiro Yamada5637b692014-09-09 11:01:52 +09001057 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +01001058 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1059 INTR_STATUS__PROGRAM_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +01001060
Masahiro Yamada43914a22014-09-09 11:01:51 +09001061 /*
1062 * if it is a raw xfer, we want to disable ecc and send the spare area.
Jason Robertsce082592010-05-13 15:57:33 +01001063 * !raw_xfer - enable ecc
1064 * raw_xfer - transfer spare
1065 */
1066 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1067
1068 /* copy buffer into DMA buffer */
1069 memcpy(denali->buf.buf, buf, mtd->writesize);
1070
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001071 if (raw_xfer) {
Jason Robertsce082592010-05-13 15:57:33 +01001072 /* transfer the data to the spare area */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001073 memcpy(denali->buf.buf + mtd->writesize,
1074 chip->oob_poi,
1075 mtd->oobsize);
Jason Robertsce082592010-05-13 15:57:33 +01001076 }
1077
Jamie Iles84457942011-05-06 15:28:55 +01001078 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001079
1080 clear_interrupts(denali);
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001081 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001082
David Woodhouseaadff492010-05-13 16:12:43 +01001083 denali_setup_dma(denali, DENALI_WRITE);
Jason Robertsce082592010-05-13 15:57:33 +01001084
1085 /* wait for operation to complete */
1086 irq_status = wait_for_irq(denali, irq_mask);
1087
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001088 if (irq_status == 0) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001089 dev_err(denali->dev, "timeout on write_page (type = %d)\n",
1090 raw_xfer);
Brian Norrisc115add2014-07-21 19:07:31 -07001091 denali->status = NAND_STATUS_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +01001092 }
1093
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001094 denali_enable_dma(denali, false);
Jamie Iles84457942011-05-06 15:28:55 +01001095 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
Josh Wufdbad98d2012-06-25 18:07:45 +08001096
1097 return 0;
Jason Robertsce082592010-05-13 15:57:33 +01001098}
1099
1100/* NAND core entry points */
1101
Masahiro Yamada43914a22014-09-09 11:01:51 +09001102/*
1103 * this is the callback that the NAND core calls to write a page. Since
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001104 * writing a page with ECC or without is similar, all the work is done
1105 * by write_page above.
Masahiro Yamada43914a22014-09-09 11:01:51 +09001106 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001107static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -07001108 const uint8_t *buf, int oob_required)
Jason Robertsce082592010-05-13 15:57:33 +01001109{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001110 /*
1111 * for regular page writes, we let HW handle all the ECC
1112 * data written to the device.
1113 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001114 return write_page(mtd, chip, buf, false);
Jason Robertsce082592010-05-13 15:57:33 +01001115}
1116
Masahiro Yamada43914a22014-09-09 11:01:51 +09001117/*
1118 * This is the callback that the NAND core calls to write a page without ECC.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001119 * raw access is similar to ECC page writes, so all the work is done in the
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001120 * write_page() function above.
Jason Robertsce082592010-05-13 15:57:33 +01001121 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001122static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -07001123 const uint8_t *buf, int oob_required)
Jason Robertsce082592010-05-13 15:57:33 +01001124{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001125 /*
1126 * for raw page writes, we want to disable ECC and simply write
1127 * whatever data is in the buffer.
1128 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001129 return write_page(mtd, chip, buf, true);
Jason Robertsce082592010-05-13 15:57:33 +01001130}
1131
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001132static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001133 int page)
1134{
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001135 return write_oob_data(mtd, chip->oob_poi, page);
Jason Robertsce082592010-05-13 15:57:33 +01001136}
1137
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001138static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
Shmulik Ladkani5c2ffb12012-05-09 13:06:35 +03001139 int page)
Jason Robertsce082592010-05-13 15:57:33 +01001140{
1141 read_oob_data(mtd, chip->oob_poi, page);
1142
Shmulik Ladkani5c2ffb12012-05-09 13:06:35 +03001143 return 0;
Jason Robertsce082592010-05-13 15:57:33 +01001144}
1145
1146static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -07001147 uint8_t *buf, int oob_required, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001148{
Mike Dunn3f91e942012-04-25 12:06:09 -07001149 unsigned int max_bitflips;
Jason Robertsce082592010-05-13 15:57:33 +01001150 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001151
1152 dma_addr_t addr = denali->buf.dma_buf;
1153 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1154
Masahiro Yamada5637b692014-09-09 11:01:52 +09001155 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +01001156 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1157 INTR_STATUS__ECC_ERR;
Jason Robertsce082592010-05-13 15:57:33 +01001158 bool check_erased_page = false;
1159
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001160 if (page != denali->page) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001161 dev_err(denali->dev,
1162 "IN %s: page %d is not equal to denali->page %d",
1163 __func__, page, denali->page);
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001164 BUG();
1165 }
1166
Jason Robertsce082592010-05-13 15:57:33 +01001167 setup_ecc_for_xfer(denali, true, false);
1168
David Woodhouseaadff492010-05-13 16:12:43 +01001169 denali_enable_dma(denali, true);
Jamie Iles84457942011-05-06 15:28:55 +01001170 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001171
1172 clear_interrupts(denali);
David Woodhouseaadff492010-05-13 16:12:43 +01001173 denali_setup_dma(denali, DENALI_READ);
Jason Robertsce082592010-05-13 15:57:33 +01001174
1175 /* wait for operation to complete */
1176 irq_status = wait_for_irq(denali, irq_mask);
1177
Jamie Iles84457942011-05-06 15:28:55 +01001178 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001179
1180 memcpy(buf, denali->buf.buf, mtd->writesize);
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001181
Mike Dunn3f91e942012-04-25 12:06:09 -07001182 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
David Woodhouseaadff492010-05-13 16:12:43 +01001183 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001184
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001185 if (check_erased_page) {
Jason Robertsce082592010-05-13 15:57:33 +01001186 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1187
1188 /* check ECC failures that may have occurred on erased pages */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001189 if (check_erased_page) {
Jason Robertsce082592010-05-13 15:57:33 +01001190 if (!is_erased(buf, denali->mtd.writesize))
Jason Robertsce082592010-05-13 15:57:33 +01001191 denali->mtd.ecc_stats.failed++;
Jason Robertsce082592010-05-13 15:57:33 +01001192 if (!is_erased(buf, denali->mtd.oobsize))
Jason Robertsce082592010-05-13 15:57:33 +01001193 denali->mtd.ecc_stats.failed++;
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001194 }
Jason Robertsce082592010-05-13 15:57:33 +01001195 }
Mike Dunn3f91e942012-04-25 12:06:09 -07001196 return max_bitflips;
Jason Robertsce082592010-05-13 15:57:33 +01001197}
1198
1199static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -07001200 uint8_t *buf, int oob_required, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001201{
1202 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001203 dma_addr_t addr = denali->buf.dma_buf;
1204 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
Jamie Iles9589bf52011-05-06 15:28:56 +01001205 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001206
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001207 if (page != denali->page) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001208 dev_err(denali->dev,
1209 "IN %s: page %d is not equal to denali->page %d",
1210 __func__, page, denali->page);
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001211 BUG();
1212 }
1213
Jason Robertsce082592010-05-13 15:57:33 +01001214 setup_ecc_for_xfer(denali, false, true);
David Woodhouseaadff492010-05-13 16:12:43 +01001215 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001216
Jamie Iles84457942011-05-06 15:28:55 +01001217 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001218
1219 clear_interrupts(denali);
David Woodhouseaadff492010-05-13 16:12:43 +01001220 denali_setup_dma(denali, DENALI_READ);
Jason Robertsce082592010-05-13 15:57:33 +01001221
1222 /* wait for operation to complete */
Brian Norrisba5f2bc2014-09-19 09:37:19 -07001223 wait_for_irq(denali, irq_mask);
Jason Robertsce082592010-05-13 15:57:33 +01001224
Jamie Iles84457942011-05-06 15:28:55 +01001225 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001226
David Woodhouseaadff492010-05-13 16:12:43 +01001227 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001228
1229 memcpy(buf, denali->buf.buf, mtd->writesize);
1230 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1231
1232 return 0;
1233}
1234
1235static uint8_t denali_read_byte(struct mtd_info *mtd)
1236{
1237 struct denali_nand_info *denali = mtd_to_denali(mtd);
1238 uint8_t result = 0xff;
1239
1240 if (denali->buf.head < denali->buf.tail)
Jason Robertsce082592010-05-13 15:57:33 +01001241 result = denali->buf.buf[denali->buf.head++];
Jason Robertsce082592010-05-13 15:57:33 +01001242
Jason Robertsce082592010-05-13 15:57:33 +01001243 return result;
1244}
1245
1246static void denali_select_chip(struct mtd_info *mtd, int chip)
1247{
1248 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001249
Jason Robertsce082592010-05-13 15:57:33 +01001250 spin_lock_irq(&denali->irq_lock);
1251 denali->flash_bank = chip;
1252 spin_unlock_irq(&denali->irq_lock);
1253}
1254
1255static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1256{
1257 struct denali_nand_info *denali = mtd_to_denali(mtd);
1258 int status = denali->status;
Masahiro Yamada81254502014-09-16 20:04:25 +09001259
Jason Robertsce082592010-05-13 15:57:33 +01001260 denali->status = 0;
1261
Jason Robertsce082592010-05-13 15:57:33 +01001262 return status;
1263}
1264
Brian Norris49c50b92014-05-06 16:02:19 -07001265static int denali_erase(struct mtd_info *mtd, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001266{
1267 struct denali_nand_info *denali = mtd_to_denali(mtd);
1268
Masahiro Yamada5637b692014-09-09 11:01:52 +09001269 uint32_t cmd, irq_status;
Jason Robertsce082592010-05-13 15:57:33 +01001270
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001271 clear_interrupts(denali);
Jason Robertsce082592010-05-13 15:57:33 +01001272
1273 /* setup page read request for access type */
1274 cmd = MODE_10 | BANK(denali->flash_bank) | page;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001275 index_addr(denali, cmd, 0x1);
Jason Robertsce082592010-05-13 15:57:33 +01001276
1277 /* wait for erase to complete or failure to occur */
Jamie Iles9589bf52011-05-06 15:28:56 +01001278 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1279 INTR_STATUS__ERASE_FAIL);
Jason Robertsce082592010-05-13 15:57:33 +01001280
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +09001281 return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS;
Jason Robertsce082592010-05-13 15:57:33 +01001282}
1283
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001284static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
Jason Robertsce082592010-05-13 15:57:33 +01001285 int page)
1286{
1287 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001288 uint32_t addr, id;
1289 int i;
Jason Robertsce082592010-05-13 15:57:33 +01001290
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001291 switch (cmd) {
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001292 case NAND_CMD_PAGEPROG:
1293 break;
1294 case NAND_CMD_STATUS:
1295 read_status(denali);
1296 break;
1297 case NAND_CMD_READID:
Florian Fainelli42af8b52010-08-30 18:32:20 +02001298 case NAND_CMD_PARAM:
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001299 reset_buf(denali);
Masahiro Yamada43914a22014-09-09 11:01:51 +09001300 /*
1301 * sometimes ManufactureId read from register is not right
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001302 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1303 * So here we send READID cmd to NAND insteand
Masahiro Yamada43914a22014-09-09 11:01:51 +09001304 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001305 addr = MODE_11 | BANK(denali->flash_bank);
1306 index_addr(denali, addr | 0, 0x90);
1307 index_addr(denali, addr | 1, 0);
grmoore@altera.comd68a5c32014-06-23 14:21:10 -05001308 for (i = 0; i < 8; i++) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001309 index_addr_read_data(denali, addr | 2, &id);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001310 write_byte_to_buf(denali, id);
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001311 }
1312 break;
1313 case NAND_CMD_READ0:
1314 case NAND_CMD_SEQIN:
1315 denali->page = page;
1316 break;
1317 case NAND_CMD_RESET:
1318 reset_bank(denali);
1319 break;
1320 case NAND_CMD_READOOB:
1321 /* TODO: Read OOB data */
1322 break;
1323 default:
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001324 pr_err(": unsupported command received 0x%x\n", cmd);
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001325 break;
Jason Robertsce082592010-05-13 15:57:33 +01001326 }
1327}
Jason Robertsce082592010-05-13 15:57:33 +01001328/* end NAND core entry points */
1329
1330/* Initialization code to bring the device up to a known good state */
1331static void denali_hw_init(struct denali_nand_info *denali)
1332{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001333 /*
1334 * tell driver how many bit controller will skip before
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001335 * writing ECC code in OOB, this register may be already
1336 * set by firmware. So we read this value out.
1337 * if this value is 0, just let it be.
Masahiro Yamada43914a22014-09-09 11:01:51 +09001338 */
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001339 denali->bbtskipbytes = ioread32(denali->flash_reg +
1340 SPARE_AREA_SKIP_BYTES);
Jamie Ilesbc27ede2011-06-06 17:11:34 +01001341 detect_max_banks(denali);
Chuanxiao Dongeda936e2010-07-27 14:17:37 +08001342 denali_nand_reset(denali);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001343 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1344 iowrite32(CHIP_EN_DONT_CARE__FLAG,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001345 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
Jason Robertsce082592010-05-13 15:57:33 +01001346
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001347 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
Jason Robertsce082592010-05-13 15:57:33 +01001348
1349 /* Should set value for these registers when init */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001350 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1351 iowrite32(1, denali->flash_reg + ECC_ENABLE);
Chuanxiao Dong5eab6aaa2010-08-12 10:07:18 +08001352 denali_nand_timing_set(denali);
1353 denali_irq_init(denali);
Jason Robertsce082592010-05-13 15:57:33 +01001354}
1355
Masahiro Yamada43914a22014-09-09 11:01:51 +09001356/*
1357 * Althogh controller spec said SLC ECC is forceb to be 4bit,
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001358 * but denali controller in MRST only support 15bit and 8bit ECC
1359 * correction
Masahiro Yamada43914a22014-09-09 11:01:51 +09001360 */
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001361#define ECC_8BITS 14
1362static struct nand_ecclayout nand_8bit_oob = {
1363 .eccbytes = 14,
Jason Robertsce082592010-05-13 15:57:33 +01001364};
1365
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001366#define ECC_15BITS 26
1367static struct nand_ecclayout nand_15bit_oob = {
1368 .eccbytes = 26,
Jason Robertsce082592010-05-13 15:57:33 +01001369};
1370
1371static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1372static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1373
1374static struct nand_bbt_descr bbt_main_descr = {
1375 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1376 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1377 .offs = 8,
1378 .len = 4,
1379 .veroffs = 12,
1380 .maxblocks = 4,
1381 .pattern = bbt_pattern,
1382};
1383
1384static struct nand_bbt_descr bbt_mirror_descr = {
1385 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1386 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1387 .offs = 8,
1388 .len = 4,
1389 .veroffs = 12,
1390 .maxblocks = 4,
1391 .pattern = mirror_pattern,
1392};
1393
Uwe Kleine-König421f91d2010-06-11 12:17:00 +02001394/* initialize driver data structures */
Brian Norris8c519432013-08-10 22:57:30 -07001395static void denali_drv_init(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001396{
1397 denali->idx = 0;
1398
1399 /* setup interrupt handler */
Masahiro Yamada43914a22014-09-09 11:01:51 +09001400 /*
1401 * the completion object will be used to notify
1402 * the callee that the interrupt is done
1403 */
Jason Robertsce082592010-05-13 15:57:33 +01001404 init_completion(&denali->complete);
1405
Masahiro Yamada43914a22014-09-09 11:01:51 +09001406 /*
1407 * the spinlock will be used to synchronize the ISR with any
1408 * element that might be access shared data (interrupt status)
1409 */
Jason Robertsce082592010-05-13 15:57:33 +01001410 spin_lock_init(&denali->irq_lock);
1411
1412 /* indicate that MTD has not selected a valid bank yet */
1413 denali->flash_bank = CHIP_SELECT_INVALID;
1414
1415 /* initialize our irq_status variable to indicate no interrupts */
1416 denali->irq_status = 0;
1417}
1418
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001419int denali_init(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001420{
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001421 int ret;
Jason Robertsce082592010-05-13 15:57:33 +01001422
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001423 if (denali->platform == INTEL_CE4100) {
Masahiro Yamada43914a22014-09-09 11:01:51 +09001424 /*
1425 * Due to a silicon limitation, we can only support
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001426 * ONFI timing mode 1 and below.
1427 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001428 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001429 pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1430 return -EINVAL;
Jason Robertsce082592010-05-13 15:57:33 +01001431 }
1432 }
1433
Huang Shijiee07caa32013-12-21 00:02:28 +08001434 /* allocate a temporary buffer for nand_scan_ident() */
1435 denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
1436 GFP_DMA | GFP_KERNEL);
1437 if (!denali->buf.buf)
1438 return -ENOMEM;
Jason Robertsce082592010-05-13 15:57:33 +01001439
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001440 denali->mtd.dev.parent = denali->dev;
Jason Robertsce082592010-05-13 15:57:33 +01001441 denali_hw_init(denali);
1442 denali_drv_init(denali);
1443
Masahiro Yamada43914a22014-09-09 11:01:51 +09001444 /*
1445 * denali_isr register is done after all the hardware
1446 * initilization is finished
1447 */
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001448 if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
Jason Robertsce082592010-05-13 15:57:33 +01001449 DENALI_NAND_NAME, denali)) {
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001450 pr_err("Spectra: Unable to allocate IRQ\n");
1451 return -ENODEV;
Jason Robertsce082592010-05-13 15:57:33 +01001452 }
1453
1454 /* now that our ISR is registered, we can enable interrupts */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +08001455 denali_set_intr_modes(denali, true);
Chuanxiao Dong5eab6aaa2010-08-12 10:07:18 +08001456 denali->mtd.name = "denali-nand";
Jason Robertsce082592010-05-13 15:57:33 +01001457 denali->mtd.owner = THIS_MODULE;
1458 denali->mtd.priv = &denali->nand;
1459
1460 /* register the driver with the NAND core subsystem */
1461 denali->nand.select_chip = denali_select_chip;
1462 denali->nand.cmdfunc = denali_cmdfunc;
1463 denali->nand.read_byte = denali_read_byte;
1464 denali->nand.waitfunc = denali_waitfunc;
1465
Masahiro Yamada43914a22014-09-09 11:01:51 +09001466 /*
1467 * scan for NAND devices attached to the controller
Jason Robertsce082592010-05-13 15:57:33 +01001468 * this is the first stage in a two step process to register
Masahiro Yamada43914a22014-09-09 11:01:51 +09001469 * with the nand subsystem
1470 */
Jamie Ilesc89eeda2011-05-06 15:28:57 +01001471 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
Jason Robertsce082592010-05-13 15:57:33 +01001472 ret = -ENXIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001473 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001474 }
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001475
Huang Shijiee07caa32013-12-21 00:02:28 +08001476 /* allocate the right size buffer now */
1477 devm_kfree(denali->dev, denali->buf.buf);
1478 denali->buf.buf = devm_kzalloc(denali->dev,
1479 denali->mtd.writesize + denali->mtd.oobsize,
1480 GFP_KERNEL);
1481 if (!denali->buf.buf) {
1482 ret = -ENOMEM;
1483 goto failed_req_irq;
1484 }
1485
1486 /* Is 32-bit DMA supported? */
1487 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1488 if (ret) {
1489 pr_err("Spectra: no usable DMA configuration\n");
1490 goto failed_req_irq;
1491 }
1492
1493 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
1494 denali->mtd.writesize + denali->mtd.oobsize,
1495 DMA_BIDIRECTIONAL);
1496 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
1497 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
1498 ret = -EIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001499 goto failed_req_irq;
Chuanxiao.Dong66406522010-08-06 18:48:21 +08001500 }
1501
Masahiro Yamada43914a22014-09-09 11:01:51 +09001502 /*
1503 * support for multi nand
1504 * MTD known nothing about multi nand, so we should tell it
1505 * the real pagesize and anything necessery
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001506 */
1507 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1508 denali->nand.chipsize <<= (denali->devnum - 1);
1509 denali->nand.page_shift += (denali->devnum - 1);
1510 denali->nand.pagemask = (denali->nand.chipsize >>
1511 denali->nand.page_shift) - 1;
1512 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1513 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1514 denali->nand.chip_shift += (denali->devnum - 1);
1515 denali->mtd.writesize <<= (denali->devnum - 1);
1516 denali->mtd.oobsize <<= (denali->devnum - 1);
1517 denali->mtd.erasesize <<= (denali->devnum - 1);
1518 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1519 denali->bbtskipbytes *= denali->devnum;
1520
Masahiro Yamada43914a22014-09-09 11:01:51 +09001521 /*
1522 * second stage of the NAND scan
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001523 * this stage requires information regarding ECC and
Masahiro Yamada43914a22014-09-09 11:01:51 +09001524 * bad block management.
1525 */
Jason Robertsce082592010-05-13 15:57:33 +01001526
1527 /* Bad block management */
1528 denali->nand.bbt_td = &bbt_main_descr;
1529 denali->nand.bbt_md = &bbt_mirror_descr;
1530
1531 /* skip the scan for now until we have OOB read and write support */
Brian Norrisbb9ebd42011-05-31 16:31:23 -07001532 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
Brian Norrisa40f7342011-05-31 16:31:22 -07001533 denali->nand.options |= NAND_SKIP_BBTSCAN;
Jason Robertsce082592010-05-13 15:57:33 +01001534 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1535
Graham Moored99d7282015-01-14 09:38:50 -06001536 /* no subpage writes on denali */
1537 denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1538
Masahiro Yamada43914a22014-09-09 11:01:51 +09001539 /*
1540 * Denali Controller only support 15bit and 8bit ECC in MRST,
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001541 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1542 * SLC if possible.
1543 * */
Huang Shijie1d0ed692013-09-25 14:58:10 +08001544 if (!nand_is_slc(&denali->nand) &&
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001545 (denali->mtd.oobsize > (denali->bbtskipbytes +
1546 ECC_15BITS * (denali->mtd.writesize /
1547 ECC_SECTOR_SIZE)))) {
1548 /* if MLC OOB size is large enough, use 15bit ECC*/
Mike Dunn6a918ba2012-03-11 14:21:11 -07001549 denali->nand.ecc.strength = 15;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001550 denali->nand.ecc.layout = &nand_15bit_oob;
1551 denali->nand.ecc.bytes = ECC_15BITS;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001552 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001553 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1554 ECC_8BITS * (denali->mtd.writesize /
1555 ECC_SECTOR_SIZE))) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001556 pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001557 goto failed_req_irq;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001558 } else {
Mike Dunn6a918ba2012-03-11 14:21:11 -07001559 denali->nand.ecc.strength = 8;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001560 denali->nand.ecc.layout = &nand_8bit_oob;
1561 denali->nand.ecc.bytes = ECC_8BITS;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001562 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +01001563 }
1564
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001565 denali->nand.ecc.bytes *= denali->devnum;
Mike Dunn6a918ba2012-03-11 14:21:11 -07001566 denali->nand.ecc.strength *= denali->devnum;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001567 denali->nand.ecc.layout->eccbytes *=
1568 denali->mtd.writesize / ECC_SECTOR_SIZE;
1569 denali->nand.ecc.layout->oobfree[0].offset =
1570 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1571 denali->nand.ecc.layout->oobfree[0].length =
1572 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1573 denali->bbtskipbytes;
1574
Masahiro Yamada43914a22014-09-09 11:01:51 +09001575 /*
1576 * Let driver know the total blocks number and how many blocks
1577 * contained by each nand chip. blksperchip will help driver to
1578 * know how many blocks is taken by FW.
1579 */
Masahiro Yamada81254502014-09-16 20:04:25 +09001580 denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift;
Chuanxiao.Dong66406522010-08-06 18:48:21 +08001581 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1582
Jason Robertsce082592010-05-13 15:57:33 +01001583 /* override the default read operations */
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001584 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
Jason Robertsce082592010-05-13 15:57:33 +01001585 denali->nand.ecc.read_page = denali_read_page;
1586 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1587 denali->nand.ecc.write_page = denali_write_page;
1588 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1589 denali->nand.ecc.read_oob = denali_read_oob;
1590 denali->nand.ecc.write_oob = denali_write_oob;
Brian Norris49c50b92014-05-06 16:02:19 -07001591 denali->nand.erase = denali_erase;
Jason Robertsce082592010-05-13 15:57:33 +01001592
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001593 if (nand_scan_tail(&denali->mtd)) {
Jason Robertsce082592010-05-13 15:57:33 +01001594 ret = -ENXIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001595 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001596 }
1597
Jamie Ilesee0e87b2011-05-23 10:23:40 +01001598 ret = mtd_device_register(&denali->mtd, NULL, 0);
Jason Robertsce082592010-05-13 15:57:33 +01001599 if (ret) {
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001600 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n",
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001601 ret);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001602 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001603 }
1604 return 0;
1605
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001606failed_req_irq:
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001607 denali_irq_cleanup(denali->irq, denali);
1608
Jason Robertsce082592010-05-13 15:57:33 +01001609 return ret;
1610}
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001611EXPORT_SYMBOL(denali_init);
Jason Robertsce082592010-05-13 15:57:33 +01001612
1613/* driver exit point */
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001614void denali_remove(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001615{
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001616 denali_irq_cleanup(denali->irq, denali);
Huang Shijiee07caa32013-12-21 00:02:28 +08001617 dma_unmap_single(denali->dev, denali->buf.dma_buf,
Masahiro Yamada81254502014-09-16 20:04:25 +09001618 denali->mtd.writesize + denali->mtd.oobsize,
1619 DMA_BIDIRECTIONAL);
Jason Robertsce082592010-05-13 15:57:33 +01001620}
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001621EXPORT_SYMBOL(denali_remove);