Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Allwinner A1X SoCs pinctrl driver. |
| 3 | * |
| 4 | * Copyright (C) 2012 Maxime Ripard |
| 5 | * |
| 6 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/io.h> |
Emilio López | 950707c | 2013-03-22 11:20:40 -0300 | [diff] [blame] | 14 | #include <linux/clk.h> |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 15 | #include <linux/gpio.h> |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 16 | #include <linux/irqdomain.h> |
Chen-Yu Tsai | 905a511 | 2014-02-11 00:22:37 +0800 | [diff] [blame] | 17 | #include <linux/irqchip/chained_irq.h> |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> |
| 21 | #include <linux/of_device.h> |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 22 | #include <linux/of_irq.h> |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 23 | #include <linux/pinctrl/consumer.h> |
| 24 | #include <linux/pinctrl/machine.h> |
| 25 | #include <linux/pinctrl/pinctrl.h> |
| 26 | #include <linux/pinctrl/pinconf-generic.h> |
| 27 | #include <linux/pinctrl/pinmux.h> |
| 28 | #include <linux/platform_device.h> |
Boris BREZILLON | cf2908e | 2014-04-10 15:52:45 +0200 | [diff] [blame] | 29 | #include <linux/reset.h> |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 30 | #include <linux/slab.h> |
| 31 | |
Maxime Ripard | 5f91077 | 2014-04-18 18:53:02 +0200 | [diff] [blame] | 32 | #include "../core.h" |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 33 | #include "pinctrl-sunxi.h" |
Maxime Ripard | eaa3d84 | 2013-01-18 22:30:35 +0100 | [diff] [blame] | 34 | |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 35 | static struct sunxi_pinctrl_group * |
| 36 | sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) |
| 37 | { |
| 38 | int i; |
| 39 | |
| 40 | for (i = 0; i < pctl->ngroups; i++) { |
| 41 | struct sunxi_pinctrl_group *grp = pctl->groups + i; |
| 42 | |
| 43 | if (!strcmp(grp->name, group)) |
| 44 | return grp; |
| 45 | } |
| 46 | |
| 47 | return NULL; |
| 48 | } |
| 49 | |
| 50 | static struct sunxi_pinctrl_function * |
| 51 | sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, |
| 52 | const char *name) |
| 53 | { |
| 54 | struct sunxi_pinctrl_function *func = pctl->functions; |
| 55 | int i; |
| 56 | |
| 57 | for (i = 0; i < pctl->nfunctions; i++) { |
| 58 | if (!func[i].name) |
| 59 | break; |
| 60 | |
| 61 | if (!strcmp(func[i].name, name)) |
| 62 | return func + i; |
| 63 | } |
| 64 | |
| 65 | return NULL; |
| 66 | } |
| 67 | |
| 68 | static struct sunxi_desc_function * |
| 69 | sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, |
| 70 | const char *pin_name, |
| 71 | const char *func_name) |
| 72 | { |
| 73 | int i; |
| 74 | |
| 75 | for (i = 0; i < pctl->desc->npins; i++) { |
| 76 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; |
| 77 | |
| 78 | if (!strcmp(pin->pin.name, pin_name)) { |
| 79 | struct sunxi_desc_function *func = pin->functions; |
| 80 | |
| 81 | while (func->name) { |
| 82 | if (!strcmp(func->name, func_name)) |
| 83 | return func; |
| 84 | |
| 85 | func++; |
| 86 | } |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | return NULL; |
| 91 | } |
| 92 | |
Maxime Ripard | 814d4f2 | 2013-06-08 12:05:43 +0200 | [diff] [blame] | 93 | static struct sunxi_desc_function * |
| 94 | sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, |
| 95 | const u16 pin_num, |
| 96 | const char *func_name) |
| 97 | { |
| 98 | int i; |
| 99 | |
| 100 | for (i = 0; i < pctl->desc->npins; i++) { |
| 101 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; |
| 102 | |
| 103 | if (pin->pin.number == pin_num) { |
| 104 | struct sunxi_desc_function *func = pin->functions; |
| 105 | |
| 106 | while (func->name) { |
| 107 | if (!strcmp(func->name, func_name)) |
| 108 | return func; |
| 109 | |
| 110 | func++; |
| 111 | } |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | return NULL; |
| 116 | } |
| 117 | |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 118 | static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) |
| 119 | { |
| 120 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 121 | |
| 122 | return pctl->ngroups; |
| 123 | } |
| 124 | |
| 125 | static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, |
| 126 | unsigned group) |
| 127 | { |
| 128 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 129 | |
| 130 | return pctl->groups[group].name; |
| 131 | } |
| 132 | |
| 133 | static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, |
| 134 | unsigned group, |
| 135 | const unsigned **pins, |
| 136 | unsigned *num_pins) |
| 137 | { |
| 138 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 139 | |
| 140 | *pins = (unsigned *)&pctl->groups[group].pin; |
| 141 | *num_pins = 1; |
| 142 | |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
| 147 | struct device_node *node, |
| 148 | struct pinctrl_map **map, |
| 149 | unsigned *num_maps) |
| 150 | { |
| 151 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 152 | unsigned long *pinconfig; |
| 153 | struct property *prop; |
| 154 | const char *function; |
| 155 | const char *group; |
| 156 | int ret, nmaps, i = 0; |
| 157 | u32 val; |
| 158 | |
| 159 | *map = NULL; |
| 160 | *num_maps = 0; |
| 161 | |
| 162 | ret = of_property_read_string(node, "allwinner,function", &function); |
| 163 | if (ret) { |
| 164 | dev_err(pctl->dev, |
| 165 | "missing allwinner,function property in node %s\n", |
| 166 | node->name); |
| 167 | return -EINVAL; |
| 168 | } |
| 169 | |
| 170 | nmaps = of_property_count_strings(node, "allwinner,pins") * 2; |
| 171 | if (nmaps < 0) { |
| 172 | dev_err(pctl->dev, |
| 173 | "missing allwinner,pins property in node %s\n", |
| 174 | node->name); |
| 175 | return -EINVAL; |
| 176 | } |
| 177 | |
| 178 | *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); |
Sachin Kamat | 3efa921 | 2013-07-29 13:49:32 +0530 | [diff] [blame] | 179 | if (!*map) |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 180 | return -ENOMEM; |
| 181 | |
| 182 | of_property_for_each_string(node, "allwinner,pins", prop, group) { |
| 183 | struct sunxi_pinctrl_group *grp = |
| 184 | sunxi_pinctrl_find_group_by_name(pctl, group); |
| 185 | int j = 0, configlen = 0; |
| 186 | |
| 187 | if (!grp) { |
| 188 | dev_err(pctl->dev, "unknown pin %s", group); |
| 189 | continue; |
| 190 | } |
| 191 | |
| 192 | if (!sunxi_pinctrl_desc_find_function_by_name(pctl, |
| 193 | grp->name, |
| 194 | function)) { |
| 195 | dev_err(pctl->dev, "unsupported function %s on pin %s", |
| 196 | function, group); |
| 197 | continue; |
| 198 | } |
| 199 | |
| 200 | (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; |
| 201 | (*map)[i].data.mux.group = group; |
| 202 | (*map)[i].data.mux.function = function; |
| 203 | |
| 204 | i++; |
| 205 | |
| 206 | (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; |
| 207 | (*map)[i].data.configs.group_or_pin = group; |
| 208 | |
| 209 | if (of_find_property(node, "allwinner,drive", NULL)) |
| 210 | configlen++; |
| 211 | if (of_find_property(node, "allwinner,pull", NULL)) |
| 212 | configlen++; |
| 213 | |
| 214 | pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); |
| 215 | |
| 216 | if (!of_property_read_u32(node, "allwinner,drive", &val)) { |
| 217 | u16 strength = (val + 1) * 10; |
| 218 | pinconfig[j++] = |
| 219 | pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, |
| 220 | strength); |
| 221 | } |
| 222 | |
| 223 | if (!of_property_read_u32(node, "allwinner,pull", &val)) { |
| 224 | enum pin_config_param pull = PIN_CONFIG_END; |
| 225 | if (val == 1) |
| 226 | pull = PIN_CONFIG_BIAS_PULL_UP; |
| 227 | else if (val == 2) |
| 228 | pull = PIN_CONFIG_BIAS_PULL_DOWN; |
| 229 | pinconfig[j++] = pinconf_to_config_packed(pull, 0); |
| 230 | } |
| 231 | |
| 232 | (*map)[i].data.configs.configs = pinconfig; |
| 233 | (*map)[i].data.configs.num_configs = configlen; |
| 234 | |
| 235 | i++; |
| 236 | } |
| 237 | |
| 238 | *num_maps = nmaps; |
| 239 | |
| 240 | return 0; |
| 241 | } |
| 242 | |
| 243 | static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, |
| 244 | struct pinctrl_map *map, |
| 245 | unsigned num_maps) |
| 246 | { |
| 247 | int i; |
| 248 | |
| 249 | for (i = 0; i < num_maps; i++) { |
| 250 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) |
| 251 | kfree(map[i].data.configs.configs); |
| 252 | } |
| 253 | |
| 254 | kfree(map); |
| 255 | } |
| 256 | |
Laurent Pinchart | 022ab14 | 2013-02-16 10:25:07 +0100 | [diff] [blame] | 257 | static const struct pinctrl_ops sunxi_pctrl_ops = { |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 258 | .dt_node_to_map = sunxi_pctrl_dt_node_to_map, |
| 259 | .dt_free_map = sunxi_pctrl_dt_free_map, |
| 260 | .get_groups_count = sunxi_pctrl_get_groups_count, |
| 261 | .get_group_name = sunxi_pctrl_get_group_name, |
| 262 | .get_group_pins = sunxi_pctrl_get_group_pins, |
| 263 | }; |
| 264 | |
| 265 | static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, |
| 266 | unsigned group, |
| 267 | unsigned long *config) |
| 268 | { |
| 269 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 270 | |
| 271 | *config = pctl->groups[group].config; |
| 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | |
| 276 | static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, |
| 277 | unsigned group, |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 278 | unsigned long *configs, |
| 279 | unsigned num_configs) |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 280 | { |
| 281 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 282 | struct sunxi_pinctrl_group *g = &pctl->groups[group]; |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 283 | unsigned long flags; |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 284 | u32 val, mask; |
| 285 | u16 strength; |
| 286 | u8 dlevel; |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 287 | int i; |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 288 | |
Linus Walleij | 6ad30ce | 2013-08-29 09:46:30 +0200 | [diff] [blame] | 289 | spin_lock_irqsave(&pctl->lock, flags); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 290 | |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 291 | for (i = 0; i < num_configs; i++) { |
| 292 | switch (pinconf_to_config_param(configs[i])) { |
| 293 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 294 | strength = pinconf_to_config_argument(configs[i]); |
Linus Walleij | 07b7eb9 | 2013-08-29 19:17:13 +0200 | [diff] [blame] | 295 | if (strength > 40) { |
| 296 | spin_unlock_irqrestore(&pctl->lock, flags); |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 297 | return -EINVAL; |
Linus Walleij | 07b7eb9 | 2013-08-29 19:17:13 +0200 | [diff] [blame] | 298 | } |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 299 | /* |
| 300 | * We convert from mA to what the register expects: |
| 301 | * 0: 10mA |
| 302 | * 1: 20mA |
| 303 | * 2: 30mA |
| 304 | * 3: 40mA |
| 305 | */ |
| 306 | dlevel = strength / 10 - 1; |
| 307 | val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); |
| 308 | mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); |
| 309 | writel((val & ~mask) |
| 310 | | dlevel << sunxi_dlevel_offset(g->pin), |
| 311 | pctl->membase + sunxi_dlevel_reg(g->pin)); |
| 312 | break; |
| 313 | case PIN_CONFIG_BIAS_PULL_UP: |
| 314 | val = readl(pctl->membase + sunxi_pull_reg(g->pin)); |
| 315 | mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); |
| 316 | writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), |
| 317 | pctl->membase + sunxi_pull_reg(g->pin)); |
| 318 | break; |
| 319 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 320 | val = readl(pctl->membase + sunxi_pull_reg(g->pin)); |
| 321 | mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); |
| 322 | writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), |
| 323 | pctl->membase + sunxi_pull_reg(g->pin)); |
| 324 | break; |
| 325 | default: |
| 326 | break; |
| 327 | } |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 328 | /* cache the config value */ |
| 329 | g->config = configs[i]; |
| 330 | } /* for each config */ |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 331 | |
Linus Walleij | 6ad30ce | 2013-08-29 09:46:30 +0200 | [diff] [blame] | 332 | spin_unlock_irqrestore(&pctl->lock, flags); |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 333 | |
| 334 | return 0; |
| 335 | } |
| 336 | |
Laurent Pinchart | 022ab14 | 2013-02-16 10:25:07 +0100 | [diff] [blame] | 337 | static const struct pinconf_ops sunxi_pconf_ops = { |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 338 | .pin_config_group_get = sunxi_pconf_group_get, |
| 339 | .pin_config_group_set = sunxi_pconf_group_set, |
| 340 | }; |
| 341 | |
| 342 | static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
| 343 | { |
| 344 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 345 | |
| 346 | return pctl->nfunctions; |
| 347 | } |
| 348 | |
| 349 | static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, |
| 350 | unsigned function) |
| 351 | { |
| 352 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 353 | |
| 354 | return pctl->functions[function].name; |
| 355 | } |
| 356 | |
| 357 | static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, |
| 358 | unsigned function, |
| 359 | const char * const **groups, |
| 360 | unsigned * const num_groups) |
| 361 | { |
| 362 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 363 | |
| 364 | *groups = pctl->functions[function].groups; |
| 365 | *num_groups = pctl->functions[function].ngroups; |
| 366 | |
| 367 | return 0; |
| 368 | } |
| 369 | |
| 370 | static void sunxi_pmx_set(struct pinctrl_dev *pctldev, |
| 371 | unsigned pin, |
| 372 | u8 config) |
| 373 | { |
| 374 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 375 | unsigned long flags; |
| 376 | u32 val, mask; |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 377 | |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 378 | spin_lock_irqsave(&pctl->lock, flags); |
| 379 | |
| 380 | val = readl(pctl->membase + sunxi_mux_reg(pin)); |
| 381 | mask = MUX_PINS_MASK << sunxi_mux_offset(pin); |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 382 | writel((val & ~mask) | config << sunxi_mux_offset(pin), |
| 383 | pctl->membase + sunxi_mux_reg(pin)); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 384 | |
| 385 | spin_unlock_irqrestore(&pctl->lock, flags); |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, |
| 389 | unsigned function, |
| 390 | unsigned group) |
| 391 | { |
| 392 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 393 | struct sunxi_pinctrl_group *g = pctl->groups + group; |
| 394 | struct sunxi_pinctrl_function *func = pctl->functions + function; |
| 395 | struct sunxi_desc_function *desc = |
| 396 | sunxi_pinctrl_desc_find_function_by_name(pctl, |
| 397 | g->name, |
| 398 | func->name); |
| 399 | |
| 400 | if (!desc) |
| 401 | return -EINVAL; |
| 402 | |
| 403 | sunxi_pmx_set(pctldev, g->pin, desc->muxval); |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 408 | static int |
| 409 | sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
| 410 | struct pinctrl_gpio_range *range, |
| 411 | unsigned offset, |
| 412 | bool input) |
| 413 | { |
| 414 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 415 | struct sunxi_desc_function *desc; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 416 | const char *func; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 417 | |
| 418 | if (input) |
| 419 | func = "gpio_in"; |
| 420 | else |
| 421 | func = "gpio_out"; |
| 422 | |
Maxime Ripard | 814d4f2 | 2013-06-08 12:05:43 +0200 | [diff] [blame] | 423 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); |
| 424 | if (!desc) |
| 425 | return -EINVAL; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 426 | |
| 427 | sunxi_pmx_set(pctldev, offset, desc->muxval); |
| 428 | |
Maxime Ripard | 814d4f2 | 2013-06-08 12:05:43 +0200 | [diff] [blame] | 429 | return 0; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 430 | } |
| 431 | |
Laurent Pinchart | 022ab14 | 2013-02-16 10:25:07 +0100 | [diff] [blame] | 432 | static const struct pinmux_ops sunxi_pmx_ops = { |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 433 | .get_functions_count = sunxi_pmx_get_funcs_cnt, |
| 434 | .get_function_name = sunxi_pmx_get_func_name, |
| 435 | .get_function_groups = sunxi_pmx_get_func_groups, |
| 436 | .enable = sunxi_pmx_enable, |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 437 | .gpio_set_direction = sunxi_pmx_gpio_set_direction, |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 438 | }; |
| 439 | |
| 440 | static struct pinctrl_desc sunxi_pctrl_desc = { |
| 441 | .confops = &sunxi_pconf_ops, |
| 442 | .pctlops = &sunxi_pctrl_ops, |
| 443 | .pmxops = &sunxi_pmx_ops, |
| 444 | }; |
| 445 | |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 446 | static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 447 | { |
| 448 | return pinctrl_request_gpio(chip->base + offset); |
| 449 | } |
| 450 | |
| 451 | static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 452 | { |
| 453 | pinctrl_free_gpio(chip->base + offset); |
| 454 | } |
| 455 | |
| 456 | static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, |
| 457 | unsigned offset) |
| 458 | { |
| 459 | return pinctrl_gpio_direction_input(chip->base + offset); |
| 460 | } |
| 461 | |
| 462 | static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 463 | { |
| 464 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); |
| 465 | |
| 466 | u32 reg = sunxi_data_reg(offset); |
| 467 | u8 index = sunxi_data_offset(offset); |
| 468 | u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; |
| 469 | |
| 470 | return val; |
| 471 | } |
| 472 | |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 473 | static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, |
| 474 | unsigned offset, int value) |
| 475 | { |
| 476 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); |
| 477 | u32 reg = sunxi_data_reg(offset); |
| 478 | u8 index = sunxi_data_offset(offset); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 479 | unsigned long flags; |
| 480 | u32 regval; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 481 | |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 482 | spin_lock_irqsave(&pctl->lock, flags); |
| 483 | |
| 484 | regval = readl(pctl->membase + reg); |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 485 | |
Maxime Ripard | df7b34f | 2013-07-25 12:41:16 +0200 | [diff] [blame] | 486 | if (value) |
| 487 | regval |= BIT(index); |
| 488 | else |
| 489 | regval &= ~(BIT(index)); |
| 490 | |
| 491 | writel(regval, pctl->membase + reg); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 492 | |
| 493 | spin_unlock_irqrestore(&pctl->lock, flags); |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 494 | } |
| 495 | |
Chen-Yu Tsai | fa8cf57 | 2014-01-16 14:34:23 +0800 | [diff] [blame] | 496 | static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, |
| 497 | unsigned offset, int value) |
| 498 | { |
| 499 | sunxi_pinctrl_gpio_set(chip, offset, value); |
| 500 | return pinctrl_gpio_direction_output(chip->base + offset); |
| 501 | } |
| 502 | |
Maxime Ripard | a0d7209 | 2013-02-03 12:10:11 +0100 | [diff] [blame] | 503 | static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, |
| 504 | const struct of_phandle_args *gpiospec, |
| 505 | u32 *flags) |
| 506 | { |
| 507 | int pin, base; |
| 508 | |
| 509 | base = PINS_PER_BANK * gpiospec->args[0]; |
| 510 | pin = base + gpiospec->args[1]; |
| 511 | |
| 512 | if (pin > (gc->base + gc->ngpio)) |
| 513 | return -EINVAL; |
| 514 | |
| 515 | if (flags) |
| 516 | *flags = gpiospec->args[2]; |
| 517 | |
| 518 | return pin; |
| 519 | } |
| 520 | |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 521 | static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 522 | { |
| 523 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); |
| 524 | struct sunxi_desc_function *desc; |
| 525 | |
Axel Lin | c9e3b2d | 2013-08-30 16:31:25 +0800 | [diff] [blame] | 526 | if (offset >= chip->ngpio) |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 527 | return -ENXIO; |
| 528 | |
| 529 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); |
| 530 | if (!desc) |
| 531 | return -EINVAL; |
| 532 | |
| 533 | pctl->irq_array[desc->irqnum] = offset; |
| 534 | |
| 535 | dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", |
| 536 | chip->label, offset + chip->base, desc->irqnum); |
| 537 | |
| 538 | return irq_find_mapping(pctl->domain, desc->irqnum); |
| 539 | } |
| 540 | |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 541 | |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 542 | static int sunxi_pinctrl_irq_set_type(struct irq_data *d, |
| 543 | unsigned int type) |
| 544 | { |
| 545 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 546 | u32 reg = sunxi_irq_cfg_reg(d->hwirq); |
| 547 | u8 index = sunxi_irq_cfg_offset(d->hwirq); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 548 | unsigned long flags; |
Maxime Ripard | 2aaaddf | 2013-08-04 12:38:47 +0200 | [diff] [blame] | 549 | u32 regval; |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 550 | u8 mode; |
| 551 | |
| 552 | switch (type) { |
| 553 | case IRQ_TYPE_EDGE_RISING: |
| 554 | mode = IRQ_EDGE_RISING; |
| 555 | break; |
| 556 | case IRQ_TYPE_EDGE_FALLING: |
| 557 | mode = IRQ_EDGE_FALLING; |
| 558 | break; |
| 559 | case IRQ_TYPE_EDGE_BOTH: |
| 560 | mode = IRQ_EDGE_BOTH; |
| 561 | break; |
| 562 | case IRQ_TYPE_LEVEL_HIGH: |
| 563 | mode = IRQ_LEVEL_HIGH; |
| 564 | break; |
| 565 | case IRQ_TYPE_LEVEL_LOW: |
| 566 | mode = IRQ_LEVEL_LOW; |
| 567 | break; |
| 568 | default: |
| 569 | return -EINVAL; |
| 570 | } |
| 571 | |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 572 | spin_lock_irqsave(&pctl->lock, flags); |
| 573 | |
Maxime Ripard | 2aaaddf | 2013-08-04 12:38:47 +0200 | [diff] [blame] | 574 | regval = readl(pctl->membase + reg); |
Hans de Goede | d82f940 | 2014-02-17 22:19:43 +0100 | [diff] [blame] | 575 | regval &= ~(IRQ_CFG_IRQ_MASK << index); |
Maxime Ripard | 2aaaddf | 2013-08-04 12:38:47 +0200 | [diff] [blame] | 576 | writel(regval | (mode << index), pctl->membase + reg); |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 577 | |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 578 | spin_unlock_irqrestore(&pctl->lock, flags); |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 579 | |
| 580 | return 0; |
| 581 | } |
| 582 | |
| 583 | static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) |
| 584 | { |
| 585 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 586 | u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq); |
| 587 | u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq); |
| 588 | u32 status_reg = sunxi_irq_status_reg(d->hwirq); |
| 589 | u8 status_idx = sunxi_irq_status_offset(d->hwirq); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 590 | unsigned long flags; |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 591 | u32 val; |
| 592 | |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 593 | spin_lock_irqsave(&pctl->lock, flags); |
| 594 | |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 595 | /* Mask the IRQ */ |
| 596 | val = readl(pctl->membase + ctrl_reg); |
| 597 | writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg); |
| 598 | |
| 599 | /* Clear the IRQ */ |
| 600 | writel(1 << status_idx, pctl->membase + status_reg); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 601 | |
| 602 | spin_unlock_irqrestore(&pctl->lock, flags); |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 603 | } |
| 604 | |
| 605 | static void sunxi_pinctrl_irq_mask(struct irq_data *d) |
| 606 | { |
| 607 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 608 | u32 reg = sunxi_irq_ctrl_reg(d->hwirq); |
| 609 | u8 idx = sunxi_irq_ctrl_offset(d->hwirq); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 610 | unsigned long flags; |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 611 | u32 val; |
| 612 | |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 613 | spin_lock_irqsave(&pctl->lock, flags); |
| 614 | |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 615 | /* Mask the IRQ */ |
| 616 | val = readl(pctl->membase + reg); |
| 617 | writel(val & ~(1 << idx), pctl->membase + reg); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 618 | |
| 619 | spin_unlock_irqrestore(&pctl->lock, flags); |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 620 | } |
| 621 | |
| 622 | static void sunxi_pinctrl_irq_unmask(struct irq_data *d) |
| 623 | { |
| 624 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 625 | struct sunxi_desc_function *func; |
| 626 | u32 reg = sunxi_irq_ctrl_reg(d->hwirq); |
| 627 | u8 idx = sunxi_irq_ctrl_offset(d->hwirq); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 628 | unsigned long flags; |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 629 | u32 val; |
| 630 | |
| 631 | func = sunxi_pinctrl_desc_find_function_by_pin(pctl, |
| 632 | pctl->irq_array[d->hwirq], |
| 633 | "irq"); |
| 634 | |
| 635 | /* Change muxing to INT mode */ |
| 636 | sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); |
| 637 | |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 638 | spin_lock_irqsave(&pctl->lock, flags); |
| 639 | |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 640 | /* Unmask the IRQ */ |
| 641 | val = readl(pctl->membase + reg); |
| 642 | writel(val | (1 << idx), pctl->membase + reg); |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 643 | |
| 644 | spin_unlock_irqrestore(&pctl->lock, flags); |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | static struct irq_chip sunxi_pinctrl_irq_chip = { |
| 648 | .irq_mask = sunxi_pinctrl_irq_mask, |
| 649 | .irq_mask_ack = sunxi_pinctrl_irq_mask_ack, |
| 650 | .irq_unmask = sunxi_pinctrl_irq_unmask, |
| 651 | .irq_set_type = sunxi_pinctrl_irq_set_type, |
| 652 | }; |
| 653 | |
| 654 | static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) |
| 655 | { |
Chen-Yu Tsai | 905a511 | 2014-02-11 00:22:37 +0800 | [diff] [blame] | 656 | struct irq_chip *chip = irq_get_chip(irq); |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 657 | struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); |
| 658 | const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); |
| 659 | |
| 660 | /* Clear all interrupts */ |
| 661 | writel(reg, pctl->membase + IRQ_STATUS_REG); |
| 662 | |
| 663 | if (reg) { |
| 664 | int irqoffset; |
| 665 | |
Chen-Yu Tsai | 905a511 | 2014-02-11 00:22:37 +0800 | [diff] [blame] | 666 | chained_irq_enter(chip, desc); |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 667 | for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) { |
| 668 | int pin_irq = irq_find_mapping(pctl->domain, irqoffset); |
| 669 | generic_handle_irq(pin_irq); |
| 670 | } |
Chen-Yu Tsai | 905a511 | 2014-02-11 00:22:37 +0800 | [diff] [blame] | 671 | chained_irq_exit(chip, desc); |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 672 | } |
| 673 | } |
| 674 | |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 675 | static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, |
| 676 | const char *name) |
| 677 | { |
| 678 | struct sunxi_pinctrl_function *func = pctl->functions; |
| 679 | |
| 680 | while (func->name) { |
| 681 | /* function already there */ |
| 682 | if (strcmp(func->name, name) == 0) { |
| 683 | func->ngroups++; |
| 684 | return -EEXIST; |
| 685 | } |
| 686 | func++; |
| 687 | } |
| 688 | |
| 689 | func->name = name; |
| 690 | func->ngroups = 1; |
| 691 | |
| 692 | pctl->nfunctions++; |
| 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | static int sunxi_pinctrl_build_state(struct platform_device *pdev) |
| 698 | { |
| 699 | struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); |
| 700 | int i; |
| 701 | |
| 702 | pctl->ngroups = pctl->desc->npins; |
| 703 | |
| 704 | /* Allocate groups */ |
| 705 | pctl->groups = devm_kzalloc(&pdev->dev, |
| 706 | pctl->ngroups * sizeof(*pctl->groups), |
| 707 | GFP_KERNEL); |
| 708 | if (!pctl->groups) |
| 709 | return -ENOMEM; |
| 710 | |
| 711 | for (i = 0; i < pctl->desc->npins; i++) { |
| 712 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; |
| 713 | struct sunxi_pinctrl_group *group = pctl->groups + i; |
| 714 | |
| 715 | group->name = pin->pin.name; |
| 716 | group->pin = pin->pin.number; |
| 717 | } |
| 718 | |
| 719 | /* |
| 720 | * We suppose that we won't have any more functions than pins, |
| 721 | * we'll reallocate that later anyway |
| 722 | */ |
| 723 | pctl->functions = devm_kzalloc(&pdev->dev, |
| 724 | pctl->desc->npins * sizeof(*pctl->functions), |
| 725 | GFP_KERNEL); |
| 726 | if (!pctl->functions) |
| 727 | return -ENOMEM; |
| 728 | |
| 729 | /* Count functions and their associated groups */ |
| 730 | for (i = 0; i < pctl->desc->npins; i++) { |
| 731 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; |
| 732 | struct sunxi_desc_function *func = pin->functions; |
| 733 | |
| 734 | while (func->name) { |
| 735 | sunxi_pinctrl_add_function(pctl, func->name); |
| 736 | func++; |
| 737 | } |
| 738 | } |
| 739 | |
| 740 | pctl->functions = krealloc(pctl->functions, |
| 741 | pctl->nfunctions * sizeof(*pctl->functions), |
| 742 | GFP_KERNEL); |
| 743 | |
| 744 | for (i = 0; i < pctl->desc->npins; i++) { |
| 745 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; |
| 746 | struct sunxi_desc_function *func = pin->functions; |
| 747 | |
| 748 | while (func->name) { |
| 749 | struct sunxi_pinctrl_function *func_item; |
| 750 | const char **func_grp; |
| 751 | |
| 752 | func_item = sunxi_pinctrl_find_function_by_name(pctl, |
| 753 | func->name); |
| 754 | if (!func_item) |
| 755 | return -EINVAL; |
| 756 | |
| 757 | if (!func_item->groups) { |
| 758 | func_item->groups = |
| 759 | devm_kzalloc(&pdev->dev, |
| 760 | func_item->ngroups * sizeof(*func_item->groups), |
| 761 | GFP_KERNEL); |
| 762 | if (!func_item->groups) |
| 763 | return -ENOMEM; |
| 764 | } |
| 765 | |
| 766 | func_grp = func_item->groups; |
| 767 | while (*func_grp) |
| 768 | func_grp++; |
| 769 | |
| 770 | *func_grp = pin->pin.name; |
| 771 | func++; |
| 772 | } |
| 773 | } |
| 774 | |
| 775 | return 0; |
| 776 | } |
| 777 | |
Maxime Ripard | 2284ba6 | 2014-04-18 20:10:41 +0200 | [diff] [blame] | 778 | int sunxi_pinctrl_init(struct platform_device *pdev, |
| 779 | const struct sunxi_pinctrl_desc *desc) |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 780 | { |
| 781 | struct device_node *node = pdev->dev.of_node; |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 782 | struct pinctrl_pin_desc *pins; |
| 783 | struct sunxi_pinctrl *pctl; |
Boris BREZILLON | cf2908e | 2014-04-10 15:52:45 +0200 | [diff] [blame] | 784 | struct reset_control *rstc; |
Maxime Ripard | 4409caf | 2014-04-26 21:59:50 +0200 | [diff] [blame] | 785 | struct resource *res; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 786 | int i, ret, last_pin; |
Emilio López | 950707c | 2013-03-22 11:20:40 -0300 | [diff] [blame] | 787 | struct clk *clk; |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 788 | |
| 789 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); |
| 790 | if (!pctl) |
| 791 | return -ENOMEM; |
| 792 | platform_set_drvdata(pdev, pctl); |
| 793 | |
Maxime Ripard | 1bee963 | 2013-08-04 12:38:48 +0200 | [diff] [blame] | 794 | spin_lock_init(&pctl->lock); |
| 795 | |
Maxime Ripard | 4409caf | 2014-04-26 21:59:50 +0200 | [diff] [blame] | 796 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 797 | pctl->membase = devm_ioremap_resource(&pdev->dev, res); |
| 798 | if (IS_ERR(pctl->membase)) |
| 799 | return PTR_ERR(pctl->membase); |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 800 | |
Maxime Ripard | 2284ba6 | 2014-04-18 20:10:41 +0200 | [diff] [blame] | 801 | pctl->desc = desc; |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 802 | |
| 803 | ret = sunxi_pinctrl_build_state(pdev); |
| 804 | if (ret) { |
| 805 | dev_err(&pdev->dev, "dt probe failed: %d\n", ret); |
| 806 | return ret; |
| 807 | } |
| 808 | |
| 809 | pins = devm_kzalloc(&pdev->dev, |
| 810 | pctl->desc->npins * sizeof(*pins), |
| 811 | GFP_KERNEL); |
| 812 | if (!pins) |
| 813 | return -ENOMEM; |
| 814 | |
| 815 | for (i = 0; i < pctl->desc->npins; i++) |
| 816 | pins[i] = pctl->desc->pins[i].pin; |
| 817 | |
| 818 | sunxi_pctrl_desc.name = dev_name(&pdev->dev); |
| 819 | sunxi_pctrl_desc.owner = THIS_MODULE; |
| 820 | sunxi_pctrl_desc.pins = pins; |
| 821 | sunxi_pctrl_desc.npins = pctl->desc->npins; |
| 822 | pctl->dev = &pdev->dev; |
| 823 | pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc, |
| 824 | &pdev->dev, pctl); |
| 825 | if (!pctl->pctl_dev) { |
| 826 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); |
| 827 | return -EINVAL; |
| 828 | } |
| 829 | |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 830 | pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); |
| 831 | if (!pctl->chip) { |
| 832 | ret = -ENOMEM; |
| 833 | goto pinctrl_error; |
| 834 | } |
| 835 | |
| 836 | last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; |
Boris BREZILLON | d83c82c | 2014-04-10 15:52:43 +0200 | [diff] [blame] | 837 | pctl->chip->owner = THIS_MODULE; |
| 838 | pctl->chip->request = sunxi_pinctrl_gpio_request, |
| 839 | pctl->chip->free = sunxi_pinctrl_gpio_free, |
| 840 | pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, |
| 841 | pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, |
| 842 | pctl->chip->get = sunxi_pinctrl_gpio_get, |
| 843 | pctl->chip->set = sunxi_pinctrl_gpio_set, |
| 844 | pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, |
| 845 | pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, |
| 846 | pctl->chip->of_gpio_n_cells = 3, |
| 847 | pctl->chip->can_sleep = false, |
| 848 | pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - |
| 849 | pctl->desc->pin_base; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 850 | pctl->chip->label = dev_name(&pdev->dev); |
| 851 | pctl->chip->dev = &pdev->dev; |
Boris BREZILLON | d83c82c | 2014-04-10 15:52:43 +0200 | [diff] [blame] | 852 | pctl->chip->base = pctl->desc->pin_base; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 853 | |
| 854 | ret = gpiochip_add(pctl->chip); |
| 855 | if (ret) |
| 856 | goto pinctrl_error; |
| 857 | |
| 858 | for (i = 0; i < pctl->desc->npins; i++) { |
| 859 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; |
| 860 | |
| 861 | ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), |
| 862 | pin->pin.number, |
| 863 | pin->pin.number, 1); |
| 864 | if (ret) |
| 865 | goto gpiochip_error; |
| 866 | } |
| 867 | |
Emilio López | 950707c | 2013-03-22 11:20:40 -0300 | [diff] [blame] | 868 | clk = devm_clk_get(&pdev->dev, NULL); |
Wei Yongjun | d72f88a | 2013-05-23 17:32:14 +0800 | [diff] [blame] | 869 | if (IS_ERR(clk)) { |
| 870 | ret = PTR_ERR(clk); |
Emilio López | 950707c | 2013-03-22 11:20:40 -0300 | [diff] [blame] | 871 | goto gpiochip_error; |
Wei Yongjun | d72f88a | 2013-05-23 17:32:14 +0800 | [diff] [blame] | 872 | } |
Emilio López | 950707c | 2013-03-22 11:20:40 -0300 | [diff] [blame] | 873 | |
Boris BREZILLON | 6415093 | 2014-04-10 15:52:40 +0200 | [diff] [blame] | 874 | ret = clk_prepare_enable(clk); |
| 875 | if (ret) |
| 876 | goto gpiochip_error; |
Emilio López | 950707c | 2013-03-22 11:20:40 -0300 | [diff] [blame] | 877 | |
Boris BREZILLON | cf2908e | 2014-04-10 15:52:45 +0200 | [diff] [blame] | 878 | rstc = devm_reset_control_get_optional(&pdev->dev, NULL); |
| 879 | if (!IS_ERR(rstc)) { |
| 880 | ret = reset_control_deassert(rstc); |
| 881 | if (ret) |
| 882 | goto clk_error; |
| 883 | } |
| 884 | |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 885 | pctl->irq = irq_of_parse_and_map(node, 0); |
| 886 | if (!pctl->irq) { |
| 887 | ret = -EINVAL; |
Boris BREZILLON | cf2908e | 2014-04-10 15:52:45 +0200 | [diff] [blame] | 888 | goto rstc_error; |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 889 | } |
| 890 | |
| 891 | pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, |
| 892 | &irq_domain_simple_ops, NULL); |
| 893 | if (!pctl->domain) { |
| 894 | dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); |
| 895 | ret = -ENOMEM; |
Boris BREZILLON | cf2908e | 2014-04-10 15:52:45 +0200 | [diff] [blame] | 896 | goto rstc_error; |
Maxime Ripard | 60242db | 2013-06-08 12:05:44 +0200 | [diff] [blame] | 897 | } |
| 898 | |
| 899 | for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { |
| 900 | int irqno = irq_create_mapping(pctl->domain, i); |
| 901 | |
| 902 | irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, |
| 903 | handle_simple_irq); |
| 904 | irq_set_chip_data(irqno, pctl); |
| 905 | }; |
| 906 | |
| 907 | irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); |
| 908 | irq_set_handler_data(pctl->irq, pctl); |
| 909 | |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 910 | dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 911 | |
| 912 | return 0; |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 913 | |
Boris BREZILLON | cf2908e | 2014-04-10 15:52:45 +0200 | [diff] [blame] | 914 | rstc_error: |
| 915 | if (!IS_ERR(rstc)) |
| 916 | reset_control_assert(rstc); |
Boris BREZILLON | e2bddc6 | 2014-04-10 15:52:41 +0200 | [diff] [blame] | 917 | clk_error: |
| 918 | clk_disable_unprepare(clk); |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 919 | gpiochip_error: |
Axel Lin | 97fc463 | 2013-05-19 13:58:37 +0800 | [diff] [blame] | 920 | if (gpiochip_remove(pctl->chip)) |
| 921 | dev_err(&pdev->dev, "failed to remove gpio chip\n"); |
Maxime Ripard | 08e9e61 | 2013-01-28 21:33:12 +0100 | [diff] [blame] | 922 | pinctrl_error: |
| 923 | pinctrl_unregister(pctl->pctl_dev); |
| 924 | return ret; |
Maxime Ripard | 0e37f88 | 2013-01-18 22:30:34 +0100 | [diff] [blame] | 925 | } |