Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel 5100 Memory Controllers kernel module |
| 3 | * |
| 4 | * This file may be distributed under the terms of the |
| 5 | * GNU General Public License. |
| 6 | * |
| 7 | * This module is based on the following document: |
| 8 | * |
| 9 | * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet |
| 10 | * http://download.intel.com/design/chipsets/datashts/318378.pdf |
| 11 | * |
Nils Carlson | bbead21 | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 12 | * The intel 5100 has two independent channels. EDAC core currently |
| 13 | * can not reflect this configuration so instead the chip-select |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 14 | * rows for each respective channel are laid out one after another, |
Nils Carlson | bbead21 | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 15 | * the first half belonging to channel 0, the second half belonging |
| 16 | * to channel 1. |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 17 | * |
| 18 | * This driver is for DDR2 DIMMs, and it uses chip select to select among the |
| 19 | * several ranks. However, instead of showing memories as ranks, it outputs |
| 20 | * them as DIMM's. An internal table creates the association between ranks |
| 21 | * and DIMM's. |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 22 | */ |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/pci.h> |
| 26 | #include <linux/pci_ids.h> |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 27 | #include <linux/edac.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/mmzone.h> |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 30 | #include <linux/debugfs.h> |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 31 | |
Borislav Petkov | 52019e4 | 2015-09-22 12:36:15 +0200 | [diff] [blame] | 32 | #include "edac_module.h" |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 33 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 34 | /* register addresses */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 35 | |
| 36 | /* device 16, func 1 */ |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 37 | #define I5100_MC 0x40 /* Memory Control Register */ |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 38 | #define I5100_MC_SCRBEN_MASK (1 << 7) |
| 39 | #define I5100_MC_SCRBDONE_MASK (1 << 4) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 40 | #define I5100_MS 0x44 /* Memory Status Register */ |
| 41 | #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 42 | #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 43 | #define I5100_TOLM 0x6c /* Top of Low Memory */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 44 | #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */ |
| 45 | #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */ |
| 46 | #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */ |
| 47 | #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 48 | #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 49 | #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16) |
| 50 | #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15) |
| 51 | #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14) |
Arthur Jones | f7952ff | 2008-07-25 01:49:05 -0700 | [diff] [blame] | 52 | #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12) |
| 53 | #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11) |
| 54 | #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10) |
| 55 | #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6) |
| 56 | #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5) |
| 57 | #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4) |
Niklas Söderlund | b6378cb | 2012-02-17 07:36:54 -0300 | [diff] [blame] | 58 | #define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 59 | #define I5100_FERR_NF_MEM_ANY_MASK \ |
| 60 | (I5100_FERR_NF_MEM_M16ERR_MASK | \ |
| 61 | I5100_FERR_NF_MEM_M15ERR_MASK | \ |
Arthur Jones | f7952ff | 2008-07-25 01:49:05 -0700 | [diff] [blame] | 62 | I5100_FERR_NF_MEM_M14ERR_MASK | \ |
| 63 | I5100_FERR_NF_MEM_M12ERR_MASK | \ |
| 64 | I5100_FERR_NF_MEM_M11ERR_MASK | \ |
| 65 | I5100_FERR_NF_MEM_M10ERR_MASK | \ |
| 66 | I5100_FERR_NF_MEM_M6ERR_MASK | \ |
| 67 | I5100_FERR_NF_MEM_M5ERR_MASK | \ |
| 68 | I5100_FERR_NF_MEM_M4ERR_MASK | \ |
| 69 | I5100_FERR_NF_MEM_M1ERR_MASK) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 70 | #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ |
Arthur Jones | 178d5a7 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 71 | #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */ |
Niklas Söderlund | 53ceafd | 2012-08-08 12:30:57 -0300 | [diff] [blame] | 72 | #define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */ |
| 73 | #define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */ |
| 74 | #define I5100_MEMXEINJMSK0_EINJEN (1 << 27) |
| 75 | #define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */ |
| 76 | #define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */ |
| 77 | |
| 78 | /* Device 19, Function 0 */ |
| 79 | #define I5100_DINJ0 0x9a |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 80 | |
| 81 | /* device 21 and 22, func 0 */ |
| 82 | #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ |
| 83 | #define I5100_DMIR 0x15c /* DIMM Interleave Range */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 84 | #define I5100_VALIDLOG 0x18c /* Valid Log Markers */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 85 | #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 86 | #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 87 | #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 88 | #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 89 | #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 90 | #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */ |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 91 | #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */ |
| 92 | |
| 93 | /* bit field accessors */ |
| 94 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 95 | static inline u32 i5100_mc_scrben(u32 mc) |
| 96 | { |
| 97 | return mc >> 7 & 1; |
| 98 | } |
| 99 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 100 | static inline u32 i5100_mc_errdeten(u32 mc) |
| 101 | { |
| 102 | return mc >> 5 & 1; |
| 103 | } |
| 104 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 105 | static inline u32 i5100_mc_scrbdone(u32 mc) |
| 106 | { |
| 107 | return mc >> 4 & 1; |
| 108 | } |
| 109 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 110 | static inline u16 i5100_spddata_rdo(u16 a) |
| 111 | { |
| 112 | return a >> 15 & 1; |
| 113 | } |
| 114 | |
| 115 | static inline u16 i5100_spddata_sbe(u16 a) |
| 116 | { |
| 117 | return a >> 13 & 1; |
| 118 | } |
| 119 | |
| 120 | static inline u16 i5100_spddata_busy(u16 a) |
| 121 | { |
| 122 | return a >> 12 & 1; |
| 123 | } |
| 124 | |
| 125 | static inline u16 i5100_spddata_data(u16 a) |
| 126 | { |
| 127 | return a & ((1 << 8) - 1); |
| 128 | } |
| 129 | |
| 130 | static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba, |
| 131 | u32 data, u32 cmd) |
| 132 | { |
| 133 | return ((dti & ((1 << 4) - 1)) << 28) | |
| 134 | ((ckovrd & 1) << 27) | |
| 135 | ((sa & ((1 << 3) - 1)) << 24) | |
| 136 | ((ba & ((1 << 8) - 1)) << 16) | |
| 137 | ((data & ((1 << 8) - 1)) << 8) | |
| 138 | (cmd & 1); |
| 139 | } |
| 140 | |
| 141 | static inline u16 i5100_tolm_tolm(u16 a) |
| 142 | { |
| 143 | return a >> 12 & ((1 << 4) - 1); |
| 144 | } |
| 145 | |
| 146 | static inline u16 i5100_mir_limit(u16 a) |
| 147 | { |
| 148 | return a >> 4 & ((1 << 12) - 1); |
| 149 | } |
| 150 | |
| 151 | static inline u16 i5100_mir_way1(u16 a) |
| 152 | { |
| 153 | return a >> 1 & 1; |
| 154 | } |
| 155 | |
| 156 | static inline u16 i5100_mir_way0(u16 a) |
| 157 | { |
| 158 | return a & 1; |
| 159 | } |
| 160 | |
| 161 | static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a) |
| 162 | { |
| 163 | return a >> 28 & 1; |
| 164 | } |
| 165 | |
| 166 | static inline u32 i5100_ferr_nf_mem_any(u32 a) |
| 167 | { |
| 168 | return a & I5100_FERR_NF_MEM_ANY_MASK; |
| 169 | } |
| 170 | |
| 171 | static inline u32 i5100_nerr_nf_mem_any(u32 a) |
| 172 | { |
| 173 | return i5100_ferr_nf_mem_any(a); |
| 174 | } |
| 175 | |
| 176 | static inline u32 i5100_dmir_limit(u32 a) |
| 177 | { |
| 178 | return a >> 16 & ((1 << 11) - 1); |
| 179 | } |
| 180 | |
| 181 | static inline u32 i5100_dmir_rank(u32 a, u32 i) |
| 182 | { |
| 183 | return a >> (4 * i) & ((1 << 2) - 1); |
| 184 | } |
| 185 | |
| 186 | static inline u16 i5100_mtr_present(u16 a) |
| 187 | { |
| 188 | return a >> 10 & 1; |
| 189 | } |
| 190 | |
| 191 | static inline u16 i5100_mtr_ethrottle(u16 a) |
| 192 | { |
| 193 | return a >> 9 & 1; |
| 194 | } |
| 195 | |
| 196 | static inline u16 i5100_mtr_width(u16 a) |
| 197 | { |
| 198 | return a >> 8 & 1; |
| 199 | } |
| 200 | |
| 201 | static inline u16 i5100_mtr_numbank(u16 a) |
| 202 | { |
| 203 | return a >> 6 & 1; |
| 204 | } |
| 205 | |
| 206 | static inline u16 i5100_mtr_numrow(u16 a) |
| 207 | { |
| 208 | return a >> 2 & ((1 << 2) - 1); |
| 209 | } |
| 210 | |
| 211 | static inline u16 i5100_mtr_numcol(u16 a) |
| 212 | { |
| 213 | return a & ((1 << 2) - 1); |
| 214 | } |
| 215 | |
| 216 | |
| 217 | static inline u32 i5100_validlog_redmemvalid(u32 a) |
| 218 | { |
| 219 | return a >> 2 & 1; |
| 220 | } |
| 221 | |
| 222 | static inline u32 i5100_validlog_recmemvalid(u32 a) |
| 223 | { |
| 224 | return a >> 1 & 1; |
| 225 | } |
| 226 | |
| 227 | static inline u32 i5100_validlog_nrecmemvalid(u32 a) |
| 228 | { |
| 229 | return a & 1; |
| 230 | } |
| 231 | |
| 232 | static inline u32 i5100_nrecmema_merr(u32 a) |
| 233 | { |
| 234 | return a >> 15 & ((1 << 5) - 1); |
| 235 | } |
| 236 | |
| 237 | static inline u32 i5100_nrecmema_bank(u32 a) |
| 238 | { |
| 239 | return a >> 12 & ((1 << 3) - 1); |
| 240 | } |
| 241 | |
| 242 | static inline u32 i5100_nrecmema_rank(u32 a) |
| 243 | { |
| 244 | return a >> 8 & ((1 << 3) - 1); |
| 245 | } |
| 246 | |
| 247 | static inline u32 i5100_nrecmema_dm_buf_id(u32 a) |
| 248 | { |
| 249 | return a & ((1 << 8) - 1); |
| 250 | } |
| 251 | |
| 252 | static inline u32 i5100_nrecmemb_cas(u32 a) |
| 253 | { |
| 254 | return a >> 16 & ((1 << 13) - 1); |
| 255 | } |
| 256 | |
| 257 | static inline u32 i5100_nrecmemb_ras(u32 a) |
| 258 | { |
| 259 | return a & ((1 << 16) - 1); |
| 260 | } |
| 261 | |
| 262 | static inline u32 i5100_redmemb_ecc_locator(u32 a) |
| 263 | { |
| 264 | return a & ((1 << 18) - 1); |
| 265 | } |
| 266 | |
| 267 | static inline u32 i5100_recmema_merr(u32 a) |
| 268 | { |
| 269 | return i5100_nrecmema_merr(a); |
| 270 | } |
| 271 | |
| 272 | static inline u32 i5100_recmema_bank(u32 a) |
| 273 | { |
| 274 | return i5100_nrecmema_bank(a); |
| 275 | } |
| 276 | |
| 277 | static inline u32 i5100_recmema_rank(u32 a) |
| 278 | { |
| 279 | return i5100_nrecmema_rank(a); |
| 280 | } |
| 281 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 282 | static inline u32 i5100_recmemb_cas(u32 a) |
| 283 | { |
| 284 | return i5100_nrecmemb_cas(a); |
| 285 | } |
| 286 | |
| 287 | static inline u32 i5100_recmemb_ras(u32 a) |
| 288 | { |
| 289 | return i5100_nrecmemb_ras(a); |
| 290 | } |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 291 | |
| 292 | /* some generic limits */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 293 | #define I5100_MAX_RANKS_PER_CHAN 6 |
| 294 | #define I5100_CHANNELS 2 |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 295 | #define I5100_MAX_RANKS_PER_DIMM 4 |
| 296 | #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 297 | #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4 |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 298 | #define I5100_MAX_RANK_INTERLEAVE 4 |
| 299 | #define I5100_MAX_DMIRS 5 |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 300 | #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 301 | |
| 302 | struct i5100_priv { |
| 303 | /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 304 | int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN]; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 305 | |
| 306 | /* |
| 307 | * mainboard chip select map -- maps i5100 chip selects to |
| 308 | * DIMM slot chip selects. In the case of only 4 ranks per |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 309 | * channel, the mapping is fairly obvious but not unique. |
| 310 | * we map -1 -> NC and assume both channels use the same |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 311 | * map... |
| 312 | * |
| 313 | */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 314 | int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM]; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 315 | |
| 316 | /* memory interleave range */ |
| 317 | struct { |
| 318 | u64 limit; |
| 319 | unsigned way[2]; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 320 | } mir[I5100_CHANNELS]; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 321 | |
| 322 | /* adjusted memory interleave range register */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 323 | unsigned amir[I5100_CHANNELS]; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 324 | |
| 325 | /* dimm interleave range */ |
| 326 | struct { |
| 327 | unsigned rank[I5100_MAX_RANK_INTERLEAVE]; |
| 328 | u64 limit; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 329 | } dmir[I5100_CHANNELS][I5100_MAX_DMIRS]; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 330 | |
| 331 | /* memory technology registers... */ |
| 332 | struct { |
| 333 | unsigned present; /* 0 or 1 */ |
| 334 | unsigned ethrottle; /* 0 or 1 */ |
| 335 | unsigned width; /* 4 or 8 bits */ |
| 336 | unsigned numbank; /* 2 or 3 lines */ |
| 337 | unsigned numrow; /* 13 .. 16 lines */ |
| 338 | unsigned numcol; /* 11 .. 12 lines */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 339 | } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 340 | |
| 341 | u64 tolm; /* top of low memory in bytes */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 342 | unsigned ranksperchan; /* number of ranks per channel */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 343 | |
| 344 | struct pci_dev *mc; /* device 16 func 1 */ |
Niklas Söderlund | 52608ba | 2012-08-08 12:30:56 -0300 | [diff] [blame] | 345 | struct pci_dev *einj; /* device 19 func 0 */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 346 | struct pci_dev *ch0mm; /* device 21 func 0 */ |
| 347 | struct pci_dev *ch1mm; /* device 22 func 0 */ |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 348 | |
| 349 | struct delayed_work i5100_scrubbing; |
| 350 | int scrub_enable; |
Niklas Söderlund | 53ceafd | 2012-08-08 12:30:57 -0300 | [diff] [blame] | 351 | |
| 352 | /* Error injection */ |
| 353 | u8 inject_channel; |
| 354 | u8 inject_hlinesel; |
| 355 | u8 inject_deviceptr1; |
| 356 | u8 inject_deviceptr2; |
| 357 | u16 inject_eccmask1; |
| 358 | u16 inject_eccmask2; |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 359 | |
| 360 | struct dentry *debugfs; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 361 | }; |
| 362 | |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 363 | static struct dentry *i5100_debugfs; |
| 364 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 365 | /* map a rank/chan to a slot number on the mainboard */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 366 | static int i5100_rank_to_slot(const struct mem_ctl_info *mci, |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 367 | int chan, int rank) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 368 | { |
| 369 | const struct i5100_priv *priv = mci->pvt_info; |
| 370 | int i; |
| 371 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 372 | for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 373 | int j; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 374 | const int numrank = priv->dimm_numrank[chan][i]; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 375 | |
| 376 | for (j = 0; j < numrank; j++) |
| 377 | if (priv->dimm_csmap[i][j] == rank) |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 378 | return i * 2 + chan; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | return -1; |
| 382 | } |
| 383 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 384 | static const char *i5100_err_msg(unsigned err) |
| 385 | { |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 386 | static const char *merrs[] = { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 387 | "unknown", /* 0 */ |
| 388 | "uncorrectable data ECC on replay", /* 1 */ |
| 389 | "unknown", /* 2 */ |
| 390 | "unknown", /* 3 */ |
| 391 | "aliased uncorrectable demand data ECC", /* 4 */ |
| 392 | "aliased uncorrectable spare-copy data ECC", /* 5 */ |
| 393 | "aliased uncorrectable patrol data ECC", /* 6 */ |
| 394 | "unknown", /* 7 */ |
| 395 | "unknown", /* 8 */ |
| 396 | "unknown", /* 9 */ |
| 397 | "non-aliased uncorrectable demand data ECC", /* 10 */ |
| 398 | "non-aliased uncorrectable spare-copy data ECC", /* 11 */ |
| 399 | "non-aliased uncorrectable patrol data ECC", /* 12 */ |
| 400 | "unknown", /* 13 */ |
| 401 | "correctable demand data ECC", /* 14 */ |
| 402 | "correctable spare-copy data ECC", /* 15 */ |
| 403 | "correctable patrol data ECC", /* 16 */ |
| 404 | "unknown", /* 17 */ |
| 405 | "SPD protocol error", /* 18 */ |
| 406 | "unknown", /* 19 */ |
| 407 | "spare copy initiated", /* 20 */ |
| 408 | "spare copy completed", /* 21 */ |
| 409 | }; |
| 410 | unsigned i; |
| 411 | |
| 412 | for (i = 0; i < ARRAY_SIZE(merrs); i++) |
| 413 | if (1 << i & err) |
| 414 | return merrs[i]; |
| 415 | |
| 416 | return "none"; |
| 417 | } |
| 418 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 419 | /* convert csrow index into a rank (per channel -- 0..5) */ |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 420 | static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) |
| 421 | { |
| 422 | const struct i5100_priv *priv = mci->pvt_info; |
| 423 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 424 | return csrow % priv->ranksperchan; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 425 | } |
| 426 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 427 | /* convert csrow index into a channel (0..1) */ |
| 428 | static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 429 | { |
| 430 | const struct i5100_priv *priv = mci->pvt_info; |
| 431 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 432 | return csrow / priv->ranksperchan; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 433 | } |
| 434 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 435 | static void i5100_handle_ce(struct mem_ctl_info *mci, |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 436 | int chan, |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 437 | unsigned bank, |
| 438 | unsigned rank, |
| 439 | unsigned long syndrome, |
| 440 | unsigned cas, |
| 441 | unsigned ras, |
| 442 | const char *msg) |
| 443 | { |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 444 | char detail[80]; |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 445 | |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 446 | /* Form out message */ |
| 447 | snprintf(detail, sizeof(detail), |
| 448 | "bank %u, cas %u, ras %u\n", |
| 449 | bank, cas, ras); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 450 | |
Mauro Carvalho Chehab | 9eb07a7 | 2012-06-04 13:27:43 -0300 | [diff] [blame] | 451 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 452 | 0, 0, syndrome, |
| 453 | chan, rank, -1, |
Mauro Carvalho Chehab | 03f7eae | 2012-06-04 11:29:25 -0300 | [diff] [blame] | 454 | msg, detail); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 455 | } |
| 456 | |
| 457 | static void i5100_handle_ue(struct mem_ctl_info *mci, |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 458 | int chan, |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 459 | unsigned bank, |
| 460 | unsigned rank, |
| 461 | unsigned long syndrome, |
| 462 | unsigned cas, |
| 463 | unsigned ras, |
| 464 | const char *msg) |
| 465 | { |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 466 | char detail[80]; |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 467 | |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 468 | /* Form out message */ |
| 469 | snprintf(detail, sizeof(detail), |
| 470 | "bank %u, cas %u, ras %u\n", |
| 471 | bank, cas, ras); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 472 | |
Mauro Carvalho Chehab | 9eb07a7 | 2012-06-04 13:27:43 -0300 | [diff] [blame] | 473 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 474 | 0, 0, syndrome, |
| 475 | chan, rank, -1, |
Mauro Carvalho Chehab | 03f7eae | 2012-06-04 11:29:25 -0300 | [diff] [blame] | 476 | msg, detail); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 477 | } |
| 478 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 479 | static void i5100_read_log(struct mem_ctl_info *mci, int chan, |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 480 | u32 ferr, u32 nerr) |
| 481 | { |
| 482 | struct i5100_priv *priv = mci->pvt_info; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 483 | struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 484 | u32 dw; |
| 485 | u32 dw2; |
| 486 | unsigned syndrome = 0; |
| 487 | unsigned ecc_loc = 0; |
| 488 | unsigned merr; |
| 489 | unsigned bank; |
| 490 | unsigned rank; |
| 491 | unsigned cas; |
| 492 | unsigned ras; |
| 493 | |
| 494 | pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); |
| 495 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 496 | if (i5100_validlog_redmemvalid(dw)) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 497 | pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 498 | syndrome = dw2; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 499 | pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 500 | ecc_loc = i5100_redmemb_ecc_locator(dw2); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 501 | } |
| 502 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 503 | if (i5100_validlog_recmemvalid(dw)) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 504 | const char *msg; |
| 505 | |
| 506 | pci_read_config_dword(pdev, I5100_RECMEMA, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 507 | merr = i5100_recmema_merr(dw2); |
| 508 | bank = i5100_recmema_bank(dw2); |
| 509 | rank = i5100_recmema_rank(dw2); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 510 | |
| 511 | pci_read_config_dword(pdev, I5100_RECMEMB, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 512 | cas = i5100_recmemb_cas(dw2); |
| 513 | ras = i5100_recmemb_ras(dw2); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 514 | |
| 515 | /* FIXME: not really sure if this is what merr is... |
| 516 | */ |
| 517 | if (!merr) |
| 518 | msg = i5100_err_msg(ferr); |
| 519 | else |
| 520 | msg = i5100_err_msg(nerr); |
| 521 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 522 | i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 523 | } |
| 524 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 525 | if (i5100_validlog_nrecmemvalid(dw)) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 526 | const char *msg; |
| 527 | |
| 528 | pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 529 | merr = i5100_nrecmema_merr(dw2); |
| 530 | bank = i5100_nrecmema_bank(dw2); |
| 531 | rank = i5100_nrecmema_rank(dw2); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 532 | |
| 533 | pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 534 | cas = i5100_nrecmemb_cas(dw2); |
| 535 | ras = i5100_nrecmemb_ras(dw2); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 536 | |
| 537 | /* FIXME: not really sure if this is what merr is... |
| 538 | */ |
| 539 | if (!merr) |
| 540 | msg = i5100_err_msg(ferr); |
| 541 | else |
| 542 | msg = i5100_err_msg(nerr); |
| 543 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 544 | i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | pci_write_config_dword(pdev, I5100_VALIDLOG, dw); |
| 548 | } |
| 549 | |
| 550 | static void i5100_check_error(struct mem_ctl_info *mci) |
| 551 | { |
| 552 | struct i5100_priv *priv = mci->pvt_info; |
Niklas Söderlund | df95e42 | 2011-12-09 13:12:15 -0300 | [diff] [blame] | 553 | u32 dw, dw2; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 554 | |
| 555 | pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 556 | if (i5100_ferr_nf_mem_any(dw)) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 557 | |
| 558 | pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 559 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 560 | i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), |
| 561 | i5100_ferr_nf_mem_any(dw), |
| 562 | i5100_nerr_nf_mem_any(dw2)); |
Niklas Söderlund | df95e42 | 2011-12-09 13:12:15 -0300 | [diff] [blame] | 563 | |
| 564 | pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 565 | } |
Niklas Söderlund | df95e42 | 2011-12-09 13:12:15 -0300 | [diff] [blame] | 566 | pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 567 | } |
| 568 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 569 | /* The i5100 chipset will scrub the entire memory once, then |
| 570 | * set a done bit. Continuous scrubbing is achieved by enqueing |
| 571 | * delayed work to a workqueue, checking every few minutes if |
| 572 | * the scrubbing has completed and if so reinitiating it. |
| 573 | */ |
| 574 | |
| 575 | static void i5100_refresh_scrubbing(struct work_struct *work) |
| 576 | { |
Geliang Tang | 1cac550 | 2016-01-01 22:59:07 +0800 | [diff] [blame] | 577 | struct delayed_work *i5100_scrubbing = to_delayed_work(work); |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 578 | struct i5100_priv *priv = container_of(i5100_scrubbing, |
| 579 | struct i5100_priv, |
| 580 | i5100_scrubbing); |
| 581 | u32 dw; |
| 582 | |
| 583 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 584 | |
| 585 | if (priv->scrub_enable) { |
| 586 | |
| 587 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 588 | |
| 589 | if (i5100_mc_scrbdone(dw)) { |
| 590 | dw |= I5100_MC_SCRBEN_MASK; |
| 591 | pci_write_config_dword(priv->mc, I5100_MC, dw); |
| 592 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 593 | } |
| 594 | |
| 595 | schedule_delayed_work(&(priv->i5100_scrubbing), |
| 596 | I5100_SCRUB_REFRESH_RATE); |
| 597 | } |
| 598 | } |
| 599 | /* |
| 600 | * The bandwidth is based on experimentation, feel free to refine it. |
| 601 | */ |
Borislav Petkov | eba042a | 2010-05-25 18:21:07 +0200 | [diff] [blame] | 602 | static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth) |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 603 | { |
| 604 | struct i5100_priv *priv = mci->pvt_info; |
| 605 | u32 dw; |
| 606 | |
| 607 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
Borislav Petkov | eba042a | 2010-05-25 18:21:07 +0200 | [diff] [blame] | 608 | if (bandwidth) { |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 609 | priv->scrub_enable = 1; |
| 610 | dw |= I5100_MC_SCRBEN_MASK; |
| 611 | schedule_delayed_work(&(priv->i5100_scrubbing), |
| 612 | I5100_SCRUB_REFRESH_RATE); |
| 613 | } else { |
| 614 | priv->scrub_enable = 0; |
| 615 | dw &= ~I5100_MC_SCRBEN_MASK; |
| 616 | cancel_delayed_work(&(priv->i5100_scrubbing)); |
| 617 | } |
| 618 | pci_write_config_dword(priv->mc, I5100_MC, dw); |
| 619 | |
| 620 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 621 | |
Borislav Petkov | eba042a | 2010-05-25 18:21:07 +0200 | [diff] [blame] | 622 | bandwidth = 5900000 * i5100_mc_scrben(dw); |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 623 | |
Borislav Petkov | 3909444 | 2010-11-24 19:52:09 +0100 | [diff] [blame] | 624 | return bandwidth; |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 625 | } |
| 626 | |
Borislav Petkov | 3909444 | 2010-11-24 19:52:09 +0100 | [diff] [blame] | 627 | static int i5100_get_scrub_rate(struct mem_ctl_info *mci) |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 628 | { |
| 629 | struct i5100_priv *priv = mci->pvt_info; |
| 630 | u32 dw; |
| 631 | |
| 632 | pci_read_config_dword(priv->mc, I5100_MC, &dw); |
| 633 | |
Borislav Petkov | 3909444 | 2010-11-24 19:52:09 +0100 | [diff] [blame] | 634 | return 5900000 * i5100_mc_scrben(dw); |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 635 | } |
| 636 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 637 | static struct pci_dev *pci_get_device_func(unsigned vendor, |
| 638 | unsigned device, |
| 639 | unsigned func) |
| 640 | { |
| 641 | struct pci_dev *ret = NULL; |
| 642 | |
| 643 | while (1) { |
| 644 | ret = pci_get_device(vendor, device, ret); |
| 645 | |
| 646 | if (!ret) |
| 647 | break; |
| 648 | |
| 649 | if (PCI_FUNC(ret->devfn) == func) |
| 650 | break; |
| 651 | } |
| 652 | |
| 653 | return ret; |
| 654 | } |
| 655 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 656 | static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 657 | { |
| 658 | struct i5100_priv *priv = mci->pvt_info; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 659 | const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow); |
| 660 | const unsigned chan = i5100_csrow_to_chan(mci, csrow); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 661 | unsigned addr_lines; |
| 662 | |
| 663 | /* dimm present? */ |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 664 | if (!priv->mtr[chan][chan_rank].present) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 665 | return 0ULL; |
| 666 | |
| 667 | addr_lines = |
| 668 | I5100_DIMM_ADDR_LINES + |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 669 | priv->mtr[chan][chan_rank].numcol + |
| 670 | priv->mtr[chan][chan_rank].numrow + |
| 671 | priv->mtr[chan][chan_rank].numbank; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 672 | |
| 673 | return (unsigned long) |
| 674 | ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE); |
| 675 | } |
| 676 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 677 | static void i5100_init_mtr(struct mem_ctl_info *mci) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 678 | { |
| 679 | struct i5100_priv *priv = mci->pvt_info; |
| 680 | struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; |
| 681 | int i; |
| 682 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 683 | for (i = 0; i < I5100_CHANNELS; i++) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 684 | int j; |
| 685 | struct pci_dev *pdev = mms[i]; |
| 686 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 687 | for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 688 | const unsigned addr = |
| 689 | (j < 4) ? I5100_MTR_0 + j * 2 : |
| 690 | I5100_MTR_4 + (j - 4) * 2; |
| 691 | u16 w; |
| 692 | |
| 693 | pci_read_config_word(pdev, addr, &w); |
| 694 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 695 | priv->mtr[i][j].present = i5100_mtr_present(w); |
| 696 | priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); |
| 697 | priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); |
| 698 | priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); |
| 699 | priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); |
| 700 | priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 701 | } |
| 702 | } |
| 703 | } |
| 704 | |
| 705 | /* |
| 706 | * FIXME: make this into a real i2c adapter (so that dimm-decode |
| 707 | * will work)? |
| 708 | */ |
| 709 | static int i5100_read_spd_byte(const struct mem_ctl_info *mci, |
| 710 | u8 ch, u8 slot, u8 addr, u8 *byte) |
| 711 | { |
| 712 | struct i5100_priv *priv = mci->pvt_info; |
| 713 | u16 w; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 714 | unsigned long et; |
| 715 | |
| 716 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 717 | if (i5100_spddata_busy(w)) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 718 | return -1; |
| 719 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 720 | pci_write_config_dword(priv->mc, I5100_SPDCMD, |
| 721 | i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr, |
| 722 | 0, 0)); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 723 | |
| 724 | /* wait up to 100ms */ |
| 725 | et = jiffies + HZ / 10; |
| 726 | udelay(100); |
| 727 | while (1) { |
| 728 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 729 | if (!i5100_spddata_busy(w)) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 730 | break; |
| 731 | udelay(100); |
| 732 | } |
| 733 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 734 | if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w)) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 735 | return -1; |
| 736 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 737 | *byte = i5100_spddata_data(w); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 738 | |
| 739 | return 0; |
| 740 | } |
| 741 | |
| 742 | /* |
| 743 | * fill dimm chip select map |
| 744 | * |
| 745 | * FIXME: |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 746 | * o not the only way to may chip selects to dimm slots |
| 747 | * o investigate if there is some way to obtain this map from the bios |
| 748 | */ |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 749 | static void i5100_init_dimm_csmap(struct mem_ctl_info *mci) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 750 | { |
| 751 | struct i5100_priv *priv = mci->pvt_info; |
| 752 | int i; |
| 753 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 754 | for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 755 | int j; |
| 756 | |
| 757 | for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++) |
| 758 | priv->dimm_csmap[i][j] = -1; /* default NC */ |
| 759 | } |
| 760 | |
| 761 | /* only 2 chip selects per slot... */ |
Nils Carlson | bbead21 | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 762 | if (priv->ranksperchan == 4) { |
| 763 | priv->dimm_csmap[0][0] = 0; |
| 764 | priv->dimm_csmap[0][1] = 3; |
| 765 | priv->dimm_csmap[1][0] = 1; |
| 766 | priv->dimm_csmap[1][1] = 2; |
| 767 | priv->dimm_csmap[2][0] = 2; |
| 768 | priv->dimm_csmap[3][0] = 3; |
| 769 | } else { |
| 770 | priv->dimm_csmap[0][0] = 0; |
| 771 | priv->dimm_csmap[0][1] = 1; |
| 772 | priv->dimm_csmap[1][0] = 2; |
| 773 | priv->dimm_csmap[1][1] = 3; |
| 774 | priv->dimm_csmap[2][0] = 4; |
| 775 | priv->dimm_csmap[2][1] = 5; |
| 776 | } |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 777 | } |
| 778 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 779 | static void i5100_init_dimm_layout(struct pci_dev *pdev, |
| 780 | struct mem_ctl_info *mci) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 781 | { |
| 782 | struct i5100_priv *priv = mci->pvt_info; |
| 783 | int i; |
| 784 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 785 | for (i = 0; i < I5100_CHANNELS; i++) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 786 | int j; |
| 787 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 788 | for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 789 | u8 rank; |
| 790 | |
| 791 | if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0) |
| 792 | priv->dimm_numrank[i][j] = 0; |
| 793 | else |
| 794 | priv->dimm_numrank[i][j] = (rank & 3) + 1; |
| 795 | } |
| 796 | } |
| 797 | |
| 798 | i5100_init_dimm_csmap(mci); |
| 799 | } |
| 800 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 801 | static void i5100_init_interleaving(struct pci_dev *pdev, |
| 802 | struct mem_ctl_info *mci) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 803 | { |
| 804 | u16 w; |
| 805 | u32 dw; |
| 806 | struct i5100_priv *priv = mci->pvt_info; |
| 807 | struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; |
| 808 | int i; |
| 809 | |
| 810 | pci_read_config_word(pdev, I5100_TOLM, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 811 | priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 812 | |
| 813 | pci_read_config_word(pdev, I5100_MIR0, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 814 | priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28; |
| 815 | priv->mir[0].way[1] = i5100_mir_way1(w); |
| 816 | priv->mir[0].way[0] = i5100_mir_way0(w); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 817 | |
| 818 | pci_read_config_word(pdev, I5100_MIR1, &w); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 819 | priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28; |
| 820 | priv->mir[1].way[1] = i5100_mir_way1(w); |
| 821 | priv->mir[1].way[0] = i5100_mir_way0(w); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 822 | |
| 823 | pci_read_config_word(pdev, I5100_AMIR_0, &w); |
| 824 | priv->amir[0] = w; |
| 825 | pci_read_config_word(pdev, I5100_AMIR_1, &w); |
| 826 | priv->amir[1] = w; |
| 827 | |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 828 | for (i = 0; i < I5100_CHANNELS; i++) { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 829 | int j; |
| 830 | |
| 831 | for (j = 0; j < 5; j++) { |
| 832 | int k; |
| 833 | |
| 834 | pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw); |
| 835 | |
| 836 | priv->dmir[i][j].limit = |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 837 | (u64) i5100_dmir_limit(dw) << 28; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 838 | for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) |
| 839 | priv->dmir[i][j].rank[k] = |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 840 | i5100_dmir_rank(dw, k); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 841 | } |
| 842 | } |
| 843 | |
| 844 | i5100_init_mtr(mci); |
| 845 | } |
| 846 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 847 | static void i5100_init_csrows(struct mem_ctl_info *mci) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 848 | { |
| 849 | int i; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 850 | struct i5100_priv *priv = mci->pvt_info; |
| 851 | |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 852 | for (i = 0; i < mci->tot_dimms; i++) { |
| 853 | struct dimm_info *dimm; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 854 | const unsigned long npages = i5100_npages(mci, i); |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 855 | const unsigned chan = i5100_csrow_to_chan(mci, i); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 856 | const unsigned rank = i5100_csrow_to_rank(mci, i); |
| 857 | |
| 858 | if (!npages) |
| 859 | continue; |
| 860 | |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 861 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
| 862 | chan, rank, 0); |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 863 | |
Mauro Carvalho Chehab | a895bf8 | 2012-01-28 09:09:38 -0300 | [diff] [blame] | 864 | dimm->nr_pages = npages; |
Dan Carpenter | 9d6c7cb | 2014-02-13 14:17:38 +0300 | [diff] [blame] | 865 | dimm->grain = 32; |
| 866 | dimm->dtype = (priv->mtr[chan][rank].width == 4) ? |
| 867 | DEV_X4 : DEV_X8; |
| 868 | dimm->mtype = MEM_RDDR2; |
| 869 | dimm->edac_mode = EDAC_SECDED; |
| 870 | snprintf(dimm->label, sizeof(dimm->label), "DIMM%u", |
| 871 | i5100_rank_to_slot(mci, chan, rank)); |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 872 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 873 | edac_dbg(2, "dimm channel %d, rank %d, size %ld\n", |
| 874 | chan, rank, (long)PAGES_TO_MiB(npages)); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 875 | } |
| 876 | } |
| 877 | |
Niklas Söderlund | 53ceafd | 2012-08-08 12:30:57 -0300 | [diff] [blame] | 878 | /**************************************************************************** |
| 879 | * Error injection routines |
| 880 | ****************************************************************************/ |
| 881 | |
| 882 | static void i5100_do_inject(struct mem_ctl_info *mci) |
| 883 | { |
| 884 | struct i5100_priv *priv = mci->pvt_info; |
| 885 | u32 mask0; |
| 886 | u16 mask1; |
| 887 | |
| 888 | /* MEM[1:0]EINJMSK0 |
| 889 | * 31 - ADDRMATCHEN |
| 890 | * 29:28 - HLINESEL |
| 891 | * 00 Reserved |
| 892 | * 01 Lower half of cache line |
| 893 | * 10 Upper half of cache line |
| 894 | * 11 Both upper and lower parts of cache line |
| 895 | * 27 - EINJEN |
| 896 | * 25:19 - XORMASK1 for deviceptr1 |
| 897 | * 9:5 - SEC2RAM for deviceptr2 |
| 898 | * 4:0 - FIR2RAM for deviceptr1 |
| 899 | */ |
| 900 | mask0 = ((priv->inject_hlinesel & 0x3) << 28) | |
| 901 | I5100_MEMXEINJMSK0_EINJEN | |
| 902 | ((priv->inject_eccmask1 & 0xffff) << 10) | |
| 903 | ((priv->inject_deviceptr2 & 0x1f) << 5) | |
| 904 | (priv->inject_deviceptr1 & 0x1f); |
| 905 | |
| 906 | /* MEM[1:0]EINJMSK1 |
| 907 | * 15:0 - XORMASK2 for deviceptr2 |
| 908 | */ |
| 909 | mask1 = priv->inject_eccmask2; |
| 910 | |
| 911 | if (priv->inject_channel == 0) { |
| 912 | pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0); |
| 913 | pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1); |
| 914 | } else { |
| 915 | pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0); |
| 916 | pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1); |
| 917 | } |
| 918 | |
| 919 | /* Error Injection Response Function |
| 920 | * Intel 5100 Memory Controller Hub Chipset (318378) datasheet |
| 921 | * hints about this register but carry no data about them. All |
| 922 | * data regarding device 19 is based on experimentation and the |
| 923 | * Intel 7300 Chipset Memory Controller Hub (318082) datasheet |
| 924 | * which appears to be accurate for the i5100 in this area. |
| 925 | * |
| 926 | * The injection code don't work without setting this register. |
| 927 | * The register needs to be flipped off then on else the hardware |
| 928 | * will only preform the first injection. |
| 929 | * |
| 930 | * Stop condition bits 7:4 |
| 931 | * 1010 - Stop after one injection |
| 932 | * 1011 - Never stop injecting faults |
| 933 | * |
| 934 | * Start condition bits 3:0 |
| 935 | * 1010 - Never start |
| 936 | * 1011 - Start immediately |
| 937 | */ |
| 938 | pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa); |
| 939 | pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab); |
| 940 | } |
| 941 | |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 942 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) |
| 943 | static ssize_t inject_enable_write(struct file *file, const char __user *data, |
| 944 | size_t count, loff_t *ppos) |
| 945 | { |
| 946 | struct device *dev = file->private_data; |
| 947 | struct mem_ctl_info *mci = to_mci(dev); |
| 948 | |
| 949 | i5100_do_inject(mci); |
| 950 | |
| 951 | return count; |
| 952 | } |
| 953 | |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 954 | static const struct file_operations i5100_inject_enable_fops = { |
Wei Yongjun | b076989 | 2013-02-26 17:18:34 +0800 | [diff] [blame] | 955 | .open = simple_open, |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 956 | .write = inject_enable_write, |
| 957 | .llseek = generic_file_llseek, |
| 958 | }; |
| 959 | |
| 960 | static int i5100_setup_debugfs(struct mem_ctl_info *mci) |
| 961 | { |
| 962 | struct i5100_priv *priv = mci->pvt_info; |
| 963 | |
| 964 | if (!i5100_debugfs) |
| 965 | return -ENODEV; |
| 966 | |
Borislav Petkov | 52019e4 | 2015-09-22 12:36:15 +0200 | [diff] [blame] | 967 | priv->debugfs = edac_debugfs_create_dir_at(mci->bus->name, i5100_debugfs); |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 968 | |
| 969 | if (!priv->debugfs) |
| 970 | return -ENOMEM; |
| 971 | |
Borislav Petkov | 52019e4 | 2015-09-22 12:36:15 +0200 | [diff] [blame] | 972 | edac_debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs, |
| 973 | &priv->inject_channel); |
| 974 | edac_debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs, |
| 975 | &priv->inject_hlinesel); |
| 976 | edac_debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs, |
| 977 | &priv->inject_deviceptr1); |
| 978 | edac_debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs, |
| 979 | &priv->inject_deviceptr2); |
| 980 | edac_debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs, |
| 981 | &priv->inject_eccmask1); |
| 982 | edac_debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs, |
| 983 | &priv->inject_eccmask2); |
| 984 | edac_debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs, |
| 985 | &mci->dev, &i5100_inject_enable_fops); |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 986 | |
| 987 | return 0; |
| 988 | |
| 989 | } |
| 990 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 991 | static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 992 | { |
| 993 | int rc; |
| 994 | struct mem_ctl_info *mci; |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 995 | struct edac_mc_layer layers[2]; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 996 | struct i5100_priv *priv; |
Niklas Söderlund | 52608ba | 2012-08-08 12:30:56 -0300 | [diff] [blame] | 997 | struct pci_dev *ch0mm, *ch1mm, *einj; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 998 | int ret = 0; |
| 999 | u32 dw; |
| 1000 | int ranksperch; |
| 1001 | |
| 1002 | if (PCI_FUNC(pdev->devfn) != 1) |
| 1003 | return -ENODEV; |
| 1004 | |
| 1005 | rc = pci_enable_device(pdev); |
| 1006 | if (rc < 0) { |
| 1007 | ret = rc; |
| 1008 | goto bail; |
| 1009 | } |
| 1010 | |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 1011 | /* ECC enabled? */ |
| 1012 | pci_read_config_dword(pdev, I5100_MC, &dw); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1013 | if (!i5100_mc_errdeten(dw)) { |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 1014 | printk(KERN_INFO "i5100_edac: ECC not enabled.\n"); |
| 1015 | ret = -ENODEV; |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1016 | goto bail_pdev; |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 1017 | } |
| 1018 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1019 | /* figure out how many ranks, from strapped state of 48GB_Mode input */ |
| 1020 | pci_read_config_dword(pdev, I5100_MS, &dw); |
| 1021 | ranksperch = !!(dw & (1 << 8)) * 2 + 4; |
| 1022 | |
Arthur Jones | 178d5a7 | 2008-07-25 01:49:06 -0700 | [diff] [blame] | 1023 | /* enable error reporting... */ |
| 1024 | pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw); |
| 1025 | dw &= ~I5100_FERR_NF_MEM_ANY_MASK; |
| 1026 | pci_write_config_dword(pdev, I5100_EMASK_MEM, dw); |
| 1027 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1028 | /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ |
| 1029 | ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, |
| 1030 | PCI_DEVICE_ID_INTEL_5100_21, 0); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1031 | if (!ch0mm) { |
| 1032 | ret = -ENODEV; |
| 1033 | goto bail_pdev; |
| 1034 | } |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1035 | |
| 1036 | rc = pci_enable_device(ch0mm); |
| 1037 | if (rc < 0) { |
| 1038 | ret = rc; |
| 1039 | goto bail_ch0; |
| 1040 | } |
| 1041 | |
| 1042 | /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */ |
| 1043 | ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, |
| 1044 | PCI_DEVICE_ID_INTEL_5100_22, 0); |
| 1045 | if (!ch1mm) { |
| 1046 | ret = -ENODEV; |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1047 | goto bail_disable_ch0; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1048 | } |
| 1049 | |
| 1050 | rc = pci_enable_device(ch1mm); |
| 1051 | if (rc < 0) { |
| 1052 | ret = rc; |
| 1053 | goto bail_ch1; |
| 1054 | } |
| 1055 | |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 1056 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
| 1057 | layers[0].size = 2; |
| 1058 | layers[0].is_virt_csrow = false; |
| 1059 | layers[1].type = EDAC_MC_LAYER_SLOT; |
| 1060 | layers[1].size = ranksperch; |
| 1061 | layers[1].is_virt_csrow = true; |
Mauro Carvalho Chehab | ca0907b | 2012-05-02 14:37:00 -0300 | [diff] [blame] | 1062 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, |
Mauro Carvalho Chehab | d1afaa0 | 2012-04-16 15:09:52 -0300 | [diff] [blame] | 1063 | sizeof(*priv)); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1064 | if (!mci) { |
| 1065 | ret = -ENOMEM; |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1066 | goto bail_disable_ch1; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1067 | } |
| 1068 | |
Niklas Söderlund | 52608ba | 2012-08-08 12:30:56 -0300 | [diff] [blame] | 1069 | |
| 1070 | /* device 19, func 0, Error injection */ |
| 1071 | einj = pci_get_device_func(PCI_VENDOR_ID_INTEL, |
| 1072 | PCI_DEVICE_ID_INTEL_5100_19, 0); |
| 1073 | if (!einj) { |
| 1074 | ret = -ENODEV; |
| 1075 | goto bail_einj; |
| 1076 | } |
| 1077 | |
| 1078 | rc = pci_enable_device(einj); |
| 1079 | if (rc < 0) { |
| 1080 | ret = rc; |
| 1081 | goto bail_disable_einj; |
| 1082 | } |
| 1083 | |
| 1084 | |
Mauro Carvalho Chehab | fd68750 | 2012-03-16 07:44:18 -0300 | [diff] [blame] | 1085 | mci->pdev = &pdev->dev; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1086 | |
| 1087 | priv = mci->pvt_info; |
Nils Carlson | b18dfd0 | 2009-12-15 16:47:40 -0800 | [diff] [blame] | 1088 | priv->ranksperchan = ranksperch; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1089 | priv->mc = pdev; |
| 1090 | priv->ch0mm = ch0mm; |
| 1091 | priv->ch1mm = ch1mm; |
Niklas Söderlund | 52608ba | 2012-08-08 12:30:56 -0300 | [diff] [blame] | 1092 | priv->einj = einj; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1093 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1094 | INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing); |
| 1095 | |
| 1096 | /* If scrubbing was already enabled by the bios, start maintaining it */ |
| 1097 | pci_read_config_dword(pdev, I5100_MC, &dw); |
| 1098 | if (i5100_mc_scrben(dw)) { |
| 1099 | priv->scrub_enable = 1; |
| 1100 | schedule_delayed_work(&(priv->i5100_scrubbing), |
| 1101 | I5100_SCRUB_REFRESH_RATE); |
| 1102 | } |
| 1103 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1104 | i5100_init_dimm_layout(pdev, mci); |
| 1105 | i5100_init_interleaving(pdev, mci); |
| 1106 | |
| 1107 | mci->mtype_cap = MEM_FLAG_FB_DDR2; |
| 1108 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; |
| 1109 | mci->edac_cap = EDAC_FLAG_SECDED; |
| 1110 | mci->mod_name = "i5100_edac.c"; |
| 1111 | mci->mod_ver = "not versioned"; |
| 1112 | mci->ctl_name = "i5100"; |
| 1113 | mci->dev_name = pci_name(pdev); |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1114 | mci->ctl_page_to_phys = NULL; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1115 | |
| 1116 | mci->edac_check = i5100_check_error; |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1117 | mci->set_sdram_scrub_rate = i5100_set_scrub_rate; |
| 1118 | mci->get_sdram_scrub_rate = i5100_get_scrub_rate; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1119 | |
Niklas Söderlund | 53ceafd | 2012-08-08 12:30:57 -0300 | [diff] [blame] | 1120 | priv->inject_channel = 0; |
| 1121 | priv->inject_hlinesel = 0; |
| 1122 | priv->inject_deviceptr1 = 0; |
| 1123 | priv->inject_deviceptr2 = 0; |
| 1124 | priv->inject_eccmask1 = 0; |
| 1125 | priv->inject_eccmask2 = 0; |
| 1126 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1127 | i5100_init_csrows(mci); |
| 1128 | |
| 1129 | /* this strange construction seems to be in every driver, dunno why */ |
| 1130 | switch (edac_op_state) { |
| 1131 | case EDAC_OPSTATE_POLL: |
| 1132 | case EDAC_OPSTATE_NMI: |
| 1133 | break; |
| 1134 | default: |
| 1135 | edac_op_state = EDAC_OPSTATE_POLL; |
| 1136 | break; |
| 1137 | } |
| 1138 | |
| 1139 | if (edac_mc_add_mc(mci)) { |
| 1140 | ret = -ENODEV; |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1141 | goto bail_scrub; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1142 | } |
| 1143 | |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 1144 | i5100_setup_debugfs(mci); |
| 1145 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1146 | return ret; |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1147 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1148 | bail_scrub: |
| 1149 | priv->scrub_enable = 0; |
| 1150 | cancel_delayed_work_sync(&(priv->i5100_scrubbing)); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1151 | edac_mc_free(mci); |
| 1152 | |
Niklas Söderlund | 52608ba | 2012-08-08 12:30:56 -0300 | [diff] [blame] | 1153 | bail_disable_einj: |
| 1154 | pci_disable_device(einj); |
| 1155 | |
| 1156 | bail_einj: |
| 1157 | pci_dev_put(einj); |
| 1158 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1159 | bail_disable_ch1: |
| 1160 | pci_disable_device(ch1mm); |
| 1161 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1162 | bail_ch1: |
| 1163 | pci_dev_put(ch1mm); |
| 1164 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1165 | bail_disable_ch0: |
| 1166 | pci_disable_device(ch0mm); |
| 1167 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1168 | bail_ch0: |
| 1169 | pci_dev_put(ch0mm); |
| 1170 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1171 | bail_pdev: |
| 1172 | pci_disable_device(pdev); |
| 1173 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1174 | bail: |
| 1175 | return ret; |
| 1176 | } |
| 1177 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 1178 | static void i5100_remove_one(struct pci_dev *pdev) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1179 | { |
| 1180 | struct mem_ctl_info *mci; |
| 1181 | struct i5100_priv *priv; |
| 1182 | |
| 1183 | mci = edac_mc_del_mc(&pdev->dev); |
| 1184 | |
| 1185 | if (!mci) |
| 1186 | return; |
| 1187 | |
| 1188 | priv = mci->pvt_info; |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1189 | |
Borislav Petkov | 52019e4 | 2015-09-22 12:36:15 +0200 | [diff] [blame] | 1190 | edac_debugfs_remove_recursive(priv->debugfs); |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 1191 | |
Nils Carlson | 295439f | 2009-12-15 16:47:42 -0800 | [diff] [blame] | 1192 | priv->scrub_enable = 0; |
| 1193 | cancel_delayed_work_sync(&(priv->i5100_scrubbing)); |
| 1194 | |
Arthur Jones | b238e57 | 2008-07-25 01:49:08 -0700 | [diff] [blame] | 1195 | pci_disable_device(pdev); |
| 1196 | pci_disable_device(priv->ch0mm); |
| 1197 | pci_disable_device(priv->ch1mm); |
Niklas Söderlund | 52608ba | 2012-08-08 12:30:56 -0300 | [diff] [blame] | 1198 | pci_disable_device(priv->einj); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1199 | pci_dev_put(priv->ch0mm); |
| 1200 | pci_dev_put(priv->ch1mm); |
Niklas Söderlund | 52608ba | 2012-08-08 12:30:56 -0300 | [diff] [blame] | 1201 | pci_dev_put(priv->einj); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1202 | |
| 1203 | edac_mc_free(mci); |
| 1204 | } |
| 1205 | |
Jingoo Han | ba935f4 | 2013-12-06 10:23:08 +0100 | [diff] [blame] | 1206 | static const struct pci_device_id i5100_pci_tbl[] = { |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1207 | /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */ |
| 1208 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) }, |
| 1209 | { 0, } |
| 1210 | }; |
| 1211 | MODULE_DEVICE_TABLE(pci, i5100_pci_tbl); |
| 1212 | |
| 1213 | static struct pci_driver i5100_driver = { |
| 1214 | .name = KBUILD_BASENAME, |
| 1215 | .probe = i5100_init_one, |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 1216 | .remove = i5100_remove_one, |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1217 | .id_table = i5100_pci_tbl, |
| 1218 | }; |
| 1219 | |
| 1220 | static int __init i5100_init(void) |
| 1221 | { |
| 1222 | int pci_rc; |
| 1223 | |
Borislav Petkov | 52019e4 | 2015-09-22 12:36:15 +0200 | [diff] [blame] | 1224 | i5100_debugfs = edac_debugfs_create_dir_at("i5100_edac", NULL); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1225 | |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 1226 | pci_rc = pci_register_driver(&i5100_driver); |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1227 | return (pci_rc < 0) ? pci_rc : 0; |
| 1228 | } |
| 1229 | |
| 1230 | static void __exit i5100_exit(void) |
| 1231 | { |
Borislav Petkov | 52019e4 | 2015-09-22 12:36:15 +0200 | [diff] [blame] | 1232 | edac_debugfs_remove(i5100_debugfs); |
Niklas Söderlund | 9cbc6d3 | 2012-08-08 12:30:58 -0300 | [diff] [blame] | 1233 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1234 | pci_unregister_driver(&i5100_driver); |
| 1235 | } |
| 1236 | |
| 1237 | module_init(i5100_init); |
| 1238 | module_exit(i5100_exit); |
| 1239 | |
| 1240 | MODULE_LICENSE("GPL"); |
| 1241 | MODULE_AUTHOR |
| 1242 | ("Arthur Jones <ajones@riverbed.com>"); |
| 1243 | MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers"); |