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Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -07001/*
David Woodhouse2f26e0a2015-09-09 11:40:47 +01002 * Copyright © 2006-2015, Intel Corporation.
3 *
4 * Authors: Ashok Raj <ashok.raj@intel.com>
5 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
6 * David Woodhouse <David.Woodhouse@intel.com>
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -07007 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070020 */
21
22#ifndef _INTEL_IOMMU_H_
23#define _INTEL_IOMMU_H_
24
25#include <linux/types.h>
Kay, Allen M38717942008-09-09 18:37:29 +030026#include <linux/iova.h>
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070027#include <linux/io.h>
David Woodhouse2f26e0a2015-09-09 11:40:47 +010028#include <linux/idr.h>
Kay, Allen M38717942008-09-09 18:37:29 +030029#include <linux/dma_remapping.h>
David Woodhouse2f26e0a2015-09-09 11:40:47 +010030#include <linux/mmu_notifier.h>
31#include <linux/list.h>
Joerg Roedelb0119e82017-02-01 13:23:08 +010032#include <linux/iommu.h>
Andy Shevchenko61012982017-03-16 16:23:55 +020033#include <linux/io-64-nonatomic-lo-hi.h>
34
Suresh Siddhafe962e92008-07-10 11:16:42 -070035#include <asm/cacheflush.h>
Fenghua Yu5b6985c2008-10-16 18:02:32 -070036#include <asm/iommu.h>
David Millerf6611972008-02-06 01:36:23 -080037
38/*
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070039 * Intel IOMMU register specification per version 1.0 public spec.
40 */
41
42#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
43#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
44#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
45#define DMAR_GCMD_REG 0x18 /* Global command register */
46#define DMAR_GSTS_REG 0x1c /* Global status register */
47#define DMAR_RTADDR_REG 0x20 /* Root entry table */
48#define DMAR_CCMD_REG 0x28 /* Context command reg */
49#define DMAR_FSTS_REG 0x34 /* Fault Status register */
50#define DMAR_FECTL_REG 0x38 /* Fault control register */
51#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
52#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
53#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
54#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
55#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
56#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
57#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
58#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
59#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
Suresh Siddhafe962e92008-07-10 11:16:42 -070060#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
61#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
Yu Zhao6ba6c3a2009-05-18 13:51:35 +080062#define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
Suresh Siddhafe962e92008-07-10 11:16:42 -070063#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
Li, Zhen-Hua82aeef02013-09-13 14:27:32 +080064#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
Suresh Siddha2ae21012008-07-10 11:16:43 -070065#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
David Woodhouse12082252015-10-07 15:37:03 +010066#define DMAR_PQH_REG 0xc0 /* Page request queue head register */
67#define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
68#define DMAR_PQA_REG 0xd0 /* Page request queue address register */
69#define DMAR_PRS_REG 0xdc /* Page request status register */
70#define DMAR_PECTL_REG 0xe0 /* Page request event control register */
71#define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
72#define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
73#define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070074
75#define OFFSET_STRIDE (9)
David Woodhouse50d3fb52015-10-13 20:48:21 +010076
David Woodhouse50d3fb52015-10-13 20:48:21 +010077#define dmar_readq(a) readq(a)
78#define dmar_writeq(a,v) writeq(v,a)
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070079
80#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
81#define DMAR_VER_MINOR(v) ((v) & 0x0f)
82
83/*
84 * Decoding Capability Register
85 */
Feng Wu07c09782015-06-09 13:20:34 +080086#define cap_pi_support(c) (((c) >> 59) & 1)
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070087#define cap_read_drain(c) (((c) >> 55) & 1)
88#define cap_write_drain(c) (((c) >> 54) & 1)
89#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
90#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
91#define cap_pgsel_inv(c) (((c) >> 39) & 1)
92
93#define cap_super_page_val(c) (((c) >> 34) & 0xf)
94#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
95 * OFFSET_STRIDE) + 21)
96
97#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
98#define cap_max_fault_reg_offset(c) \
99 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
100
101#define cap_zlr(c) (((c) >> 22) & 1)
102#define cap_isoch(c) (((c) >> 23) & 1)
103#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
104#define cap_sagaw(c) (((c) >> 8) & 0x1f)
105#define cap_caching_mode(c) (((c) >> 7) & 1)
106#define cap_phmr(c) (((c) >> 6) & 1)
107#define cap_plmr(c) (((c) >> 5) & 1)
108#define cap_rwbf(c) (((c) >> 4) & 1)
109#define cap_afl(c) (((c) >> 3) & 1)
110#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
111/*
112 * Extended Capability Register
113 */
114
David Woodhousebd00c602015-06-09 15:06:55 +0100115#define ecap_pasid(e) ((e >> 40) & 0x1)
David Woodhouse4423f5e2015-03-25 15:43:39 +0000116#define ecap_pss(e) ((e >> 35) & 0x1f)
117#define ecap_eafs(e) ((e >> 34) & 0x1)
118#define ecap_nwfs(e) ((e >> 33) & 0x1)
119#define ecap_srs(e) ((e >> 31) & 0x1)
120#define ecap_ers(e) ((e >> 30) & 0x1)
121#define ecap_prs(e) ((e >> 29) & 0x1)
David Woodhouseae853dd2015-09-09 11:58:59 +0100122#define ecap_broken_pasid(e) ((e >> 28) & 0x1)
David Woodhouse4423f5e2015-03-25 15:43:39 +0000123#define ecap_dis(e) ((e >> 27) & 0x1)
124#define ecap_nest(e) ((e >> 26) & 0x1)
125#define ecap_mts(e) ((e >> 25) & 0x1)
126#define ecap_ecs(e) ((e >> 24) & 0x1)
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700127#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
David Woodhouse44caf2f2015-02-13 14:25:24 +0000128#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700129#define ecap_coherent(e) ((e) & 0x1)
Suresh Siddhafe962e92008-07-10 11:16:42 -0700130#define ecap_qis(e) ((e) & 0x2)
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -0700131#define ecap_pass_through(e) ((e >> 6) & 0x1)
Suresh Siddhaad3ad3f2008-07-10 11:16:40 -0700132#define ecap_eim_support(e) ((e >> 4) & 0x1)
133#define ecap_ir_support(e) ((e >> 3) & 0x1)
Yu Zhao93a23a72009-05-18 13:51:37 +0800134#define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700135#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
Sheng Yang58c610b2009-03-18 15:33:05 +0800136#define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700137
138/* IOTLB_REG */
Youquan Song3481f212008-10-16 16:31:55 -0700139#define DMA_TLB_FLUSH_GRANU_OFFSET 60
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700140#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
141#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
142#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
CQ Tangaaa59302017-01-30 09:39:52 -0800143#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
144#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700145#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
146#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
147#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
148#define DMA_TLB_IVT (((u64)1) << 63)
149#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
150#define DMA_TLB_MAX_SIZE (0x3f)
151
Suresh Siddhafe962e92008-07-10 11:16:42 -0700152/* INVALID_DESC */
Youquan Song3481f212008-10-16 16:31:55 -0700153#define DMA_CCMD_INVL_GRANU_OFFSET 61
CQ Tangaaa59302017-01-30 09:39:52 -0800154#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
155#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
156#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
Suresh Siddhafe962e92008-07-10 11:16:42 -0700157#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
158#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
159#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
160#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
161#define DMA_ID_TLB_ADDR(addr) (addr)
162#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
163
mark grossf8bab732008-02-08 04:18:38 -0800164/* PMEN_REG */
165#define DMA_PMEN_EPM (((u32)1)<<31)
166#define DMA_PMEN_PRS (((u32)1)<<0)
167
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700168/* GCMD_REG */
169#define DMA_GCMD_TE (((u32)1) << 31)
170#define DMA_GCMD_SRTP (((u32)1) << 30)
171#define DMA_GCMD_SFL (((u32)1) << 29)
172#define DMA_GCMD_EAFL (((u32)1) << 28)
173#define DMA_GCMD_WBF (((u32)1) << 27)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700174#define DMA_GCMD_QIE (((u32)1) << 26)
175#define DMA_GCMD_SIRTP (((u32)1) << 24)
176#define DMA_GCMD_IRE (((u32) 1) << 25)
Han, Weidong161fde02009-04-03 17:15:47 +0800177#define DMA_GCMD_CFI (((u32) 1) << 23)
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700178
179/* GSTS_REG */
180#define DMA_GSTS_TES (((u32)1) << 31)
181#define DMA_GSTS_RTPS (((u32)1) << 30)
182#define DMA_GSTS_FLS (((u32)1) << 29)
183#define DMA_GSTS_AFLS (((u32)1) << 28)
184#define DMA_GSTS_WBFS (((u32)1) << 27)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700185#define DMA_GSTS_QIES (((u32)1) << 26)
186#define DMA_GSTS_IRTPS (((u32)1) << 24)
187#define DMA_GSTS_IRES (((u32)1) << 25)
Han, Weidong161fde02009-04-03 17:15:47 +0800188#define DMA_GSTS_CFIS (((u32)1) << 23)
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700189
David Woodhouse4423f5e2015-03-25 15:43:39 +0000190/* DMA_RTADDR_REG */
191#define DMA_RTADDR_RTT (((u64)1) << 11)
192
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700193/* CCMD_REG */
194#define DMA_CCMD_ICC (((u64)1) << 63)
195#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
196#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
197#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
198#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
199#define DMA_CCMD_MASK_NOBIT 0
200#define DMA_CCMD_MASK_1BIT 1
201#define DMA_CCMD_MASK_2BIT 2
202#define DMA_CCMD_MASK_3BIT 3
203#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
204#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
205
206/* FECTL_REG */
207#define DMA_FECTL_IM (((u32)1) << 31)
208
209/* FSTS_REG */
210#define DMA_FSTS_PPF ((u32)2)
211#define DMA_FSTS_PFO ((u32)1)
Yu Zhao704126a2009-01-04 16:28:52 +0800212#define DMA_FSTS_IQE (1 << 4)
Yu Zhao6ba6c3a2009-05-18 13:51:35 +0800213#define DMA_FSTS_ICE (1 << 5)
214#define DMA_FSTS_ITE (1 << 6)
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700215#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
216
217/* FRCD_REG, 32 bits access */
218#define DMA_FRCD_F (((u32)1) << 31)
219#define dma_frcd_type(d) ((d >> 30) & 1)
220#define dma_frcd_fault_reason(c) (c & 0xff)
221#define dma_frcd_source_id(c) (c & 0xffff)
Fenghua Yu5b6985c2008-10-16 18:02:32 -0700222/* low 64 bit */
223#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700224
David Woodhouse46924002016-02-15 12:42:38 +0000225/* PRS_REG */
226#define DMA_PRS_PPR ((u32)1)
227
Fenghua Yu5b6985c2008-10-16 18:02:32 -0700228#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
229do { \
230 cycles_t start_time = get_cycles(); \
231 while (1) { \
232 sts = op(iommu->reg + offset); \
233 if (cond) \
234 break; \
Suresh Siddhacf1337f2008-07-10 11:16:41 -0700235 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
Fenghua Yu5b6985c2008-10-16 18:02:32 -0700236 panic("DMAR hardware is malfunctioning\n"); \
237 cpu_relax(); \
238 } \
239} while (0)
Suresh Siddhacf1337f2008-07-10 11:16:41 -0700240
Suresh Siddhafe962e92008-07-10 11:16:42 -0700241#define QI_LENGTH 256 /* queue length */
242
243enum {
244 QI_FREE,
245 QI_IN_USE,
Yu Zhao6ba6c3a2009-05-18 13:51:35 +0800246 QI_DONE,
247 QI_ABORT
Suresh Siddhafe962e92008-07-10 11:16:42 -0700248};
249
250#define QI_CC_TYPE 0x1
251#define QI_IOTLB_TYPE 0x2
252#define QI_DIOTLB_TYPE 0x3
253#define QI_IEC_TYPE 0x4
254#define QI_IWD_TYPE 0x5
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100255#define QI_EIOTLB_TYPE 0x6
256#define QI_PC_TYPE 0x7
257#define QI_DEIOTLB_TYPE 0x8
David Woodhousea222a7f2015-10-07 23:35:18 +0100258#define QI_PGRP_RESP_TYPE 0x9
259#define QI_PSTRM_RESP_TYPE 0xa
Suresh Siddhafe962e92008-07-10 11:16:42 -0700260
261#define QI_IEC_SELECTIVE (((u64)1) << 4)
262#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
263#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
264
265#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
266#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
267
Youquan Song3481f212008-10-16 16:31:55 -0700268#define QI_IOTLB_DID(did) (((u64)did) << 16)
269#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
270#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
271#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
Fenghua Yu5b6985c2008-10-16 18:02:32 -0700272#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
Youquan Song3481f212008-10-16 16:31:55 -0700273#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
274#define QI_IOTLB_AM(am) (((u8)am))
275
276#define QI_CC_FM(fm) (((u64)fm) << 48)
277#define QI_CC_SID(sid) (((u64)sid) << 32)
278#define QI_CC_DID(did) (((u64)did) << 16)
279#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
280
Yu Zhao6ba6c3a2009-05-18 13:51:35 +0800281#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
282#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
283#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
284#define QI_DEV_IOTLB_SIZE 1
285#define QI_DEV_IOTLB_MAX_INVS 32
286
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100287#define QI_PC_PASID(pasid) (((u64)pasid) << 32)
288#define QI_PC_DID(did) (((u64)did) << 16)
289#define QI_PC_GRAN(gran) (((u64)gran) << 4)
290
291#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
292#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
293
294#define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
295#define QI_EIOTLB_GL(gl) (((u64)gl) << 7)
296#define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
297#define QI_EIOTLB_AM(am) (((u64)am))
298#define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
299#define QI_EIOTLB_DID(did) (((u64)did) << 16)
300#define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
301
302#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
303#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
304#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
305#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
CQ Tangaaa59302017-01-30 09:39:52 -0800306#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
307#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100308#define QI_DEV_EIOTLB_MAX_INVS 32
309
David Woodhousea222a7f2015-10-07 23:35:18 +0100310#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
311#define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
312#define QI_PGRP_RESP_CODE(res) ((u64)(res))
313#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
314#define QI_PGRP_DID(did) (((u64)(did)) << 16)
315#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
316
317#define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
318#define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
319#define QI_PSTRM_RESP_CODE(res) ((u64)(res))
320#define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
321#define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
322#define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
323#define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
324
325#define QI_RESP_SUCCESS 0x0
326#define QI_RESP_INVALID 0x1
327#define QI_RESP_FAILURE 0xf
328
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100329#define QI_GRAN_ALL_ALL 0
330#define QI_GRAN_NONG_ALL 1
331#define QI_GRAN_NONG_PASID 2
332#define QI_GRAN_PSI_PASID 3
333
Suresh Siddhafe962e92008-07-10 11:16:42 -0700334struct qi_desc {
335 u64 low, high;
336};
337
338struct q_inval {
Thomas Gleixner3b8f4042011-07-19 17:02:07 +0200339 raw_spinlock_t q_lock;
Suresh Siddhafe962e92008-07-10 11:16:42 -0700340 struct qi_desc *desc; /* invalidation queue */
341 int *desc_status; /* desc status */
342 int free_head; /* first free entry */
343 int free_tail; /* last free entry */
344 int free_cnt;
345};
346
Suresh Siddhad3f13812011-08-23 17:05:25 -0700347#ifdef CONFIG_IRQ_REMAP
Suresh Siddha2ae21012008-07-10 11:16:43 -0700348/* 1MB - maximum possible interrupt remapping table size */
349#define INTR_REMAP_PAGE_ORDER 8
350#define INTR_REMAP_TABLE_REG_SIZE 0xf
Joerg Roedelaf3b3582015-06-12 15:00:21 +0200351#define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
Suresh Siddha2ae21012008-07-10 11:16:43 -0700352
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700353#define INTR_REMAP_TABLE_ENTRIES 65536
354
Jiang Liub106ee62015-04-13 14:11:32 +0800355struct irq_domain;
356
Suresh Siddha2ae21012008-07-10 11:16:43 -0700357struct ir_table {
358 struct irte *base;
Jiang Liu360eb3c2014-01-06 14:18:08 +0800359 unsigned long *bitmap;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700360};
361#endif
362
Youquan Songa77b67d2008-10-16 16:31:56 -0700363struct iommu_flush {
David Woodhouse4c25a2c2009-05-10 17:16:06 +0100364 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
365 u8 fm, u64 type);
David Woodhouse1f0ef2a2009-05-10 19:58:49 +0100366 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
367 unsigned int size_order, u64 type);
Youquan Songa77b67d2008-10-16 16:31:56 -0700368};
369
Fenghua Yuf59c7b62009-03-27 14:22:42 -0700370enum {
371 SR_DMAR_FECTL_REG,
372 SR_DMAR_FEDATA_REG,
373 SR_DMAR_FEADDR_REG,
374 SR_DMAR_FEUADDR_REG,
375 MAX_SR_DMAR_REGS
376};
377
Joerg Roedel4158c2e2015-06-12 10:14:02 +0200378#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
379#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
380
David Woodhouse8a94ade2015-03-24 14:54:56 +0000381struct pasid_entry;
382struct pasid_state_entry;
David Woodhousea222a7f2015-10-07 23:35:18 +0100383struct page_req_dsc;
David Woodhouse8a94ade2015-03-24 14:54:56 +0000384
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700385struct intel_iommu {
386 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
Donald Dutile6f5cf522012-06-04 17:29:02 -0400387 u64 reg_phys; /* physical address of hw register set */
388 u64 reg_size; /* size of hw register set */
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700389 u64 cap;
390 u64 ecap;
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700391 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
Thomas Gleixner1f5b3c32011-07-19 16:19:51 +0200392 raw_spinlock_t register_lock; /* protect register handling */
Suresh Siddhac42d9f32008-07-10 11:16:36 -0700393 int seq_id; /* sequence id of the iommu */
Weidong Han1b573682008-12-08 15:34:06 +0800394 int agaw; /* agaw of this iommu */
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -0700395 int msagaw; /* max sagaw of this iommu */
David Woodhouse12082252015-10-07 15:37:03 +0100396 unsigned int irq, pr_irq;
David Woodhouse67ccac42014-03-09 13:49:45 -0700397 u16 segment; /* PCI segment# */
Suresh Siddha9d783ba2009-03-16 17:04:55 -0700398 unsigned char name[13]; /* Device Name */
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700399
Suresh Siddhad3f13812011-08-23 17:05:25 -0700400#ifdef CONFIG_INTEL_IOMMU
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700401 unsigned long *domain_ids; /* bitmap of domains */
Joerg Roedel8bf47812015-07-21 10:41:21 +0200402 struct dmar_domain ***domains; /* ptr to domains */
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700403 spinlock_t lock; /* protect context, domain ids */
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700404 struct root_entry *root_entry; /* virtual address */
405
Youquan Songa77b67d2008-10-16 16:31:56 -0700406 struct iommu_flush flush;
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700407#endif
David Woodhouse8a94ade2015-03-24 14:54:56 +0000408#ifdef CONFIG_INTEL_IOMMU_SVM
409 /* These are large and need to be contiguous, so we allocate just
410 * one for now. We'll maybe want to rethink that if we truly give
411 * devices away to userspace processes (e.g. for DPDK) and don't
412 * want to trust that userspace will use *only* the PASID it was
413 * told to. But while it's all driver-arbitrated, we're fine. */
414 struct pasid_entry *pasid_table;
415 struct pasid_state_entry *pasid_state_table;
David Woodhousea222a7f2015-10-07 23:35:18 +0100416 struct page_req_dsc *prq;
417 unsigned char prq_name[16]; /* Name for PRQ interrupt */
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100418 struct idr pasid_idr;
David Woodhouse91017042016-09-12 10:49:11 +0800419 u32 pasid_max;
David Woodhouse8a94ade2015-03-24 14:54:56 +0000420#endif
Suresh Siddhafe962e92008-07-10 11:16:42 -0700421 struct q_inval *qi; /* Queued invalidation info */
Fenghua Yuf59c7b62009-03-27 14:22:42 -0700422 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
423
Suresh Siddhad3f13812011-08-23 17:05:25 -0700424#ifdef CONFIG_IRQ_REMAP
Suresh Siddha2ae21012008-07-10 11:16:43 -0700425 struct ir_table *ir_table; /* Interrupt remapping info */
Jiang Liub106ee62015-04-13 14:11:32 +0800426 struct irq_domain *ir_domain;
427 struct irq_domain *ir_msi_domain;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700428#endif
Joerg Roedelb0119e82017-02-01 13:23:08 +0100429 struct iommu_device iommu; /* IOMMU core code handle */
Suresh Siddhaee34b322009-10-02 11:01:21 -0700430 int node;
Joerg Roedel4158c2e2015-06-12 10:14:02 +0200431 u32 flags; /* Software defined flags */
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700432};
433
Suresh Siddhafe962e92008-07-10 11:16:42 -0700434static inline void __iommu_flush_cache(
435 struct intel_iommu *iommu, void *addr, int size)
436{
437 if (!ecap_coherent(iommu->ecap))
438 clflush_cache_range(addr, size);
439}
440
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700441extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800442extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
Suresh Siddhae61d98d2008-07-10 11:16:35 -0700443
Suresh Siddha2ae21012008-07-10 11:16:43 -0700444extern int dmar_enable_qi(struct intel_iommu *iommu);
Suresh Siddhaeba67e52009-03-16 17:04:56 -0700445extern void dmar_disable_qi(struct intel_iommu *iommu);
Fenghua Yuf59c7b62009-03-27 14:22:42 -0700446extern int dmar_reenable_qi(struct intel_iommu *iommu);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700447extern void qi_global_iec(struct intel_iommu *iommu);
Keshavamurthy, Anil Se8204822007-10-21 16:41:55 -0700448
David Woodhouse4c25a2c2009-05-10 17:16:06 +0100449extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
450 u8 fm, u64 type);
David Woodhouse1f0ef2a2009-05-10 19:58:49 +0100451extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
452 unsigned int size_order, u64 type);
Yu Zhao6ba6c3a2009-05-18 13:51:35 +0800453extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
454 u64 addr, unsigned mask);
Youquan Song3481f212008-10-16 16:31:55 -0700455
Yu Zhao704126a2009-01-04 16:28:52 +0800456extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
Kay, Allen M38717942008-09-09 18:37:29 +0300457
Youquan Song074835f2009-09-09 12:05:39 -0400458extern int dmar_ir_support(void);
459
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100460#ifdef CONFIG_INTEL_IOMMU_SVM
David Woodhouse8a94ade2015-03-24 14:54:56 +0000461extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
462extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
David Woodhousea222a7f2015-10-07 23:35:18 +0100463extern int intel_svm_enable_prq(struct intel_iommu *iommu);
464extern int intel_svm_finish_prq(struct intel_iommu *iommu);
David Woodhouse8a94ade2015-03-24 14:54:56 +0000465
David Woodhouse0204a492015-10-13 17:18:10 +0100466struct svm_dev_ops;
467
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100468struct intel_svm_dev {
469 struct list_head list;
470 struct rcu_head rcu;
471 struct device *dev;
David Woodhouse0204a492015-10-13 17:18:10 +0100472 struct svm_dev_ops *ops;
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100473 int users;
474 u16 did;
475 u16 dev_iotlb:1;
476 u16 sid, qdep;
477};
478
479struct intel_svm {
480 struct mmu_notifier notifier;
481 struct mm_struct *mm;
482 struct intel_iommu *iommu;
David Woodhouse569e4f72015-10-15 13:59:14 +0100483 int flags;
David Woodhouse2f26e0a2015-09-09 11:40:47 +0100484 int pasid;
485 struct list_head devs;
486};
487
488extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev);
489extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
490#endif
491
Alex Williamsona5459cf2014-06-12 16:12:31 -0600492extern const struct attribute_group *intel_iommu_groups[];
493
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700494#endif