Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
| 3 | * |
| 4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
| 5 | * David Mosberger-Tang |
| 6 | * |
| 7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/pci.h> |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 14 | #include <linux/pm.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 15 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <linux/module.h> |
| 17 | #include <linux/spinlock.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 18 | #include <linux/string.h> |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 19 | #include <linux/log2.h> |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 20 | #include <linux/pci-aspm.h> |
Stephen Rothwell | c300bd2fb | 2008-07-10 02:16:44 +0200 | [diff] [blame] | 21 | #include <linux/pm_wakeup.h> |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 22 | #include <linux/interrupt.h> |
Yuji Shimada | 32a9a682 | 2009-03-16 17:13:39 +0900 | [diff] [blame] | 23 | #include <linux/device.h> |
Rafael J. Wysocki | b67ea76 | 2010-02-17 23:44:09 +0100 | [diff] [blame] | 24 | #include <linux/pm_runtime.h> |
Yuji Shimada | 32a9a682 | 2009-03-16 17:13:39 +0900 | [diff] [blame] | 25 | #include <asm/setup.h> |
Greg KH | bc56b9e | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 26 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | |
Alan Stern | 00240c3 | 2009-04-27 13:33:16 -0400 | [diff] [blame] | 28 | const char *pci_power_names[] = { |
| 29 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", |
| 30 | }; |
| 31 | EXPORT_SYMBOL_GPL(pci_power_names); |
| 32 | |
Rafael J. Wysocki | 93177a7 | 2010-01-02 22:57:24 +0100 | [diff] [blame] | 33 | int isa_dma_bridge_buggy; |
| 34 | EXPORT_SYMBOL(isa_dma_bridge_buggy); |
| 35 | |
| 36 | int pci_pci_problems; |
| 37 | EXPORT_SYMBOL(pci_pci_problems); |
| 38 | |
Rafael J. Wysocki | 1ae861e | 2009-12-31 12:15:54 +0100 | [diff] [blame] | 39 | unsigned int pci_pm_d3_delay; |
| 40 | |
Matthew Garrett | df17e62 | 2010-10-04 14:22:29 -0400 | [diff] [blame] | 41 | static void pci_pme_list_scan(struct work_struct *work); |
| 42 | |
| 43 | static LIST_HEAD(pci_pme_list); |
| 44 | static DEFINE_MUTEX(pci_pme_list_mutex); |
| 45 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); |
| 46 | |
| 47 | struct pci_pme_device { |
| 48 | struct list_head list; |
| 49 | struct pci_dev *dev; |
| 50 | }; |
| 51 | |
| 52 | #define PME_TIMEOUT 1000 /* How long between PME checks */ |
| 53 | |
Rafael J. Wysocki | 1ae861e | 2009-12-31 12:15:54 +0100 | [diff] [blame] | 54 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
| 55 | { |
| 56 | unsigned int delay = dev->d3_delay; |
| 57 | |
| 58 | if (delay < pci_pm_d3_delay) |
| 59 | delay = pci_pm_d3_delay; |
| 60 | |
| 61 | msleep(delay); |
| 62 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 64 | #ifdef CONFIG_PCI_DOMAINS |
| 65 | int pci_domains_supported = 1; |
| 66 | #endif |
| 67 | |
Atsushi Nemoto | 4516a61 | 2007-02-05 16:36:06 -0800 | [diff] [blame] | 68 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
| 69 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) |
| 70 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ |
| 71 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; |
| 72 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; |
| 73 | |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 74 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
| 75 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) |
| 76 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ |
| 77 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; |
| 78 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; |
| 79 | |
Jon Mason | 5f39e67 | 2011-10-03 09:50:20 -0500 | [diff] [blame] | 80 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 81 | |
Jesse Barnes | ac1aa47 | 2009-10-26 13:20:44 -0700 | [diff] [blame] | 82 | /* |
| 83 | * The default CLS is used if arch didn't set CLS explicitly and not |
| 84 | * all pci devices agree on the same value. Arch can override either |
| 85 | * the dfl or actual value as it sees fit. Don't forget this is |
| 86 | * measured in 32-bit words, not bytes. |
| 87 | */ |
Tejun Heo | 98e724c | 2009-10-08 18:59:53 +0900 | [diff] [blame] | 88 | u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; |
Jesse Barnes | ac1aa47 | 2009-10-26 13:20:44 -0700 | [diff] [blame] | 89 | u8 pci_cache_line_size; |
| 90 | |
Myron Stowe | 96c5590 | 2011-10-28 15:48:38 -0600 | [diff] [blame] | 91 | /* |
| 92 | * If we set up a device for bus mastering, we need to check the latency |
| 93 | * timer as certain BIOSes forget to set it properly. |
| 94 | */ |
| 95 | unsigned int pcibios_max_latency = 255; |
| 96 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | /** |
| 98 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children |
| 99 | * @bus: pointer to PCI bus structure to search |
| 100 | * |
| 101 | * Given a PCI bus, returns the highest PCI bus number present in the set |
| 102 | * including the given PCI bus and its list of child PCI buses. |
| 103 | */ |
Sam Ravnborg | 96bde06 | 2007-03-26 21:53:30 -0800 | [diff] [blame] | 104 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | { |
| 106 | struct list_head *tmp; |
| 107 | unsigned char max, n; |
| 108 | |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 109 | max = bus->subordinate; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | list_for_each(tmp, &bus->children) { |
| 111 | n = pci_bus_max_busnr(pci_bus_b(tmp)); |
| 112 | if(n > max) |
| 113 | max = n; |
| 114 | } |
| 115 | return max; |
| 116 | } |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 117 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | |
Andrew Morton | 1684f5d | 2008-12-01 14:30:30 -0800 | [diff] [blame] | 119 | #ifdef CONFIG_HAS_IOMEM |
| 120 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) |
| 121 | { |
| 122 | /* |
| 123 | * Make sure the BAR is actually a memory resource, not an IO resource |
| 124 | */ |
| 125 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { |
| 126 | WARN_ON(1); |
| 127 | return NULL; |
| 128 | } |
| 129 | return ioremap_nocache(pci_resource_start(pdev, bar), |
| 130 | pci_resource_len(pdev, bar)); |
| 131 | } |
| 132 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); |
| 133 | #endif |
| 134 | |
Kristen Accardi | b82db5c | 2006-01-17 16:56:56 -0800 | [diff] [blame] | 135 | #if 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | /** |
| 137 | * pci_max_busnr - returns maximum PCI bus number |
| 138 | * |
| 139 | * Returns the highest PCI bus number present in the system global list of |
| 140 | * PCI buses. |
| 141 | */ |
| 142 | unsigned char __devinit |
| 143 | pci_max_busnr(void) |
| 144 | { |
| 145 | struct pci_bus *bus = NULL; |
| 146 | unsigned char max, n; |
| 147 | |
| 148 | max = 0; |
| 149 | while ((bus = pci_find_next_bus(bus)) != NULL) { |
| 150 | n = pci_bus_max_busnr(bus); |
| 151 | if(n > max) |
| 152 | max = n; |
| 153 | } |
| 154 | return max; |
| 155 | } |
| 156 | |
Adrian Bunk | 54c762f | 2005-12-22 01:08:52 +0100 | [diff] [blame] | 157 | #endif /* 0 */ |
| 158 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 159 | #define PCI_FIND_CAP_TTL 48 |
| 160 | |
| 161 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, |
| 162 | u8 pos, int cap, int *ttl) |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 163 | { |
| 164 | u8 id; |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 165 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 166 | while ((*ttl)--) { |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 167 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
| 168 | if (pos < 0x40) |
| 169 | break; |
| 170 | pos &= ~3; |
| 171 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, |
| 172 | &id); |
| 173 | if (id == 0xff) |
| 174 | break; |
| 175 | if (id == cap) |
| 176 | return pos; |
| 177 | pos += PCI_CAP_LIST_NEXT; |
| 178 | } |
| 179 | return 0; |
| 180 | } |
| 181 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 182 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
| 183 | u8 pos, int cap) |
| 184 | { |
| 185 | int ttl = PCI_FIND_CAP_TTL; |
| 186 | |
| 187 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); |
| 188 | } |
| 189 | |
Roland Dreier | 24a4e37 | 2005-10-28 17:35:34 -0700 | [diff] [blame] | 190 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
| 191 | { |
| 192 | return __pci_find_next_cap(dev->bus, dev->devfn, |
| 193 | pos + PCI_CAP_LIST_NEXT, cap); |
| 194 | } |
| 195 | EXPORT_SYMBOL_GPL(pci_find_next_capability); |
| 196 | |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 197 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
| 198 | unsigned int devfn, u8 hdr_type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | { |
| 200 | u16 status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | |
| 202 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); |
| 203 | if (!(status & PCI_STATUS_CAP_LIST)) |
| 204 | return 0; |
| 205 | |
| 206 | switch (hdr_type) { |
| 207 | case PCI_HEADER_TYPE_NORMAL: |
| 208 | case PCI_HEADER_TYPE_BRIDGE: |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 209 | return PCI_CAPABILITY_LIST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 210 | case PCI_HEADER_TYPE_CARDBUS: |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 211 | return PCI_CB_CAPABILITY_LIST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | default: |
| 213 | return 0; |
| 214 | } |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 215 | |
| 216 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | /** |
| 220 | * pci_find_capability - query for devices' capabilities |
| 221 | * @dev: PCI device to query |
| 222 | * @cap: capability code |
| 223 | * |
| 224 | * Tell if a device supports a given PCI capability. |
| 225 | * Returns the address of the requested capability structure within the |
| 226 | * device's PCI configuration space or 0 in case the device does not |
| 227 | * support it. Possible values for @cap: |
| 228 | * |
| 229 | * %PCI_CAP_ID_PM Power Management |
| 230 | * %PCI_CAP_ID_AGP Accelerated Graphics Port |
| 231 | * %PCI_CAP_ID_VPD Vital Product Data |
| 232 | * %PCI_CAP_ID_SLOTID Slot Identification |
| 233 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
| 234 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
| 235 | * %PCI_CAP_ID_PCIX PCI-X |
| 236 | * %PCI_CAP_ID_EXP PCI Express |
| 237 | */ |
| 238 | int pci_find_capability(struct pci_dev *dev, int cap) |
| 239 | { |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 240 | int pos; |
| 241 | |
| 242 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); |
| 243 | if (pos) |
| 244 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); |
| 245 | |
| 246 | return pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | /** |
| 250 | * pci_bus_find_capability - query for devices' capabilities |
| 251 | * @bus: the PCI bus to query |
| 252 | * @devfn: PCI device to query |
| 253 | * @cap: capability code |
| 254 | * |
| 255 | * Like pci_find_capability() but works for pci devices that do not have a |
| 256 | * pci_dev structure set up yet. |
| 257 | * |
| 258 | * Returns the address of the requested capability structure within the |
| 259 | * device's PCI configuration space or 0 in case the device does not |
| 260 | * support it. |
| 261 | */ |
| 262 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) |
| 263 | { |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 264 | int pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | u8 hdr_type; |
| 266 | |
| 267 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); |
| 268 | |
Michael Ellerman | d3bac11 | 2006-11-22 18:26:16 +1100 | [diff] [blame] | 269 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
| 270 | if (pos) |
| 271 | pos = __pci_find_next_cap(bus, devfn, pos, cap); |
| 272 | |
| 273 | return pos; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | /** |
| 277 | * pci_find_ext_capability - Find an extended capability |
| 278 | * @dev: PCI device to query |
| 279 | * @cap: capability code |
| 280 | * |
| 281 | * Returns the address of the requested extended capability structure |
| 282 | * within the device's PCI configuration space or 0 if the device does |
| 283 | * not support it. Possible values for @cap: |
| 284 | * |
| 285 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting |
| 286 | * %PCI_EXT_CAP_ID_VC Virtual Channel |
| 287 | * %PCI_EXT_CAP_ID_DSN Device Serial Number |
| 288 | * %PCI_EXT_CAP_ID_PWR Power Budgeting |
| 289 | */ |
| 290 | int pci_find_ext_capability(struct pci_dev *dev, int cap) |
| 291 | { |
| 292 | u32 header; |
Zhao, Yu | 557848c | 2008-10-13 19:18:07 +0800 | [diff] [blame] | 293 | int ttl; |
| 294 | int pos = PCI_CFG_SPACE_SIZE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | |
Zhao, Yu | 557848c | 2008-10-13 19:18:07 +0800 | [diff] [blame] | 296 | /* minimum 8 bytes per capability */ |
| 297 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; |
| 298 | |
| 299 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | return 0; |
| 301 | |
| 302 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
| 303 | return 0; |
| 304 | |
| 305 | /* |
| 306 | * If we have no capabilities, this is indicated by cap ID, |
| 307 | * cap version and next pointer all being 0. |
| 308 | */ |
| 309 | if (header == 0) |
| 310 | return 0; |
| 311 | |
| 312 | while (ttl-- > 0) { |
| 313 | if (PCI_EXT_CAP_ID(header) == cap) |
| 314 | return pos; |
| 315 | |
| 316 | pos = PCI_EXT_CAP_NEXT(header); |
Zhao, Yu | 557848c | 2008-10-13 19:18:07 +0800 | [diff] [blame] | 317 | if (pos < PCI_CFG_SPACE_SIZE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 318 | break; |
| 319 | |
| 320 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
| 321 | break; |
| 322 | } |
| 323 | |
| 324 | return 0; |
| 325 | } |
Brice Goglin | 3a720d7 | 2006-05-23 06:10:01 -0400 | [diff] [blame] | 326 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | |
Jesse Barnes | cf4c43d | 2009-07-15 13:13:00 -0700 | [diff] [blame] | 328 | /** |
| 329 | * pci_bus_find_ext_capability - find an extended capability |
| 330 | * @bus: the PCI bus to query |
| 331 | * @devfn: PCI device to query |
| 332 | * @cap: capability code |
| 333 | * |
| 334 | * Like pci_find_ext_capability() but works for pci devices that do not have a |
| 335 | * pci_dev structure set up yet. |
| 336 | * |
| 337 | * Returns the address of the requested capability structure within the |
| 338 | * device's PCI configuration space or 0 in case the device does not |
| 339 | * support it. |
| 340 | */ |
| 341 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, |
| 342 | int cap) |
| 343 | { |
| 344 | u32 header; |
| 345 | int ttl; |
| 346 | int pos = PCI_CFG_SPACE_SIZE; |
| 347 | |
| 348 | /* minimum 8 bytes per capability */ |
| 349 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; |
| 350 | |
| 351 | if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) |
| 352 | return 0; |
| 353 | if (header == 0xffffffff || header == 0) |
| 354 | return 0; |
| 355 | |
| 356 | while (ttl-- > 0) { |
| 357 | if (PCI_EXT_CAP_ID(header) == cap) |
| 358 | return pos; |
| 359 | |
| 360 | pos = PCI_EXT_CAP_NEXT(header); |
| 361 | if (pos < PCI_CFG_SPACE_SIZE) |
| 362 | break; |
| 363 | |
| 364 | if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) |
| 365 | break; |
| 366 | } |
| 367 | |
| 368 | return 0; |
| 369 | } |
| 370 | |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 371 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
| 372 | { |
| 373 | int rc, ttl = PCI_FIND_CAP_TTL; |
| 374 | u8 cap, mask; |
| 375 | |
| 376 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) |
| 377 | mask = HT_3BIT_CAP_MASK; |
| 378 | else |
| 379 | mask = HT_5BIT_CAP_MASK; |
| 380 | |
| 381 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, |
| 382 | PCI_CAP_ID_HT, &ttl); |
| 383 | while (pos) { |
| 384 | rc = pci_read_config_byte(dev, pos + 3, &cap); |
| 385 | if (rc != PCIBIOS_SUCCESSFUL) |
| 386 | return 0; |
| 387 | |
| 388 | if ((cap & mask) == ht_cap) |
| 389 | return pos; |
| 390 | |
Brice Goglin | 47a4d5b | 2007-01-10 23:15:29 -0800 | [diff] [blame] | 391 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
| 392 | pos + PCI_CAP_LIST_NEXT, |
Michael Ellerman | 687d5fe | 2006-11-22 18:26:18 +1100 | [diff] [blame] | 393 | PCI_CAP_ID_HT, &ttl); |
| 394 | } |
| 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | /** |
| 399 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities |
| 400 | * @dev: PCI device to query |
| 401 | * @pos: Position from which to continue searching |
| 402 | * @ht_cap: Hypertransport capability code |
| 403 | * |
| 404 | * To be used in conjunction with pci_find_ht_capability() to search for |
| 405 | * all capabilities matching @ht_cap. @pos should always be a value returned |
| 406 | * from pci_find_ht_capability(). |
| 407 | * |
| 408 | * NB. To be 100% safe against broken PCI devices, the caller should take |
| 409 | * steps to avoid an infinite loop. |
| 410 | */ |
| 411 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) |
| 412 | { |
| 413 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); |
| 414 | } |
| 415 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); |
| 416 | |
| 417 | /** |
| 418 | * pci_find_ht_capability - query a device's Hypertransport capabilities |
| 419 | * @dev: PCI device to query |
| 420 | * @ht_cap: Hypertransport capability code |
| 421 | * |
| 422 | * Tell if a device supports a given Hypertransport capability. |
| 423 | * Returns an address within the device's PCI configuration space |
| 424 | * or 0 in case the device does not support the request capability. |
| 425 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, |
| 426 | * which has a Hypertransport capability matching @ht_cap. |
| 427 | */ |
| 428 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) |
| 429 | { |
| 430 | int pos; |
| 431 | |
| 432 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); |
| 433 | if (pos) |
| 434 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); |
| 435 | |
| 436 | return pos; |
| 437 | } |
| 438 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); |
| 439 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | /** |
| 441 | * pci_find_parent_resource - return resource region of parent bus of given region |
| 442 | * @dev: PCI device structure contains resources to be searched |
| 443 | * @res: child resource record for which parent is sought |
| 444 | * |
| 445 | * For given resource region of given device, return the resource |
| 446 | * region of parent bus the given region is contained in or where |
| 447 | * it should be allocated from. |
| 448 | */ |
| 449 | struct resource * |
| 450 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) |
| 451 | { |
| 452 | const struct pci_bus *bus = dev->bus; |
| 453 | int i; |
Bjorn Helgaas | 89a74ec | 2010-02-23 10:24:31 -0700 | [diff] [blame] | 454 | struct resource *best = NULL, *r; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 455 | |
Bjorn Helgaas | 89a74ec | 2010-02-23 10:24:31 -0700 | [diff] [blame] | 456 | pci_bus_for_each_resource(bus, r, i) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | if (!r) |
| 458 | continue; |
| 459 | if (res->start && !(res->start >= r->start && res->end <= r->end)) |
| 460 | continue; /* Not contained */ |
| 461 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) |
| 462 | continue; /* Wrong type */ |
| 463 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) |
| 464 | return r; /* Exact match */ |
Linus Torvalds | 8c8def2 | 2009-11-09 12:04:32 -0800 | [diff] [blame] | 465 | /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ |
| 466 | if (r->flags & IORESOURCE_PREFETCH) |
| 467 | continue; |
| 468 | /* .. but we can put a prefetchable resource inside a non-prefetchable one */ |
| 469 | if (!best) |
| 470 | best = r; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | } |
| 472 | return best; |
| 473 | } |
| 474 | |
| 475 | /** |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 476 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) |
| 477 | * @dev: PCI device to have its BARs restored |
| 478 | * |
| 479 | * Restore the BAR values for a given device, so as to make it |
| 480 | * accessible by its driver. |
| 481 | */ |
Adrian Bunk | ad668599 | 2007-10-27 03:06:22 +0200 | [diff] [blame] | 482 | static void |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 483 | pci_restore_bars(struct pci_dev *dev) |
| 484 | { |
Yu Zhao | bc5f5a8 | 2008-11-22 02:40:00 +0800 | [diff] [blame] | 485 | int i; |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 486 | |
Yu Zhao | bc5f5a8 | 2008-11-22 02:40:00 +0800 | [diff] [blame] | 487 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
Yu Zhao | 14add80 | 2008-11-22 02:38:52 +0800 | [diff] [blame] | 488 | pci_update_resource(dev, i); |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 489 | } |
| 490 | |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 491 | static struct pci_platform_pm_ops *pci_platform_pm; |
| 492 | |
| 493 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) |
| 494 | { |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 495 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
| 496 | || !ops->sleep_wake || !ops->can_wakeup) |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 497 | return -EINVAL; |
| 498 | pci_platform_pm = ops; |
| 499 | return 0; |
| 500 | } |
| 501 | |
| 502 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) |
| 503 | { |
| 504 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; |
| 505 | } |
| 506 | |
| 507 | static inline int platform_pci_set_power_state(struct pci_dev *dev, |
| 508 | pci_power_t t) |
| 509 | { |
| 510 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; |
| 511 | } |
| 512 | |
| 513 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
| 514 | { |
| 515 | return pci_platform_pm ? |
| 516 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; |
| 517 | } |
Randy Dunlap | 8f7020d | 2005-10-23 11:57:38 -0700 | [diff] [blame] | 518 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 519 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
| 520 | { |
| 521 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; |
| 522 | } |
| 523 | |
| 524 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
| 525 | { |
| 526 | return pci_platform_pm ? |
| 527 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; |
| 528 | } |
| 529 | |
Rafael J. Wysocki | b67ea76 | 2010-02-17 23:44:09 +0100 | [diff] [blame] | 530 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
| 531 | { |
| 532 | return pci_platform_pm ? |
| 533 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; |
| 534 | } |
| 535 | |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 536 | /** |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 537 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
| 538 | * given PCI device |
| 539 | * @dev: PCI device to handle. |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 540 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | * |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 542 | * RETURN VALUE: |
| 543 | * -EINVAL if the requested state is invalid. |
| 544 | * -EIO if device does not support PCI PM or its PM capabilities register has a |
| 545 | * wrong version, or device doesn't support the requested state. |
| 546 | * 0 if device already is in the requested state. |
| 547 | * 0 if device's power state has been successfully changed. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | */ |
Rafael J. Wysocki | f00a20e | 2009-03-16 22:40:08 +0100 | [diff] [blame] | 549 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 551 | u16 pmcsr; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 552 | bool need_restore = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | |
Rafael J. Wysocki | 4a86590 | 2009-03-16 22:40:36 +0100 | [diff] [blame] | 554 | /* Check if we're already there */ |
| 555 | if (dev->current_state == state) |
| 556 | return 0; |
| 557 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 558 | if (!dev->pm_cap) |
Andrew Lunn | cca03de | 2007-07-09 11:55:58 -0700 | [diff] [blame] | 559 | return -EIO; |
| 560 | |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 561 | if (state < PCI_D0 || state > PCI_D3hot) |
| 562 | return -EINVAL; |
| 563 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 564 | /* Validate current state: |
| 565 | * Can enter D0 from any state, but if we can only go deeper |
| 566 | * to sleep if we're already in a low power state |
| 567 | */ |
Rafael J. Wysocki | 4a86590 | 2009-03-16 22:40:36 +0100 | [diff] [blame] | 568 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 569 | && dev->current_state > state) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 570 | dev_err(&dev->dev, "invalid power transition " |
| 571 | "(from state %d to %d)\n", dev->current_state, state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 572 | return -EINVAL; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 573 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 574 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | /* check if this device supports the desired state */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 576 | if ((state == PCI_D1 && !dev->d1_support) |
| 577 | || (state == PCI_D2 && !dev->d2_support)) |
Daniel Ritz | 3fe9d19 | 2005-08-17 15:32:19 -0700 | [diff] [blame] | 578 | return -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 579 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 580 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 581 | |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 582 | /* If we're (effectively) in D3, force entire word to 0. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | * This doesn't affect PME_Status, disables PME_En, and |
| 584 | * sets PowerState to 0. |
| 585 | */ |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 586 | switch (dev->current_state) { |
John W. Linville | d3535fb | 2005-09-28 17:50:51 -0400 | [diff] [blame] | 587 | case PCI_D0: |
| 588 | case PCI_D1: |
| 589 | case PCI_D2: |
| 590 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
| 591 | pmcsr |= state; |
| 592 | break; |
Rafael J. Wysocki | f62795f | 2009-05-18 22:51:12 +0200 | [diff] [blame] | 593 | case PCI_D3hot: |
| 594 | case PCI_D3cold: |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 595 | case PCI_UNKNOWN: /* Boot-up */ |
| 596 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot |
Rafael J. Wysocki | f00a20e | 2009-03-16 22:40:08 +0100 | [diff] [blame] | 597 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 598 | need_restore = true; |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 599 | /* Fall-through: force to D0 */ |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 600 | default: |
John W. Linville | d3535fb | 2005-09-28 17:50:51 -0400 | [diff] [blame] | 601 | pmcsr = 0; |
John W. Linville | 32a3658 | 2005-09-14 09:52:42 -0400 | [diff] [blame] | 602 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 603 | } |
| 604 | |
| 605 | /* enter specified state */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 606 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | |
| 608 | /* Mandatory power management transition delays */ |
| 609 | /* see PCI PM 1.1 5.6.1 table 18 */ |
| 610 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
Rafael J. Wysocki | 1ae861e | 2009-12-31 12:15:54 +0100 | [diff] [blame] | 611 | pci_dev_d3_sleep(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
Rafael J. Wysocki | aa8c6c9 | 2009-01-16 21:54:43 +0100 | [diff] [blame] | 613 | udelay(PCI_PM_D2_DELAY); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | |
Rafael J. Wysocki | e13cdbd | 2009-10-05 00:48:40 +0200 | [diff] [blame] | 615 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
| 616 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
| 617 | if (dev->current_state != state && printk_ratelimit()) |
| 618 | dev_info(&dev->dev, "Refused to change power state, " |
| 619 | "currently in D%d\n", dev->current_state); |
John W. Linville | 064b53db | 2005-07-27 10:19:44 -0400 | [diff] [blame] | 620 | |
| 621 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT |
| 622 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
| 623 | * from D3hot to D0 _may_ perform an internal reset, thereby |
| 624 | * going to "D0 Uninitialized" rather than "D0 Initialized". |
| 625 | * For example, at least some versions of the 3c905B and the |
| 626 | * 3c556B exhibit this behaviour. |
| 627 | * |
| 628 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave |
| 629 | * devices in a D3hot state at boot. Consequently, we need to |
| 630 | * restore at least the BARs so that the device will be |
| 631 | * accessible to its driver. |
| 632 | */ |
| 633 | if (need_restore) |
| 634 | pci_restore_bars(dev); |
| 635 | |
Rafael J. Wysocki | f00a20e | 2009-03-16 22:40:08 +0100 | [diff] [blame] | 636 | if (dev->bus->self) |
Shaohua Li | 7d715a6 | 2008-02-25 09:46:41 +0800 | [diff] [blame] | 637 | pcie_aspm_pm_state_change(dev->bus->self); |
| 638 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | return 0; |
| 640 | } |
| 641 | |
| 642 | /** |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 643 | * pci_update_current_state - Read PCI power state of given device from its |
| 644 | * PCI PM registers and cache it |
| 645 | * @dev: PCI device to handle. |
Rafael J. Wysocki | f06fc0b | 2008-12-27 16:30:52 +0100 | [diff] [blame] | 646 | * @state: State to cache in case the device doesn't have the PM capability |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 647 | */ |
Rafael J. Wysocki | 73410429 | 2009-01-07 13:07:15 +0100 | [diff] [blame] | 648 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 649 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 650 | if (dev->pm_cap) { |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 651 | u16 pmcsr; |
| 652 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 653 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 654 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
Rafael J. Wysocki | f06fc0b | 2008-12-27 16:30:52 +0100 | [diff] [blame] | 655 | } else { |
| 656 | dev->current_state = state; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 657 | } |
| 658 | } |
| 659 | |
| 660 | /** |
Rafael J. Wysocki | 0e5dd46 | 2009-03-26 22:51:40 +0100 | [diff] [blame] | 661 | * pci_platform_power_transition - Use platform to change device power state |
| 662 | * @dev: PCI device to handle. |
| 663 | * @state: State to put the device into. |
| 664 | */ |
| 665 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) |
| 666 | { |
| 667 | int error; |
| 668 | |
| 669 | if (platform_pci_power_manageable(dev)) { |
| 670 | error = platform_pci_set_power_state(dev, state); |
| 671 | if (!error) |
| 672 | pci_update_current_state(dev, state); |
Ajaykumar Hotchandani | b51306c | 2011-12-12 13:57:36 +0530 | [diff] [blame] | 673 | /* Fall back to PCI_D0 if native PM is not supported */ |
| 674 | if (!dev->pm_cap) |
| 675 | dev->current_state = PCI_D0; |
Rafael J. Wysocki | 0e5dd46 | 2009-03-26 22:51:40 +0100 | [diff] [blame] | 676 | } else { |
| 677 | error = -ENODEV; |
| 678 | /* Fall back to PCI_D0 if native PM is not supported */ |
Rafael J. Wysocki | b3bad72 | 2009-05-17 20:17:06 +0200 | [diff] [blame] | 679 | if (!dev->pm_cap) |
| 680 | dev->current_state = PCI_D0; |
Rafael J. Wysocki | 0e5dd46 | 2009-03-26 22:51:40 +0100 | [diff] [blame] | 681 | } |
| 682 | |
| 683 | return error; |
| 684 | } |
| 685 | |
| 686 | /** |
| 687 | * __pci_start_power_transition - Start power transition of a PCI device |
| 688 | * @dev: PCI device to handle. |
| 689 | * @state: State to put the device into. |
| 690 | */ |
| 691 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) |
| 692 | { |
| 693 | if (state == PCI_D0) |
| 694 | pci_platform_power_transition(dev, PCI_D0); |
| 695 | } |
| 696 | |
| 697 | /** |
| 698 | * __pci_complete_power_transition - Complete power transition of a PCI device |
| 699 | * @dev: PCI device to handle. |
| 700 | * @state: State to put the device into. |
| 701 | * |
| 702 | * This function should not be called directly by device drivers. |
| 703 | */ |
| 704 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) |
| 705 | { |
Matthew Garrett | cc2893b | 2010-04-22 09:30:51 -0400 | [diff] [blame] | 706 | return state >= PCI_D0 ? |
Rafael J. Wysocki | 0e5dd46 | 2009-03-26 22:51:40 +0100 | [diff] [blame] | 707 | pci_platform_power_transition(dev, state) : -EINVAL; |
| 708 | } |
| 709 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); |
| 710 | |
| 711 | /** |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 712 | * pci_set_power_state - Set the power state of a PCI device |
| 713 | * @dev: PCI device to handle. |
| 714 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
| 715 | * |
Nick Andrew | 877d031 | 2009-01-26 11:06:57 +0100 | [diff] [blame] | 716 | * Transition a device to a new power state, using the platform firmware and/or |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 717 | * the device's PCI PM registers. |
| 718 | * |
| 719 | * RETURN VALUE: |
| 720 | * -EINVAL if the requested state is invalid. |
| 721 | * -EIO if device does not support PCI PM or its PM capabilities register has a |
| 722 | * wrong version, or device doesn't support the requested state. |
| 723 | * 0 if device already is in the requested state. |
| 724 | * 0 if device's power state has been successfully changed. |
| 725 | */ |
| 726 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
| 727 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 728 | int error; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 729 | |
| 730 | /* bound the state we're entering */ |
| 731 | if (state > PCI_D3hot) |
| 732 | state = PCI_D3hot; |
| 733 | else if (state < PCI_D0) |
| 734 | state = PCI_D0; |
| 735 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) |
| 736 | /* |
| 737 | * If the device or the parent bridge do not support PCI PM, |
| 738 | * ignore the request if we're doing anything other than putting |
| 739 | * it into D0 (which would only happen on boot). |
| 740 | */ |
| 741 | return 0; |
| 742 | |
Rafael J. Wysocki | 0e5dd46 | 2009-03-26 22:51:40 +0100 | [diff] [blame] | 743 | __pci_start_power_transition(dev, state); |
| 744 | |
Alan Cox | 979b179 | 2008-07-24 17:18:38 +0100 | [diff] [blame] | 745 | /* This device is quirked not to be put into D3, so |
| 746 | don't put it in D3 */ |
| 747 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
| 748 | return 0; |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 749 | |
Rafael J. Wysocki | f00a20e | 2009-03-16 22:40:08 +0100 | [diff] [blame] | 750 | error = pci_raw_set_power_state(dev, state); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 751 | |
Rafael J. Wysocki | 0e5dd46 | 2009-03-26 22:51:40 +0100 | [diff] [blame] | 752 | if (!__pci_complete_power_transition(dev, state)) |
| 753 | error = 0; |
Naga Chumbalkar | 1a680b7 | 2011-03-21 03:29:08 +0000 | [diff] [blame] | 754 | /* |
| 755 | * When aspm_policy is "powersave" this call ensures |
| 756 | * that ASPM is configured. |
| 757 | */ |
| 758 | if (!error && dev->bus->self) |
| 759 | pcie_aspm_powersave_config_link(dev->bus->self); |
Rafael J. Wysocki | 44e4e66 | 2008-07-07 03:32:52 +0200 | [diff] [blame] | 760 | |
| 761 | return error; |
| 762 | } |
| 763 | |
| 764 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 765 | * pci_choose_state - Choose the power state of a PCI device |
| 766 | * @dev: PCI device to be suspended |
| 767 | * @state: target sleep state for the whole system. This is the value |
| 768 | * that is passed to suspend() function. |
| 769 | * |
| 770 | * Returns PCI power state suitable for given device and given system |
| 771 | * message. |
| 772 | */ |
| 773 | |
| 774 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) |
| 775 | { |
Shaohua Li | ab826ca | 2007-07-20 10:03:22 +0800 | [diff] [blame] | 776 | pci_power_t ret; |
David Shaohua Li | 0f64474 | 2005-03-19 00:15:48 -0500 | [diff] [blame] | 777 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
| 779 | return PCI_D0; |
| 780 | |
Rafael J. Wysocki | 961d912 | 2008-07-07 03:32:02 +0200 | [diff] [blame] | 781 | ret = platform_pci_choose_state(dev); |
| 782 | if (ret != PCI_POWER_ERROR) |
| 783 | return ret; |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 784 | |
| 785 | switch (state.event) { |
| 786 | case PM_EVENT_ON: |
| 787 | return PCI_D0; |
| 788 | case PM_EVENT_FREEZE: |
David Brownell | b887d2e | 2006-08-14 23:11:05 -0700 | [diff] [blame] | 789 | case PM_EVENT_PRETHAW: |
| 790 | /* REVISIT both freeze and pre-thaw "should" use D0 */ |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 791 | case PM_EVENT_SUSPEND: |
Rafael J. Wysocki | 3a2d5b7 | 2008-02-23 19:13:25 +0100 | [diff] [blame] | 792 | case PM_EVENT_HIBERNATE: |
Pavel Machek | ca078ba | 2005-09-03 15:56:57 -0700 | [diff] [blame] | 793 | return PCI_D3hot; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 794 | default: |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 795 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
| 796 | state.event); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | BUG(); |
| 798 | } |
| 799 | return PCI_D0; |
| 800 | } |
| 801 | |
| 802 | EXPORT_SYMBOL(pci_choose_state); |
| 803 | |
Yu Zhao | 8985851 | 2009-02-16 02:55:47 +0800 | [diff] [blame] | 804 | #define PCI_EXP_SAVE_REGS 7 |
| 805 | |
Yu Zhao | 1b6b8ce | 2009-04-09 14:57:39 +0800 | [diff] [blame] | 806 | #define pcie_cap_has_devctl(type, flags) 1 |
| 807 | #define pcie_cap_has_lnkctl(type, flags) \ |
| 808 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ |
| 809 | (type == PCI_EXP_TYPE_ROOT_PORT || \ |
| 810 | type == PCI_EXP_TYPE_ENDPOINT || \ |
| 811 | type == PCI_EXP_TYPE_LEG_END)) |
| 812 | #define pcie_cap_has_sltctl(type, flags) \ |
| 813 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ |
| 814 | ((type == PCI_EXP_TYPE_ROOT_PORT) || \ |
| 815 | (type == PCI_EXP_TYPE_DOWNSTREAM && \ |
| 816 | (flags & PCI_EXP_FLAGS_SLOT)))) |
| 817 | #define pcie_cap_has_rtctl(type, flags) \ |
| 818 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ |
| 819 | (type == PCI_EXP_TYPE_ROOT_PORT || \ |
| 820 | type == PCI_EXP_TYPE_RC_EC)) |
| 821 | #define pcie_cap_has_devctl2(type, flags) \ |
| 822 | ((flags & PCI_EXP_FLAGS_VERS) > 1) |
| 823 | #define pcie_cap_has_lnkctl2(type, flags) \ |
| 824 | ((flags & PCI_EXP_FLAGS_VERS) > 1) |
| 825 | #define pcie_cap_has_sltctl2(type, flags) \ |
| 826 | ((flags & PCI_EXP_FLAGS_VERS) > 1) |
| 827 | |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 828 | static int pci_save_pcie_state(struct pci_dev *dev) |
| 829 | { |
| 830 | int pos, i = 0; |
| 831 | struct pci_cap_saved_state *save_state; |
| 832 | u16 *cap; |
Yu Zhao | 1b6b8ce | 2009-04-09 14:57:39 +0800 | [diff] [blame] | 833 | u16 flags; |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 834 | |
Kenji Kaneshige | 06a1cba | 2009-11-11 14:30:56 +0900 | [diff] [blame] | 835 | pos = pci_pcie_cap(dev); |
| 836 | if (!pos) |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 837 | return 0; |
| 838 | |
Eric W. Biederman | 9f35575 | 2007-03-08 13:06:13 -0700 | [diff] [blame] | 839 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 840 | if (!save_state) { |
Harvey Harrison | e496b61 | 2009-01-07 16:22:37 -0800 | [diff] [blame] | 841 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 842 | return -ENOMEM; |
| 843 | } |
Alex Williamson | 24a4742f | 2011-05-10 10:02:11 -0600 | [diff] [blame] | 844 | cap = (u16 *)&save_state->cap.data[0]; |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 845 | |
Yu Zhao | 1b6b8ce | 2009-04-09 14:57:39 +0800 | [diff] [blame] | 846 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); |
| 847 | |
| 848 | if (pcie_cap_has_devctl(dev->pcie_type, flags)) |
| 849 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); |
| 850 | if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) |
| 851 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); |
| 852 | if (pcie_cap_has_sltctl(dev->pcie_type, flags)) |
| 853 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); |
| 854 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) |
| 855 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); |
| 856 | if (pcie_cap_has_devctl2(dev->pcie_type, flags)) |
| 857 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); |
| 858 | if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) |
| 859 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); |
| 860 | if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) |
| 861 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 862 | |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 863 | return 0; |
| 864 | } |
| 865 | |
| 866 | static void pci_restore_pcie_state(struct pci_dev *dev) |
| 867 | { |
| 868 | int i = 0, pos; |
| 869 | struct pci_cap_saved_state *save_state; |
| 870 | u16 *cap; |
Yu Zhao | 1b6b8ce | 2009-04-09 14:57:39 +0800 | [diff] [blame] | 871 | u16 flags; |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 872 | |
| 873 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
| 874 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
| 875 | if (!save_state || pos <= 0) |
| 876 | return; |
Alex Williamson | 24a4742f | 2011-05-10 10:02:11 -0600 | [diff] [blame] | 877 | cap = (u16 *)&save_state->cap.data[0]; |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 878 | |
Yu Zhao | 1b6b8ce | 2009-04-09 14:57:39 +0800 | [diff] [blame] | 879 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); |
| 880 | |
| 881 | if (pcie_cap_has_devctl(dev->pcie_type, flags)) |
| 882 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); |
| 883 | if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) |
| 884 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); |
| 885 | if (pcie_cap_has_sltctl(dev->pcie_type, flags)) |
| 886 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); |
| 887 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) |
| 888 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); |
| 889 | if (pcie_cap_has_devctl2(dev->pcie_type, flags)) |
| 890 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); |
| 891 | if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) |
| 892 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); |
| 893 | if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) |
| 894 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 895 | } |
| 896 | |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 897 | |
| 898 | static int pci_save_pcix_state(struct pci_dev *dev) |
| 899 | { |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 900 | int pos; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 901 | struct pci_cap_saved_state *save_state; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 902 | |
| 903 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 904 | if (pos <= 0) |
| 905 | return 0; |
| 906 | |
Shaohua Li | f34303d | 2007-12-18 09:56:47 +0800 | [diff] [blame] | 907 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 908 | if (!save_state) { |
Harvey Harrison | e496b61 | 2009-01-07 16:22:37 -0800 | [diff] [blame] | 909 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 910 | return -ENOMEM; |
| 911 | } |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 912 | |
Alex Williamson | 24a4742f | 2011-05-10 10:02:11 -0600 | [diff] [blame] | 913 | pci_read_config_word(dev, pos + PCI_X_CMD, |
| 914 | (u16 *)save_state->cap.data); |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 915 | |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 916 | return 0; |
| 917 | } |
| 918 | |
| 919 | static void pci_restore_pcix_state(struct pci_dev *dev) |
| 920 | { |
| 921 | int i = 0, pos; |
| 922 | struct pci_cap_saved_state *save_state; |
| 923 | u16 *cap; |
| 924 | |
| 925 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
| 926 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 927 | if (!save_state || pos <= 0) |
| 928 | return; |
Alex Williamson | 24a4742f | 2011-05-10 10:02:11 -0600 | [diff] [blame] | 929 | cap = (u16 *)&save_state->cap.data[0]; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 930 | |
| 931 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 935 | /** |
| 936 | * pci_save_state - save the PCI configuration space of a device before suspending |
| 937 | * @dev: - PCI device that we're dealing with |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 938 | */ |
| 939 | int |
| 940 | pci_save_state(struct pci_dev *dev) |
| 941 | { |
| 942 | int i; |
| 943 | /* XXX: 100% dword access ok here? */ |
| 944 | for (i = 0; i < 16; i++) |
Kleber Sacilotto de Souza | 9e0b5b2 | 2009-11-25 00:55:51 -0200 | [diff] [blame] | 945 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
Rafael J. Wysocki | aa8c6c9 | 2009-01-16 21:54:43 +0100 | [diff] [blame] | 946 | dev->state_saved = true; |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 947 | if ((i = pci_save_pcie_state(dev)) != 0) |
| 948 | return i; |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 949 | if ((i = pci_save_pcix_state(dev)) != 0) |
| 950 | return i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 951 | return 0; |
| 952 | } |
| 953 | |
| 954 | /** |
| 955 | * pci_restore_state - Restore the saved state of a PCI device |
| 956 | * @dev: - PCI device that we're dealing with |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | */ |
Jon Mason | 1d3c16a | 2010-11-30 17:43:26 -0600 | [diff] [blame] | 958 | void pci_restore_state(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 959 | { |
| 960 | int i; |
Al Viro | b4482a4 | 2007-10-14 19:35:40 +0100 | [diff] [blame] | 961 | u32 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | |
Alek Du | c82f63e | 2009-08-08 08:46:19 +0800 | [diff] [blame] | 963 | if (!dev->state_saved) |
Jon Mason | 1d3c16a | 2010-11-30 17:43:26 -0600 | [diff] [blame] | 964 | return; |
Rafael J. Wysocki | 4b77b0a | 2009-09-09 23:49:59 +0200 | [diff] [blame] | 965 | |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 966 | /* PCI Express register must be restored first */ |
| 967 | pci_restore_pcie_state(dev); |
Hao, Xudong | 1900ca1 | 2011-12-17 21:24:40 +0800 | [diff] [blame] | 968 | pci_restore_ats_state(dev); |
Michael S. Tsirkin | b56a5a2 | 2006-08-21 16:22:22 +0300 | [diff] [blame] | 969 | |
Yu, Luming | 8b8c8d2 | 2006-04-25 00:00:34 -0700 | [diff] [blame] | 970 | /* |
| 971 | * The Base Address register should be programmed before the command |
| 972 | * register(s) |
| 973 | */ |
| 974 | for (i = 15; i >= 0; i--) { |
Dave Jones | 04d9c1a | 2006-04-18 21:06:51 -0700 | [diff] [blame] | 975 | pci_read_config_dword(dev, i * 4, &val); |
| 976 | if (val != dev->saved_config_space[i]) { |
Vincent Palatin | 85b8582 | 2011-12-05 11:51:18 -0800 | [diff] [blame] | 977 | dev_dbg(&dev->dev, "restoring config " |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 978 | "space at offset %#x (was %#x, writing %#x)\n", |
| 979 | i, val, (int)dev->saved_config_space[i]); |
Dave Jones | 04d9c1a | 2006-04-18 21:06:51 -0700 | [diff] [blame] | 980 | pci_write_config_dword(dev,i * 4, |
| 981 | dev->saved_config_space[i]); |
| 982 | } |
| 983 | } |
Stephen Hemminger | cc692a5 | 2006-11-08 16:17:15 -0800 | [diff] [blame] | 984 | pci_restore_pcix_state(dev); |
Shaohua Li | 41017f0 | 2006-02-08 17:11:38 +0800 | [diff] [blame] | 985 | pci_restore_msi_state(dev); |
Yu Zhao | 8c5cdb6 | 2009-03-20 11:25:12 +0800 | [diff] [blame] | 986 | pci_restore_iov_state(dev); |
Michael Ellerman | 8fed4b6 | 2007-01-25 19:34:08 +1100 | [diff] [blame] | 987 | |
Rafael J. Wysocki | 4b77b0a | 2009-09-09 23:49:59 +0200 | [diff] [blame] | 988 | dev->state_saved = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 989 | } |
| 990 | |
Alex Williamson | ffbdd3f | 2011-05-10 10:02:27 -0600 | [diff] [blame] | 991 | struct pci_saved_state { |
| 992 | u32 config_space[16]; |
| 993 | struct pci_cap_saved_data cap[0]; |
| 994 | }; |
| 995 | |
| 996 | /** |
| 997 | * pci_store_saved_state - Allocate and return an opaque struct containing |
| 998 | * the device saved state. |
| 999 | * @dev: PCI device that we're dealing with |
| 1000 | * |
| 1001 | * Rerturn NULL if no state or error. |
| 1002 | */ |
| 1003 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) |
| 1004 | { |
| 1005 | struct pci_saved_state *state; |
| 1006 | struct pci_cap_saved_state *tmp; |
| 1007 | struct pci_cap_saved_data *cap; |
| 1008 | struct hlist_node *pos; |
| 1009 | size_t size; |
| 1010 | |
| 1011 | if (!dev->state_saved) |
| 1012 | return NULL; |
| 1013 | |
| 1014 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); |
| 1015 | |
| 1016 | hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) |
| 1017 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
| 1018 | |
| 1019 | state = kzalloc(size, GFP_KERNEL); |
| 1020 | if (!state) |
| 1021 | return NULL; |
| 1022 | |
| 1023 | memcpy(state->config_space, dev->saved_config_space, |
| 1024 | sizeof(state->config_space)); |
| 1025 | |
| 1026 | cap = state->cap; |
| 1027 | hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) { |
| 1028 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
| 1029 | memcpy(cap, &tmp->cap, len); |
| 1030 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); |
| 1031 | } |
| 1032 | /* Empty cap_save terminates list */ |
| 1033 | |
| 1034 | return state; |
| 1035 | } |
| 1036 | EXPORT_SYMBOL_GPL(pci_store_saved_state); |
| 1037 | |
| 1038 | /** |
| 1039 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. |
| 1040 | * @dev: PCI device that we're dealing with |
| 1041 | * @state: Saved state returned from pci_store_saved_state() |
| 1042 | */ |
| 1043 | int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state) |
| 1044 | { |
| 1045 | struct pci_cap_saved_data *cap; |
| 1046 | |
| 1047 | dev->state_saved = false; |
| 1048 | |
| 1049 | if (!state) |
| 1050 | return 0; |
| 1051 | |
| 1052 | memcpy(dev->saved_config_space, state->config_space, |
| 1053 | sizeof(state->config_space)); |
| 1054 | |
| 1055 | cap = state->cap; |
| 1056 | while (cap->size) { |
| 1057 | struct pci_cap_saved_state *tmp; |
| 1058 | |
| 1059 | tmp = pci_find_saved_cap(dev, cap->cap_nr); |
| 1060 | if (!tmp || tmp->cap.size != cap->size) |
| 1061 | return -EINVAL; |
| 1062 | |
| 1063 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); |
| 1064 | cap = (struct pci_cap_saved_data *)((u8 *)cap + |
| 1065 | sizeof(struct pci_cap_saved_data) + cap->size); |
| 1066 | } |
| 1067 | |
| 1068 | dev->state_saved = true; |
| 1069 | return 0; |
| 1070 | } |
| 1071 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
| 1072 | |
| 1073 | /** |
| 1074 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, |
| 1075 | * and free the memory allocated for it. |
| 1076 | * @dev: PCI device that we're dealing with |
| 1077 | * @state: Pointer to saved state returned from pci_store_saved_state() |
| 1078 | */ |
| 1079 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
| 1080 | struct pci_saved_state **state) |
| 1081 | { |
| 1082 | int ret = pci_load_saved_state(dev, *state); |
| 1083 | kfree(*state); |
| 1084 | *state = NULL; |
| 1085 | return ret; |
| 1086 | } |
| 1087 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); |
| 1088 | |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 1089 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
| 1090 | { |
| 1091 | int err; |
| 1092 | |
| 1093 | err = pci_set_power_state(dev, PCI_D0); |
| 1094 | if (err < 0 && err != -EIO) |
| 1095 | return err; |
| 1096 | err = pcibios_enable_device(dev, bars); |
| 1097 | if (err < 0) |
| 1098 | return err; |
| 1099 | pci_fixup_device(pci_fixup_enable, dev); |
| 1100 | |
| 1101 | return 0; |
| 1102 | } |
| 1103 | |
| 1104 | /** |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 1105 | * pci_reenable_device - Resume abandoned device |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 1106 | * @dev: PCI device to be resumed |
| 1107 | * |
| 1108 | * Note this function is a backend of pci_default_resume and is not supposed |
| 1109 | * to be called by normal code, write proper resume handler and use it instead. |
| 1110 | */ |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 1111 | int pci_reenable_device(struct pci_dev *dev) |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 1112 | { |
Yuji Shimada | 296ccb0 | 2009-04-03 16:41:46 +0900 | [diff] [blame] | 1113 | if (pci_is_enabled(dev)) |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 1114 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
| 1115 | return 0; |
| 1116 | } |
| 1117 | |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 1118 | static int __pci_enable_device_flags(struct pci_dev *dev, |
| 1119 | resource_size_t flags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1120 | { |
| 1121 | int err; |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 1122 | int i, bars = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1123 | |
Jesse Barnes | 97c145f | 2010-11-05 15:16:36 -0400 | [diff] [blame] | 1124 | /* |
| 1125 | * Power state could be unknown at this point, either due to a fresh |
| 1126 | * boot or a device removal call. So get the current power state |
| 1127 | * so that things like MSI message writing will behave as expected |
| 1128 | * (e.g. if the device really is in D0 at enable time). |
| 1129 | */ |
| 1130 | if (dev->pm_cap) { |
| 1131 | u16 pmcsr; |
| 1132 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
| 1133 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
| 1134 | } |
| 1135 | |
Hidetoshi Seto | 9fb625c | 2006-12-18 10:28:43 +0900 | [diff] [blame] | 1136 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
| 1137 | return 0; /* already enabled */ |
| 1138 | |
Yinghai Lu | 497f16f | 2011-12-17 18:33:37 -0800 | [diff] [blame] | 1139 | /* only skip sriov related */ |
| 1140 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
| 1141 | if (dev->resource[i].flags & flags) |
| 1142 | bars |= (1 << i); |
| 1143 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 1144 | if (dev->resource[i].flags & flags) |
| 1145 | bars |= (1 << i); |
| 1146 | |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 1147 | err = do_pci_enable_device(dev, bars); |
Greg Kroah-Hartman | 95a6296 | 2005-07-28 11:37:33 -0700 | [diff] [blame] | 1148 | if (err < 0) |
Hidetoshi Seto | 38cc130 | 2006-12-18 10:30:00 +0900 | [diff] [blame] | 1149 | atomic_dec(&dev->enable_cnt); |
Hidetoshi Seto | 9fb625c | 2006-12-18 10:28:43 +0900 | [diff] [blame] | 1150 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1151 | } |
| 1152 | |
| 1153 | /** |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 1154 | * pci_enable_device_io - Initialize a device for use with IO space |
| 1155 | * @dev: PCI device to be initialized |
| 1156 | * |
| 1157 | * Initialize device before it's used by a driver. Ask low-level code |
| 1158 | * to enable I/O resources. Wake up the device if it was suspended. |
| 1159 | * Beware, this function can fail. |
| 1160 | */ |
| 1161 | int pci_enable_device_io(struct pci_dev *dev) |
| 1162 | { |
| 1163 | return __pci_enable_device_flags(dev, IORESOURCE_IO); |
| 1164 | } |
| 1165 | |
| 1166 | /** |
| 1167 | * pci_enable_device_mem - Initialize a device for use with Memory space |
| 1168 | * @dev: PCI device to be initialized |
| 1169 | * |
| 1170 | * Initialize device before it's used by a driver. Ask low-level code |
| 1171 | * to enable Memory resources. Wake up the device if it was suspended. |
| 1172 | * Beware, this function can fail. |
| 1173 | */ |
| 1174 | int pci_enable_device_mem(struct pci_dev *dev) |
| 1175 | { |
| 1176 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); |
| 1177 | } |
| 1178 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | /** |
| 1180 | * pci_enable_device - Initialize device before it's used by a driver. |
| 1181 | * @dev: PCI device to be initialized |
| 1182 | * |
| 1183 | * Initialize device before it's used by a driver. Ask low-level code |
| 1184 | * to enable I/O and memory. Wake up the device if it was suspended. |
| 1185 | * Beware, this function can fail. |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 1186 | * |
| 1187 | * Note we don't actually enable the device many times if we call |
| 1188 | * this function repeatedly (we just increment the count). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1189 | */ |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 1190 | int pci_enable_device(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1191 | { |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 1192 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1193 | } |
| 1194 | |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1195 | /* |
| 1196 | * Managed PCI resources. This manages device on/off, intx/msi/msix |
| 1197 | * on/off and BAR regions. pci_dev itself records msi/msix status, so |
| 1198 | * there's no need to track it separately. pci_devres is initialized |
| 1199 | * when a device is enabled using managed PCI device enable interface. |
| 1200 | */ |
| 1201 | struct pci_devres { |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 1202 | unsigned int enabled:1; |
| 1203 | unsigned int pinned:1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1204 | unsigned int orig_intx:1; |
| 1205 | unsigned int restore_intx:1; |
| 1206 | u32 region_mask; |
| 1207 | }; |
| 1208 | |
| 1209 | static void pcim_release(struct device *gendev, void *res) |
| 1210 | { |
| 1211 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); |
| 1212 | struct pci_devres *this = res; |
| 1213 | int i; |
| 1214 | |
| 1215 | if (dev->msi_enabled) |
| 1216 | pci_disable_msi(dev); |
| 1217 | if (dev->msix_enabled) |
| 1218 | pci_disable_msix(dev); |
| 1219 | |
| 1220 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
| 1221 | if (this->region_mask & (1 << i)) |
| 1222 | pci_release_region(dev, i); |
| 1223 | |
| 1224 | if (this->restore_intx) |
| 1225 | pci_intx(dev, this->orig_intx); |
| 1226 | |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 1227 | if (this->enabled && !this->pinned) |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1228 | pci_disable_device(dev); |
| 1229 | } |
| 1230 | |
| 1231 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) |
| 1232 | { |
| 1233 | struct pci_devres *dr, *new_dr; |
| 1234 | |
| 1235 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); |
| 1236 | if (dr) |
| 1237 | return dr; |
| 1238 | |
| 1239 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); |
| 1240 | if (!new_dr) |
| 1241 | return NULL; |
| 1242 | return devres_get(&pdev->dev, new_dr, NULL, NULL); |
| 1243 | } |
| 1244 | |
| 1245 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) |
| 1246 | { |
| 1247 | if (pci_is_managed(pdev)) |
| 1248 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); |
| 1249 | return NULL; |
| 1250 | } |
| 1251 | |
| 1252 | /** |
| 1253 | * pcim_enable_device - Managed pci_enable_device() |
| 1254 | * @pdev: PCI device to be initialized |
| 1255 | * |
| 1256 | * Managed pci_enable_device(). |
| 1257 | */ |
| 1258 | int pcim_enable_device(struct pci_dev *pdev) |
| 1259 | { |
| 1260 | struct pci_devres *dr; |
| 1261 | int rc; |
| 1262 | |
| 1263 | dr = get_pci_dr(pdev); |
| 1264 | if (unlikely(!dr)) |
| 1265 | return -ENOMEM; |
Tejun Heo | b95d58e | 2008-01-30 18:20:04 +0900 | [diff] [blame] | 1266 | if (dr->enabled) |
| 1267 | return 0; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1268 | |
| 1269 | rc = pci_enable_device(pdev); |
| 1270 | if (!rc) { |
| 1271 | pdev->is_managed = 1; |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 1272 | dr->enabled = 1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1273 | } |
| 1274 | return rc; |
| 1275 | } |
| 1276 | |
| 1277 | /** |
| 1278 | * pcim_pin_device - Pin managed PCI device |
| 1279 | * @pdev: PCI device to pin |
| 1280 | * |
| 1281 | * Pin managed PCI device @pdev. Pinned device won't be disabled on |
| 1282 | * driver detach. @pdev must have been enabled with |
| 1283 | * pcim_enable_device(). |
| 1284 | */ |
| 1285 | void pcim_pin_device(struct pci_dev *pdev) |
| 1286 | { |
| 1287 | struct pci_devres *dr; |
| 1288 | |
| 1289 | dr = find_pci_dr(pdev); |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 1290 | WARN_ON(!dr || !dr->enabled); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1291 | if (dr) |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 1292 | dr->pinned = 1; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1293 | } |
| 1294 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1295 | /** |
| 1296 | * pcibios_disable_device - disable arch specific PCI resources for device dev |
| 1297 | * @dev: the PCI device to disable |
| 1298 | * |
| 1299 | * Disables architecture specific PCI resources for the device. This |
| 1300 | * is the default implementation. Architecture implementations can |
| 1301 | * override this. |
| 1302 | */ |
| 1303 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} |
| 1304 | |
Rafael J. Wysocki | fa58d30 | 2009-01-07 13:03:42 +0100 | [diff] [blame] | 1305 | static void do_pci_disable_device(struct pci_dev *dev) |
| 1306 | { |
| 1307 | u16 pci_command; |
| 1308 | |
| 1309 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
| 1310 | if (pci_command & PCI_COMMAND_MASTER) { |
| 1311 | pci_command &= ~PCI_COMMAND_MASTER; |
| 1312 | pci_write_config_word(dev, PCI_COMMAND, pci_command); |
| 1313 | } |
| 1314 | |
| 1315 | pcibios_disable_device(dev); |
| 1316 | } |
| 1317 | |
| 1318 | /** |
| 1319 | * pci_disable_enabled_device - Disable device without updating enable_cnt |
| 1320 | * @dev: PCI device to disable |
| 1321 | * |
| 1322 | * NOTE: This function is a backend of PCI power management routines and is |
| 1323 | * not supposed to be called drivers. |
| 1324 | */ |
| 1325 | void pci_disable_enabled_device(struct pci_dev *dev) |
| 1326 | { |
Yuji Shimada | 296ccb0 | 2009-04-03 16:41:46 +0900 | [diff] [blame] | 1327 | if (pci_is_enabled(dev)) |
Rafael J. Wysocki | fa58d30 | 2009-01-07 13:03:42 +0100 | [diff] [blame] | 1328 | do_pci_disable_device(dev); |
| 1329 | } |
| 1330 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1331 | /** |
| 1332 | * pci_disable_device - Disable PCI device after use |
| 1333 | * @dev: PCI device to be disabled |
| 1334 | * |
| 1335 | * Signal to the system that the PCI device is not in use by the system |
| 1336 | * anymore. This only involves disabling PCI bus-mastering, if active. |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 1337 | * |
| 1338 | * Note we don't actually disable the device until all callers of |
Roman Fietze | ee6583f | 2010-05-18 14:45:47 +0200 | [diff] [blame] | 1339 | * pci_enable_device() have called pci_disable_device(). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1340 | */ |
| 1341 | void |
| 1342 | pci_disable_device(struct pci_dev *dev) |
| 1343 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1344 | struct pci_devres *dr; |
Shaohua Li | 99dc804 | 2006-05-26 10:58:27 +0800 | [diff] [blame] | 1345 | |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1346 | dr = find_pci_dr(dev); |
| 1347 | if (dr) |
Tejun Heo | 7f375f3 | 2007-02-25 04:36:01 -0800 | [diff] [blame] | 1348 | dr->enabled = 0; |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 1349 | |
Inaky Perez-Gonzalez | bae94d0 | 2006-11-22 12:40:31 -0800 | [diff] [blame] | 1350 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
| 1351 | return; |
| 1352 | |
Rafael J. Wysocki | fa58d30 | 2009-01-07 13:03:42 +0100 | [diff] [blame] | 1353 | do_pci_disable_device(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1354 | |
Rafael J. Wysocki | fa58d30 | 2009-01-07 13:03:42 +0100 | [diff] [blame] | 1355 | dev->is_busmaster = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1356 | } |
| 1357 | |
| 1358 | /** |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 1359 | * pcibios_set_pcie_reset_state - set reset state for device dev |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 1360 | * @dev: the PCIe device reset |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 1361 | * @state: Reset state to enter into |
| 1362 | * |
| 1363 | * |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 1364 | * Sets the PCIe reset state for the device. This is the default |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 1365 | * implementation. Architecture implementations can override this. |
| 1366 | */ |
| 1367 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, |
| 1368 | enum pcie_reset_state state) |
| 1369 | { |
| 1370 | return -EINVAL; |
| 1371 | } |
| 1372 | |
| 1373 | /** |
| 1374 | * pci_set_pcie_reset_state - set reset state for device dev |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 1375 | * @dev: the PCIe device reset |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 1376 | * @state: Reset state to enter into |
| 1377 | * |
| 1378 | * |
| 1379 | * Sets the PCI reset state for the device. |
| 1380 | */ |
| 1381 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
| 1382 | { |
| 1383 | return pcibios_set_pcie_reset_state(dev, state); |
| 1384 | } |
| 1385 | |
| 1386 | /** |
Rafael J. Wysocki | 58ff463 | 2010-02-17 23:36:58 +0100 | [diff] [blame] | 1387 | * pci_check_pme_status - Check if given device has generated PME. |
| 1388 | * @dev: Device to check. |
| 1389 | * |
| 1390 | * Check the PME status of the device and if set, clear it and clear PME enable |
| 1391 | * (if set). Return 'true' if PME status and PME enable were both set or |
| 1392 | * 'false' otherwise. |
| 1393 | */ |
| 1394 | bool pci_check_pme_status(struct pci_dev *dev) |
| 1395 | { |
| 1396 | int pmcsr_pos; |
| 1397 | u16 pmcsr; |
| 1398 | bool ret = false; |
| 1399 | |
| 1400 | if (!dev->pm_cap) |
| 1401 | return false; |
| 1402 | |
| 1403 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; |
| 1404 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); |
| 1405 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) |
| 1406 | return false; |
| 1407 | |
| 1408 | /* Clear PME status. */ |
| 1409 | pmcsr |= PCI_PM_CTRL_PME_STATUS; |
| 1410 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { |
| 1411 | /* Disable PME to avoid interrupt flood. */ |
| 1412 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; |
| 1413 | ret = true; |
| 1414 | } |
| 1415 | |
| 1416 | pci_write_config_word(dev, pmcsr_pos, pmcsr); |
| 1417 | |
| 1418 | return ret; |
| 1419 | } |
| 1420 | |
| 1421 | /** |
Rafael J. Wysocki | b67ea76 | 2010-02-17 23:44:09 +0100 | [diff] [blame] | 1422 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. |
| 1423 | * @dev: Device to handle. |
Rafael J. Wysocki | 379021d | 2011-10-03 23:16:33 +0200 | [diff] [blame] | 1424 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
Rafael J. Wysocki | b67ea76 | 2010-02-17 23:44:09 +0100 | [diff] [blame] | 1425 | * |
| 1426 | * Check if @dev has generated PME and queue a resume request for it in that |
| 1427 | * case. |
| 1428 | */ |
Rafael J. Wysocki | 379021d | 2011-10-03 23:16:33 +0200 | [diff] [blame] | 1429 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
Rafael J. Wysocki | b67ea76 | 2010-02-17 23:44:09 +0100 | [diff] [blame] | 1430 | { |
Rafael J. Wysocki | 379021d | 2011-10-03 23:16:33 +0200 | [diff] [blame] | 1431 | if (pme_poll_reset && dev->pme_poll) |
| 1432 | dev->pme_poll = false; |
| 1433 | |
Rafael J. Wysocki | c125e96 | 2010-07-05 22:43:53 +0200 | [diff] [blame] | 1434 | if (pci_check_pme_status(dev)) { |
Rafael J. Wysocki | c125e96 | 2010-07-05 22:43:53 +0200 | [diff] [blame] | 1435 | pci_wakeup_event(dev); |
Rafael J. Wysocki | 0f953bf | 2010-12-29 13:22:08 +0100 | [diff] [blame] | 1436 | pm_request_resume(&dev->dev); |
Rafael J. Wysocki | c125e96 | 2010-07-05 22:43:53 +0200 | [diff] [blame] | 1437 | } |
Rafael J. Wysocki | b67ea76 | 2010-02-17 23:44:09 +0100 | [diff] [blame] | 1438 | return 0; |
| 1439 | } |
| 1440 | |
| 1441 | /** |
| 1442 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. |
| 1443 | * @bus: Top bus of the subtree to walk. |
| 1444 | */ |
| 1445 | void pci_pme_wakeup_bus(struct pci_bus *bus) |
| 1446 | { |
| 1447 | if (bus) |
Rafael J. Wysocki | 379021d | 2011-10-03 23:16:33 +0200 | [diff] [blame] | 1448 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
Rafael J. Wysocki | b67ea76 | 2010-02-17 23:44:09 +0100 | [diff] [blame] | 1449 | } |
| 1450 | |
| 1451 | /** |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1452 | * pci_pme_capable - check the capability of PCI device to generate PME# |
| 1453 | * @dev: PCI device to handle. |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1454 | * @state: PCI state from which device will issue PME#. |
| 1455 | */ |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 1456 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1457 | { |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1458 | if (!dev->pm_cap) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1459 | return false; |
| 1460 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1461 | return !!(dev->pme_support & (1 << state)); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1462 | } |
| 1463 | |
Matthew Garrett | df17e62 | 2010-10-04 14:22:29 -0400 | [diff] [blame] | 1464 | static void pci_pme_list_scan(struct work_struct *work) |
| 1465 | { |
Rafael J. Wysocki | 379021d | 2011-10-03 23:16:33 +0200 | [diff] [blame] | 1466 | struct pci_pme_device *pme_dev, *n; |
Matthew Garrett | df17e62 | 2010-10-04 14:22:29 -0400 | [diff] [blame] | 1467 | |
| 1468 | mutex_lock(&pci_pme_list_mutex); |
| 1469 | if (!list_empty(&pci_pme_list)) { |
Rafael J. Wysocki | 379021d | 2011-10-03 23:16:33 +0200 | [diff] [blame] | 1470 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
| 1471 | if (pme_dev->dev->pme_poll) { |
| 1472 | pci_pme_wakeup(pme_dev->dev, NULL); |
| 1473 | } else { |
| 1474 | list_del(&pme_dev->list); |
| 1475 | kfree(pme_dev); |
| 1476 | } |
| 1477 | } |
| 1478 | if (!list_empty(&pci_pme_list)) |
| 1479 | schedule_delayed_work(&pci_pme_work, |
| 1480 | msecs_to_jiffies(PME_TIMEOUT)); |
Matthew Garrett | df17e62 | 2010-10-04 14:22:29 -0400 | [diff] [blame] | 1481 | } |
| 1482 | mutex_unlock(&pci_pme_list_mutex); |
| 1483 | } |
| 1484 | |
| 1485 | /** |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1486 | * pci_pme_active - enable or disable PCI device's PME# function |
| 1487 | * @dev: PCI device to handle. |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1488 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
| 1489 | * |
| 1490 | * The caller must verify that the device is capable of generating PME# before |
| 1491 | * calling this function with @enable equal to 'true'. |
| 1492 | */ |
Rafael J. Wysocki | 5a6c9b6 | 2008-08-08 00:14:24 +0200 | [diff] [blame] | 1493 | void pci_pme_active(struct pci_dev *dev, bool enable) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1494 | { |
| 1495 | u16 pmcsr; |
| 1496 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1497 | if (!dev->pm_cap) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1498 | return; |
| 1499 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1500 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1501 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
| 1502 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; |
| 1503 | if (!enable) |
| 1504 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; |
| 1505 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1506 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1507 | |
Matthew Garrett | df17e62 | 2010-10-04 14:22:29 -0400 | [diff] [blame] | 1508 | /* PCI (as opposed to PCIe) PME requires that the device have |
| 1509 | its PME# line hooked up correctly. Not all hardware vendors |
| 1510 | do this, so the PME never gets delivered and the device |
| 1511 | remains asleep. The easiest way around this is to |
| 1512 | periodically walk the list of suspended devices and check |
| 1513 | whether any have their PME flag set. The assumption is that |
| 1514 | we'll wake up often enough anyway that this won't be a huge |
| 1515 | hit, and the power savings from the devices will still be a |
| 1516 | win. */ |
| 1517 | |
Rafael J. Wysocki | 379021d | 2011-10-03 23:16:33 +0200 | [diff] [blame] | 1518 | if (dev->pme_poll) { |
Matthew Garrett | df17e62 | 2010-10-04 14:22:29 -0400 | [diff] [blame] | 1519 | struct pci_pme_device *pme_dev; |
| 1520 | if (enable) { |
| 1521 | pme_dev = kmalloc(sizeof(struct pci_pme_device), |
| 1522 | GFP_KERNEL); |
| 1523 | if (!pme_dev) |
| 1524 | goto out; |
| 1525 | pme_dev->dev = dev; |
| 1526 | mutex_lock(&pci_pme_list_mutex); |
| 1527 | list_add(&pme_dev->list, &pci_pme_list); |
| 1528 | if (list_is_singular(&pci_pme_list)) |
| 1529 | schedule_delayed_work(&pci_pme_work, |
| 1530 | msecs_to_jiffies(PME_TIMEOUT)); |
| 1531 | mutex_unlock(&pci_pme_list_mutex); |
| 1532 | } else { |
| 1533 | mutex_lock(&pci_pme_list_mutex); |
| 1534 | list_for_each_entry(pme_dev, &pci_pme_list, list) { |
| 1535 | if (pme_dev->dev == dev) { |
| 1536 | list_del(&pme_dev->list); |
| 1537 | kfree(pme_dev); |
| 1538 | break; |
| 1539 | } |
| 1540 | } |
| 1541 | mutex_unlock(&pci_pme_list_mutex); |
| 1542 | } |
| 1543 | } |
| 1544 | |
| 1545 | out: |
Vincent Palatin | 85b8582 | 2011-12-05 11:51:18 -0800 | [diff] [blame] | 1546 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1547 | } |
| 1548 | |
| 1549 | /** |
Rafael J. Wysocki | 6cbf821 | 2010-02-17 23:44:58 +0100 | [diff] [blame] | 1550 | * __pci_enable_wake - enable PCI device as wakeup event source |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1551 | * @dev: PCI device affected |
| 1552 | * @state: PCI state from which device will issue wakeup events |
Rafael J. Wysocki | 6cbf821 | 2010-02-17 23:44:58 +0100 | [diff] [blame] | 1553 | * @runtime: True if the events are to be generated at run time |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1554 | * @enable: True to enable event generation; false to disable |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1555 | * |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1556 | * This enables the device as a wakeup event source, or disables it. |
| 1557 | * When such events involves platform-specific hooks, those hooks are |
| 1558 | * called automatically by this routine. |
| 1559 | * |
| 1560 | * Devices with legacy power management (no standard PCI PM capabilities) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1561 | * always require such platform hooks. |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1562 | * |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1563 | * RETURN VALUE: |
| 1564 | * 0 is returned on success |
| 1565 | * -EINVAL is returned if device is not supposed to wake up the system |
| 1566 | * Error code depending on the platform is returned if both the platform and |
| 1567 | * the native mechanism fail to enable the generation of wake-up events |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1568 | */ |
Rafael J. Wysocki | 6cbf821 | 2010-02-17 23:44:58 +0100 | [diff] [blame] | 1569 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
| 1570 | bool runtime, bool enable) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1571 | { |
Rafael J. Wysocki | 5bcc2fb | 2009-09-08 23:12:59 +0200 | [diff] [blame] | 1572 | int ret = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1573 | |
Rafael J. Wysocki | 6cbf821 | 2010-02-17 23:44:58 +0100 | [diff] [blame] | 1574 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1575 | return -EINVAL; |
| 1576 | |
Rafael J. Wysocki | e80bb09 | 2009-09-08 23:14:49 +0200 | [diff] [blame] | 1577 | /* Don't do the same thing twice in a row for one device. */ |
| 1578 | if (!!enable == !!dev->wakeup_prepared) |
| 1579 | return 0; |
| 1580 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1581 | /* |
| 1582 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don |
| 1583 | * Anderson we should be doing PME# wake enable followed by ACPI wake |
| 1584 | * enable. To disable wake-up we call the platform first, for symmetry. |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1585 | */ |
| 1586 | |
Rafael J. Wysocki | 5bcc2fb | 2009-09-08 23:12:59 +0200 | [diff] [blame] | 1587 | if (enable) { |
| 1588 | int error; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1589 | |
Rafael J. Wysocki | 5bcc2fb | 2009-09-08 23:12:59 +0200 | [diff] [blame] | 1590 | if (pci_pme_capable(dev, state)) |
| 1591 | pci_pme_active(dev, true); |
| 1592 | else |
| 1593 | ret = 1; |
Rafael J. Wysocki | 6cbf821 | 2010-02-17 23:44:58 +0100 | [diff] [blame] | 1594 | error = runtime ? platform_pci_run_wake(dev, true) : |
| 1595 | platform_pci_sleep_wake(dev, true); |
Rafael J. Wysocki | 5bcc2fb | 2009-09-08 23:12:59 +0200 | [diff] [blame] | 1596 | if (ret) |
| 1597 | ret = error; |
Rafael J. Wysocki | e80bb09 | 2009-09-08 23:14:49 +0200 | [diff] [blame] | 1598 | if (!ret) |
| 1599 | dev->wakeup_prepared = true; |
Rafael J. Wysocki | 5bcc2fb | 2009-09-08 23:12:59 +0200 | [diff] [blame] | 1600 | } else { |
Rafael J. Wysocki | 6cbf821 | 2010-02-17 23:44:58 +0100 | [diff] [blame] | 1601 | if (runtime) |
| 1602 | platform_pci_run_wake(dev, false); |
| 1603 | else |
| 1604 | platform_pci_sleep_wake(dev, false); |
Rafael J. Wysocki | 5bcc2fb | 2009-09-08 23:12:59 +0200 | [diff] [blame] | 1605 | pci_pme_active(dev, false); |
Rafael J. Wysocki | e80bb09 | 2009-09-08 23:14:49 +0200 | [diff] [blame] | 1606 | dev->wakeup_prepared = false; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1607 | } |
| 1608 | |
Rafael J. Wysocki | 5bcc2fb | 2009-09-08 23:12:59 +0200 | [diff] [blame] | 1609 | return ret; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1610 | } |
Rafael J. Wysocki | 6cbf821 | 2010-02-17 23:44:58 +0100 | [diff] [blame] | 1611 | EXPORT_SYMBOL(__pci_enable_wake); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1612 | |
| 1613 | /** |
Rafael J. Wysocki | 0235c4f | 2008-08-18 21:38:00 +0200 | [diff] [blame] | 1614 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold |
| 1615 | * @dev: PCI device to prepare |
| 1616 | * @enable: True to enable wake-up event generation; false to disable |
| 1617 | * |
| 1618 | * Many drivers want the device to wake up the system from D3_hot or D3_cold |
| 1619 | * and this function allows them to set that up cleanly - pci_enable_wake() |
| 1620 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI |
| 1621 | * ordering constraints. |
| 1622 | * |
| 1623 | * This function only returns error code if the device is not capable of |
| 1624 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to |
| 1625 | * enable wake-up power for it. |
| 1626 | */ |
| 1627 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
| 1628 | { |
| 1629 | return pci_pme_capable(dev, PCI_D3cold) ? |
| 1630 | pci_enable_wake(dev, PCI_D3cold, enable) : |
| 1631 | pci_enable_wake(dev, PCI_D3hot, enable); |
| 1632 | } |
| 1633 | |
| 1634 | /** |
Jesse Barnes | 3713907 | 2008-07-28 11:49:26 -0700 | [diff] [blame] | 1635 | * pci_target_state - find an appropriate low power state for a given PCI dev |
| 1636 | * @dev: PCI device |
| 1637 | * |
| 1638 | * Use underlying platform code to find a supported low power state for @dev. |
| 1639 | * If the platform can't manage @dev, return the deepest state from which it |
| 1640 | * can generate wake events, based on any available PME info. |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1641 | */ |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 1642 | pci_power_t pci_target_state(struct pci_dev *dev) |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1643 | { |
| 1644 | pci_power_t target_state = PCI_D3hot; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1645 | |
| 1646 | if (platform_pci_power_manageable(dev)) { |
| 1647 | /* |
| 1648 | * Call the platform to choose the target state of the device |
| 1649 | * and enable wake-up from this state if supported. |
| 1650 | */ |
| 1651 | pci_power_t state = platform_pci_choose_state(dev); |
| 1652 | |
| 1653 | switch (state) { |
| 1654 | case PCI_POWER_ERROR: |
| 1655 | case PCI_UNKNOWN: |
| 1656 | break; |
| 1657 | case PCI_D1: |
| 1658 | case PCI_D2: |
| 1659 | if (pci_no_d1d2(dev)) |
| 1660 | break; |
| 1661 | default: |
| 1662 | target_state = state; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1663 | } |
Rafael J. Wysocki | d2abdf6 | 2009-06-14 21:25:02 +0200 | [diff] [blame] | 1664 | } else if (!dev->pm_cap) { |
| 1665 | target_state = PCI_D0; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1666 | } else if (device_may_wakeup(&dev->dev)) { |
| 1667 | /* |
| 1668 | * Find the deepest state from which the device can generate |
| 1669 | * wake-up events, make it the target state and enable device |
| 1670 | * to generate PME#. |
| 1671 | */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1672 | if (dev->pme_support) { |
| 1673 | while (target_state |
| 1674 | && !(dev->pme_support & (1 << target_state))) |
| 1675 | target_state--; |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1676 | } |
| 1677 | } |
| 1678 | |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 1679 | return target_state; |
| 1680 | } |
| 1681 | |
| 1682 | /** |
| 1683 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state |
| 1684 | * @dev: Device to handle. |
| 1685 | * |
| 1686 | * Choose the power state appropriate for the device depending on whether |
| 1687 | * it can wake up the system and/or is power manageable by the platform |
| 1688 | * (PCI_D3hot is the default) and put the device into that state. |
| 1689 | */ |
| 1690 | int pci_prepare_to_sleep(struct pci_dev *dev) |
| 1691 | { |
| 1692 | pci_power_t target_state = pci_target_state(dev); |
| 1693 | int error; |
| 1694 | |
| 1695 | if (target_state == PCI_POWER_ERROR) |
| 1696 | return -EIO; |
| 1697 | |
Rafael J. Wysocki | 8efb8c7 | 2009-03-30 21:46:27 +0200 | [diff] [blame] | 1698 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
Rafael J. Wysocki | c157dfa | 2008-07-13 22:45:06 +0200 | [diff] [blame] | 1699 | |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1700 | error = pci_set_power_state(dev, target_state); |
| 1701 | |
| 1702 | if (error) |
| 1703 | pci_enable_wake(dev, target_state, false); |
| 1704 | |
| 1705 | return error; |
| 1706 | } |
| 1707 | |
| 1708 | /** |
Randy Dunlap | 443bd1c | 2008-07-21 09:27:18 -0700 | [diff] [blame] | 1709 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1710 | * @dev: Device to handle. |
| 1711 | * |
Thomas Weber | 8839316 | 2010-03-16 11:47:56 +0100 | [diff] [blame] | 1712 | * Disable device's system wake-up capability and put it into D0. |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 1713 | */ |
| 1714 | int pci_back_from_sleep(struct pci_dev *dev) |
| 1715 | { |
| 1716 | pci_enable_wake(dev, PCI_D0, false); |
| 1717 | return pci_set_power_state(dev, PCI_D0); |
| 1718 | } |
| 1719 | |
| 1720 | /** |
Rafael J. Wysocki | 6cbf821 | 2010-02-17 23:44:58 +0100 | [diff] [blame] | 1721 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. |
| 1722 | * @dev: PCI device being suspended. |
| 1723 | * |
| 1724 | * Prepare @dev to generate wake-up events at run time and put it into a low |
| 1725 | * power state. |
| 1726 | */ |
| 1727 | int pci_finish_runtime_suspend(struct pci_dev *dev) |
| 1728 | { |
| 1729 | pci_power_t target_state = pci_target_state(dev); |
| 1730 | int error; |
| 1731 | |
| 1732 | if (target_state == PCI_POWER_ERROR) |
| 1733 | return -EIO; |
| 1734 | |
| 1735 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
| 1736 | |
| 1737 | error = pci_set_power_state(dev, target_state); |
| 1738 | |
| 1739 | if (error) |
| 1740 | __pci_enable_wake(dev, target_state, true, false); |
| 1741 | |
| 1742 | return error; |
| 1743 | } |
| 1744 | |
| 1745 | /** |
Rafael J. Wysocki | b67ea76 | 2010-02-17 23:44:09 +0100 | [diff] [blame] | 1746 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. |
| 1747 | * @dev: Device to check. |
| 1748 | * |
| 1749 | * Return true if the device itself is cabable of generating wake-up events |
| 1750 | * (through the platform or using the native PCIe PME) or if the device supports |
| 1751 | * PME and one of its upstream bridges can generate wake-up events. |
| 1752 | */ |
| 1753 | bool pci_dev_run_wake(struct pci_dev *dev) |
| 1754 | { |
| 1755 | struct pci_bus *bus = dev->bus; |
| 1756 | |
| 1757 | if (device_run_wake(&dev->dev)) |
| 1758 | return true; |
| 1759 | |
| 1760 | if (!dev->pme_support) |
| 1761 | return false; |
| 1762 | |
| 1763 | while (bus->parent) { |
| 1764 | struct pci_dev *bridge = bus->self; |
| 1765 | |
| 1766 | if (device_run_wake(&bridge->dev)) |
| 1767 | return true; |
| 1768 | |
| 1769 | bus = bus->parent; |
| 1770 | } |
| 1771 | |
| 1772 | /* We have reached the root bus. */ |
| 1773 | if (bus->bridge) |
| 1774 | return device_run_wake(bus->bridge); |
| 1775 | |
| 1776 | return false; |
| 1777 | } |
| 1778 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); |
| 1779 | |
| 1780 | /** |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1781 | * pci_pm_init - Initialize PM functions of given PCI device |
| 1782 | * @dev: PCI device to handle. |
| 1783 | */ |
| 1784 | void pci_pm_init(struct pci_dev *dev) |
| 1785 | { |
| 1786 | int pm; |
| 1787 | u16 pmc; |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1788 | |
Rafael J. Wysocki | bb910a7 | 2010-02-27 21:37:37 +0100 | [diff] [blame] | 1789 | pm_runtime_forbid(&dev->dev); |
Rafael J. Wysocki | a1e4d72 | 2010-02-08 19:16:33 +0100 | [diff] [blame] | 1790 | device_enable_async_suspend(&dev->dev); |
Rafael J. Wysocki | e80bb09 | 2009-09-08 23:14:49 +0200 | [diff] [blame] | 1791 | dev->wakeup_prepared = false; |
Rafael J. Wysocki | bb910a7 | 2010-02-27 21:37:37 +0100 | [diff] [blame] | 1792 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1793 | dev->pm_cap = 0; |
| 1794 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1795 | /* find PCI PM capability in list */ |
| 1796 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1797 | if (!pm) |
Linus Torvalds | 50246dd | 2009-01-16 08:14:51 -0800 | [diff] [blame] | 1798 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1799 | /* Check device's ability to generate PME# */ |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1800 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1801 | |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1802 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
| 1803 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", |
| 1804 | pmc & PCI_PM_CAP_VER_MASK); |
Linus Torvalds | 50246dd | 2009-01-16 08:14:51 -0800 | [diff] [blame] | 1805 | return; |
David Brownell | 075c177 | 2007-04-26 00:12:06 -0700 | [diff] [blame] | 1806 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1807 | |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1808 | dev->pm_cap = pm; |
Rafael J. Wysocki | 1ae861e | 2009-12-31 12:15:54 +0100 | [diff] [blame] | 1809 | dev->d3_delay = PCI_PM_D3_WAIT; |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1810 | |
| 1811 | dev->d1_support = false; |
| 1812 | dev->d2_support = false; |
| 1813 | if (!pci_no_d1d2(dev)) { |
Bjorn Helgaas | c9ed77e | 2008-08-22 09:37:02 -0600 | [diff] [blame] | 1814 | if (pmc & PCI_PM_CAP_D1) |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1815 | dev->d1_support = true; |
Bjorn Helgaas | c9ed77e | 2008-08-22 09:37:02 -0600 | [diff] [blame] | 1816 | if (pmc & PCI_PM_CAP_D2) |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1817 | dev->d2_support = true; |
Bjorn Helgaas | c9ed77e | 2008-08-22 09:37:02 -0600 | [diff] [blame] | 1818 | |
| 1819 | if (dev->d1_support || dev->d2_support) |
| 1820 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", |
Jesse Barnes | ec84f12 | 2008-09-23 11:43:34 -0700 | [diff] [blame] | 1821 | dev->d1_support ? " D1" : "", |
| 1822 | dev->d2_support ? " D2" : ""); |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1823 | } |
| 1824 | |
| 1825 | pmc &= PCI_PM_CAP_PME_MASK; |
| 1826 | if (pmc) { |
Bjorn Helgaas | 10c3d71 | 2009-11-04 10:32:42 -0700 | [diff] [blame] | 1827 | dev_printk(KERN_DEBUG, &dev->dev, |
| 1828 | "PME# supported from%s%s%s%s%s\n", |
Bjorn Helgaas | c9ed77e | 2008-08-22 09:37:02 -0600 | [diff] [blame] | 1829 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
| 1830 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", |
| 1831 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", |
| 1832 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", |
| 1833 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1834 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
Rafael J. Wysocki | 379021d | 2011-10-03 23:16:33 +0200 | [diff] [blame] | 1835 | dev->pme_poll = true; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1836 | /* |
| 1837 | * Make device's PM flags reflect the wake-up capability, but |
| 1838 | * let the user space enable it to wake up the system as needed. |
| 1839 | */ |
| 1840 | device_set_wakeup_capable(&dev->dev, true); |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1841 | /* Disable the PME# generation functionality */ |
Rafael J. Wysocki | 337001b | 2008-07-07 03:36:24 +0200 | [diff] [blame] | 1842 | pci_pme_active(dev, false); |
| 1843 | } else { |
| 1844 | dev->pme_support = 0; |
Rafael J. Wysocki | eb9d0fe | 2008-07-07 03:34:48 +0200 | [diff] [blame] | 1845 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1846 | } |
| 1847 | |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1848 | /** |
Jesse Barnes | eb9c39d | 2008-12-17 12:10:05 -0800 | [diff] [blame] | 1849 | * platform_pci_wakeup_init - init platform wakeup if present |
| 1850 | * @dev: PCI device |
| 1851 | * |
| 1852 | * Some devices don't have PCI PM caps but can still generate wakeup |
| 1853 | * events through platform methods (like ACPI events). If @dev supports |
| 1854 | * platform wakeup events, set the device flag to indicate as much. This |
| 1855 | * may be redundant if the device also supports PCI PM caps, but double |
| 1856 | * initialization should be safe in that case. |
| 1857 | */ |
| 1858 | void platform_pci_wakeup_init(struct pci_dev *dev) |
| 1859 | { |
| 1860 | if (!platform_pci_can_wakeup(dev)) |
| 1861 | return; |
| 1862 | |
| 1863 | device_set_wakeup_capable(&dev->dev, true); |
Jesse Barnes | eb9c39d | 2008-12-17 12:10:05 -0800 | [diff] [blame] | 1864 | platform_pci_sleep_wake(dev, false); |
| 1865 | } |
| 1866 | |
| 1867 | /** |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 1868 | * pci_add_save_buffer - allocate buffer for saving given capability registers |
| 1869 | * @dev: the PCI device |
| 1870 | * @cap: the capability to allocate the buffer for |
| 1871 | * @size: requested size of the buffer |
| 1872 | */ |
| 1873 | static int pci_add_cap_save_buffer( |
| 1874 | struct pci_dev *dev, char cap, unsigned int size) |
| 1875 | { |
| 1876 | int pos; |
| 1877 | struct pci_cap_saved_state *save_state; |
| 1878 | |
| 1879 | pos = pci_find_capability(dev, cap); |
| 1880 | if (pos <= 0) |
| 1881 | return 0; |
| 1882 | |
| 1883 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); |
| 1884 | if (!save_state) |
| 1885 | return -ENOMEM; |
| 1886 | |
Alex Williamson | 24a4742f | 2011-05-10 10:02:11 -0600 | [diff] [blame] | 1887 | save_state->cap.cap_nr = cap; |
| 1888 | save_state->cap.size = size; |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 1889 | pci_add_saved_cap(dev, save_state); |
| 1890 | |
| 1891 | return 0; |
| 1892 | } |
| 1893 | |
| 1894 | /** |
| 1895 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities |
| 1896 | * @dev: the PCI device |
| 1897 | */ |
| 1898 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) |
| 1899 | { |
| 1900 | int error; |
| 1901 | |
Yu Zhao | 8985851 | 2009-02-16 02:55:47 +0800 | [diff] [blame] | 1902 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
| 1903 | PCI_EXP_SAVE_REGS * sizeof(u16)); |
Rafael J. Wysocki | 63f4898 | 2008-12-07 22:02:58 +0100 | [diff] [blame] | 1904 | if (error) |
| 1905 | dev_err(&dev->dev, |
| 1906 | "unable to preallocate PCI Express save buffer\n"); |
| 1907 | |
| 1908 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); |
| 1909 | if (error) |
| 1910 | dev_err(&dev->dev, |
| 1911 | "unable to preallocate PCI-X save buffer\n"); |
| 1912 | } |
| 1913 | |
| 1914 | /** |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1915 | * pci_enable_ari - enable ARI forwarding if hardware support it |
| 1916 | * @dev: the PCI device |
| 1917 | */ |
| 1918 | void pci_enable_ari(struct pci_dev *dev) |
| 1919 | { |
| 1920 | int pos; |
| 1921 | u32 cap; |
Chris Wright | 864d296 | 2011-07-13 10:14:33 -0700 | [diff] [blame] | 1922 | u16 flags, ctrl; |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1923 | struct pci_dev *bridge; |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1924 | |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 1925 | if (!pci_is_pcie(dev) || dev->devfn) |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1926 | return; |
| 1927 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1928 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1929 | if (!pos) |
| 1930 | return; |
| 1931 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1932 | bridge = dev->bus->self; |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 1933 | if (!bridge || !pci_is_pcie(bridge)) |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1934 | return; |
| 1935 | |
Kenji Kaneshige | 06a1cba | 2009-11-11 14:30:56 +0900 | [diff] [blame] | 1936 | pos = pci_pcie_cap(bridge); |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1937 | if (!pos) |
| 1938 | return; |
| 1939 | |
Chris Wright | 864d296 | 2011-07-13 10:14:33 -0700 | [diff] [blame] | 1940 | /* ARI is a PCIe v2 feature */ |
| 1941 | pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags); |
| 1942 | if ((flags & PCI_EXP_FLAGS_VERS) < 2) |
| 1943 | return; |
| 1944 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1945 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1946 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
| 1947 | return; |
| 1948 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1949 | pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1950 | ctrl |= PCI_EXP_DEVCTL2_ARI; |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1951 | pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1952 | |
Zhao, Yu | 8113587 | 2008-10-23 13:15:39 +0800 | [diff] [blame] | 1953 | bridge->ari_enabled = 1; |
Yu Zhao | 58c3a72 | 2008-10-14 14:02:53 +0800 | [diff] [blame] | 1954 | } |
| 1955 | |
Jesse Barnes | b48d442 | 2010-10-19 13:07:57 -0700 | [diff] [blame] | 1956 | /** |
| 1957 | * pci_enable_ido - enable ID-based ordering on a device |
| 1958 | * @dev: the PCI device |
| 1959 | * @type: which types of IDO to enable |
| 1960 | * |
| 1961 | * Enable ID-based ordering on @dev. @type can contain the bits |
| 1962 | * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate |
| 1963 | * which types of transactions are allowed to be re-ordered. |
| 1964 | */ |
| 1965 | void pci_enable_ido(struct pci_dev *dev, unsigned long type) |
| 1966 | { |
| 1967 | int pos; |
| 1968 | u16 ctrl; |
| 1969 | |
| 1970 | pos = pci_pcie_cap(dev); |
| 1971 | if (!pos) |
| 1972 | return; |
| 1973 | |
| 1974 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); |
| 1975 | if (type & PCI_EXP_IDO_REQUEST) |
| 1976 | ctrl |= PCI_EXP_IDO_REQ_EN; |
| 1977 | if (type & PCI_EXP_IDO_COMPLETION) |
| 1978 | ctrl |= PCI_EXP_IDO_CMP_EN; |
| 1979 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); |
| 1980 | } |
| 1981 | EXPORT_SYMBOL(pci_enable_ido); |
| 1982 | |
| 1983 | /** |
| 1984 | * pci_disable_ido - disable ID-based ordering on a device |
| 1985 | * @dev: the PCI device |
| 1986 | * @type: which types of IDO to disable |
| 1987 | */ |
| 1988 | void pci_disable_ido(struct pci_dev *dev, unsigned long type) |
| 1989 | { |
| 1990 | int pos; |
| 1991 | u16 ctrl; |
| 1992 | |
| 1993 | if (!pci_is_pcie(dev)) |
| 1994 | return; |
| 1995 | |
| 1996 | pos = pci_pcie_cap(dev); |
| 1997 | if (!pos) |
| 1998 | return; |
| 1999 | |
| 2000 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); |
| 2001 | if (type & PCI_EXP_IDO_REQUEST) |
| 2002 | ctrl &= ~PCI_EXP_IDO_REQ_EN; |
| 2003 | if (type & PCI_EXP_IDO_COMPLETION) |
| 2004 | ctrl &= ~PCI_EXP_IDO_CMP_EN; |
| 2005 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); |
| 2006 | } |
| 2007 | EXPORT_SYMBOL(pci_disable_ido); |
| 2008 | |
Jesse Barnes | 48a92a8 | 2011-01-10 12:46:36 -0800 | [diff] [blame] | 2009 | /** |
| 2010 | * pci_enable_obff - enable optimized buffer flush/fill |
| 2011 | * @dev: PCI device |
| 2012 | * @type: type of signaling to use |
| 2013 | * |
| 2014 | * Try to enable @type OBFF signaling on @dev. It will try using WAKE# |
| 2015 | * signaling if possible, falling back to message signaling only if |
| 2016 | * WAKE# isn't supported. @type should indicate whether the PCIe link |
| 2017 | * be brought out of L0s or L1 to send the message. It should be either |
| 2018 | * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0. |
| 2019 | * |
| 2020 | * If your device can benefit from receiving all messages, even at the |
| 2021 | * power cost of bringing the link back up from a low power state, use |
| 2022 | * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the |
| 2023 | * preferred type). |
| 2024 | * |
| 2025 | * RETURNS: |
| 2026 | * Zero on success, appropriate error number on failure. |
| 2027 | */ |
| 2028 | int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) |
| 2029 | { |
| 2030 | int pos; |
| 2031 | u32 cap; |
| 2032 | u16 ctrl; |
| 2033 | int ret; |
| 2034 | |
| 2035 | if (!pci_is_pcie(dev)) |
| 2036 | return -ENOTSUPP; |
| 2037 | |
| 2038 | pos = pci_pcie_cap(dev); |
| 2039 | if (!pos) |
| 2040 | return -ENOTSUPP; |
| 2041 | |
| 2042 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); |
| 2043 | if (!(cap & PCI_EXP_OBFF_MASK)) |
| 2044 | return -ENOTSUPP; /* no OBFF support at all */ |
| 2045 | |
| 2046 | /* Make sure the topology supports OBFF as well */ |
| 2047 | if (dev->bus) { |
| 2048 | ret = pci_enable_obff(dev->bus->self, type); |
| 2049 | if (ret) |
| 2050 | return ret; |
| 2051 | } |
| 2052 | |
| 2053 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); |
| 2054 | if (cap & PCI_EXP_OBFF_WAKE) |
| 2055 | ctrl |= PCI_EXP_OBFF_WAKE_EN; |
| 2056 | else { |
| 2057 | switch (type) { |
| 2058 | case PCI_EXP_OBFF_SIGNAL_L0: |
| 2059 | if (!(ctrl & PCI_EXP_OBFF_WAKE_EN)) |
| 2060 | ctrl |= PCI_EXP_OBFF_MSGA_EN; |
| 2061 | break; |
| 2062 | case PCI_EXP_OBFF_SIGNAL_ALWAYS: |
| 2063 | ctrl &= ~PCI_EXP_OBFF_WAKE_EN; |
| 2064 | ctrl |= PCI_EXP_OBFF_MSGB_EN; |
| 2065 | break; |
| 2066 | default: |
| 2067 | WARN(1, "bad OBFF signal type\n"); |
| 2068 | return -ENOTSUPP; |
| 2069 | } |
| 2070 | } |
| 2071 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); |
| 2072 | |
| 2073 | return 0; |
| 2074 | } |
| 2075 | EXPORT_SYMBOL(pci_enable_obff); |
| 2076 | |
| 2077 | /** |
| 2078 | * pci_disable_obff - disable optimized buffer flush/fill |
| 2079 | * @dev: PCI device |
| 2080 | * |
| 2081 | * Disable OBFF on @dev. |
| 2082 | */ |
| 2083 | void pci_disable_obff(struct pci_dev *dev) |
| 2084 | { |
| 2085 | int pos; |
| 2086 | u16 ctrl; |
| 2087 | |
| 2088 | if (!pci_is_pcie(dev)) |
| 2089 | return; |
| 2090 | |
| 2091 | pos = pci_pcie_cap(dev); |
| 2092 | if (!pos) |
| 2093 | return; |
| 2094 | |
| 2095 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); |
| 2096 | ctrl &= ~PCI_EXP_OBFF_WAKE_EN; |
| 2097 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); |
| 2098 | } |
| 2099 | EXPORT_SYMBOL(pci_disable_obff); |
| 2100 | |
Jesse Barnes | 51c2e0a | 2011-01-14 08:53:04 -0800 | [diff] [blame] | 2101 | /** |
| 2102 | * pci_ltr_supported - check whether a device supports LTR |
| 2103 | * @dev: PCI device |
| 2104 | * |
| 2105 | * RETURNS: |
| 2106 | * True if @dev supports latency tolerance reporting, false otherwise. |
| 2107 | */ |
| 2108 | bool pci_ltr_supported(struct pci_dev *dev) |
| 2109 | { |
| 2110 | int pos; |
| 2111 | u32 cap; |
| 2112 | |
| 2113 | if (!pci_is_pcie(dev)) |
| 2114 | return false; |
| 2115 | |
| 2116 | pos = pci_pcie_cap(dev); |
| 2117 | if (!pos) |
| 2118 | return false; |
| 2119 | |
| 2120 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); |
| 2121 | |
| 2122 | return cap & PCI_EXP_DEVCAP2_LTR; |
| 2123 | } |
| 2124 | EXPORT_SYMBOL(pci_ltr_supported); |
| 2125 | |
| 2126 | /** |
| 2127 | * pci_enable_ltr - enable latency tolerance reporting |
| 2128 | * @dev: PCI device |
| 2129 | * |
| 2130 | * Enable LTR on @dev if possible, which means enabling it first on |
| 2131 | * upstream ports. |
| 2132 | * |
| 2133 | * RETURNS: |
| 2134 | * Zero on success, errno on failure. |
| 2135 | */ |
| 2136 | int pci_enable_ltr(struct pci_dev *dev) |
| 2137 | { |
| 2138 | int pos; |
| 2139 | u16 ctrl; |
| 2140 | int ret; |
| 2141 | |
| 2142 | if (!pci_ltr_supported(dev)) |
| 2143 | return -ENOTSUPP; |
| 2144 | |
| 2145 | pos = pci_pcie_cap(dev); |
| 2146 | if (!pos) |
| 2147 | return -ENOTSUPP; |
| 2148 | |
| 2149 | /* Only primary function can enable/disable LTR */ |
| 2150 | if (PCI_FUNC(dev->devfn) != 0) |
| 2151 | return -EINVAL; |
| 2152 | |
| 2153 | /* Enable upstream ports first */ |
| 2154 | if (dev->bus) { |
| 2155 | ret = pci_enable_ltr(dev->bus->self); |
| 2156 | if (ret) |
| 2157 | return ret; |
| 2158 | } |
| 2159 | |
| 2160 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); |
| 2161 | ctrl |= PCI_EXP_LTR_EN; |
| 2162 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); |
| 2163 | |
| 2164 | return 0; |
| 2165 | } |
| 2166 | EXPORT_SYMBOL(pci_enable_ltr); |
| 2167 | |
| 2168 | /** |
| 2169 | * pci_disable_ltr - disable latency tolerance reporting |
| 2170 | * @dev: PCI device |
| 2171 | */ |
| 2172 | void pci_disable_ltr(struct pci_dev *dev) |
| 2173 | { |
| 2174 | int pos; |
| 2175 | u16 ctrl; |
| 2176 | |
| 2177 | if (!pci_ltr_supported(dev)) |
| 2178 | return; |
| 2179 | |
| 2180 | pos = pci_pcie_cap(dev); |
| 2181 | if (!pos) |
| 2182 | return; |
| 2183 | |
| 2184 | /* Only primary function can enable/disable LTR */ |
| 2185 | if (PCI_FUNC(dev->devfn) != 0) |
| 2186 | return; |
| 2187 | |
| 2188 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); |
| 2189 | ctrl &= ~PCI_EXP_LTR_EN; |
| 2190 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); |
| 2191 | } |
| 2192 | EXPORT_SYMBOL(pci_disable_ltr); |
| 2193 | |
| 2194 | static int __pci_ltr_scale(int *val) |
| 2195 | { |
| 2196 | int scale = 0; |
| 2197 | |
| 2198 | while (*val > 1023) { |
| 2199 | *val = (*val + 31) / 32; |
| 2200 | scale++; |
| 2201 | } |
| 2202 | return scale; |
| 2203 | } |
| 2204 | |
| 2205 | /** |
| 2206 | * pci_set_ltr - set LTR latency values |
| 2207 | * @dev: PCI device |
| 2208 | * @snoop_lat_ns: snoop latency in nanoseconds |
| 2209 | * @nosnoop_lat_ns: nosnoop latency in nanoseconds |
| 2210 | * |
| 2211 | * Figure out the scale and set the LTR values accordingly. |
| 2212 | */ |
| 2213 | int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns) |
| 2214 | { |
| 2215 | int pos, ret, snoop_scale, nosnoop_scale; |
| 2216 | u16 val; |
| 2217 | |
| 2218 | if (!pci_ltr_supported(dev)) |
| 2219 | return -ENOTSUPP; |
| 2220 | |
| 2221 | snoop_scale = __pci_ltr_scale(&snoop_lat_ns); |
| 2222 | nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns); |
| 2223 | |
| 2224 | if (snoop_lat_ns > PCI_LTR_VALUE_MASK || |
| 2225 | nosnoop_lat_ns > PCI_LTR_VALUE_MASK) |
| 2226 | return -EINVAL; |
| 2227 | |
| 2228 | if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) || |
| 2229 | (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT))) |
| 2230 | return -EINVAL; |
| 2231 | |
| 2232 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); |
| 2233 | if (!pos) |
| 2234 | return -ENOTSUPP; |
| 2235 | |
| 2236 | val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns; |
| 2237 | ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val); |
| 2238 | if (ret != 4) |
| 2239 | return -EIO; |
| 2240 | |
| 2241 | val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns; |
| 2242 | ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val); |
| 2243 | if (ret != 4) |
| 2244 | return -EIO; |
| 2245 | |
| 2246 | return 0; |
| 2247 | } |
| 2248 | EXPORT_SYMBOL(pci_set_ltr); |
| 2249 | |
Chris Wright | 5d990b6 | 2009-12-04 12:15:21 -0800 | [diff] [blame] | 2250 | static int pci_acs_enable; |
| 2251 | |
| 2252 | /** |
| 2253 | * pci_request_acs - ask for ACS to be enabled if supported |
| 2254 | */ |
| 2255 | void pci_request_acs(void) |
| 2256 | { |
| 2257 | pci_acs_enable = 1; |
| 2258 | } |
| 2259 | |
Bjorn Helgaas | 57c2cf7 | 2008-12-11 11:24:23 -0700 | [diff] [blame] | 2260 | /** |
Allen Kay | ae21ee6 | 2009-10-07 10:27:17 -0700 | [diff] [blame] | 2261 | * pci_enable_acs - enable ACS if hardware support it |
| 2262 | * @dev: the PCI device |
| 2263 | */ |
| 2264 | void pci_enable_acs(struct pci_dev *dev) |
| 2265 | { |
| 2266 | int pos; |
| 2267 | u16 cap; |
| 2268 | u16 ctrl; |
| 2269 | |
Chris Wright | 5d990b6 | 2009-12-04 12:15:21 -0800 | [diff] [blame] | 2270 | if (!pci_acs_enable) |
| 2271 | return; |
| 2272 | |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 2273 | if (!pci_is_pcie(dev)) |
Allen Kay | ae21ee6 | 2009-10-07 10:27:17 -0700 | [diff] [blame] | 2274 | return; |
| 2275 | |
| 2276 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
| 2277 | if (!pos) |
| 2278 | return; |
| 2279 | |
| 2280 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); |
| 2281 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); |
| 2282 | |
| 2283 | /* Source Validation */ |
| 2284 | ctrl |= (cap & PCI_ACS_SV); |
| 2285 | |
| 2286 | /* P2P Request Redirect */ |
| 2287 | ctrl |= (cap & PCI_ACS_RR); |
| 2288 | |
| 2289 | /* P2P Completion Redirect */ |
| 2290 | ctrl |= (cap & PCI_ACS_CR); |
| 2291 | |
| 2292 | /* Upstream Forwarding */ |
| 2293 | ctrl |= (cap & PCI_ACS_UF); |
| 2294 | |
| 2295 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); |
| 2296 | } |
| 2297 | |
| 2298 | /** |
Bjorn Helgaas | 57c2cf7 | 2008-12-11 11:24:23 -0700 | [diff] [blame] | 2299 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge |
| 2300 | * @dev: the PCI device |
| 2301 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) |
| 2302 | * |
| 2303 | * Perform INTx swizzling for a device behind one level of bridge. This is |
| 2304 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices |
Matthew Wilcox | 46b952a | 2009-07-01 14:24:30 -0700 | [diff] [blame] | 2305 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
| 2306 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of |
| 2307 | * the PCI Express Base Specification, Revision 2.1) |
Bjorn Helgaas | 57c2cf7 | 2008-12-11 11:24:23 -0700 | [diff] [blame] | 2308 | */ |
| 2309 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) |
| 2310 | { |
Matthew Wilcox | 46b952a | 2009-07-01 14:24:30 -0700 | [diff] [blame] | 2311 | int slot; |
| 2312 | |
| 2313 | if (pci_ari_enabled(dev->bus)) |
| 2314 | slot = 0; |
| 2315 | else |
| 2316 | slot = PCI_SLOT(dev->devfn); |
| 2317 | |
| 2318 | return (((pin - 1) + slot) % 4) + 1; |
Bjorn Helgaas | 57c2cf7 | 2008-12-11 11:24:23 -0700 | [diff] [blame] | 2319 | } |
| 2320 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2321 | int |
| 2322 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
| 2323 | { |
| 2324 | u8 pin; |
| 2325 | |
Kristen Accardi | 514d207 | 2005-11-02 16:24:39 -0800 | [diff] [blame] | 2326 | pin = dev->pin; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2327 | if (!pin) |
| 2328 | return -1; |
Bjorn Helgaas | 878f2e5 | 2008-12-09 16:11:46 -0700 | [diff] [blame] | 2329 | |
Kenji Kaneshige | 8784fd4 | 2009-05-26 16:07:33 +0900 | [diff] [blame] | 2330 | while (!pci_is_root_bus(dev->bus)) { |
Bjorn Helgaas | 57c2cf7 | 2008-12-11 11:24:23 -0700 | [diff] [blame] | 2331 | pin = pci_swizzle_interrupt_pin(dev, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2332 | dev = dev->bus->self; |
| 2333 | } |
| 2334 | *bridge = dev; |
| 2335 | return pin; |
| 2336 | } |
| 2337 | |
| 2338 | /** |
Bjorn Helgaas | 68feac8 | 2008-12-16 21:36:55 -0700 | [diff] [blame] | 2339 | * pci_common_swizzle - swizzle INTx all the way to root bridge |
| 2340 | * @dev: the PCI device |
| 2341 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) |
| 2342 | * |
| 2343 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI |
| 2344 | * bridges all the way up to a PCI root bus. |
| 2345 | */ |
| 2346 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) |
| 2347 | { |
| 2348 | u8 pin = *pinp; |
| 2349 | |
Kenji Kaneshige | 1eb3948 | 2009-05-26 16:08:36 +0900 | [diff] [blame] | 2350 | while (!pci_is_root_bus(dev->bus)) { |
Bjorn Helgaas | 68feac8 | 2008-12-16 21:36:55 -0700 | [diff] [blame] | 2351 | pin = pci_swizzle_interrupt_pin(dev, pin); |
| 2352 | dev = dev->bus->self; |
| 2353 | } |
| 2354 | *pinp = pin; |
| 2355 | return PCI_SLOT(dev->devfn); |
| 2356 | } |
| 2357 | |
| 2358 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2359 | * pci_release_region - Release a PCI bar |
| 2360 | * @pdev: PCI device whose resources were previously reserved by pci_request_region |
| 2361 | * @bar: BAR to release |
| 2362 | * |
| 2363 | * Releases the PCI I/O and memory resources previously reserved by a |
| 2364 | * successful call to pci_request_region. Call this function only |
| 2365 | * after all use of the PCI regions has ceased. |
| 2366 | */ |
| 2367 | void pci_release_region(struct pci_dev *pdev, int bar) |
| 2368 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 2369 | struct pci_devres *dr; |
| 2370 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2371 | if (pci_resource_len(pdev, bar) == 0) |
| 2372 | return; |
| 2373 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) |
| 2374 | release_region(pci_resource_start(pdev, bar), |
| 2375 | pci_resource_len(pdev, bar)); |
| 2376 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) |
| 2377 | release_mem_region(pci_resource_start(pdev, bar), |
| 2378 | pci_resource_len(pdev, bar)); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 2379 | |
| 2380 | dr = find_pci_dr(pdev); |
| 2381 | if (dr) |
| 2382 | dr->region_mask &= ~(1 << bar); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2383 | } |
| 2384 | |
| 2385 | /** |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 2386 | * __pci_request_region - Reserved PCI I/O and memory resource |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2387 | * @pdev: PCI device whose resources are to be reserved |
| 2388 | * @bar: BAR to be reserved |
| 2389 | * @res_name: Name to be associated with resource. |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 2390 | * @exclusive: whether the region access is exclusive or not |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2391 | * |
| 2392 | * Mark the PCI region associated with PCI device @pdev BR @bar as |
| 2393 | * being reserved by owner @res_name. Do not access any |
| 2394 | * address inside the PCI regions unless this call returns |
| 2395 | * successfully. |
| 2396 | * |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 2397 | * If @exclusive is set, then the region is marked so that userspace |
| 2398 | * is explicitly not allowed to map the resource via /dev/mem or |
| 2399 | * sysfs MMIO access. |
| 2400 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2401 | * Returns 0 on success, or %EBUSY on error. A warning |
| 2402 | * message is also printed on failure. |
| 2403 | */ |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2404 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
| 2405 | int exclusive) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2406 | { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 2407 | struct pci_devres *dr; |
| 2408 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2409 | if (pci_resource_len(pdev, bar) == 0) |
| 2410 | return 0; |
| 2411 | |
| 2412 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
| 2413 | if (!request_region(pci_resource_start(pdev, bar), |
| 2414 | pci_resource_len(pdev, bar), res_name)) |
| 2415 | goto err_out; |
| 2416 | } |
| 2417 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2418 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
| 2419 | pci_resource_len(pdev, bar), res_name, |
| 2420 | exclusive)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2421 | goto err_out; |
| 2422 | } |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 2423 | |
| 2424 | dr = find_pci_dr(pdev); |
| 2425 | if (dr) |
| 2426 | dr->region_mask |= 1 << bar; |
| 2427 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2428 | return 0; |
| 2429 | |
| 2430 | err_out: |
Bjorn Helgaas | c7dabef | 2009-10-27 13:26:47 -0600 | [diff] [blame] | 2431 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
Benjamin Herrenschmidt | 096e6f6 | 2008-10-20 15:07:37 +1100 | [diff] [blame] | 2432 | &pdev->resource[bar]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2433 | return -EBUSY; |
| 2434 | } |
| 2435 | |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2436 | /** |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 2437 | * pci_request_region - Reserve PCI I/O and memory resource |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2438 | * @pdev: PCI device whose resources are to be reserved |
| 2439 | * @bar: BAR to be reserved |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 2440 | * @res_name: Name to be associated with resource |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2441 | * |
Randy Dunlap | f5ddcac | 2009-01-09 17:03:20 -0800 | [diff] [blame] | 2442 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2443 | * being reserved by owner @res_name. Do not access any |
| 2444 | * address inside the PCI regions unless this call returns |
| 2445 | * successfully. |
| 2446 | * |
| 2447 | * Returns 0 on success, or %EBUSY on error. A warning |
| 2448 | * message is also printed on failure. |
| 2449 | */ |
| 2450 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
| 2451 | { |
| 2452 | return __pci_request_region(pdev, bar, res_name, 0); |
| 2453 | } |
| 2454 | |
| 2455 | /** |
| 2456 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource |
| 2457 | * @pdev: PCI device whose resources are to be reserved |
| 2458 | * @bar: BAR to be reserved |
| 2459 | * @res_name: Name to be associated with resource. |
| 2460 | * |
| 2461 | * Mark the PCI region associated with PCI device @pdev BR @bar as |
| 2462 | * being reserved by owner @res_name. Do not access any |
| 2463 | * address inside the PCI regions unless this call returns |
| 2464 | * successfully. |
| 2465 | * |
| 2466 | * Returns 0 on success, or %EBUSY on error. A warning |
| 2467 | * message is also printed on failure. |
| 2468 | * |
| 2469 | * The key difference that _exclusive makes it that userspace is |
| 2470 | * explicitly not allowed to map the resource via /dev/mem or |
| 2471 | * sysfs. |
| 2472 | */ |
| 2473 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) |
| 2474 | { |
| 2475 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); |
| 2476 | } |
| 2477 | /** |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2478 | * pci_release_selected_regions - Release selected PCI I/O and memory resources |
| 2479 | * @pdev: PCI device whose resources were previously reserved |
| 2480 | * @bars: Bitmask of BARs to be released |
| 2481 | * |
| 2482 | * Release selected PCI I/O and memory resources previously reserved. |
| 2483 | * Call this function only after all use of the PCI regions has ceased. |
| 2484 | */ |
| 2485 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) |
| 2486 | { |
| 2487 | int i; |
| 2488 | |
| 2489 | for (i = 0; i < 6; i++) |
| 2490 | if (bars & (1 << i)) |
| 2491 | pci_release_region(pdev, i); |
| 2492 | } |
| 2493 | |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2494 | int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
| 2495 | const char *res_name, int excl) |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2496 | { |
| 2497 | int i; |
| 2498 | |
| 2499 | for (i = 0; i < 6; i++) |
| 2500 | if (bars & (1 << i)) |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2501 | if (__pci_request_region(pdev, i, res_name, excl)) |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2502 | goto err_out; |
| 2503 | return 0; |
| 2504 | |
| 2505 | err_out: |
| 2506 | while(--i >= 0) |
| 2507 | if (bars & (1 << i)) |
| 2508 | pci_release_region(pdev, i); |
| 2509 | |
| 2510 | return -EBUSY; |
| 2511 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2512 | |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2513 | |
| 2514 | /** |
| 2515 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources |
| 2516 | * @pdev: PCI device whose resources are to be reserved |
| 2517 | * @bars: Bitmask of BARs to be requested |
| 2518 | * @res_name: Name to be associated with resource |
| 2519 | */ |
| 2520 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, |
| 2521 | const char *res_name) |
| 2522 | { |
| 2523 | return __pci_request_selected_regions(pdev, bars, res_name, 0); |
| 2524 | } |
| 2525 | |
| 2526 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, |
| 2527 | int bars, const char *res_name) |
| 2528 | { |
| 2529 | return __pci_request_selected_regions(pdev, bars, res_name, |
| 2530 | IORESOURCE_EXCLUSIVE); |
| 2531 | } |
| 2532 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2533 | /** |
| 2534 | * pci_release_regions - Release reserved PCI I/O and memory resources |
| 2535 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions |
| 2536 | * |
| 2537 | * Releases all PCI I/O and memory resources previously reserved by a |
| 2538 | * successful call to pci_request_regions. Call this function only |
| 2539 | * after all use of the PCI regions has ceased. |
| 2540 | */ |
| 2541 | |
| 2542 | void pci_release_regions(struct pci_dev *pdev) |
| 2543 | { |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2544 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2545 | } |
| 2546 | |
| 2547 | /** |
| 2548 | * pci_request_regions - Reserved PCI I/O and memory resources |
| 2549 | * @pdev: PCI device whose resources are to be reserved |
| 2550 | * @res_name: Name to be associated with resource. |
| 2551 | * |
| 2552 | * Mark all PCI regions associated with PCI device @pdev as |
| 2553 | * being reserved by owner @res_name. Do not access any |
| 2554 | * address inside the PCI regions unless this call returns |
| 2555 | * successfully. |
| 2556 | * |
| 2557 | * Returns 0 on success, or %EBUSY on error. A warning |
| 2558 | * message is also printed on failure. |
| 2559 | */ |
Jeff Garzik | 3c990e9 | 2006-03-04 21:52:42 -0500 | [diff] [blame] | 2560 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2561 | { |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 2562 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2563 | } |
| 2564 | |
| 2565 | /** |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2566 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources |
| 2567 | * @pdev: PCI device whose resources are to be reserved |
| 2568 | * @res_name: Name to be associated with resource. |
| 2569 | * |
| 2570 | * Mark all PCI regions associated with PCI device @pdev as |
| 2571 | * being reserved by owner @res_name. Do not access any |
| 2572 | * address inside the PCI regions unless this call returns |
| 2573 | * successfully. |
| 2574 | * |
| 2575 | * pci_request_regions_exclusive() will mark the region so that |
| 2576 | * /dev/mem and the sysfs MMIO access will not be allowed. |
| 2577 | * |
| 2578 | * Returns 0 on success, or %EBUSY on error. A warning |
| 2579 | * message is also printed on failure. |
| 2580 | */ |
| 2581 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) |
| 2582 | { |
| 2583 | return pci_request_selected_regions_exclusive(pdev, |
| 2584 | ((1 << 6) - 1), res_name); |
| 2585 | } |
| 2586 | |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 2587 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
| 2588 | { |
| 2589 | u16 old_cmd, cmd; |
| 2590 | |
| 2591 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); |
| 2592 | if (enable) |
| 2593 | cmd = old_cmd | PCI_COMMAND_MASTER; |
| 2594 | else |
| 2595 | cmd = old_cmd & ~PCI_COMMAND_MASTER; |
| 2596 | if (cmd != old_cmd) { |
| 2597 | dev_dbg(&dev->dev, "%s bus mastering\n", |
| 2598 | enable ? "enabling" : "disabling"); |
| 2599 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 2600 | } |
| 2601 | dev->is_busmaster = enable; |
| 2602 | } |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 2603 | |
| 2604 | /** |
Myron Stowe | 96c5590 | 2011-10-28 15:48:38 -0600 | [diff] [blame] | 2605 | * pcibios_set_master - enable PCI bus-mastering for device dev |
| 2606 | * @dev: the PCI device to enable |
| 2607 | * |
| 2608 | * Enables PCI bus-mastering for the device. This is the default |
| 2609 | * implementation. Architecture specific implementations can override |
| 2610 | * this if necessary. |
| 2611 | */ |
| 2612 | void __weak pcibios_set_master(struct pci_dev *dev) |
| 2613 | { |
| 2614 | u8 lat; |
| 2615 | |
Myron Stowe | f676678 | 2011-10-28 15:49:20 -0600 | [diff] [blame] | 2616 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
| 2617 | if (pci_is_pcie(dev)) |
| 2618 | return; |
| 2619 | |
Myron Stowe | 96c5590 | 2011-10-28 15:48:38 -0600 | [diff] [blame] | 2620 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
| 2621 | if (lat < 16) |
| 2622 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; |
| 2623 | else if (lat > pcibios_max_latency) |
| 2624 | lat = pcibios_max_latency; |
| 2625 | else |
| 2626 | return; |
| 2627 | dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); |
| 2628 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
| 2629 | } |
| 2630 | |
| 2631 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2632 | * pci_set_master - enables bus-mastering for device dev |
| 2633 | * @dev: the PCI device to enable |
| 2634 | * |
| 2635 | * Enables bus-mastering on the device and calls pcibios_set_master() |
| 2636 | * to do the needed arch specific settings. |
| 2637 | */ |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 2638 | void pci_set_master(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2639 | { |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 2640 | __pci_set_master(dev, true); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2641 | pcibios_set_master(dev); |
| 2642 | } |
| 2643 | |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 2644 | /** |
| 2645 | * pci_clear_master - disables bus-mastering for device dev |
| 2646 | * @dev: the PCI device to disable |
| 2647 | */ |
| 2648 | void pci_clear_master(struct pci_dev *dev) |
| 2649 | { |
| 2650 | __pci_set_master(dev, false); |
| 2651 | } |
| 2652 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2653 | /** |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 2654 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
| 2655 | * @dev: the PCI device for which MWI is to be enabled |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2656 | * |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 2657 | * Helper function for pci_set_mwi. |
| 2658 | * Originally copied from drivers/net/acenic.c. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2659 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
| 2660 | * |
| 2661 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 2662 | */ |
Tejun Heo | 15ea76d | 2009-09-22 17:34:48 +0900 | [diff] [blame] | 2663 | int pci_set_cacheline_size(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2664 | { |
| 2665 | u8 cacheline_size; |
| 2666 | |
| 2667 | if (!pci_cache_line_size) |
Tejun Heo | 15ea76d | 2009-09-22 17:34:48 +0900 | [diff] [blame] | 2668 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2669 | |
| 2670 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be |
| 2671 | equal to or multiple of the right value. */ |
| 2672 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); |
| 2673 | if (cacheline_size >= pci_cache_line_size && |
| 2674 | (cacheline_size % pci_cache_line_size) == 0) |
| 2675 | return 0; |
| 2676 | |
| 2677 | /* Write the correct value. */ |
| 2678 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); |
| 2679 | /* Read it back. */ |
| 2680 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); |
| 2681 | if (cacheline_size == pci_cache_line_size) |
| 2682 | return 0; |
| 2683 | |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 2684 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
| 2685 | "supported\n", pci_cache_line_size << 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2686 | |
| 2687 | return -EINVAL; |
| 2688 | } |
Tejun Heo | 15ea76d | 2009-09-22 17:34:48 +0900 | [diff] [blame] | 2689 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
| 2690 | |
| 2691 | #ifdef PCI_DISABLE_MWI |
| 2692 | int pci_set_mwi(struct pci_dev *dev) |
| 2693 | { |
| 2694 | return 0; |
| 2695 | } |
| 2696 | |
| 2697 | int pci_try_set_mwi(struct pci_dev *dev) |
| 2698 | { |
| 2699 | return 0; |
| 2700 | } |
| 2701 | |
| 2702 | void pci_clear_mwi(struct pci_dev *dev) |
| 2703 | { |
| 2704 | } |
| 2705 | |
| 2706 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2707 | |
| 2708 | /** |
| 2709 | * pci_set_mwi - enables memory-write-invalidate PCI transaction |
| 2710 | * @dev: the PCI device for which MWI is enabled |
| 2711 | * |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 2712 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2713 | * |
| 2714 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 2715 | */ |
| 2716 | int |
| 2717 | pci_set_mwi(struct pci_dev *dev) |
| 2718 | { |
| 2719 | int rc; |
| 2720 | u16 cmd; |
| 2721 | |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 2722 | rc = pci_set_cacheline_size(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2723 | if (rc) |
| 2724 | return rc; |
| 2725 | |
| 2726 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 2727 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { |
Bjorn Helgaas | 80ccba1 | 2008-06-13 10:52:11 -0600 | [diff] [blame] | 2728 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2729 | cmd |= PCI_COMMAND_INVALIDATE; |
| 2730 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 2731 | } |
| 2732 | |
| 2733 | return 0; |
| 2734 | } |
| 2735 | |
| 2736 | /** |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 2737 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction |
| 2738 | * @dev: the PCI device for which MWI is enabled |
| 2739 | * |
| 2740 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
| 2741 | * Callers are not required to check the return value. |
| 2742 | * |
| 2743 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
| 2744 | */ |
| 2745 | int pci_try_set_mwi(struct pci_dev *dev) |
| 2746 | { |
| 2747 | int rc = pci_set_mwi(dev); |
| 2748 | return rc; |
| 2749 | } |
| 2750 | |
| 2751 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2752 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev |
| 2753 | * @dev: the PCI device to disable |
| 2754 | * |
| 2755 | * Disables PCI Memory-Write-Invalidate transaction on the device |
| 2756 | */ |
| 2757 | void |
| 2758 | pci_clear_mwi(struct pci_dev *dev) |
| 2759 | { |
| 2760 | u16 cmd; |
| 2761 | |
| 2762 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 2763 | if (cmd & PCI_COMMAND_INVALIDATE) { |
| 2764 | cmd &= ~PCI_COMMAND_INVALIDATE; |
| 2765 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 2766 | } |
| 2767 | } |
Matthew Wilcox | edb2d97 | 2006-10-10 08:01:21 -0600 | [diff] [blame] | 2768 | #endif /* ! PCI_DISABLE_MWI */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2769 | |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 2770 | /** |
| 2771 | * pci_intx - enables/disables PCI INTx for device dev |
Randy Dunlap | 8f7020d | 2005-10-23 11:57:38 -0700 | [diff] [blame] | 2772 | * @pdev: the PCI device to operate on |
| 2773 | * @enable: boolean: whether to enable or disable PCI INTx |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 2774 | * |
| 2775 | * Enables/disables PCI INTx for device dev |
| 2776 | */ |
| 2777 | void |
| 2778 | pci_intx(struct pci_dev *pdev, int enable) |
| 2779 | { |
| 2780 | u16 pci_command, new; |
| 2781 | |
| 2782 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); |
| 2783 | |
| 2784 | if (enable) { |
| 2785 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
| 2786 | } else { |
| 2787 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
| 2788 | } |
| 2789 | |
| 2790 | if (new != pci_command) { |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 2791 | struct pci_devres *dr; |
| 2792 | |
Brett M Russ | 2fd9d74 | 2005-09-09 10:02:22 -0700 | [diff] [blame] | 2793 | pci_write_config_word(pdev, PCI_COMMAND, new); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 2794 | |
| 2795 | dr = find_pci_dr(pdev); |
| 2796 | if (dr && !dr->restore_intx) { |
| 2797 | dr->restore_intx = 1; |
| 2798 | dr->orig_intx = !enable; |
| 2799 | } |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 2800 | } |
| 2801 | } |
| 2802 | |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 2803 | /** |
Jan Kiszka | a2e2778 | 2011-11-04 09:46:00 +0100 | [diff] [blame] | 2804 | * pci_intx_mask_supported - probe for INTx masking support |
Randy Dunlap | 6e9292c | 2012-01-21 11:02:35 -0800 | [diff] [blame] | 2805 | * @dev: the PCI device to operate on |
Jan Kiszka | a2e2778 | 2011-11-04 09:46:00 +0100 | [diff] [blame] | 2806 | * |
| 2807 | * Check if the device dev support INTx masking via the config space |
| 2808 | * command word. |
| 2809 | */ |
| 2810 | bool pci_intx_mask_supported(struct pci_dev *dev) |
| 2811 | { |
| 2812 | bool mask_supported = false; |
| 2813 | u16 orig, new; |
| 2814 | |
| 2815 | pci_cfg_access_lock(dev); |
| 2816 | |
| 2817 | pci_read_config_word(dev, PCI_COMMAND, &orig); |
| 2818 | pci_write_config_word(dev, PCI_COMMAND, |
| 2819 | orig ^ PCI_COMMAND_INTX_DISABLE); |
| 2820 | pci_read_config_word(dev, PCI_COMMAND, &new); |
| 2821 | |
| 2822 | /* |
| 2823 | * There's no way to protect against hardware bugs or detect them |
| 2824 | * reliably, but as long as we know what the value should be, let's |
| 2825 | * go ahead and check it. |
| 2826 | */ |
| 2827 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { |
| 2828 | dev_err(&dev->dev, "Command register changed from " |
| 2829 | "0x%x to 0x%x: driver or hardware bug?\n", orig, new); |
| 2830 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { |
| 2831 | mask_supported = true; |
| 2832 | pci_write_config_word(dev, PCI_COMMAND, orig); |
| 2833 | } |
| 2834 | |
| 2835 | pci_cfg_access_unlock(dev); |
| 2836 | return mask_supported; |
| 2837 | } |
| 2838 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); |
| 2839 | |
| 2840 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) |
| 2841 | { |
| 2842 | struct pci_bus *bus = dev->bus; |
| 2843 | bool mask_updated = true; |
| 2844 | u32 cmd_status_dword; |
| 2845 | u16 origcmd, newcmd; |
| 2846 | unsigned long flags; |
| 2847 | bool irq_pending; |
| 2848 | |
| 2849 | /* |
| 2850 | * We do a single dword read to retrieve both command and status. |
| 2851 | * Document assumptions that make this possible. |
| 2852 | */ |
| 2853 | BUILD_BUG_ON(PCI_COMMAND % 4); |
| 2854 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); |
| 2855 | |
| 2856 | raw_spin_lock_irqsave(&pci_lock, flags); |
| 2857 | |
| 2858 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); |
| 2859 | |
| 2860 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; |
| 2861 | |
| 2862 | /* |
| 2863 | * Check interrupt status register to see whether our device |
| 2864 | * triggered the interrupt (when masking) or the next IRQ is |
| 2865 | * already pending (when unmasking). |
| 2866 | */ |
| 2867 | if (mask != irq_pending) { |
| 2868 | mask_updated = false; |
| 2869 | goto done; |
| 2870 | } |
| 2871 | |
| 2872 | origcmd = cmd_status_dword; |
| 2873 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; |
| 2874 | if (mask) |
| 2875 | newcmd |= PCI_COMMAND_INTX_DISABLE; |
| 2876 | if (newcmd != origcmd) |
| 2877 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); |
| 2878 | |
| 2879 | done: |
| 2880 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
| 2881 | |
| 2882 | return mask_updated; |
| 2883 | } |
| 2884 | |
| 2885 | /** |
| 2886 | * pci_check_and_mask_intx - mask INTx on pending interrupt |
Randy Dunlap | 6e9292c | 2012-01-21 11:02:35 -0800 | [diff] [blame] | 2887 | * @dev: the PCI device to operate on |
Jan Kiszka | a2e2778 | 2011-11-04 09:46:00 +0100 | [diff] [blame] | 2888 | * |
| 2889 | * Check if the device dev has its INTx line asserted, mask it and |
| 2890 | * return true in that case. False is returned if not interrupt was |
| 2891 | * pending. |
| 2892 | */ |
| 2893 | bool pci_check_and_mask_intx(struct pci_dev *dev) |
| 2894 | { |
| 2895 | return pci_check_and_set_intx_mask(dev, true); |
| 2896 | } |
| 2897 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); |
| 2898 | |
| 2899 | /** |
| 2900 | * pci_check_and_mask_intx - unmask INTx of no interrupt is pending |
Randy Dunlap | 6e9292c | 2012-01-21 11:02:35 -0800 | [diff] [blame] | 2901 | * @dev: the PCI device to operate on |
Jan Kiszka | a2e2778 | 2011-11-04 09:46:00 +0100 | [diff] [blame] | 2902 | * |
| 2903 | * Check if the device dev has its INTx line asserted, unmask it if not |
| 2904 | * and return true. False is returned and the mask remains active if |
| 2905 | * there was still an interrupt pending. |
| 2906 | */ |
| 2907 | bool pci_check_and_unmask_intx(struct pci_dev *dev) |
| 2908 | { |
| 2909 | return pci_check_and_set_intx_mask(dev, false); |
| 2910 | } |
| 2911 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); |
| 2912 | |
| 2913 | /** |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 2914 | * pci_msi_off - disables any msi or msix capabilities |
Randy Dunlap | 8d7d86e | 2007-03-16 19:55:52 -0700 | [diff] [blame] | 2915 | * @dev: the PCI device to operate on |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 2916 | * |
| 2917 | * If you want to use msi see pci_enable_msi and friends. |
| 2918 | * This is a lower level primitive that allows us to disable |
| 2919 | * msi operation at the device level. |
| 2920 | */ |
| 2921 | void pci_msi_off(struct pci_dev *dev) |
| 2922 | { |
| 2923 | int pos; |
| 2924 | u16 control; |
| 2925 | |
| 2926 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
| 2927 | if (pos) { |
| 2928 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
| 2929 | control &= ~PCI_MSI_FLAGS_ENABLE; |
| 2930 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
| 2931 | } |
| 2932 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
| 2933 | if (pos) { |
| 2934 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
| 2935 | control &= ~PCI_MSIX_FLAGS_ENABLE; |
| 2936 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
| 2937 | } |
| 2938 | } |
Michael S. Tsirkin | b03214d | 2010-06-23 22:49:06 -0600 | [diff] [blame] | 2939 | EXPORT_SYMBOL_GPL(pci_msi_off); |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 2940 | |
FUJITA Tomonori | 4d57cdf | 2008-02-04 22:27:55 -0800 | [diff] [blame] | 2941 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
| 2942 | { |
| 2943 | return dma_set_max_seg_size(&dev->dev, size); |
| 2944 | } |
| 2945 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); |
FUJITA Tomonori | 4d57cdf | 2008-02-04 22:27:55 -0800 | [diff] [blame] | 2946 | |
FUJITA Tomonori | 59fc67d | 2008-02-04 22:28:14 -0800 | [diff] [blame] | 2947 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
| 2948 | { |
| 2949 | return dma_set_seg_boundary(&dev->dev, mask); |
| 2950 | } |
| 2951 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); |
FUJITA Tomonori | 59fc67d | 2008-02-04 22:28:14 -0800 | [diff] [blame] | 2952 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2953 | static int pcie_flr(struct pci_dev *dev, int probe) |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2954 | { |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2955 | int i; |
| 2956 | int pos; |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2957 | u32 cap; |
Shmulik Ravid | 04b55c4 | 2009-12-03 22:27:51 +0200 | [diff] [blame] | 2958 | u16 status, control; |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2959 | |
Kenji Kaneshige | 06a1cba | 2009-11-11 14:30:56 +0900 | [diff] [blame] | 2960 | pos = pci_pcie_cap(dev); |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2961 | if (!pos) |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2962 | return -ENOTTY; |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2963 | |
| 2964 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2965 | if (!(cap & PCI_EXP_DEVCAP_FLR)) |
| 2966 | return -ENOTTY; |
| 2967 | |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 2968 | if (probe) |
| 2969 | return 0; |
| 2970 | |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2971 | /* Wait for Transaction Pending bit clean */ |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2972 | for (i = 0; i < 4; i++) { |
| 2973 | if (i) |
| 2974 | msleep((1 << (i - 1)) * 100); |
Sheng Yang | 5fe5db0 | 2009-02-09 14:53:47 +0800 | [diff] [blame] | 2975 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2976 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); |
| 2977 | if (!(status & PCI_EXP_DEVSTA_TRPND)) |
| 2978 | goto clear; |
| 2979 | } |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2980 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2981 | dev_err(&dev->dev, "transaction is not cleared; " |
| 2982 | "proceeding with reset anyway\n"); |
Sheng Yang | 5fe5db0 | 2009-02-09 14:53:47 +0800 | [diff] [blame] | 2983 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2984 | clear: |
Shmulik Ravid | 04b55c4 | 2009-12-03 22:27:51 +0200 | [diff] [blame] | 2985 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); |
| 2986 | control |= PCI_EXP_DEVCTL_BCR_FLR; |
| 2987 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control); |
| 2988 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2989 | msleep(100); |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2990 | |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 2991 | return 0; |
| 2992 | } |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 2993 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2994 | static int pci_af_flr(struct pci_dev *dev, int probe) |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 2995 | { |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2996 | int i; |
| 2997 | int pos; |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 2998 | u8 cap; |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 2999 | u8 status; |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 3000 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3001 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
| 3002 | if (!pos) |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 3003 | return -ENOTTY; |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3004 | |
| 3005 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 3006 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
| 3007 | return -ENOTTY; |
| 3008 | |
| 3009 | if (probe) |
| 3010 | return 0; |
| 3011 | |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 3012 | /* Wait for Transaction Pending bit clean */ |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3013 | for (i = 0; i < 4; i++) { |
| 3014 | if (i) |
| 3015 | msleep((1 << (i - 1)) * 100); |
Sheng Yang | 5fe5db0 | 2009-02-09 14:53:47 +0800 | [diff] [blame] | 3016 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3017 | pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); |
| 3018 | if (!(status & PCI_AF_STATUS_TP)) |
| 3019 | goto clear; |
| 3020 | } |
| 3021 | |
| 3022 | dev_err(&dev->dev, "transaction is not cleared; " |
| 3023 | "proceeding with reset anyway\n"); |
| 3024 | |
| 3025 | clear: |
| 3026 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 3027 | msleep(100); |
Sheng Yang | 5fe5db0 | 2009-02-09 14:53:47 +0800 | [diff] [blame] | 3028 | |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 3029 | return 0; |
| 3030 | } |
| 3031 | |
Rafael J. Wysocki | 83d74e0 | 2011-03-05 21:48:44 +0100 | [diff] [blame] | 3032 | /** |
| 3033 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. |
| 3034 | * @dev: Device to reset. |
| 3035 | * @probe: If set, only check if the device can be reset this way. |
| 3036 | * |
| 3037 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is |
| 3038 | * unset, it will be reinitialized internally when going from PCI_D3hot to |
| 3039 | * PCI_D0. If that's the case and the device is not in a low-power state |
| 3040 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. |
| 3041 | * |
| 3042 | * NOTE: This causes the caller to sleep for twice the device power transition |
| 3043 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms |
| 3044 | * by devault (i.e. unless the @dev's d3_delay field has a different value). |
| 3045 | * Moreover, only devices in D0 can be reset by this function. |
| 3046 | */ |
Yu Zhao | f85876b | 2009-06-13 15:52:14 +0800 | [diff] [blame] | 3047 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 3048 | { |
Yu Zhao | f85876b | 2009-06-13 15:52:14 +0800 | [diff] [blame] | 3049 | u16 csr; |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 3050 | |
Yu Zhao | f85876b | 2009-06-13 15:52:14 +0800 | [diff] [blame] | 3051 | if (!dev->pm_cap) |
| 3052 | return -ENOTTY; |
Sheng Yang | d91cdc7 | 2008-11-11 17:17:47 +0800 | [diff] [blame] | 3053 | |
Yu Zhao | f85876b | 2009-06-13 15:52:14 +0800 | [diff] [blame] | 3054 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
| 3055 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) |
| 3056 | return -ENOTTY; |
Sheng Yang | 1ca8879 | 2008-11-11 17:17:48 +0800 | [diff] [blame] | 3057 | |
Yu Zhao | f85876b | 2009-06-13 15:52:14 +0800 | [diff] [blame] | 3058 | if (probe) |
| 3059 | return 0; |
| 3060 | |
| 3061 | if (dev->current_state != PCI_D0) |
| 3062 | return -EINVAL; |
| 3063 | |
| 3064 | csr &= ~PCI_PM_CTRL_STATE_MASK; |
| 3065 | csr |= PCI_D3hot; |
| 3066 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); |
Rafael J. Wysocki | 1ae861e | 2009-12-31 12:15:54 +0100 | [diff] [blame] | 3067 | pci_dev_d3_sleep(dev); |
Yu Zhao | f85876b | 2009-06-13 15:52:14 +0800 | [diff] [blame] | 3068 | |
| 3069 | csr &= ~PCI_PM_CTRL_STATE_MASK; |
| 3070 | csr |= PCI_D0; |
| 3071 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); |
Rafael J. Wysocki | 1ae861e | 2009-12-31 12:15:54 +0100 | [diff] [blame] | 3072 | pci_dev_d3_sleep(dev); |
Yu Zhao | f85876b | 2009-06-13 15:52:14 +0800 | [diff] [blame] | 3073 | |
| 3074 | return 0; |
| 3075 | } |
| 3076 | |
Yu Zhao | c12ff1d | 2009-06-13 15:52:15 +0800 | [diff] [blame] | 3077 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) |
| 3078 | { |
| 3079 | u16 ctrl; |
| 3080 | struct pci_dev *pdev; |
| 3081 | |
Yu Zhao | 654b75e | 2009-06-26 14:04:46 +0800 | [diff] [blame] | 3082 | if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) |
Yu Zhao | c12ff1d | 2009-06-13 15:52:15 +0800 | [diff] [blame] | 3083 | return -ENOTTY; |
| 3084 | |
| 3085 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) |
| 3086 | if (pdev != dev) |
| 3087 | return -ENOTTY; |
| 3088 | |
| 3089 | if (probe) |
| 3090 | return 0; |
| 3091 | |
| 3092 | pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); |
| 3093 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; |
| 3094 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); |
| 3095 | msleep(100); |
| 3096 | |
| 3097 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
| 3098 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); |
| 3099 | msleep(100); |
| 3100 | |
| 3101 | return 0; |
| 3102 | } |
| 3103 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3104 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3105 | { |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3106 | int rc; |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3107 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3108 | might_sleep(); |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3109 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3110 | if (!probe) { |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 3111 | pci_cfg_access_lock(dev); |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3112 | /* block PM suspend, driver probe, etc. */ |
Greg Kroah-Hartman | 8e9394c | 2010-02-17 10:57:05 -0800 | [diff] [blame] | 3113 | device_lock(&dev->dev); |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3114 | } |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3115 | |
Dexuan Cui | b9c3b26 | 2009-12-07 13:03:21 +0800 | [diff] [blame] | 3116 | rc = pci_dev_specific_reset(dev, probe); |
| 3117 | if (rc != -ENOTTY) |
| 3118 | goto done; |
| 3119 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3120 | rc = pcie_flr(dev, probe); |
| 3121 | if (rc != -ENOTTY) |
| 3122 | goto done; |
| 3123 | |
| 3124 | rc = pci_af_flr(dev, probe); |
Yu Zhao | f85876b | 2009-06-13 15:52:14 +0800 | [diff] [blame] | 3125 | if (rc != -ENOTTY) |
| 3126 | goto done; |
| 3127 | |
| 3128 | rc = pci_pm_reset(dev, probe); |
Yu Zhao | c12ff1d | 2009-06-13 15:52:15 +0800 | [diff] [blame] | 3129 | if (rc != -ENOTTY) |
| 3130 | goto done; |
| 3131 | |
| 3132 | rc = pci_parent_bus_reset(dev, probe); |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3133 | done: |
| 3134 | if (!probe) { |
Greg Kroah-Hartman | 8e9394c | 2010-02-17 10:57:05 -0800 | [diff] [blame] | 3135 | device_unlock(&dev->dev); |
Jan Kiszka | fb51ccb | 2011-11-04 09:45:59 +0100 | [diff] [blame] | 3136 | pci_cfg_access_unlock(dev); |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3137 | } |
| 3138 | |
| 3139 | return rc; |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3140 | } |
| 3141 | |
| 3142 | /** |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3143 | * __pci_reset_function - reset a PCI device function |
| 3144 | * @dev: PCI device to reset |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3145 | * |
| 3146 | * Some devices allow an individual function to be reset without affecting |
| 3147 | * other functions in the same device. The PCI device must be responsive |
| 3148 | * to PCI config space in order to use this function. |
| 3149 | * |
| 3150 | * The device function is presumed to be unused when this function is called. |
| 3151 | * Resetting the device will make the contents of PCI configuration space |
| 3152 | * random, so any caller of this must be prepared to reinitialise the |
| 3153 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, |
| 3154 | * etc. |
| 3155 | * |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3156 | * Returns 0 if the device function was successfully reset or negative if the |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3157 | * device doesn't support resetting a single function. |
| 3158 | */ |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3159 | int __pci_reset_function(struct pci_dev *dev) |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3160 | { |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3161 | return pci_dev_reset(dev, 0); |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3162 | } |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3163 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3164 | |
| 3165 | /** |
Michael S. Tsirkin | 711d577 | 2009-07-27 23:37:48 +0300 | [diff] [blame] | 3166 | * pci_probe_reset_function - check whether the device can be safely reset |
| 3167 | * @dev: PCI device to reset |
| 3168 | * |
| 3169 | * Some devices allow an individual function to be reset without affecting |
| 3170 | * other functions in the same device. The PCI device must be responsive |
| 3171 | * to PCI config space in order to use this function. |
| 3172 | * |
| 3173 | * Returns 0 if the device function can be reset or negative if the |
| 3174 | * device doesn't support resetting a single function. |
| 3175 | */ |
| 3176 | int pci_probe_reset_function(struct pci_dev *dev) |
| 3177 | { |
| 3178 | return pci_dev_reset(dev, 1); |
| 3179 | } |
| 3180 | |
| 3181 | /** |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3182 | * pci_reset_function - quiesce and reset a PCI device function |
| 3183 | * @dev: PCI device to reset |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3184 | * |
| 3185 | * Some devices allow an individual function to be reset without affecting |
| 3186 | * other functions in the same device. The PCI device must be responsive |
| 3187 | * to PCI config space in order to use this function. |
| 3188 | * |
| 3189 | * This function does not just reset the PCI portion of a device, but |
| 3190 | * clears all the state associated with the device. This function differs |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3191 | * from __pci_reset_function in that it saves and restores device state |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3192 | * over the reset. |
| 3193 | * |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3194 | * Returns 0 if the device function was successfully reset or negative if the |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3195 | * device doesn't support resetting a single function. |
| 3196 | */ |
| 3197 | int pci_reset_function(struct pci_dev *dev) |
| 3198 | { |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3199 | int rc; |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3200 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3201 | rc = pci_dev_reset(dev, 1); |
| 3202 | if (rc) |
| 3203 | return rc; |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3204 | |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3205 | pci_save_state(dev); |
| 3206 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3207 | /* |
| 3208 | * both INTx and MSI are disabled after the Interrupt Disable bit |
| 3209 | * is set and the Bus Master bit is cleared. |
| 3210 | */ |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3211 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); |
| 3212 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3213 | rc = pci_dev_reset(dev, 0); |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3214 | |
| 3215 | pci_restore_state(dev); |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3216 | |
Yu Zhao | 8c1c699 | 2009-06-13 15:52:13 +0800 | [diff] [blame] | 3217 | return rc; |
Sheng Yang | 8dd7f80 | 2008-10-21 17:38:25 +0800 | [diff] [blame] | 3218 | } |
| 3219 | EXPORT_SYMBOL_GPL(pci_reset_function); |
| 3220 | |
| 3221 | /** |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3222 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count |
| 3223 | * @dev: PCI device to query |
| 3224 | * |
| 3225 | * Returns mmrbc: maximum designed memory read count in bytes |
| 3226 | * or appropriate error value. |
| 3227 | */ |
| 3228 | int pcix_get_max_mmrbc(struct pci_dev *dev) |
| 3229 | { |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3230 | int cap; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3231 | u32 stat; |
| 3232 | |
| 3233 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 3234 | if (!cap) |
| 3235 | return -EINVAL; |
| 3236 | |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3237 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3238 | return -EINVAL; |
| 3239 | |
Dean Nelson | 25daeb5 | 2010-03-09 22:26:40 -0500 | [diff] [blame] | 3240 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3241 | } |
| 3242 | EXPORT_SYMBOL(pcix_get_max_mmrbc); |
| 3243 | |
| 3244 | /** |
| 3245 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count |
| 3246 | * @dev: PCI device to query |
| 3247 | * |
| 3248 | * Returns mmrbc: maximum memory read count in bytes |
| 3249 | * or appropriate error value. |
| 3250 | */ |
| 3251 | int pcix_get_mmrbc(struct pci_dev *dev) |
| 3252 | { |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3253 | int cap; |
Dean Nelson | bdc2bda | 2010-03-09 22:26:48 -0500 | [diff] [blame] | 3254 | u16 cmd; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3255 | |
| 3256 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 3257 | if (!cap) |
| 3258 | return -EINVAL; |
| 3259 | |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3260 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
| 3261 | return -EINVAL; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3262 | |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3263 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3264 | } |
| 3265 | EXPORT_SYMBOL(pcix_get_mmrbc); |
| 3266 | |
| 3267 | /** |
| 3268 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count |
| 3269 | * @dev: PCI device to query |
| 3270 | * @mmrbc: maximum memory read count in bytes |
| 3271 | * valid values are 512, 1024, 2048, 4096 |
| 3272 | * |
| 3273 | * If possible sets maximum memory read byte count, some bridges have erratas |
| 3274 | * that prevent this. |
| 3275 | */ |
| 3276 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) |
| 3277 | { |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3278 | int cap; |
Dean Nelson | bdc2bda | 2010-03-09 22:26:48 -0500 | [diff] [blame] | 3279 | u32 stat, v, o; |
| 3280 | u16 cmd; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3281 | |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 3282 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3283 | return -EINVAL; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3284 | |
| 3285 | v = ffs(mmrbc) - 10; |
| 3286 | |
| 3287 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 3288 | if (!cap) |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3289 | return -EINVAL; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3290 | |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3291 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
| 3292 | return -EINVAL; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3293 | |
| 3294 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) |
| 3295 | return -E2BIG; |
| 3296 | |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3297 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
| 3298 | return -EINVAL; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3299 | |
| 3300 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; |
| 3301 | if (o != v) { |
| 3302 | if (v > o && dev->bus && |
| 3303 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
| 3304 | return -EIO; |
| 3305 | |
| 3306 | cmd &= ~PCI_X_CMD_MAX_READ; |
| 3307 | cmd |= v << 2; |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3308 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
| 3309 | return -EIO; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3310 | } |
Dean Nelson | 7c9e2b1 | 2010-03-09 22:26:55 -0500 | [diff] [blame] | 3311 | return 0; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3312 | } |
| 3313 | EXPORT_SYMBOL(pcix_set_mmrbc); |
| 3314 | |
| 3315 | /** |
| 3316 | * pcie_get_readrq - get PCI Express read request size |
| 3317 | * @dev: PCI device to query |
| 3318 | * |
| 3319 | * Returns maximum memory read request in bytes |
| 3320 | * or appropriate error value. |
| 3321 | */ |
| 3322 | int pcie_get_readrq(struct pci_dev *dev) |
| 3323 | { |
| 3324 | int ret, cap; |
| 3325 | u16 ctl; |
| 3326 | |
Kenji Kaneshige | 06a1cba | 2009-11-11 14:30:56 +0900 | [diff] [blame] | 3327 | cap = pci_pcie_cap(dev); |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3328 | if (!cap) |
| 3329 | return -EINVAL; |
| 3330 | |
| 3331 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); |
| 3332 | if (!ret) |
Julia Lawall | 93e75fa | 2010-08-05 22:23:16 +0200 | [diff] [blame] | 3333 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3334 | |
| 3335 | return ret; |
| 3336 | } |
| 3337 | EXPORT_SYMBOL(pcie_get_readrq); |
| 3338 | |
| 3339 | /** |
| 3340 | * pcie_set_readrq - set PCI Express maximum memory read request |
| 3341 | * @dev: PCI device to query |
Randy Dunlap | 42e61f4 | 2007-07-23 21:42:11 -0700 | [diff] [blame] | 3342 | * @rq: maximum memory read count in bytes |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3343 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
| 3344 | * |
Jon Mason | c9b378c | 2011-06-28 18:26:25 -0500 | [diff] [blame] | 3345 | * If possible sets maximum memory read request in bytes |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3346 | */ |
| 3347 | int pcie_set_readrq(struct pci_dev *dev, int rq) |
| 3348 | { |
| 3349 | int cap, err = -EINVAL; |
| 3350 | u16 ctl, v; |
| 3351 | |
vignesh babu | 229f5af | 2007-08-13 18:23:14 +0530 | [diff] [blame] | 3352 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3353 | goto out; |
| 3354 | |
Kenji Kaneshige | 06a1cba | 2009-11-11 14:30:56 +0900 | [diff] [blame] | 3355 | cap = pci_pcie_cap(dev); |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3356 | if (!cap) |
| 3357 | goto out; |
| 3358 | |
| 3359 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); |
| 3360 | if (err) |
| 3361 | goto out; |
Benjamin Herrenschmidt | a1c473a | 2011-10-14 14:56:15 -0500 | [diff] [blame] | 3362 | /* |
| 3363 | * If using the "performance" PCIe config, we clamp the |
| 3364 | * read rq size to the max packet size to prevent the |
| 3365 | * host bridge generating requests larger than we can |
| 3366 | * cope with |
| 3367 | */ |
| 3368 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { |
| 3369 | int mps = pcie_get_mps(dev); |
| 3370 | |
| 3371 | if (mps < 0) |
| 3372 | return mps; |
| 3373 | if (mps < rq) |
| 3374 | rq = mps; |
| 3375 | } |
| 3376 | |
| 3377 | v = (ffs(rq) - 8) << 12; |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3378 | |
| 3379 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { |
| 3380 | ctl &= ~PCI_EXP_DEVCTL_READRQ; |
| 3381 | ctl |= v; |
Jon Mason | c9b378c | 2011-06-28 18:26:25 -0500 | [diff] [blame] | 3382 | err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl); |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 3383 | } |
| 3384 | |
| 3385 | out: |
| 3386 | return err; |
| 3387 | } |
| 3388 | EXPORT_SYMBOL(pcie_set_readrq); |
| 3389 | |
| 3390 | /** |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 3391 | * pcie_get_mps - get PCI Express maximum payload size |
| 3392 | * @dev: PCI device to query |
| 3393 | * |
| 3394 | * Returns maximum payload size in bytes |
| 3395 | * or appropriate error value. |
| 3396 | */ |
| 3397 | int pcie_get_mps(struct pci_dev *dev) |
| 3398 | { |
| 3399 | int ret, cap; |
| 3400 | u16 ctl; |
| 3401 | |
| 3402 | cap = pci_pcie_cap(dev); |
| 3403 | if (!cap) |
| 3404 | return -EINVAL; |
| 3405 | |
| 3406 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); |
| 3407 | if (!ret) |
| 3408 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
| 3409 | |
| 3410 | return ret; |
| 3411 | } |
| 3412 | |
| 3413 | /** |
| 3414 | * pcie_set_mps - set PCI Express maximum payload size |
| 3415 | * @dev: PCI device to query |
Randy Dunlap | 47c08f3 | 2011-08-20 11:49:43 -0700 | [diff] [blame] | 3416 | * @mps: maximum payload size in bytes |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 3417 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
| 3418 | * |
| 3419 | * If possible sets maximum payload size |
| 3420 | */ |
| 3421 | int pcie_set_mps(struct pci_dev *dev, int mps) |
| 3422 | { |
| 3423 | int cap, err = -EINVAL; |
| 3424 | u16 ctl, v; |
| 3425 | |
| 3426 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) |
| 3427 | goto out; |
| 3428 | |
| 3429 | v = ffs(mps) - 8; |
| 3430 | if (v > dev->pcie_mpss) |
| 3431 | goto out; |
| 3432 | v <<= 5; |
| 3433 | |
| 3434 | cap = pci_pcie_cap(dev); |
| 3435 | if (!cap) |
| 3436 | goto out; |
| 3437 | |
| 3438 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); |
| 3439 | if (err) |
| 3440 | goto out; |
| 3441 | |
| 3442 | if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) { |
| 3443 | ctl &= ~PCI_EXP_DEVCTL_PAYLOAD; |
| 3444 | ctl |= v; |
| 3445 | err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl); |
| 3446 | } |
| 3447 | out: |
| 3448 | return err; |
| 3449 | } |
| 3450 | |
| 3451 | /** |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 3452 | * pci_select_bars - Make BAR mask from the type of resource |
Randy Dunlap | f95d882 | 2007-02-10 14:41:56 -0800 | [diff] [blame] | 3453 | * @dev: the PCI device for which BAR mask is made |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 3454 | * @flags: resource type mask to be selected |
| 3455 | * |
| 3456 | * This helper routine makes bar mask from the type of resource. |
| 3457 | */ |
| 3458 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) |
| 3459 | { |
| 3460 | int i, bars = 0; |
| 3461 | for (i = 0; i < PCI_NUM_RESOURCES; i++) |
| 3462 | if (pci_resource_flags(dev, i) & flags) |
| 3463 | bars |= (1 << i); |
| 3464 | return bars; |
| 3465 | } |
| 3466 | |
Yu Zhao | 613e7ed | 2008-11-22 02:41:27 +0800 | [diff] [blame] | 3467 | /** |
| 3468 | * pci_resource_bar - get position of the BAR associated with a resource |
| 3469 | * @dev: the PCI device |
| 3470 | * @resno: the resource number |
| 3471 | * @type: the BAR type to be filled in |
| 3472 | * |
| 3473 | * Returns BAR position in config space, or 0 if the BAR is invalid. |
| 3474 | */ |
| 3475 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) |
| 3476 | { |
Yu Zhao | d1b054d | 2009-03-20 11:25:11 +0800 | [diff] [blame] | 3477 | int reg; |
| 3478 | |
Yu Zhao | 613e7ed | 2008-11-22 02:41:27 +0800 | [diff] [blame] | 3479 | if (resno < PCI_ROM_RESOURCE) { |
| 3480 | *type = pci_bar_unknown; |
| 3481 | return PCI_BASE_ADDRESS_0 + 4 * resno; |
| 3482 | } else if (resno == PCI_ROM_RESOURCE) { |
| 3483 | *type = pci_bar_mem32; |
| 3484 | return dev->rom_base_reg; |
Yu Zhao | d1b054d | 2009-03-20 11:25:11 +0800 | [diff] [blame] | 3485 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
| 3486 | /* device specific resource */ |
| 3487 | reg = pci_iov_resource_bar(dev, resno, type); |
| 3488 | if (reg) |
| 3489 | return reg; |
Yu Zhao | 613e7ed | 2008-11-22 02:41:27 +0800 | [diff] [blame] | 3490 | } |
| 3491 | |
Bjorn Helgaas | 865df57 | 2009-11-04 10:32:57 -0700 | [diff] [blame] | 3492 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
Yu Zhao | 613e7ed | 2008-11-22 02:41:27 +0800 | [diff] [blame] | 3493 | return 0; |
| 3494 | } |
| 3495 | |
Mike Travis | 95a8b6e | 2010-02-02 14:38:13 -0800 | [diff] [blame] | 3496 | /* Some architectures require additional programming to enable VGA */ |
| 3497 | static arch_set_vga_state_t arch_set_vga_state; |
| 3498 | |
| 3499 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) |
| 3500 | { |
| 3501 | arch_set_vga_state = func; /* NULL disables */ |
| 3502 | } |
| 3503 | |
| 3504 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, |
Dave Airlie | 7ad35cf | 2011-05-25 14:00:49 +1000 | [diff] [blame] | 3505 | unsigned int command_bits, u32 flags) |
Mike Travis | 95a8b6e | 2010-02-02 14:38:13 -0800 | [diff] [blame] | 3506 | { |
| 3507 | if (arch_set_vga_state) |
| 3508 | return arch_set_vga_state(dev, decode, command_bits, |
Dave Airlie | 7ad35cf | 2011-05-25 14:00:49 +1000 | [diff] [blame] | 3509 | flags); |
Mike Travis | 95a8b6e | 2010-02-02 14:38:13 -0800 | [diff] [blame] | 3510 | return 0; |
| 3511 | } |
| 3512 | |
Benjamin Herrenschmidt | deb2d2e | 2009-08-11 15:52:06 +1000 | [diff] [blame] | 3513 | /** |
| 3514 | * pci_set_vga_state - set VGA decode state on device and parents if requested |
Randy Dunlap | 19eea63 | 2009-09-17 15:28:22 -0700 | [diff] [blame] | 3515 | * @dev: the PCI device |
| 3516 | * @decode: true = enable decoding, false = disable decoding |
| 3517 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY |
Randy Dunlap | 3f37d62 | 2011-05-25 19:21:25 -0700 | [diff] [blame] | 3518 | * @flags: traverse ancestors and change bridges |
Dave Airlie | 3448a19 | 2010-06-01 15:32:24 +1000 | [diff] [blame] | 3519 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
Benjamin Herrenschmidt | deb2d2e | 2009-08-11 15:52:06 +1000 | [diff] [blame] | 3520 | */ |
| 3521 | int pci_set_vga_state(struct pci_dev *dev, bool decode, |
Dave Airlie | 3448a19 | 2010-06-01 15:32:24 +1000 | [diff] [blame] | 3522 | unsigned int command_bits, u32 flags) |
Benjamin Herrenschmidt | deb2d2e | 2009-08-11 15:52:06 +1000 | [diff] [blame] | 3523 | { |
| 3524 | struct pci_bus *bus; |
| 3525 | struct pci_dev *bridge; |
| 3526 | u16 cmd; |
Mike Travis | 95a8b6e | 2010-02-02 14:38:13 -0800 | [diff] [blame] | 3527 | int rc; |
Benjamin Herrenschmidt | deb2d2e | 2009-08-11 15:52:06 +1000 | [diff] [blame] | 3528 | |
Dave Airlie | 3448a19 | 2010-06-01 15:32:24 +1000 | [diff] [blame] | 3529 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
Benjamin Herrenschmidt | deb2d2e | 2009-08-11 15:52:06 +1000 | [diff] [blame] | 3530 | |
Mike Travis | 95a8b6e | 2010-02-02 14:38:13 -0800 | [diff] [blame] | 3531 | /* ARCH specific VGA enables */ |
Dave Airlie | 3448a19 | 2010-06-01 15:32:24 +1000 | [diff] [blame] | 3532 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
Mike Travis | 95a8b6e | 2010-02-02 14:38:13 -0800 | [diff] [blame] | 3533 | if (rc) |
| 3534 | return rc; |
| 3535 | |
Dave Airlie | 3448a19 | 2010-06-01 15:32:24 +1000 | [diff] [blame] | 3536 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
| 3537 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 3538 | if (decode == true) |
| 3539 | cmd |= command_bits; |
| 3540 | else |
| 3541 | cmd &= ~command_bits; |
| 3542 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 3543 | } |
Benjamin Herrenschmidt | deb2d2e | 2009-08-11 15:52:06 +1000 | [diff] [blame] | 3544 | |
Dave Airlie | 3448a19 | 2010-06-01 15:32:24 +1000 | [diff] [blame] | 3545 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
Benjamin Herrenschmidt | deb2d2e | 2009-08-11 15:52:06 +1000 | [diff] [blame] | 3546 | return 0; |
| 3547 | |
| 3548 | bus = dev->bus; |
| 3549 | while (bus) { |
| 3550 | bridge = bus->self; |
| 3551 | if (bridge) { |
| 3552 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, |
| 3553 | &cmd); |
| 3554 | if (decode == true) |
| 3555 | cmd |= PCI_BRIDGE_CTL_VGA; |
| 3556 | else |
| 3557 | cmd &= ~PCI_BRIDGE_CTL_VGA; |
| 3558 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, |
| 3559 | cmd); |
| 3560 | } |
| 3561 | bus = bus->parent; |
| 3562 | } |
| 3563 | return 0; |
| 3564 | } |
| 3565 | |
Yuji Shimada | 32a9a682 | 2009-03-16 17:13:39 +0900 | [diff] [blame] | 3566 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
| 3567 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; |
Thomas Gleixner | e9d1e49 | 2009-11-06 22:41:23 +0000 | [diff] [blame] | 3568 | static DEFINE_SPINLOCK(resource_alignment_lock); |
Yuji Shimada | 32a9a682 | 2009-03-16 17:13:39 +0900 | [diff] [blame] | 3569 | |
| 3570 | /** |
| 3571 | * pci_specified_resource_alignment - get resource alignment specified by user. |
| 3572 | * @dev: the PCI device to get |
| 3573 | * |
| 3574 | * RETURNS: Resource alignment if it is specified. |
| 3575 | * Zero if it is not specified. |
| 3576 | */ |
| 3577 | resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) |
| 3578 | { |
| 3579 | int seg, bus, slot, func, align_order, count; |
| 3580 | resource_size_t align = 0; |
| 3581 | char *p; |
| 3582 | |
| 3583 | spin_lock(&resource_alignment_lock); |
| 3584 | p = resource_alignment_param; |
| 3585 | while (*p) { |
| 3586 | count = 0; |
| 3587 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && |
| 3588 | p[count] == '@') { |
| 3589 | p += count + 1; |
| 3590 | } else { |
| 3591 | align_order = -1; |
| 3592 | } |
| 3593 | if (sscanf(p, "%x:%x:%x.%x%n", |
| 3594 | &seg, &bus, &slot, &func, &count) != 4) { |
| 3595 | seg = 0; |
| 3596 | if (sscanf(p, "%x:%x.%x%n", |
| 3597 | &bus, &slot, &func, &count) != 3) { |
| 3598 | /* Invalid format */ |
| 3599 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", |
| 3600 | p); |
| 3601 | break; |
| 3602 | } |
| 3603 | } |
| 3604 | p += count; |
| 3605 | if (seg == pci_domain_nr(dev->bus) && |
| 3606 | bus == dev->bus->number && |
| 3607 | slot == PCI_SLOT(dev->devfn) && |
| 3608 | func == PCI_FUNC(dev->devfn)) { |
| 3609 | if (align_order == -1) { |
| 3610 | align = PAGE_SIZE; |
| 3611 | } else { |
| 3612 | align = 1 << align_order; |
| 3613 | } |
| 3614 | /* Found */ |
| 3615 | break; |
| 3616 | } |
| 3617 | if (*p != ';' && *p != ',') { |
| 3618 | /* End of param or invalid format */ |
| 3619 | break; |
| 3620 | } |
| 3621 | p++; |
| 3622 | } |
| 3623 | spin_unlock(&resource_alignment_lock); |
| 3624 | return align; |
| 3625 | } |
| 3626 | |
| 3627 | /** |
| 3628 | * pci_is_reassigndev - check if specified PCI is target device to reassign |
| 3629 | * @dev: the PCI device to check |
| 3630 | * |
| 3631 | * RETURNS: non-zero for PCI device is a target device to reassign, |
| 3632 | * or zero is not. |
| 3633 | */ |
| 3634 | int pci_is_reassigndev(struct pci_dev *dev) |
| 3635 | { |
| 3636 | return (pci_specified_resource_alignment(dev) != 0); |
| 3637 | } |
| 3638 | |
| 3639 | ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
| 3640 | { |
| 3641 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) |
| 3642 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; |
| 3643 | spin_lock(&resource_alignment_lock); |
| 3644 | strncpy(resource_alignment_param, buf, count); |
| 3645 | resource_alignment_param[count] = '\0'; |
| 3646 | spin_unlock(&resource_alignment_lock); |
| 3647 | return count; |
| 3648 | } |
| 3649 | |
| 3650 | ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
| 3651 | { |
| 3652 | size_t count; |
| 3653 | spin_lock(&resource_alignment_lock); |
| 3654 | count = snprintf(buf, size, "%s", resource_alignment_param); |
| 3655 | spin_unlock(&resource_alignment_lock); |
| 3656 | return count; |
| 3657 | } |
| 3658 | |
| 3659 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) |
| 3660 | { |
| 3661 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); |
| 3662 | } |
| 3663 | |
| 3664 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, |
| 3665 | const char *buf, size_t count) |
| 3666 | { |
| 3667 | return pci_set_resource_alignment_param(buf, count); |
| 3668 | } |
| 3669 | |
| 3670 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, |
| 3671 | pci_resource_alignment_store); |
| 3672 | |
| 3673 | static int __init pci_resource_alignment_sysfs_init(void) |
| 3674 | { |
| 3675 | return bus_create_file(&pci_bus_type, |
| 3676 | &bus_attr_resource_alignment); |
| 3677 | } |
| 3678 | |
| 3679 | late_initcall(pci_resource_alignment_sysfs_init); |
| 3680 | |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 3681 | static void __devinit pci_no_domains(void) |
| 3682 | { |
| 3683 | #ifdef CONFIG_PCI_DOMAINS |
| 3684 | pci_domains_supported = 0; |
| 3685 | #endif |
| 3686 | } |
| 3687 | |
Andrew Patterson | 0ef5f8f | 2008-11-10 15:30:50 -0700 | [diff] [blame] | 3688 | /** |
| 3689 | * pci_ext_cfg_enabled - can we access extended PCI config space? |
| 3690 | * @dev: The PCI device of the root bridge. |
| 3691 | * |
| 3692 | * Returns 1 if we can access PCI extended config space (offsets |
| 3693 | * greater than 0xff). This is the default implementation. Architecture |
| 3694 | * implementations can override this. |
| 3695 | */ |
| 3696 | int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) |
| 3697 | { |
| 3698 | return 1; |
| 3699 | } |
| 3700 | |
Benjamin Herrenschmidt | 2d1c861 | 2009-12-09 17:52:13 +1100 | [diff] [blame] | 3701 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
| 3702 | { |
| 3703 | } |
| 3704 | EXPORT_SYMBOL(pci_fixup_cardbus); |
| 3705 | |
Al Viro | ad04d31 | 2008-11-22 17:37:14 +0000 | [diff] [blame] | 3706 | static int __init pci_setup(char *str) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3707 | { |
| 3708 | while (str) { |
| 3709 | char *k = strchr(str, ','); |
| 3710 | if (k) |
| 3711 | *k++ = 0; |
| 3712 | if (*str && (str = pcibios_setup(str)) && *str) { |
Matthew Wilcox | 309e57d | 2006-03-05 22:33:34 -0700 | [diff] [blame] | 3713 | if (!strcmp(str, "nomsi")) { |
| 3714 | pci_no_msi(); |
Randy Dunlap | 7f78576 | 2007-10-05 13:17:58 -0700 | [diff] [blame] | 3715 | } else if (!strcmp(str, "noaer")) { |
| 3716 | pci_no_aer(); |
Ram Pai | f483d39 | 2011-07-07 11:19:10 -0700 | [diff] [blame] | 3717 | } else if (!strncmp(str, "realloc", 7)) { |
| 3718 | pci_realloc(); |
Jeff Garzik | 32a2eea | 2007-10-11 16:57:27 -0400 | [diff] [blame] | 3719 | } else if (!strcmp(str, "nodomains")) { |
| 3720 | pci_no_domains(); |
Atsushi Nemoto | 4516a61 | 2007-02-05 16:36:06 -0800 | [diff] [blame] | 3721 | } else if (!strncmp(str, "cbiosize=", 9)) { |
| 3722 | pci_cardbus_io_size = memparse(str + 9, &str); |
| 3723 | } else if (!strncmp(str, "cbmemsize=", 10)) { |
| 3724 | pci_cardbus_mem_size = memparse(str + 10, &str); |
Yuji Shimada | 32a9a682 | 2009-03-16 17:13:39 +0900 | [diff] [blame] | 3725 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
| 3726 | pci_set_resource_alignment_param(str + 19, |
| 3727 | strlen(str + 19)); |
Andrew Patterson | 43c1640 | 2009-04-22 16:52:09 -0600 | [diff] [blame] | 3728 | } else if (!strncmp(str, "ecrc=", 5)) { |
| 3729 | pcie_ecrc_get_policy(str + 5); |
Eric W. Biederman | 2876048 | 2009-09-09 14:09:24 -0700 | [diff] [blame] | 3730 | } else if (!strncmp(str, "hpiosize=", 9)) { |
| 3731 | pci_hotplug_io_size = memparse(str + 9, &str); |
| 3732 | } else if (!strncmp(str, "hpmemsize=", 10)) { |
| 3733 | pci_hotplug_mem_size = memparse(str + 10, &str); |
Jon Mason | 5f39e67 | 2011-10-03 09:50:20 -0500 | [diff] [blame] | 3734 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
| 3735 | pcie_bus_config = PCIE_BUS_TUNE_OFF; |
Jon Mason | b03e749 | 2011-07-20 15:20:54 -0500 | [diff] [blame] | 3736 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
| 3737 | pcie_bus_config = PCIE_BUS_SAFE; |
| 3738 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { |
| 3739 | pcie_bus_config = PCIE_BUS_PERFORMANCE; |
Jon Mason | 5f39e67 | 2011-10-03 09:50:20 -0500 | [diff] [blame] | 3740 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
| 3741 | pcie_bus_config = PCIE_BUS_PEER2PEER; |
Matthew Wilcox | 309e57d | 2006-03-05 22:33:34 -0700 | [diff] [blame] | 3742 | } else { |
| 3743 | printk(KERN_ERR "PCI: Unknown option `%s'\n", |
| 3744 | str); |
| 3745 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3746 | } |
| 3747 | str = k; |
| 3748 | } |
Andi Kleen | 0637a70 | 2006-09-26 10:52:41 +0200 | [diff] [blame] | 3749 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3750 | } |
Andi Kleen | 0637a70 | 2006-09-26 10:52:41 +0200 | [diff] [blame] | 3751 | early_param("pci", pci_setup); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3752 | |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 3753 | EXPORT_SYMBOL(pci_reenable_device); |
Benjamin Herrenschmidt | b718989 | 2007-12-20 15:28:08 +1100 | [diff] [blame] | 3754 | EXPORT_SYMBOL(pci_enable_device_io); |
| 3755 | EXPORT_SYMBOL(pci_enable_device_mem); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3756 | EXPORT_SYMBOL(pci_enable_device); |
Tejun Heo | 9ac7849 | 2007-01-20 16:00:26 +0900 | [diff] [blame] | 3757 | EXPORT_SYMBOL(pcim_enable_device); |
| 3758 | EXPORT_SYMBOL(pcim_pin_device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3759 | EXPORT_SYMBOL(pci_disable_device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3760 | EXPORT_SYMBOL(pci_find_capability); |
| 3761 | EXPORT_SYMBOL(pci_bus_find_capability); |
| 3762 | EXPORT_SYMBOL(pci_release_regions); |
| 3763 | EXPORT_SYMBOL(pci_request_regions); |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 3764 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3765 | EXPORT_SYMBOL(pci_release_region); |
| 3766 | EXPORT_SYMBOL(pci_request_region); |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 3767 | EXPORT_SYMBOL(pci_request_region_exclusive); |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 3768 | EXPORT_SYMBOL(pci_release_selected_regions); |
| 3769 | EXPORT_SYMBOL(pci_request_selected_regions); |
Arjan van de Ven | e8de148 | 2008-10-22 19:55:31 -0700 | [diff] [blame] | 3770 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3771 | EXPORT_SYMBOL(pci_set_master); |
Ben Hutchings | 6a47907 | 2008-12-23 03:08:29 +0000 | [diff] [blame] | 3772 | EXPORT_SYMBOL(pci_clear_master); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3773 | EXPORT_SYMBOL(pci_set_mwi); |
Randy Dunlap | 694625c | 2007-07-09 11:55:54 -0700 | [diff] [blame] | 3774 | EXPORT_SYMBOL(pci_try_set_mwi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3775 | EXPORT_SYMBOL(pci_clear_mwi); |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 3776 | EXPORT_SYMBOL_GPL(pci_intx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3777 | EXPORT_SYMBOL(pci_assign_resource); |
| 3778 | EXPORT_SYMBOL(pci_find_parent_resource); |
Hidetoshi Seto | c87deff | 2006-12-18 10:31:06 +0900 | [diff] [blame] | 3779 | EXPORT_SYMBOL(pci_select_bars); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3780 | |
| 3781 | EXPORT_SYMBOL(pci_set_power_state); |
| 3782 | EXPORT_SYMBOL(pci_save_state); |
| 3783 | EXPORT_SYMBOL(pci_restore_state); |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 3784 | EXPORT_SYMBOL(pci_pme_capable); |
Rafael J. Wysocki | 5a6c9b6 | 2008-08-08 00:14:24 +0200 | [diff] [blame] | 3785 | EXPORT_SYMBOL(pci_pme_active); |
Rafael J. Wysocki | 0235c4f | 2008-08-18 21:38:00 +0200 | [diff] [blame] | 3786 | EXPORT_SYMBOL(pci_wake_from_d3); |
Rafael J. Wysocki | e5899e1 | 2008-07-19 14:39:24 +0200 | [diff] [blame] | 3787 | EXPORT_SYMBOL(pci_target_state); |
Rafael J. Wysocki | 404cc2d | 2008-07-07 03:35:26 +0200 | [diff] [blame] | 3788 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
| 3789 | EXPORT_SYMBOL(pci_back_from_sleep); |
Brian King | f7bdd12 | 2007-04-06 16:39:36 -0500 | [diff] [blame] | 3790 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |