Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / e2d54fe76997301b49311bde7ba8ef52b47896f9 / . / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
blob: b3abb8d8b2f6add6af321ecadc1a7ed9ca158cca [file] [log] [blame]
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
Andreas Fenkart55143432014-11-08 15:33:09 +0100[diff] [blame]22#include <linux/platform_data/hsmmc-omap.h>
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_7xx.h"
34#include "cm2_7xx.h"
35#include "prm7xx.h"
36#include "i2c.h"
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]37#include "wd_timer.h"
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]38#include "soc.h"
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]39
40/* Base offset for all DRA7XX interrupts external to MPUSS */
41#define DRA7XX_IRQ_GIC_START 32
42
43/* Base offset for all DRA7XX dma requests */
44#define DRA7XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
51/*
Tomi Valkeinen42121682014-09-15 13:12:18 -0500[diff] [blame]52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
72/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */
76static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
117 },
118 },
119};
120
121/*
122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */
125static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4",
127};
128
129/* l4_cfg */
130static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 },
139 },
140};
141
142/* l4_per1 */
143static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_per2 */
156static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 },
165 },
166};
167
168/* l4_per3 */
169static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'atl' class
196 *
197 */
198
199static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl",
201};
202
203/* atl */
204static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216};
217
218/*
219 * 'bb2d' class
220 *
221 */
222
223static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d",
225};
226
227/* bb2d */
228static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
238 },
239 },
240};
241
242/*
243 * 'counter' class
244 *
245 */
246
247static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1,
254};
255
256static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc,
259};
260
261/* counter_32k */
262static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 },
273 },
274};
275
276/*
277 * 'ctrl_module' class
278 *
279 */
280
281static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
283};
284
285/* ctrl_module_wkup */
286static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = {
291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 },
294 },
295};
296
297/*
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]298 * 'gmac' class
299 * cpsw/gmac sub system
300 */
301static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0,
303 .sysc_offs = 0x8,
304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3,
310};
311
312static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc,
315};
316
317static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1,
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331};
332
333/*
334 * 'mdio' class
335 */
336static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
338};
339
340static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
345};
346
347/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]348 * 'dcan' class
349 *
350 */
351
352static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan",
354};
355
356/* dcan1 */
357static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
Roger Quadrosa2416232017-03-13 13:53:15 +0200[diff] [blame]362 .flags = HWMOD_CLKDM_NOAUTO,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]363 .prcm = {
364 .omap4 = {
365 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
366 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
367 .modulemode = MODULEMODE_SWCTRL,
368 },
369 },
370};
371
372/* dcan2 */
373static struct omap_hwmod dra7xx_dcan2_hwmod = {
374 .name = "dcan2",
375 .class = &dra7xx_dcan_hwmod_class,
376 .clkdm_name = "l4per2_clkdm",
377 .main_clk = "sys_clkin1",
Roger Quadrosa2416232017-03-13 13:53:15 +0200[diff] [blame]378 .flags = HWMOD_CLKDM_NOAUTO,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]379 .prcm = {
380 .omap4 = {
381 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
382 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
383 .modulemode = MODULEMODE_SWCTRL,
384 },
385 },
386};
387
Vignesh Rb05ff3c2016-04-10 13:20:09 -0600[diff] [blame]388/* pwmss */
389static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
390 .rev_offs = 0x0,
391 .sysc_offs = 0x4,
392 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
393 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
394 .sysc_fields = &omap_hwmod_sysc_type2,
395};
396
397/*
398 * epwmss class
399 */
400static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
401 .name = "epwmss",
402 .sysc = &dra7xx_epwmss_sysc,
403};
404
405/* epwmss0 */
406static struct omap_hwmod dra7xx_epwmss0_hwmod = {
407 .name = "epwmss0",
408 .class = &dra7xx_epwmss_hwmod_class,
409 .clkdm_name = "l4per2_clkdm",
410 .main_clk = "l4_root_clk_div",
411 .prcm = {
412 .omap4 = {
413 .modulemode = MODULEMODE_SWCTRL,
414 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
415 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
416 },
417 },
418};
419
420/* epwmss1 */
421static struct omap_hwmod dra7xx_epwmss1_hwmod = {
422 .name = "epwmss1",
423 .class = &dra7xx_epwmss_hwmod_class,
424 .clkdm_name = "l4per2_clkdm",
425 .main_clk = "l4_root_clk_div",
426 .prcm = {
427 .omap4 = {
428 .modulemode = MODULEMODE_SWCTRL,
429 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
430 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
431 },
432 },
433};
434
435/* epwmss2 */
436static struct omap_hwmod dra7xx_epwmss2_hwmod = {
437 .name = "epwmss2",
438 .class = &dra7xx_epwmss_hwmod_class,
439 .clkdm_name = "l4per2_clkdm",
440 .main_clk = "l4_root_clk_div",
441 .prcm = {
442 .omap4 = {
443 .modulemode = MODULEMODE_SWCTRL,
444 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
445 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
446 },
447 },
448};
449
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]450/*
451 * 'dma' class
452 *
453 */
454
455static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
456 .rev_offs = 0x0000,
457 .sysc_offs = 0x002c,
458 .syss_offs = 0x0028,
459 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
460 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
461 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
462 SYSS_HAS_RESET_STATUS),
463 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
464 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
465 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
466 .sysc_fields = &omap_hwmod_sysc_type1,
467};
468
469static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
470 .name = "dma",
471 .sysc = &dra7xx_dma_sysc,
472};
473
474/* dma dev_attr */
475static struct omap_dma_dev_attr dma_dev_attr = {
476 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
477 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
478 .lch_count = 32,
479};
480
481/* dma_system */
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]482static struct omap_hwmod dra7xx_dma_system_hwmod = {
483 .name = "dma_system",
484 .class = &dra7xx_dma_hwmod_class,
485 .clkdm_name = "dma_clkdm",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]486 .main_clk = "l3_iclk_div",
487 .prcm = {
488 .omap4 = {
489 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
490 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
491 },
492 },
493 .dev_attr = &dma_dev_attr,
494};
495
496/*
Peter Ujfalusi34b41822016-02-25 16:50:18 +0200[diff] [blame]497 * 'tpcc' class
498 *
499 */
500static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
501 .name = "tpcc",
502};
503
504static struct omap_hwmod dra7xx_tpcc_hwmod = {
505 .name = "tpcc",
506 .class = &dra7xx_tpcc_hwmod_class,
507 .clkdm_name = "l3main1_clkdm",
508 .main_clk = "l3_iclk_div",
509 .prcm = {
510 .omap4 = {
511 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
512 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
513 },
514 },
515};
516
517/*
518 * 'tptc' class
519 *
520 */
521static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
522 .name = "tptc",
523};
524
525/* tptc0 */
526static struct omap_hwmod dra7xx_tptc0_hwmod = {
527 .name = "tptc0",
528 .class = &dra7xx_tptc_hwmod_class,
529 .clkdm_name = "l3main1_clkdm",
530 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
531 .main_clk = "l3_iclk_div",
532 .prcm = {
533 .omap4 = {
534 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
535 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
536 .modulemode = MODULEMODE_HWCTRL,
537 },
538 },
539};
540
541/* tptc1 */
542static struct omap_hwmod dra7xx_tptc1_hwmod = {
543 .name = "tptc1",
544 .class = &dra7xx_tptc_hwmod_class,
545 .clkdm_name = "l3main1_clkdm",
546 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
547 .main_clk = "l3_iclk_div",
548 .prcm = {
549 .omap4 = {
550 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
551 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
552 .modulemode = MODULEMODE_HWCTRL,
553 },
554 },
555};
556
557/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]558 * 'dss' class
559 *
560 */
561
562static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
563 .rev_offs = 0x0000,
564 .syss_offs = 0x0014,
565 .sysc_flags = SYSS_HAS_RESET_STATUS,
566};
567
568static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
569 .name = "dss",
570 .sysc = &dra7xx_dss_sysc,
571 .reset = omap_dss_reset,
572};
573
574/* dss */
575static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
576 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
577 { .dma_req = -1 }
578};
579
580static struct omap_hwmod_opt_clk dss_opt_clks[] = {
581 { .role = "dss_clk", .clk = "dss_dss_clk" },
582 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
583 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
584 { .role = "video2_clk", .clk = "dss_video2_clk" },
585 { .role = "video1_clk", .clk = "dss_video1_clk" },
586 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
Tomi Valkeinen2d5a3c82015-02-23 12:53:56 +0200[diff] [blame]587 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]588};
589
590static struct omap_hwmod dra7xx_dss_hwmod = {
591 .name = "dss_core",
592 .class = &dra7xx_dss_hwmod_class,
593 .clkdm_name = "dss_clkdm",
594 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
595 .sdma_reqs = dra7xx_dss_sdma_reqs,
596 .main_clk = "dss_dss_clk",
597 .prcm = {
598 .omap4 = {
599 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
600 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
601 .modulemode = MODULEMODE_SWCTRL,
602 },
603 },
604 .opt_clks = dss_opt_clks,
605 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
606};
607
608/*
609 * 'dispc' class
610 * display controller
611 */
612
613static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
614 .rev_offs = 0x0000,
615 .sysc_offs = 0x0010,
616 .syss_offs = 0x0014,
617 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
618 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
619 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
620 SYSS_HAS_RESET_STATUS),
621 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
622 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
623 .sysc_fields = &omap_hwmod_sysc_type1,
624};
625
626static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
627 .name = "dispc",
628 .sysc = &dra7xx_dispc_sysc,
629};
630
631/* dss_dispc */
632/* dss_dispc dev_attr */
633static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
634 .has_framedonetv_irq = 1,
635 .manager_count = 4,
636};
637
638static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
639 .name = "dss_dispc",
640 .class = &dra7xx_dispc_hwmod_class,
641 .clkdm_name = "dss_clkdm",
642 .main_clk = "dss_dss_clk",
643 .prcm = {
644 .omap4 = {
645 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
646 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
647 },
648 },
649 .dev_attr = &dss_dispc_dev_attr,
Tomi Valkeinena3818c62014-10-09 16:45:56 +0300[diff] [blame]650 .parent_hwmod = &dra7xx_dss_hwmod,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]651};
652
653/*
654 * 'hdmi' class
655 * hdmi controller
656 */
657
658static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
659 .rev_offs = 0x0000,
660 .sysc_offs = 0x0010,
661 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
662 SYSC_HAS_SOFTRESET),
663 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
664 SIDLE_SMART_WKUP),
665 .sysc_fields = &omap_hwmod_sysc_type2,
666};
667
668static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
669 .name = "hdmi",
670 .sysc = &dra7xx_hdmi_sysc,
671};
672
673/* dss_hdmi */
674
675static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
676 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
677};
678
679static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
680 .name = "dss_hdmi",
681 .class = &dra7xx_hdmi_hwmod_class,
682 .clkdm_name = "dss_clkdm",
683 .main_clk = "dss_48mhz_clk",
684 .prcm = {
685 .omap4 = {
686 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
687 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
688 },
689 },
690 .opt_clks = dss_hdmi_opt_clks,
691 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
Tomi Valkeinena3818c62014-10-09 16:45:56 +0300[diff] [blame]692 .parent_hwmod = &dra7xx_dss_hwmod,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]693};
694
Joel Fernandes628d7582016-10-18 10:55:22 +0300[diff] [blame]695/* AES (the 'P' (public) device) */
696static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
697 .rev_offs = 0x0080,
698 .sysc_offs = 0x0084,
699 .syss_offs = 0x0088,
700 .sysc_flags = SYSS_HAS_RESET_STATUS,
701};
702
703static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
704 .name = "aes",
705 .sysc = &dra7xx_aes_sysc,
706 .rev = 2,
707};
708
709/* AES1 */
710static struct omap_hwmod dra7xx_aes1_hwmod = {
711 .name = "aes1",
712 .class = &dra7xx_aes_hwmod_class,
713 .clkdm_name = "l4sec_clkdm",
714 .main_clk = "l3_iclk_div",
715 .prcm = {
716 .omap4 = {
717 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
718 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
720 },
721 },
722};
723
724/* AES2 */
725static struct omap_hwmod dra7xx_aes2_hwmod = {
726 .name = "aes2",
727 .class = &dra7xx_aes_hwmod_class,
728 .clkdm_name = "l4sec_clkdm",
729 .main_clk = "l3_iclk_div",
730 .prcm = {
731 .omap4 = {
732 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
733 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
734 .modulemode = MODULEMODE_HWCTRL,
735 },
736 },
737};
738
Lokesh Vutla7e45f172016-10-18 10:55:23 +0300[diff] [blame]739/* sha0 HIB2 (the 'P' (public) device) */
740static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
741 .rev_offs = 0x100,
742 .sysc_offs = 0x110,
743 .syss_offs = 0x114,
744 .sysc_flags = SYSS_HAS_RESET_STATUS,
745};
746
747static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
748 .name = "sham",
749 .sysc = &dra7xx_sha0_sysc,
750 .rev = 2,
751};
752
753struct omap_hwmod dra7xx_sha0_hwmod = {
754 .name = "sham",
755 .class = &dra7xx_sha0_hwmod_class,
756 .clkdm_name = "l4sec_clkdm",
757 .main_clk = "l3_iclk_div",
758 .prcm = {
759 .omap4 = {
760 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
761 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
762 .modulemode = MODULEMODE_HWCTRL,
763 },
764 },
765};
766
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]767/*
768 * 'elm' class
769 *
770 */
771
772static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
773 .rev_offs = 0x0000,
774 .sysc_offs = 0x0010,
775 .syss_offs = 0x0014,
776 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
777 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
778 SYSS_HAS_RESET_STATUS),
779 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
780 SIDLE_SMART_WKUP),
781 .sysc_fields = &omap_hwmod_sysc_type1,
782};
783
784static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
785 .name = "elm",
786 .sysc = &dra7xx_elm_sysc,
787};
788
789/* elm */
790
791static struct omap_hwmod dra7xx_elm_hwmod = {
792 .name = "elm",
793 .class = &dra7xx_elm_hwmod_class,
794 .clkdm_name = "l4per_clkdm",
795 .main_clk = "l3_iclk_div",
796 .prcm = {
797 .omap4 = {
798 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
799 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
800 },
801 },
802};
803
804/*
805 * 'gpio' class
806 *
807 */
808
809static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
810 .rev_offs = 0x0000,
811 .sysc_offs = 0x0010,
812 .syss_offs = 0x0114,
813 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
814 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
815 SYSS_HAS_RESET_STATUS),
816 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
817 SIDLE_SMART_WKUP),
818 .sysc_fields = &omap_hwmod_sysc_type1,
819};
820
821static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
822 .name = "gpio",
823 .sysc = &dra7xx_gpio_sysc,
824 .rev = 2,
825};
826
827/* gpio dev_attr */
828static struct omap_gpio_dev_attr gpio_dev_attr = {
829 .bank_width = 32,
830 .dbck_flag = true,
831};
832
833/* gpio1 */
834static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
835 { .role = "dbclk", .clk = "gpio1_dbclk" },
836};
837
838static struct omap_hwmod dra7xx_gpio1_hwmod = {
839 .name = "gpio1",
840 .class = &dra7xx_gpio_hwmod_class,
841 .clkdm_name = "wkupaon_clkdm",
842 .main_clk = "wkupaon_iclk_mux",
843 .prcm = {
844 .omap4 = {
845 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
846 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
847 .modulemode = MODULEMODE_HWCTRL,
848 },
849 },
850 .opt_clks = gpio1_opt_clks,
851 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
852 .dev_attr = &gpio_dev_attr,
853};
854
855/* gpio2 */
856static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
857 { .role = "dbclk", .clk = "gpio2_dbclk" },
858};
859
860static struct omap_hwmod dra7xx_gpio2_hwmod = {
861 .name = "gpio2",
862 .class = &dra7xx_gpio_hwmod_class,
863 .clkdm_name = "l4per_clkdm",
864 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
865 .main_clk = "l3_iclk_div",
866 .prcm = {
867 .omap4 = {
868 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
869 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
870 .modulemode = MODULEMODE_HWCTRL,
871 },
872 },
873 .opt_clks = gpio2_opt_clks,
874 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
875 .dev_attr = &gpio_dev_attr,
876};
877
878/* gpio3 */
879static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
880 { .role = "dbclk", .clk = "gpio3_dbclk" },
881};
882
883static struct omap_hwmod dra7xx_gpio3_hwmod = {
884 .name = "gpio3",
885 .class = &dra7xx_gpio_hwmod_class,
886 .clkdm_name = "l4per_clkdm",
887 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
888 .main_clk = "l3_iclk_div",
889 .prcm = {
890 .omap4 = {
891 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
892 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
893 .modulemode = MODULEMODE_HWCTRL,
894 },
895 },
896 .opt_clks = gpio3_opt_clks,
897 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
898 .dev_attr = &gpio_dev_attr,
899};
900
901/* gpio4 */
902static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
903 { .role = "dbclk", .clk = "gpio4_dbclk" },
904};
905
906static struct omap_hwmod dra7xx_gpio4_hwmod = {
907 .name = "gpio4",
908 .class = &dra7xx_gpio_hwmod_class,
909 .clkdm_name = "l4per_clkdm",
910 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
911 .main_clk = "l3_iclk_div",
912 .prcm = {
913 .omap4 = {
914 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
915 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
916 .modulemode = MODULEMODE_HWCTRL,
917 },
918 },
919 .opt_clks = gpio4_opt_clks,
920 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
921 .dev_attr = &gpio_dev_attr,
922};
923
924/* gpio5 */
925static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
926 { .role = "dbclk", .clk = "gpio5_dbclk" },
927};
928
929static struct omap_hwmod dra7xx_gpio5_hwmod = {
930 .name = "gpio5",
931 .class = &dra7xx_gpio_hwmod_class,
932 .clkdm_name = "l4per_clkdm",
933 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
934 .main_clk = "l3_iclk_div",
935 .prcm = {
936 .omap4 = {
937 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
938 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
939 .modulemode = MODULEMODE_HWCTRL,
940 },
941 },
942 .opt_clks = gpio5_opt_clks,
943 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
944 .dev_attr = &gpio_dev_attr,
945};
946
947/* gpio6 */
948static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
949 { .role = "dbclk", .clk = "gpio6_dbclk" },
950};
951
952static struct omap_hwmod dra7xx_gpio6_hwmod = {
953 .name = "gpio6",
954 .class = &dra7xx_gpio_hwmod_class,
955 .clkdm_name = "l4per_clkdm",
956 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
957 .main_clk = "l3_iclk_div",
958 .prcm = {
959 .omap4 = {
960 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
961 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
962 .modulemode = MODULEMODE_HWCTRL,
963 },
964 },
965 .opt_clks = gpio6_opt_clks,
966 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
967 .dev_attr = &gpio_dev_attr,
968};
969
970/* gpio7 */
971static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
972 { .role = "dbclk", .clk = "gpio7_dbclk" },
973};
974
975static struct omap_hwmod dra7xx_gpio7_hwmod = {
976 .name = "gpio7",
977 .class = &dra7xx_gpio_hwmod_class,
978 .clkdm_name = "l4per_clkdm",
979 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
980 .main_clk = "l3_iclk_div",
981 .prcm = {
982 .omap4 = {
983 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
984 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
985 .modulemode = MODULEMODE_HWCTRL,
986 },
987 },
988 .opt_clks = gpio7_opt_clks,
989 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
990 .dev_attr = &gpio_dev_attr,
991};
992
993/* gpio8 */
994static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
995 { .role = "dbclk", .clk = "gpio8_dbclk" },
996};
997
998static struct omap_hwmod dra7xx_gpio8_hwmod = {
999 .name = "gpio8",
1000 .class = &dra7xx_gpio_hwmod_class,
1001 .clkdm_name = "l4per_clkdm",
1002 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1003 .main_clk = "l3_iclk_div",
1004 .prcm = {
1005 .omap4 = {
1006 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1007 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1008 .modulemode = MODULEMODE_HWCTRL,
1009 },
1010 },
1011 .opt_clks = gpio8_opt_clks,
1012 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
1013 .dev_attr = &gpio_dev_attr,
1014};
1015
1016/*
1017 * 'gpmc' class
1018 *
1019 */
1020
1021static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1022 .rev_offs = 0x0000,
1023 .sysc_offs = 0x0010,
1024 .syss_offs = 0x0014,
1025 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1026 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
Roger Quadros91a57732015-07-08 17:34:43 +0300[diff] [blame]1027 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1028 .sysc_fields = &omap_hwmod_sysc_type1,
1029};
1030
1031static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1032 .name = "gpmc",
1033 .sysc = &dra7xx_gpmc_sysc,
1034};
1035
1036/* gpmc */
1037
1038static struct omap_hwmod dra7xx_gpmc_hwmod = {
1039 .name = "gpmc",
1040 .class = &dra7xx_gpmc_hwmod_class,
1041 .clkdm_name = "l3main1_clkdm",
Tony Lindgren63aa9452015-06-01 19:22:10 -0600[diff] [blame]1042 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
Roger Quadros91a57732015-07-08 17:34:43 +0300[diff] [blame]1043 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1044 .main_clk = "l3_iclk_div",
1045 .prcm = {
1046 .omap4 = {
1047 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1048 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1049 .modulemode = MODULEMODE_HWCTRL,
1050 },
1051 },
1052};
1053
1054/*
1055 * 'hdq1w' class
1056 *
1057 */
1058
1059static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1060 .rev_offs = 0x0000,
1061 .sysc_offs = 0x0014,
1062 .syss_offs = 0x0018,
1063 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1064 SYSS_HAS_RESET_STATUS),
1065 .sysc_fields = &omap_hwmod_sysc_type1,
1066};
1067
1068static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1069 .name = "hdq1w",
1070 .sysc = &dra7xx_hdq1w_sysc,
1071};
1072
1073/* hdq1w */
1074
1075static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1076 .name = "hdq1w",
1077 .class = &dra7xx_hdq1w_hwmod_class,
1078 .clkdm_name = "l4per_clkdm",
1079 .flags = HWMOD_INIT_NO_RESET,
1080 .main_clk = "func_12m_fclk",
1081 .prcm = {
1082 .omap4 = {
1083 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1084 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1085 .modulemode = MODULEMODE_SWCTRL,
1086 },
1087 },
1088};
1089
1090/*
1091 * 'i2c' class
1092 *
1093 */
1094
1095static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1096 .sysc_offs = 0x0010,
1097 .syss_offs = 0x0090,
1098 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1099 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1100 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1101 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1102 SIDLE_SMART_WKUP),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1103 .sysc_fields = &omap_hwmod_sysc_type1,
1104};
1105
1106static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1107 .name = "i2c",
1108 .sysc = &dra7xx_i2c_sysc,
1109 .reset = &omap_i2c_reset,
1110 .rev = OMAP_I2C_IP_VERSION_2,
1111};
1112
1113/* i2c dev_attr */
1114static struct omap_i2c_dev_attr i2c_dev_attr = {
1115 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1116};
1117
1118/* i2c1 */
1119static struct omap_hwmod dra7xx_i2c1_hwmod = {
1120 .name = "i2c1",
1121 .class = &dra7xx_i2c_hwmod_class,
1122 .clkdm_name = "l4per_clkdm",
1123 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1124 .main_clk = "func_96m_fclk",
1125 .prcm = {
1126 .omap4 = {
1127 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1128 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1129 .modulemode = MODULEMODE_SWCTRL,
1130 },
1131 },
1132 .dev_attr = &i2c_dev_attr,
1133};
1134
1135/* i2c2 */
1136static struct omap_hwmod dra7xx_i2c2_hwmod = {
1137 .name = "i2c2",
1138 .class = &dra7xx_i2c_hwmod_class,
1139 .clkdm_name = "l4per_clkdm",
1140 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1141 .main_clk = "func_96m_fclk",
1142 .prcm = {
1143 .omap4 = {
1144 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1145 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1146 .modulemode = MODULEMODE_SWCTRL,
1147 },
1148 },
1149 .dev_attr = &i2c_dev_attr,
1150};
1151
1152/* i2c3 */
1153static struct omap_hwmod dra7xx_i2c3_hwmod = {
1154 .name = "i2c3",
1155 .class = &dra7xx_i2c_hwmod_class,
1156 .clkdm_name = "l4per_clkdm",
1157 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1158 .main_clk = "func_96m_fclk",
1159 .prcm = {
1160 .omap4 = {
1161 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1162 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1163 .modulemode = MODULEMODE_SWCTRL,
1164 },
1165 },
1166 .dev_attr = &i2c_dev_attr,
1167};
1168
1169/* i2c4 */
1170static struct omap_hwmod dra7xx_i2c4_hwmod = {
1171 .name = "i2c4",
1172 .class = &dra7xx_i2c_hwmod_class,
1173 .clkdm_name = "l4per_clkdm",
1174 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1175 .main_clk = "func_96m_fclk",
1176 .prcm = {
1177 .omap4 = {
1178 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1179 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1180 .modulemode = MODULEMODE_SWCTRL,
1181 },
1182 },
1183 .dev_attr = &i2c_dev_attr,
1184};
1185
1186/* i2c5 */
1187static struct omap_hwmod dra7xx_i2c5_hwmod = {
1188 .name = "i2c5",
1189 .class = &dra7xx_i2c_hwmod_class,
1190 .clkdm_name = "ipu_clkdm",
1191 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1192 .main_clk = "func_96m_fclk",
1193 .prcm = {
1194 .omap4 = {
1195 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1196 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1197 .modulemode = MODULEMODE_SWCTRL,
1198 },
1199 },
1200 .dev_attr = &i2c_dev_attr,
1201};
1202
1203/*
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]1204 * 'mailbox' class
1205 *
1206 */
1207
1208static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1209 .rev_offs = 0x0000,
1210 .sysc_offs = 0x0010,
1211 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1212 SYSC_HAS_SOFTRESET),
1213 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1214 .sysc_fields = &omap_hwmod_sysc_type2,
1215};
1216
1217static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1218 .name = "mailbox",
1219 .sysc = &dra7xx_mailbox_sysc,
1220};
1221
1222/* mailbox1 */
1223static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1224 .name = "mailbox1",
1225 .class = &dra7xx_mailbox_hwmod_class,
1226 .clkdm_name = "l4cfg_clkdm",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1230 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1231 },
1232 },
1233};
1234
1235/* mailbox2 */
1236static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1237 .name = "mailbox2",
1238 .class = &dra7xx_mailbox_hwmod_class,
1239 .clkdm_name = "l4cfg_clkdm",
1240 .prcm = {
1241 .omap4 = {
1242 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1243 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1244 },
1245 },
1246};
1247
1248/* mailbox3 */
1249static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1250 .name = "mailbox3",
1251 .class = &dra7xx_mailbox_hwmod_class,
1252 .clkdm_name = "l4cfg_clkdm",
1253 .prcm = {
1254 .omap4 = {
1255 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1256 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1257 },
1258 },
1259};
1260
1261/* mailbox4 */
1262static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1263 .name = "mailbox4",
1264 .class = &dra7xx_mailbox_hwmod_class,
1265 .clkdm_name = "l4cfg_clkdm",
1266 .prcm = {
1267 .omap4 = {
1268 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1269 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1270 },
1271 },
1272};
1273
1274/* mailbox5 */
1275static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1276 .name = "mailbox5",
1277 .class = &dra7xx_mailbox_hwmod_class,
1278 .clkdm_name = "l4cfg_clkdm",
1279 .prcm = {
1280 .omap4 = {
1281 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1282 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1283 },
1284 },
1285};
1286
1287/* mailbox6 */
1288static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1289 .name = "mailbox6",
1290 .class = &dra7xx_mailbox_hwmod_class,
1291 .clkdm_name = "l4cfg_clkdm",
1292 .prcm = {
1293 .omap4 = {
1294 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1295 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1296 },
1297 },
1298};
1299
1300/* mailbox7 */
1301static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1302 .name = "mailbox7",
1303 .class = &dra7xx_mailbox_hwmod_class,
1304 .clkdm_name = "l4cfg_clkdm",
1305 .prcm = {
1306 .omap4 = {
1307 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1308 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1309 },
1310 },
1311};
1312
1313/* mailbox8 */
1314static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1315 .name = "mailbox8",
1316 .class = &dra7xx_mailbox_hwmod_class,
1317 .clkdm_name = "l4cfg_clkdm",
1318 .prcm = {
1319 .omap4 = {
1320 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1321 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1322 },
1323 },
1324};
1325
1326/* mailbox9 */
1327static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1328 .name = "mailbox9",
1329 .class = &dra7xx_mailbox_hwmod_class,
1330 .clkdm_name = "l4cfg_clkdm",
1331 .prcm = {
1332 .omap4 = {
1333 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1334 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1335 },
1336 },
1337};
1338
1339/* mailbox10 */
1340static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1341 .name = "mailbox10",
1342 .class = &dra7xx_mailbox_hwmod_class,
1343 .clkdm_name = "l4cfg_clkdm",
1344 .prcm = {
1345 .omap4 = {
1346 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1347 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1348 },
1349 },
1350};
1351
1352/* mailbox11 */
1353static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1354 .name = "mailbox11",
1355 .class = &dra7xx_mailbox_hwmod_class,
1356 .clkdm_name = "l4cfg_clkdm",
1357 .prcm = {
1358 .omap4 = {
1359 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1360 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1361 },
1362 },
1363};
1364
1365/* mailbox12 */
1366static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1367 .name = "mailbox12",
1368 .class = &dra7xx_mailbox_hwmod_class,
1369 .clkdm_name = "l4cfg_clkdm",
1370 .prcm = {
1371 .omap4 = {
1372 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1373 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1374 },
1375 },
1376};
1377
1378/* mailbox13 */
1379static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1380 .name = "mailbox13",
1381 .class = &dra7xx_mailbox_hwmod_class,
1382 .clkdm_name = "l4cfg_clkdm",
1383 .prcm = {
1384 .omap4 = {
1385 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1386 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1387 },
1388 },
1389};
1390
1391/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1392 * 'mcspi' class
1393 *
1394 */
1395
1396static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1397 .rev_offs = 0x0000,
1398 .sysc_offs = 0x0010,
1399 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1400 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1401 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1402 SIDLE_SMART_WKUP),
1403 .sysc_fields = &omap_hwmod_sysc_type2,
1404};
1405
1406static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1407 .name = "mcspi",
1408 .sysc = &dra7xx_mcspi_sysc,
1409 .rev = OMAP4_MCSPI_REV,
1410};
1411
1412/* mcspi1 */
1413/* mcspi1 dev_attr */
1414static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1415 .num_chipselect = 4,
1416};
1417
1418static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1419 .name = "mcspi1",
1420 .class = &dra7xx_mcspi_hwmod_class,
1421 .clkdm_name = "l4per_clkdm",
1422 .main_clk = "func_48m_fclk",
1423 .prcm = {
1424 .omap4 = {
1425 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1426 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1427 .modulemode = MODULEMODE_SWCTRL,
1428 },
1429 },
1430 .dev_attr = &mcspi1_dev_attr,
1431};
1432
1433/* mcspi2 */
1434/* mcspi2 dev_attr */
1435static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1436 .num_chipselect = 2,
1437};
1438
1439static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1440 .name = "mcspi2",
1441 .class = &dra7xx_mcspi_hwmod_class,
1442 .clkdm_name = "l4per_clkdm",
1443 .main_clk = "func_48m_fclk",
1444 .prcm = {
1445 .omap4 = {
1446 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1447 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1448 .modulemode = MODULEMODE_SWCTRL,
1449 },
1450 },
1451 .dev_attr = &mcspi2_dev_attr,
1452};
1453
1454/* mcspi3 */
1455/* mcspi3 dev_attr */
1456static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1457 .num_chipselect = 2,
1458};
1459
1460static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1461 .name = "mcspi3",
1462 .class = &dra7xx_mcspi_hwmod_class,
1463 .clkdm_name = "l4per_clkdm",
1464 .main_clk = "func_48m_fclk",
1465 .prcm = {
1466 .omap4 = {
1467 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1468 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1469 .modulemode = MODULEMODE_SWCTRL,
1470 },
1471 },
1472 .dev_attr = &mcspi3_dev_attr,
1473};
1474
1475/* mcspi4 */
1476/* mcspi4 dev_attr */
1477static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1478 .num_chipselect = 1,
1479};
1480
1481static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1482 .name = "mcspi4",
1483 .class = &dra7xx_mcspi_hwmod_class,
1484 .clkdm_name = "l4per_clkdm",
1485 .main_clk = "func_48m_fclk",
1486 .prcm = {
1487 .omap4 = {
1488 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1489 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1490 .modulemode = MODULEMODE_SWCTRL,
1491 },
1492 },
1493 .dev_attr = &mcspi4_dev_attr,
1494};
1495
1496/*
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]1497 * 'mcasp' class
1498 *
1499 */
1500static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1501 .sysc_offs = 0x0004,
1502 .sysc_flags = SYSC_HAS_SIDLEMODE,
1503 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1504 .sysc_fields = &omap_hwmod_sysc_type3,
1505};
1506
1507static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1508 .name = "mcasp",
1509 .sysc = &dra7xx_mcasp_sysc,
1510};
1511
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]1512/* mcasp1 */
1513static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1514 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1515 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1516};
1517
1518static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1519 .name = "mcasp1",
1520 .class = &dra7xx_mcasp_hwmod_class,
1521 .clkdm_name = "ipu_clkdm",
1522 .main_clk = "mcasp1_aux_gfclk_mux",
1523 .flags = HWMOD_OPT_CLKS_NEEDED,
1524 .prcm = {
1525 .omap4 = {
1526 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1527 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1528 .modulemode = MODULEMODE_SWCTRL,
1529 },
1530 },
1531 .opt_clks = mcasp1_opt_clks,
1532 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1533};
1534
1535/* mcasp2 */
1536static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1537 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1538 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1539};
1540
1541static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1542 .name = "mcasp2",
1543 .class = &dra7xx_mcasp_hwmod_class,
1544 .clkdm_name = "l4per2_clkdm",
1545 .main_clk = "mcasp2_aux_gfclk_mux",
1546 .flags = HWMOD_OPT_CLKS_NEEDED,
1547 .prcm = {
1548 .omap4 = {
1549 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1550 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1551 .modulemode = MODULEMODE_SWCTRL,
1552 },
1553 },
1554 .opt_clks = mcasp2_opt_clks,
1555 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1556};
1557
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]1558/* mcasp3 */
1559static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1560 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1561};
1562
1563static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1564 .name = "mcasp3",
1565 .class = &dra7xx_mcasp_hwmod_class,
1566 .clkdm_name = "l4per2_clkdm",
1567 .main_clk = "mcasp3_aux_gfclk_mux",
1568 .flags = HWMOD_OPT_CLKS_NEEDED,
1569 .prcm = {
1570 .omap4 = {
1571 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1572 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1573 .modulemode = MODULEMODE_SWCTRL,
1574 },
1575 },
1576 .opt_clks = mcasp3_opt_clks,
1577 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1578};
1579
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]1580/* mcasp4 */
1581static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1582 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1583};
1584
1585static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1586 .name = "mcasp4",
1587 .class = &dra7xx_mcasp_hwmod_class,
1588 .clkdm_name = "l4per2_clkdm",
1589 .main_clk = "mcasp4_aux_gfclk_mux",
1590 .flags = HWMOD_OPT_CLKS_NEEDED,
1591 .prcm = {
1592 .omap4 = {
1593 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1594 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1595 .modulemode = MODULEMODE_SWCTRL,
1596 },
1597 },
1598 .opt_clks = mcasp4_opt_clks,
1599 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1600};
1601
1602/* mcasp5 */
1603static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1604 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1605};
1606
1607static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1608 .name = "mcasp5",
1609 .class = &dra7xx_mcasp_hwmod_class,
1610 .clkdm_name = "l4per2_clkdm",
1611 .main_clk = "mcasp5_aux_gfclk_mux",
1612 .flags = HWMOD_OPT_CLKS_NEEDED,
1613 .prcm = {
1614 .omap4 = {
1615 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1616 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1617 .modulemode = MODULEMODE_SWCTRL,
1618 },
1619 },
1620 .opt_clks = mcasp5_opt_clks,
1621 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1622};
1623
1624/* mcasp6 */
1625static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1626 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1627};
1628
1629static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1630 .name = "mcasp6",
1631 .class = &dra7xx_mcasp_hwmod_class,
1632 .clkdm_name = "l4per2_clkdm",
1633 .main_clk = "mcasp6_aux_gfclk_mux",
1634 .flags = HWMOD_OPT_CLKS_NEEDED,
1635 .prcm = {
1636 .omap4 = {
1637 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1638 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1639 .modulemode = MODULEMODE_SWCTRL,
1640 },
1641 },
1642 .opt_clks = mcasp6_opt_clks,
1643 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1644};
1645
1646/* mcasp7 */
1647static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1648 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1649};
1650
1651static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1652 .name = "mcasp7",
1653 .class = &dra7xx_mcasp_hwmod_class,
1654 .clkdm_name = "l4per2_clkdm",
1655 .main_clk = "mcasp7_aux_gfclk_mux",
1656 .flags = HWMOD_OPT_CLKS_NEEDED,
1657 .prcm = {
1658 .omap4 = {
1659 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1660 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1661 .modulemode = MODULEMODE_SWCTRL,
1662 },
1663 },
1664 .opt_clks = mcasp7_opt_clks,
1665 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1666};
1667
1668/* mcasp8 */
1669static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1670 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1671};
1672
1673static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1674 .name = "mcasp8",
1675 .class = &dra7xx_mcasp_hwmod_class,
1676 .clkdm_name = "l4per2_clkdm",
1677 .main_clk = "mcasp8_aux_gfclk_mux",
1678 .flags = HWMOD_OPT_CLKS_NEEDED,
1679 .prcm = {
1680 .omap4 = {
1681 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1682 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1683 .modulemode = MODULEMODE_SWCTRL,
1684 },
1685 },
1686 .opt_clks = mcasp8_opt_clks,
1687 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1688};
1689
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]1690/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1691 * 'mmc' class
1692 *
1693 */
1694
1695static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1696 .rev_offs = 0x0000,
1697 .sysc_offs = 0x0010,
1698 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1699 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1700 SYSC_HAS_SOFTRESET),
1701 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1702 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1703 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1704 .sysc_fields = &omap_hwmod_sysc_type2,
1705};
1706
1707static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1708 .name = "mmc",
1709 .sysc = &dra7xx_mmc_sysc,
1710};
1711
1712/* mmc1 */
1713static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1714 { .role = "clk32k", .clk = "mmc1_clk32k" },
1715};
1716
1717/* mmc1 dev_attr */
Andreas Fenkart55143432014-11-08 15:33:09 +0100[diff] [blame]1718static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1719 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1720};
1721
1722static struct omap_hwmod dra7xx_mmc1_hwmod = {
1723 .name = "mmc1",
1724 .class = &dra7xx_mmc_hwmod_class,
1725 .clkdm_name = "l3init_clkdm",
1726 .main_clk = "mmc1_fclk_div",
1727 .prcm = {
1728 .omap4 = {
1729 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1730 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1731 .modulemode = MODULEMODE_SWCTRL,
1732 },
1733 },
1734 .opt_clks = mmc1_opt_clks,
1735 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1736 .dev_attr = &mmc1_dev_attr,
1737};
1738
1739/* mmc2 */
1740static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1741 { .role = "clk32k", .clk = "mmc2_clk32k" },
1742};
1743
1744static struct omap_hwmod dra7xx_mmc2_hwmod = {
1745 .name = "mmc2",
1746 .class = &dra7xx_mmc_hwmod_class,
1747 .clkdm_name = "l3init_clkdm",
1748 .main_clk = "mmc2_fclk_div",
1749 .prcm = {
1750 .omap4 = {
1751 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1752 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1753 .modulemode = MODULEMODE_SWCTRL,
1754 },
1755 },
1756 .opt_clks = mmc2_opt_clks,
1757 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1758};
1759
1760/* mmc3 */
1761static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1762 { .role = "clk32k", .clk = "mmc3_clk32k" },
1763};
1764
1765static struct omap_hwmod dra7xx_mmc3_hwmod = {
1766 .name = "mmc3",
1767 .class = &dra7xx_mmc_hwmod_class,
1768 .clkdm_name = "l4per_clkdm",
1769 .main_clk = "mmc3_gfclk_div",
1770 .prcm = {
1771 .omap4 = {
1772 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1773 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1774 .modulemode = MODULEMODE_SWCTRL,
1775 },
1776 },
1777 .opt_clks = mmc3_opt_clks,
1778 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1779};
1780
1781/* mmc4 */
1782static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1783 { .role = "clk32k", .clk = "mmc4_clk32k" },
1784};
1785
1786static struct omap_hwmod dra7xx_mmc4_hwmod = {
1787 .name = "mmc4",
1788 .class = &dra7xx_mmc_hwmod_class,
1789 .clkdm_name = "l4per_clkdm",
1790 .main_clk = "mmc4_gfclk_div",
1791 .prcm = {
1792 .omap4 = {
1793 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1794 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1795 .modulemode = MODULEMODE_SWCTRL,
1796 },
1797 },
1798 .opt_clks = mmc4_opt_clks,
1799 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1800};
1801
1802/*
1803 * 'mpu' class
1804 *
1805 */
1806
1807static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1808 .name = "mpu",
1809};
1810
1811/* mpu */
1812static struct omap_hwmod dra7xx_mpu_hwmod = {
1813 .name = "mpu",
1814 .class = &dra7xx_mpu_hwmod_class,
1815 .clkdm_name = "mpu_clkdm",
1816 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1817 .main_clk = "dpll_mpu_m2_ck",
1818 .prcm = {
1819 .omap4 = {
1820 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1821 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1822 },
1823 },
1824};
1825
1826/*
1827 * 'ocp2scp' class
1828 *
1829 */
1830
1831static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1832 .rev_offs = 0x0000,
1833 .sysc_offs = 0x0010,
1834 .syss_offs = 0x0014,
1835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1836 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
Kishon Vijay Abraham I4965be12016-02-09 14:35:43 +0530[diff] [blame]1837 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1838 .sysc_fields = &omap_hwmod_sysc_type1,
1839};
1840
1841static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1842 .name = "ocp2scp",
1843 .sysc = &dra7xx_ocp2scp_sysc,
1844};
1845
1846/* ocp2scp1 */
1847static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1848 .name = "ocp2scp1",
1849 .class = &dra7xx_ocp2scp_hwmod_class,
1850 .clkdm_name = "l3init_clkdm",
1851 .main_clk = "l4_root_clk_div",
1852 .prcm = {
1853 .omap4 = {
1854 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1855 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1856 .modulemode = MODULEMODE_HWCTRL,
1857 },
1858 },
1859};
1860
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]1861/* ocp2scp3 */
1862static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1863 .name = "ocp2scp3",
1864 .class = &dra7xx_ocp2scp_hwmod_class,
1865 .clkdm_name = "l3init_clkdm",
1866 .main_clk = "l4_root_clk_div",
1867 .prcm = {
1868 .omap4 = {
1869 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1870 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1871 .modulemode = MODULEMODE_HWCTRL,
1872 },
1873 },
1874};
1875
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1876/*
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1877 * 'PCIE' class
1878 *
1879 */
1880
Sekhar Nori1c96bee2016-02-18 16:49:56 +0530[diff] [blame]1881/*
1882 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1883 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1884 * associated with an IP automatically leaving the driver to handle that
1885 * by itself. This does not work for PCIeSS which needs the reset lines
1886 * deasserted for the driver to start accessing registers.
1887 *
1888 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1889 * lines after asserting them.
1890 */
1891static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1892{
1893 int i;
1894
1895 for (i = 0; i < oh->rst_lines_cnt; i++) {
1896 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1897 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1898 }
1899
1900 return 0;
1901}
1902
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1903static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1904 .name = "pcie",
Sekhar Nori1c96bee2016-02-18 16:49:56 +0530[diff] [blame]1905 .reset = dra7xx_pciess_reset,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1906};
1907
1908/* pcie1 */
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1909static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1910 { .name = "pcie", .rst_shift = 0 },
1911};
1912
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1913static struct omap_hwmod dra7xx_pciess1_hwmod = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1914 .name = "pcie1",
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1915 .class = &dra7xx_pciess_hwmod_class,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1916 .clkdm_name = "pcie_clkdm",
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1917 .rst_lines = dra7xx_pciess1_resets,
1918 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1919 .main_clk = "l4_root_clk_div",
1920 .prcm = {
1921 .omap4 = {
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1922 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1923 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1924 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1925 .modulemode = MODULEMODE_SWCTRL,
1926 },
1927 },
1928};
1929
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1930/* pcie2 */
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1931static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1932 { .name = "pcie", .rst_shift = 1 },
1933};
1934
1935/* pcie2 */
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1936static struct omap_hwmod dra7xx_pciess2_hwmod = {
1937 .name = "pcie2",
1938 .class = &dra7xx_pciess_hwmod_class,
1939 .clkdm_name = "pcie_clkdm",
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1940 .rst_lines = dra7xx_pciess2_resets,
1941 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1942 .main_clk = "l4_root_clk_div",
1943 .prcm = {
1944 .omap4 = {
1945 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1946 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1947 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1948 .modulemode = MODULEMODE_SWCTRL,
1949 },
1950 },
1951};
1952
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1953/*
1954 * 'qspi' class
1955 *
1956 */
1957
1958static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1959 .sysc_offs = 0x0010,
1960 .sysc_flags = SYSC_HAS_SIDLEMODE,
1961 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1962 SIDLE_SMART_WKUP),
1963 .sysc_fields = &omap_hwmod_sysc_type2,
1964};
1965
1966static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1967 .name = "qspi",
1968 .sysc = &dra7xx_qspi_sysc,
1969};
1970
1971/* qspi */
1972static struct omap_hwmod dra7xx_qspi_hwmod = {
1973 .name = "qspi",
1974 .class = &dra7xx_qspi_hwmod_class,
1975 .clkdm_name = "l4per2_clkdm",
1976 .main_clk = "qspi_gfclk_div",
1977 .prcm = {
1978 .omap4 = {
1979 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1980 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1981 .modulemode = MODULEMODE_SWCTRL,
1982 },
1983 },
1984};
1985
1986/*
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]1987 * 'rtcss' class
1988 *
1989 */
1990static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1991 .sysc_offs = 0x0078,
1992 .sysc_flags = SYSC_HAS_SIDLEMODE,
1993 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1994 SIDLE_SMART_WKUP),
1995 .sysc_fields = &omap_hwmod_sysc_type3,
1996};
1997
1998static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1999 .name = "rtcss",
2000 .sysc = &dra7xx_rtcss_sysc,
Lokesh Vutlad7d31b82016-04-10 13:20:10 -0600[diff] [blame]2001 .unlock = &omap_hwmod_rtc_unlock,
2002 .lock = &omap_hwmod_rtc_lock,
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]2003};
2004
2005/* rtcss */
2006static struct omap_hwmod dra7xx_rtcss_hwmod = {
2007 .name = "rtcss",
2008 .class = &dra7xx_rtcss_hwmod_class,
2009 .clkdm_name = "rtc_clkdm",
2010 .main_clk = "sys_32k_ck",
2011 .prcm = {
2012 .omap4 = {
2013 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2014 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2015 .modulemode = MODULEMODE_SWCTRL,
2016 },
2017 },
2018};
2019
2020/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2021 * 'sata' class
2022 *
2023 */
2024
2025static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2026 .sysc_offs = 0x0000,
2027 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2028 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2029 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2030 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2031 .sysc_fields = &omap_hwmod_sysc_type2,
2032};
2033
2034static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2035 .name = "sata",
2036 .sysc = &dra7xx_sata_sysc,
2037};
2038
2039/* sata */
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2040
2041static struct omap_hwmod dra7xx_sata_hwmod = {
2042 .name = "sata",
2043 .class = &dra7xx_sata_hwmod_class,
2044 .clkdm_name = "l3init_clkdm",
2045 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2046 .main_clk = "func_48m_fclk",
Roger Quadros1ea09992014-07-06 15:51:24 -0600[diff] [blame]2047 .mpu_rt_idx = 1,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2048 .prcm = {
2049 .omap4 = {
2050 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2051 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2052 .modulemode = MODULEMODE_SWCTRL,
2053 },
2054 },
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2055};
2056
2057/*
2058 * 'smartreflex' class
2059 *
2060 */
2061
2062/* The IP is not compliant to type1 / type2 scheme */
2063static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2064 .sidle_shift = 24,
2065 .enwkup_shift = 26,
2066};
2067
2068static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2069 .sysc_offs = 0x0038,
2070 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2071 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2072 SIDLE_SMART_WKUP),
2073 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2074};
2075
2076static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2077 .name = "smartreflex",
2078 .sysc = &dra7xx_smartreflex_sysc,
2079 .rev = 2,
2080};
2081
2082/* smartreflex_core */
2083/* smartreflex_core dev_attr */
2084static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2085 .sensor_voltdm_name = "core",
2086};
2087
2088static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2089 .name = "smartreflex_core",
2090 .class = &dra7xx_smartreflex_hwmod_class,
2091 .clkdm_name = "coreaon_clkdm",
2092 .main_clk = "wkupaon_iclk_mux",
2093 .prcm = {
2094 .omap4 = {
2095 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2096 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2097 .modulemode = MODULEMODE_SWCTRL,
2098 },
2099 },
2100 .dev_attr = &smartreflex_core_dev_attr,
2101};
2102
2103/* smartreflex_mpu */
2104/* smartreflex_mpu dev_attr */
2105static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2106 .sensor_voltdm_name = "mpu",
2107};
2108
2109static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2110 .name = "smartreflex_mpu",
2111 .class = &dra7xx_smartreflex_hwmod_class,
2112 .clkdm_name = "coreaon_clkdm",
2113 .main_clk = "wkupaon_iclk_mux",
2114 .prcm = {
2115 .omap4 = {
2116 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2117 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2118 .modulemode = MODULEMODE_SWCTRL,
2119 },
2120 },
2121 .dev_attr = &smartreflex_mpu_dev_attr,
2122};
2123
2124/*
2125 * 'spinlock' class
2126 *
2127 */
2128
2129static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2130 .rev_offs = 0x0000,
2131 .sysc_offs = 0x0010,
2132 .syss_offs = 0x0014,
Suman Annac317d0f2014-01-10 17:43:08 -0600[diff] [blame]2133 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2134 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2135 SYSS_HAS_RESET_STATUS),
2136 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2137 .sysc_fields = &omap_hwmod_sysc_type1,
2138};
2139
2140static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2141 .name = "spinlock",
2142 .sysc = &dra7xx_spinlock_sysc,
2143};
2144
2145/* spinlock */
2146static struct omap_hwmod dra7xx_spinlock_hwmod = {
2147 .name = "spinlock",
2148 .class = &dra7xx_spinlock_hwmod_class,
2149 .clkdm_name = "l4cfg_clkdm",
2150 .main_clk = "l3_iclk_div",
2151 .prcm = {
2152 .omap4 = {
2153 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2154 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2155 },
2156 },
2157};
2158
2159/*
2160 * 'timer' class
2161 *
2162 * This class contains several variants: ['timer_1ms', 'timer_secure',
2163 * 'timer']
2164 */
2165
2166static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2167 .rev_offs = 0x0000,
2168 .sysc_offs = 0x0010,
2169 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2170 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2171 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2172 SIDLE_SMART_WKUP),
2173 .sysc_fields = &omap_hwmod_sysc_type2,
2174};
2175
2176static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2177 .name = "timer",
2178 .sysc = &dra7xx_timer_1ms_sysc,
2179};
2180
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2181static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2182 .rev_offs = 0x0000,
2183 .sysc_offs = 0x0010,
2184 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2185 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2186 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2187 SIDLE_SMART_WKUP),
2188 .sysc_fields = &omap_hwmod_sysc_type2,
2189};
2190
2191static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2192 .name = "timer",
2193 .sysc = &dra7xx_timer_sysc,
2194};
2195
2196/* timer1 */
2197static struct omap_hwmod dra7xx_timer1_hwmod = {
2198 .name = "timer1",
2199 .class = &dra7xx_timer_1ms_hwmod_class,
2200 .clkdm_name = "wkupaon_clkdm",
2201 .main_clk = "timer1_gfclk_mux",
2202 .prcm = {
2203 .omap4 = {
2204 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2205 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2206 .modulemode = MODULEMODE_SWCTRL,
2207 },
2208 },
2209};
2210
2211/* timer2 */
2212static struct omap_hwmod dra7xx_timer2_hwmod = {
2213 .name = "timer2",
2214 .class = &dra7xx_timer_1ms_hwmod_class,
2215 .clkdm_name = "l4per_clkdm",
2216 .main_clk = "timer2_gfclk_mux",
2217 .prcm = {
2218 .omap4 = {
2219 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2220 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2221 .modulemode = MODULEMODE_SWCTRL,
2222 },
2223 },
2224};
2225
2226/* timer3 */
2227static struct omap_hwmod dra7xx_timer3_hwmod = {
2228 .name = "timer3",
2229 .class = &dra7xx_timer_hwmod_class,
2230 .clkdm_name = "l4per_clkdm",
2231 .main_clk = "timer3_gfclk_mux",
2232 .prcm = {
2233 .omap4 = {
2234 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2235 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2236 .modulemode = MODULEMODE_SWCTRL,
2237 },
2238 },
2239};
2240
2241/* timer4 */
2242static struct omap_hwmod dra7xx_timer4_hwmod = {
2243 .name = "timer4",
Suman Annaedec1782015-03-16 15:54:54 -0500[diff] [blame]2244 .class = &dra7xx_timer_hwmod_class,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2245 .clkdm_name = "l4per_clkdm",
2246 .main_clk = "timer4_gfclk_mux",
2247 .prcm = {
2248 .omap4 = {
2249 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2250 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2251 .modulemode = MODULEMODE_SWCTRL,
2252 },
2253 },
2254};
2255
2256/* timer5 */
2257static struct omap_hwmod dra7xx_timer5_hwmod = {
2258 .name = "timer5",
2259 .class = &dra7xx_timer_hwmod_class,
2260 .clkdm_name = "ipu_clkdm",
2261 .main_clk = "timer5_gfclk_mux",
2262 .prcm = {
2263 .omap4 = {
2264 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2265 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2266 .modulemode = MODULEMODE_SWCTRL,
2267 },
2268 },
2269};
2270
2271/* timer6 */
2272static struct omap_hwmod dra7xx_timer6_hwmod = {
2273 .name = "timer6",
2274 .class = &dra7xx_timer_hwmod_class,
2275 .clkdm_name = "ipu_clkdm",
2276 .main_clk = "timer6_gfclk_mux",
2277 .prcm = {
2278 .omap4 = {
2279 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2280 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2281 .modulemode = MODULEMODE_SWCTRL,
2282 },
2283 },
2284};
2285
2286/* timer7 */
2287static struct omap_hwmod dra7xx_timer7_hwmod = {
2288 .name = "timer7",
2289 .class = &dra7xx_timer_hwmod_class,
2290 .clkdm_name = "ipu_clkdm",
2291 .main_clk = "timer7_gfclk_mux",
2292 .prcm = {
2293 .omap4 = {
2294 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2295 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2296 .modulemode = MODULEMODE_SWCTRL,
2297 },
2298 },
2299};
2300
2301/* timer8 */
2302static struct omap_hwmod dra7xx_timer8_hwmod = {
2303 .name = "timer8",
2304 .class = &dra7xx_timer_hwmod_class,
2305 .clkdm_name = "ipu_clkdm",
2306 .main_clk = "timer8_gfclk_mux",
2307 .prcm = {
2308 .omap4 = {
2309 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2310 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2311 .modulemode = MODULEMODE_SWCTRL,
2312 },
2313 },
2314};
2315
2316/* timer9 */
2317static struct omap_hwmod dra7xx_timer9_hwmod = {
2318 .name = "timer9",
2319 .class = &dra7xx_timer_hwmod_class,
2320 .clkdm_name = "l4per_clkdm",
2321 .main_clk = "timer9_gfclk_mux",
2322 .prcm = {
2323 .omap4 = {
2324 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2325 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2326 .modulemode = MODULEMODE_SWCTRL,
2327 },
2328 },
2329};
2330
2331/* timer10 */
2332static struct omap_hwmod dra7xx_timer10_hwmod = {
2333 .name = "timer10",
2334 .class = &dra7xx_timer_1ms_hwmod_class,
2335 .clkdm_name = "l4per_clkdm",
2336 .main_clk = "timer10_gfclk_mux",
2337 .prcm = {
2338 .omap4 = {
2339 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2340 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2341 .modulemode = MODULEMODE_SWCTRL,
2342 },
2343 },
2344};
2345
2346/* timer11 */
2347static struct omap_hwmod dra7xx_timer11_hwmod = {
2348 .name = "timer11",
2349 .class = &dra7xx_timer_hwmod_class,
2350 .clkdm_name = "l4per_clkdm",
2351 .main_clk = "timer11_gfclk_mux",
2352 .prcm = {
2353 .omap4 = {
2354 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2355 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2356 .modulemode = MODULEMODE_SWCTRL,
2357 },
2358 },
2359};
2360
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]2361/* timer12 */
2362static struct omap_hwmod dra7xx_timer12_hwmod = {
2363 .name = "timer12",
2364 .class = &dra7xx_timer_hwmod_class,
2365 .clkdm_name = "wkupaon_clkdm",
2366 .main_clk = "secure_32k_clk_src_ck",
2367 .prcm = {
2368 .omap4 = {
2369 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2370 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2371 },
2372 },
2373};
2374
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]2375/* timer13 */
2376static struct omap_hwmod dra7xx_timer13_hwmod = {
2377 .name = "timer13",
2378 .class = &dra7xx_timer_hwmod_class,
2379 .clkdm_name = "l4per3_clkdm",
2380 .main_clk = "timer13_gfclk_mux",
2381 .prcm = {
2382 .omap4 = {
2383 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2384 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2385 .modulemode = MODULEMODE_SWCTRL,
2386 },
2387 },
2388};
2389
2390/* timer14 */
2391static struct omap_hwmod dra7xx_timer14_hwmod = {
2392 .name = "timer14",
2393 .class = &dra7xx_timer_hwmod_class,
2394 .clkdm_name = "l4per3_clkdm",
2395 .main_clk = "timer14_gfclk_mux",
2396 .prcm = {
2397 .omap4 = {
2398 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2399 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2400 .modulemode = MODULEMODE_SWCTRL,
2401 },
2402 },
2403};
2404
2405/* timer15 */
2406static struct omap_hwmod dra7xx_timer15_hwmod = {
2407 .name = "timer15",
2408 .class = &dra7xx_timer_hwmod_class,
2409 .clkdm_name = "l4per3_clkdm",
2410 .main_clk = "timer15_gfclk_mux",
2411 .prcm = {
2412 .omap4 = {
2413 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2414 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2415 .modulemode = MODULEMODE_SWCTRL,
2416 },
2417 },
2418};
2419
2420/* timer16 */
2421static struct omap_hwmod dra7xx_timer16_hwmod = {
2422 .name = "timer16",
2423 .class = &dra7xx_timer_hwmod_class,
2424 .clkdm_name = "l4per3_clkdm",
2425 .main_clk = "timer16_gfclk_mux",
2426 .prcm = {
2427 .omap4 = {
2428 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2429 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2430 .modulemode = MODULEMODE_SWCTRL,
2431 },
2432 },
2433};
2434
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2435/*
2436 * 'uart' class
2437 *
2438 */
2439
2440static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2441 .rev_offs = 0x0050,
2442 .sysc_offs = 0x0054,
2443 .syss_offs = 0x0058,
2444 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2445 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2446 SYSS_HAS_RESET_STATUS),
2447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2448 SIDLE_SMART_WKUP),
2449 .sysc_fields = &omap_hwmod_sysc_type1,
2450};
2451
2452static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2453 .name = "uart",
2454 .sysc = &dra7xx_uart_sysc,
2455};
2456
2457/* uart1 */
2458static struct omap_hwmod dra7xx_uart1_hwmod = {
2459 .name = "uart1",
2460 .class = &dra7xx_uart_hwmod_class,
2461 .clkdm_name = "l4per_clkdm",
2462 .main_clk = "uart1_gfclk_mux",
Rajendra Nayak38958c12013-12-12 15:22:49 +0530[diff] [blame]2463 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2464 .prcm = {
2465 .omap4 = {
2466 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2467 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2468 .modulemode = MODULEMODE_SWCTRL,
2469 },
2470 },
2471};
2472
2473/* uart2 */
2474static struct omap_hwmod dra7xx_uart2_hwmod = {
2475 .name = "uart2",
2476 .class = &dra7xx_uart_hwmod_class,
2477 .clkdm_name = "l4per_clkdm",
2478 .main_clk = "uart2_gfclk_mux",
2479 .flags = HWMOD_SWSUP_SIDLE_ACT,
2480 .prcm = {
2481 .omap4 = {
2482 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2483 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2484 .modulemode = MODULEMODE_SWCTRL,
2485 },
2486 },
2487};
2488
2489/* uart3 */
2490static struct omap_hwmod dra7xx_uart3_hwmod = {
2491 .name = "uart3",
2492 .class = &dra7xx_uart_hwmod_class,
2493 .clkdm_name = "l4per_clkdm",
2494 .main_clk = "uart3_gfclk_mux",
Lokesh Vutla1c7e36b2015-01-08 17:22:04 +0530[diff] [blame]2495 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2496 .prcm = {
2497 .omap4 = {
2498 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2499 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2500 .modulemode = MODULEMODE_SWCTRL,
2501 },
2502 },
2503};
2504
2505/* uart4 */
2506static struct omap_hwmod dra7xx_uart4_hwmod = {
2507 .name = "uart4",
2508 .class = &dra7xx_uart_hwmod_class,
2509 .clkdm_name = "l4per_clkdm",
2510 .main_clk = "uart4_gfclk_mux",
J.D. Schroederb0340852015-10-22 19:24:16 -0500[diff] [blame]2511 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2512 .prcm = {
2513 .omap4 = {
2514 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2515 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2516 .modulemode = MODULEMODE_SWCTRL,
2517 },
2518 },
2519};
2520
2521/* uart5 */
2522static struct omap_hwmod dra7xx_uart5_hwmod = {
2523 .name = "uart5",
2524 .class = &dra7xx_uart_hwmod_class,
2525 .clkdm_name = "l4per_clkdm",
2526 .main_clk = "uart5_gfclk_mux",
2527 .flags = HWMOD_SWSUP_SIDLE_ACT,
2528 .prcm = {
2529 .omap4 = {
2530 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2531 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2532 .modulemode = MODULEMODE_SWCTRL,
2533 },
2534 },
2535};
2536
2537/* uart6 */
2538static struct omap_hwmod dra7xx_uart6_hwmod = {
2539 .name = "uart6",
2540 .class = &dra7xx_uart_hwmod_class,
2541 .clkdm_name = "ipu_clkdm",
2542 .main_clk = "uart6_gfclk_mux",
2543 .flags = HWMOD_SWSUP_SIDLE_ACT,
2544 .prcm = {
2545 .omap4 = {
2546 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2547 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2548 .modulemode = MODULEMODE_SWCTRL,
2549 },
2550 },
2551};
2552
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]2553/* uart7 */
2554static struct omap_hwmod dra7xx_uart7_hwmod = {
2555 .name = "uart7",
2556 .class = &dra7xx_uart_hwmod_class,
2557 .clkdm_name = "l4per2_clkdm",
2558 .main_clk = "uart7_gfclk_mux",
2559 .flags = HWMOD_SWSUP_SIDLE_ACT,
2560 .prcm = {
2561 .omap4 = {
2562 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2563 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2564 .modulemode = MODULEMODE_SWCTRL,
2565 },
2566 },
2567};
2568
2569/* uart8 */
2570static struct omap_hwmod dra7xx_uart8_hwmod = {
2571 .name = "uart8",
2572 .class = &dra7xx_uart_hwmod_class,
2573 .clkdm_name = "l4per2_clkdm",
2574 .main_clk = "uart8_gfclk_mux",
2575 .flags = HWMOD_SWSUP_SIDLE_ACT,
2576 .prcm = {
2577 .omap4 = {
2578 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2579 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2580 .modulemode = MODULEMODE_SWCTRL,
2581 },
2582 },
2583};
2584
2585/* uart9 */
2586static struct omap_hwmod dra7xx_uart9_hwmod = {
2587 .name = "uart9",
2588 .class = &dra7xx_uart_hwmod_class,
2589 .clkdm_name = "l4per2_clkdm",
2590 .main_clk = "uart9_gfclk_mux",
2591 .flags = HWMOD_SWSUP_SIDLE_ACT,
2592 .prcm = {
2593 .omap4 = {
2594 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2595 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2596 .modulemode = MODULEMODE_SWCTRL,
2597 },
2598 },
2599};
2600
2601/* uart10 */
2602static struct omap_hwmod dra7xx_uart10_hwmod = {
2603 .name = "uart10",
2604 .class = &dra7xx_uart_hwmod_class,
2605 .clkdm_name = "wkupaon_clkdm",
2606 .main_clk = "uart10_gfclk_mux",
2607 .flags = HWMOD_SWSUP_SIDLE_ACT,
2608 .prcm = {
2609 .omap4 = {
2610 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2611 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2612 .modulemode = MODULEMODE_SWCTRL,
2613 },
2614 },
2615};
2616
Joel Fernandesc3118642016-10-18 10:55:21 +0300[diff] [blame]2617/* DES (the 'P' (public) device) */
2618static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2619 .rev_offs = 0x0030,
2620 .sysc_offs = 0x0034,
2621 .syss_offs = 0x0038,
2622 .sysc_flags = SYSS_HAS_RESET_STATUS,
2623};
2624
2625static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2626 .name = "des",
2627 .sysc = &dra7xx_des_sysc,
2628};
2629
2630/* DES */
2631static struct omap_hwmod dra7xx_des_hwmod = {
2632 .name = "des",
2633 .class = &dra7xx_des_hwmod_class,
2634 .clkdm_name = "l4sec_clkdm",
2635 .main_clk = "l3_iclk_div",
2636 .prcm = {
2637 .omap4 = {
2638 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2639 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2640 .modulemode = MODULEMODE_HWCTRL,
2641 },
2642 },
2643};
2644
Joel Fernandes7a825cc2016-10-18 10:55:24 +0300[diff] [blame]2645/* rng */
2646static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2647 .rev_offs = 0x1fe0,
2648 .sysc_offs = 0x1fe4,
2649 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2650 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2651 .sysc_fields = &omap_hwmod_sysc_type1,
2652};
2653
2654static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2655 .name = "rng",
2656 .sysc = &dra7xx_rng_sysc,
2657};
2658
2659static struct omap_hwmod dra7xx_rng_hwmod = {
2660 .name = "rng",
2661 .class = &dra7xx_rng_hwmod_class,
2662 .flags = HWMOD_SWSUP_SIDLE,
2663 .clkdm_name = "l4sec_clkdm",
2664 .prcm = {
2665 .omap4 = {
2666 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2667 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2668 .modulemode = MODULEMODE_HWCTRL,
2669 },
2670 },
2671};
2672
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2673/*
2674 * 'usb_otg_ss' class
2675 *
2676 */
2677
Roger Quadrosd904b382014-07-06 15:51:24 -0600[diff] [blame]2678static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2679 .rev_offs = 0x0000,
2680 .sysc_offs = 0x0010,
2681 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2682 SYSC_HAS_SIDLEMODE),
2683 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2684 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2685 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2686 .sysc_fields = &omap_hwmod_sysc_type2,
2687};
2688
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2689static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2690 .name = "usb_otg_ss",
Roger Quadrosd904b382014-07-06 15:51:24 -0600[diff] [blame]2691 .sysc = &dra7xx_usb_otg_ss_sysc,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2692};
2693
2694/* usb_otg_ss1 */
2695static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2696 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2697};
2698
2699static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2700 .name = "usb_otg_ss1",
2701 .class = &dra7xx_usb_otg_ss_hwmod_class,
2702 .clkdm_name = "l3init_clkdm",
2703 .main_clk = "dpll_core_h13x2_ck",
Roger Quadrose2d54fe2017-03-13 13:53:16 +0200[diff] [blame^]2704 .flags = HWMOD_CLKDM_NOAUTO,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2705 .prcm = {
2706 .omap4 = {
2707 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2708 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2709 .modulemode = MODULEMODE_HWCTRL,
2710 },
2711 },
2712 .opt_clks = usb_otg_ss1_opt_clks,
2713 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2714};
2715
2716/* usb_otg_ss2 */
2717static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2718 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2719};
2720
2721static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2722 .name = "usb_otg_ss2",
2723 .class = &dra7xx_usb_otg_ss_hwmod_class,
2724 .clkdm_name = "l3init_clkdm",
2725 .main_clk = "dpll_core_h13x2_ck",
Roger Quadrose2d54fe2017-03-13 13:53:16 +0200[diff] [blame^]2726 .flags = HWMOD_CLKDM_NOAUTO,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2727 .prcm = {
2728 .omap4 = {
2729 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2730 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2731 .modulemode = MODULEMODE_HWCTRL,
2732 },
2733 },
2734 .opt_clks = usb_otg_ss2_opt_clks,
2735 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2736};
2737
2738/* usb_otg_ss3 */
2739static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2740 .name = "usb_otg_ss3",
2741 .class = &dra7xx_usb_otg_ss_hwmod_class,
2742 .clkdm_name = "l3init_clkdm",
2743 .main_clk = "dpll_core_h13x2_ck",
2744 .prcm = {
2745 .omap4 = {
2746 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2747 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2748 .modulemode = MODULEMODE_HWCTRL,
2749 },
2750 },
2751};
2752
2753/* usb_otg_ss4 */
2754static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2755 .name = "usb_otg_ss4",
2756 .class = &dra7xx_usb_otg_ss_hwmod_class,
2757 .clkdm_name = "l3init_clkdm",
2758 .main_clk = "dpll_core_h13x2_ck",
2759 .prcm = {
2760 .omap4 = {
2761 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2762 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2763 .modulemode = MODULEMODE_HWCTRL,
2764 },
2765 },
2766};
2767
2768/*
2769 * 'vcp' class
2770 *
2771 */
2772
2773static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2774 .name = "vcp",
2775};
2776
2777/* vcp1 */
2778static struct omap_hwmod dra7xx_vcp1_hwmod = {
2779 .name = "vcp1",
2780 .class = &dra7xx_vcp_hwmod_class,
2781 .clkdm_name = "l3main1_clkdm",
2782 .main_clk = "l3_iclk_div",
2783 .prcm = {
2784 .omap4 = {
2785 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2786 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2787 },
2788 },
2789};
2790
2791/* vcp2 */
2792static struct omap_hwmod dra7xx_vcp2_hwmod = {
2793 .name = "vcp2",
2794 .class = &dra7xx_vcp_hwmod_class,
2795 .clkdm_name = "l3main1_clkdm",
2796 .main_clk = "l3_iclk_div",
2797 .prcm = {
2798 .omap4 = {
2799 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2800 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2801 },
2802 },
2803};
2804
2805/*
2806 * 'wd_timer' class
2807 *
2808 */
2809
2810static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2811 .rev_offs = 0x0000,
2812 .sysc_offs = 0x0010,
2813 .syss_offs = 0x0014,
2814 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2815 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2816 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2817 SIDLE_SMART_WKUP),
2818 .sysc_fields = &omap_hwmod_sysc_type1,
2819};
2820
2821static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2822 .name = "wd_timer",
2823 .sysc = &dra7xx_wd_timer_sysc,
2824 .pre_shutdown = &omap2_wd_timer_disable,
2825 .reset = &omap2_wd_timer_reset,
2826};
2827
2828/* wd_timer2 */
2829static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2830 .name = "wd_timer2",
2831 .class = &dra7xx_wd_timer_hwmod_class,
2832 .clkdm_name = "wkupaon_clkdm",
2833 .main_clk = "sys_32k_ck",
2834 .prcm = {
2835 .omap4 = {
2836 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2837 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2838 .modulemode = MODULEMODE_SWCTRL,
2839 },
2840 },
2841};
2842
2843
2844/*
2845 * Interfaces
2846 */
2847
Tomi Valkeinen42121682014-09-15 13:12:18 -0500[diff] [blame]2848/* l3_main_1 -> dmm */
2849static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2850 .master = &dra7xx_l3_main_1_hwmod,
2851 .slave = &dra7xx_dmm_hwmod,
2852 .clk = "l3_iclk_div",
2853 .user = OCP_USER_SDMA,
2854};
2855
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2856/* l3_main_2 -> l3_instr */
2857static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2858 .master = &dra7xx_l3_main_2_hwmod,
2859 .slave = &dra7xx_l3_instr_hwmod,
2860 .clk = "l3_iclk_div",
2861 .user = OCP_USER_MPU | OCP_USER_SDMA,
2862};
2863
2864/* l4_cfg -> l3_main_1 */
2865static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2866 .master = &dra7xx_l4_cfg_hwmod,
2867 .slave = &dra7xx_l3_main_1_hwmod,
2868 .clk = "l3_iclk_div",
2869 .user = OCP_USER_MPU | OCP_USER_SDMA,
2870};
2871
2872/* mpu -> l3_main_1 */
2873static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2874 .master = &dra7xx_mpu_hwmod,
2875 .slave = &dra7xx_l3_main_1_hwmod,
2876 .clk = "l3_iclk_div",
2877 .user = OCP_USER_MPU,
2878};
2879
2880/* l3_main_1 -> l3_main_2 */
2881static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2882 .master = &dra7xx_l3_main_1_hwmod,
2883 .slave = &dra7xx_l3_main_2_hwmod,
2884 .clk = "l3_iclk_div",
2885 .user = OCP_USER_MPU,
2886};
2887
2888/* l4_cfg -> l3_main_2 */
2889static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2890 .master = &dra7xx_l4_cfg_hwmod,
2891 .slave = &dra7xx_l3_main_2_hwmod,
2892 .clk = "l3_iclk_div",
2893 .user = OCP_USER_MPU | OCP_USER_SDMA,
2894};
2895
2896/* l3_main_1 -> l4_cfg */
2897static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2898 .master = &dra7xx_l3_main_1_hwmod,
2899 .slave = &dra7xx_l4_cfg_hwmod,
2900 .clk = "l3_iclk_div",
2901 .user = OCP_USER_MPU | OCP_USER_SDMA,
2902};
2903
2904/* l3_main_1 -> l4_per1 */
2905static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2906 .master = &dra7xx_l3_main_1_hwmod,
2907 .slave = &dra7xx_l4_per1_hwmod,
2908 .clk = "l3_iclk_div",
2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2910};
2911
2912/* l3_main_1 -> l4_per2 */
2913static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2914 .master = &dra7xx_l3_main_1_hwmod,
2915 .slave = &dra7xx_l4_per2_hwmod,
2916 .clk = "l3_iclk_div",
2917 .user = OCP_USER_MPU | OCP_USER_SDMA,
2918};
2919
2920/* l3_main_1 -> l4_per3 */
2921static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2922 .master = &dra7xx_l3_main_1_hwmod,
2923 .slave = &dra7xx_l4_per3_hwmod,
2924 .clk = "l3_iclk_div",
2925 .user = OCP_USER_MPU | OCP_USER_SDMA,
2926};
2927
2928/* l3_main_1 -> l4_wkup */
2929static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2930 .master = &dra7xx_l3_main_1_hwmod,
2931 .slave = &dra7xx_l4_wkup_hwmod,
2932 .clk = "wkupaon_iclk_mux",
2933 .user = OCP_USER_MPU | OCP_USER_SDMA,
2934};
2935
2936/* l4_per2 -> atl */
2937static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2938 .master = &dra7xx_l4_per2_hwmod,
2939 .slave = &dra7xx_atl_hwmod,
2940 .clk = "l3_iclk_div",
2941 .user = OCP_USER_MPU | OCP_USER_SDMA,
2942};
2943
2944/* l3_main_1 -> bb2d */
2945static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2946 .master = &dra7xx_l3_main_1_hwmod,
2947 .slave = &dra7xx_bb2d_hwmod,
2948 .clk = "l3_iclk_div",
2949 .user = OCP_USER_MPU | OCP_USER_SDMA,
2950};
2951
2952/* l4_wkup -> counter_32k */
2953static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2954 .master = &dra7xx_l4_wkup_hwmod,
2955 .slave = &dra7xx_counter_32k_hwmod,
2956 .clk = "wkupaon_iclk_mux",
2957 .user = OCP_USER_MPU | OCP_USER_SDMA,
2958};
2959
2960/* l4_wkup -> ctrl_module_wkup */
2961static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2962 .master = &dra7xx_l4_wkup_hwmod,
2963 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2964 .clk = "wkupaon_iclk_mux",
2965 .user = OCP_USER_MPU | OCP_USER_SDMA,
2966};
2967
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]2968static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2969 .master = &dra7xx_l4_per2_hwmod,
2970 .slave = &dra7xx_gmac_hwmod,
2971 .clk = "dpll_gmac_ck",
2972 .user = OCP_USER_MPU,
2973};
2974
2975static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2976 .master = &dra7xx_gmac_hwmod,
2977 .slave = &dra7xx_mdio_hwmod,
2978 .user = OCP_USER_MPU,
2979};
2980
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2981/* l4_wkup -> dcan1 */
2982static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2983 .master = &dra7xx_l4_wkup_hwmod,
2984 .slave = &dra7xx_dcan1_hwmod,
2985 .clk = "wkupaon_iclk_mux",
2986 .user = OCP_USER_MPU | OCP_USER_SDMA,
2987};
2988
2989/* l4_per2 -> dcan2 */
2990static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2991 .master = &dra7xx_l4_per2_hwmod,
2992 .slave = &dra7xx_dcan2_hwmod,
2993 .clk = "l3_iclk_div",
2994 .user = OCP_USER_MPU | OCP_USER_SDMA,
2995};
2996
2997static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2998 {
2999 .pa_start = 0x4a056000,
3000 .pa_end = 0x4a056fff,
3001 .flags = ADDR_TYPE_RT
3002 },
3003 { }
3004};
3005
3006/* l4_cfg -> dma_system */
3007static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3008 .master = &dra7xx_l4_cfg_hwmod,
3009 .slave = &dra7xx_dma_system_hwmod,
3010 .clk = "l3_iclk_div",
3011 .addr = dra7xx_dma_system_addrs,
3012 .user = OCP_USER_MPU | OCP_USER_SDMA,
3013};
3014
Peter Ujfalusi34b41822016-02-25 16:50:18 +0200[diff] [blame]3015/* l3_main_1 -> tpcc */
3016static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
3017 .master = &dra7xx_l3_main_1_hwmod,
3018 .slave = &dra7xx_tpcc_hwmod,
3019 .clk = "l3_iclk_div",
3020 .user = OCP_USER_MPU,
3021};
3022
3023/* l3_main_1 -> tptc0 */
3024static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
3025 .master = &dra7xx_l3_main_1_hwmod,
3026 .slave = &dra7xx_tptc0_hwmod,
3027 .clk = "l3_iclk_div",
3028 .user = OCP_USER_MPU,
3029};
3030
3031/* l3_main_1 -> tptc1 */
3032static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
3033 .master = &dra7xx_l3_main_1_hwmod,
3034 .slave = &dra7xx_tptc1_hwmod,
3035 .clk = "l3_iclk_div",
3036 .user = OCP_USER_MPU,
3037};
3038
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3039/* l3_main_1 -> dss */
3040static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3041 .master = &dra7xx_l3_main_1_hwmod,
3042 .slave = &dra7xx_dss_hwmod,
3043 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3044 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045};
3046
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3047/* l3_main_1 -> dispc */
3048static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3049 .master = &dra7xx_l3_main_1_hwmod,
3050 .slave = &dra7xx_dss_dispc_hwmod,
3051 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3052 .user = OCP_USER_MPU | OCP_USER_SDMA,
3053};
3054
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3055/* l3_main_1 -> dispc */
3056static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3057 .master = &dra7xx_l3_main_1_hwmod,
3058 .slave = &dra7xx_dss_hdmi_hwmod,
3059 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3060 .user = OCP_USER_MPU | OCP_USER_SDMA,
3061};
3062
Joel Fernandes628d7582016-10-18 10:55:22 +0300[diff] [blame]3063/* l3_main_1 -> aes1 */
3064static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3065 .master = &dra7xx_l3_main_1_hwmod,
3066 .slave = &dra7xx_aes1_hwmod,
3067 .clk = "l3_iclk_div",
3068 .user = OCP_USER_MPU | OCP_USER_SDMA,
3069};
3070
3071/* l3_main_1 -> aes2 */
3072static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3073 .master = &dra7xx_l3_main_1_hwmod,
3074 .slave = &dra7xx_aes2_hwmod,
3075 .clk = "l3_iclk_div",
3076 .user = OCP_USER_MPU | OCP_USER_SDMA,
3077};
3078
Lokesh Vutla7e45f172016-10-18 10:55:23 +0300[diff] [blame]3079/* l3_main_1 -> sha0 */
3080static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3081 .master = &dra7xx_l3_main_1_hwmod,
3082 .slave = &dra7xx_sha0_hwmod,
3083 .clk = "l3_iclk_div",
3084 .user = OCP_USER_MPU | OCP_USER_SDMA,
3085};
3086
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]3087/* l4_per2 -> mcasp1 */
3088static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3089 .master = &dra7xx_l4_per2_hwmod,
3090 .slave = &dra7xx_mcasp1_hwmod,
3091 .clk = "l4_root_clk_div",
3092 .user = OCP_USER_MPU | OCP_USER_SDMA,
3093};
3094
3095/* l3_main_1 -> mcasp1 */
3096static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3097 .master = &dra7xx_l3_main_1_hwmod,
3098 .slave = &dra7xx_mcasp1_hwmod,
3099 .clk = "l3_iclk_div",
3100 .user = OCP_USER_MPU | OCP_USER_SDMA,
3101};
3102
3103/* l4_per2 -> mcasp2 */
3104static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3105 .master = &dra7xx_l4_per2_hwmod,
3106 .slave = &dra7xx_mcasp2_hwmod,
3107 .clk = "l4_root_clk_div",
3108 .user = OCP_USER_MPU | OCP_USER_SDMA,
3109};
3110
3111/* l3_main_1 -> mcasp2 */
3112static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3113 .master = &dra7xx_l3_main_1_hwmod,
3114 .slave = &dra7xx_mcasp2_hwmod,
3115 .clk = "l3_iclk_div",
3116 .user = OCP_USER_MPU | OCP_USER_SDMA,
3117};
3118
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]3119/* l4_per2 -> mcasp3 */
3120static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3121 .master = &dra7xx_l4_per2_hwmod,
3122 .slave = &dra7xx_mcasp3_hwmod,
3123 .clk = "l4_root_clk_div",
3124 .user = OCP_USER_MPU | OCP_USER_SDMA,
3125};
3126
3127/* l3_main_1 -> mcasp3 */
3128static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3129 .master = &dra7xx_l3_main_1_hwmod,
3130 .slave = &dra7xx_mcasp3_hwmod,
3131 .clk = "l3_iclk_div",
3132 .user = OCP_USER_MPU | OCP_USER_SDMA,
3133};
3134
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]3135/* l4_per2 -> mcasp4 */
3136static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3137 .master = &dra7xx_l4_per2_hwmod,
3138 .slave = &dra7xx_mcasp4_hwmod,
3139 .clk = "l4_root_clk_div",
3140 .user = OCP_USER_MPU | OCP_USER_SDMA,
3141};
3142
3143/* l4_per2 -> mcasp5 */
3144static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3145 .master = &dra7xx_l4_per2_hwmod,
3146 .slave = &dra7xx_mcasp5_hwmod,
3147 .clk = "l4_root_clk_div",
3148 .user = OCP_USER_MPU | OCP_USER_SDMA,
3149};
3150
3151/* l4_per2 -> mcasp6 */
3152static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3153 .master = &dra7xx_l4_per2_hwmod,
3154 .slave = &dra7xx_mcasp6_hwmod,
3155 .clk = "l4_root_clk_div",
3156 .user = OCP_USER_MPU | OCP_USER_SDMA,
3157};
3158
3159/* l4_per2 -> mcasp7 */
3160static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3161 .master = &dra7xx_l4_per2_hwmod,
3162 .slave = &dra7xx_mcasp7_hwmod,
3163 .clk = "l4_root_clk_div",
3164 .user = OCP_USER_MPU | OCP_USER_SDMA,
3165};
3166
3167/* l4_per2 -> mcasp8 */
3168static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3169 .master = &dra7xx_l4_per2_hwmod,
3170 .slave = &dra7xx_mcasp8_hwmod,
3171 .clk = "l4_root_clk_div",
3172 .user = OCP_USER_MPU | OCP_USER_SDMA,
3173};
3174
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3175/* l4_per1 -> elm */
3176static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3177 .master = &dra7xx_l4_per1_hwmod,
3178 .slave = &dra7xx_elm_hwmod,
3179 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3180 .user = OCP_USER_MPU | OCP_USER_SDMA,
3181};
3182
3183/* l4_wkup -> gpio1 */
3184static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3185 .master = &dra7xx_l4_wkup_hwmod,
3186 .slave = &dra7xx_gpio1_hwmod,
3187 .clk = "wkupaon_iclk_mux",
3188 .user = OCP_USER_MPU | OCP_USER_SDMA,
3189};
3190
3191/* l4_per1 -> gpio2 */
3192static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3193 .master = &dra7xx_l4_per1_hwmod,
3194 .slave = &dra7xx_gpio2_hwmod,
3195 .clk = "l3_iclk_div",
3196 .user = OCP_USER_MPU | OCP_USER_SDMA,
3197};
3198
3199/* l4_per1 -> gpio3 */
3200static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3201 .master = &dra7xx_l4_per1_hwmod,
3202 .slave = &dra7xx_gpio3_hwmod,
3203 .clk = "l3_iclk_div",
3204 .user = OCP_USER_MPU | OCP_USER_SDMA,
3205};
3206
3207/* l4_per1 -> gpio4 */
3208static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3209 .master = &dra7xx_l4_per1_hwmod,
3210 .slave = &dra7xx_gpio4_hwmod,
3211 .clk = "l3_iclk_div",
3212 .user = OCP_USER_MPU | OCP_USER_SDMA,
3213};
3214
3215/* l4_per1 -> gpio5 */
3216static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3217 .master = &dra7xx_l4_per1_hwmod,
3218 .slave = &dra7xx_gpio5_hwmod,
3219 .clk = "l3_iclk_div",
3220 .user = OCP_USER_MPU | OCP_USER_SDMA,
3221};
3222
3223/* l4_per1 -> gpio6 */
3224static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3225 .master = &dra7xx_l4_per1_hwmod,
3226 .slave = &dra7xx_gpio6_hwmod,
3227 .clk = "l3_iclk_div",
3228 .user = OCP_USER_MPU | OCP_USER_SDMA,
3229};
3230
3231/* l4_per1 -> gpio7 */
3232static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3233 .master = &dra7xx_l4_per1_hwmod,
3234 .slave = &dra7xx_gpio7_hwmod,
3235 .clk = "l3_iclk_div",
3236 .user = OCP_USER_MPU | OCP_USER_SDMA,
3237};
3238
3239/* l4_per1 -> gpio8 */
3240static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3241 .master = &dra7xx_l4_per1_hwmod,
3242 .slave = &dra7xx_gpio8_hwmod,
3243 .clk = "l3_iclk_div",
3244 .user = OCP_USER_MPU | OCP_USER_SDMA,
3245};
3246
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3247/* l3_main_1 -> gpmc */
3248static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3249 .master = &dra7xx_l3_main_1_hwmod,
3250 .slave = &dra7xx_gpmc_hwmod,
3251 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3252 .user = OCP_USER_MPU | OCP_USER_SDMA,
3253};
3254
3255static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3256 {
3257 .pa_start = 0x480b2000,
3258 .pa_end = 0x480b201f,
3259 .flags = ADDR_TYPE_RT
3260 },
3261 { }
3262};
3263
3264/* l4_per1 -> hdq1w */
3265static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3266 .master = &dra7xx_l4_per1_hwmod,
3267 .slave = &dra7xx_hdq1w_hwmod,
3268 .clk = "l3_iclk_div",
3269 .addr = dra7xx_hdq1w_addrs,
3270 .user = OCP_USER_MPU | OCP_USER_SDMA,
3271};
3272
3273/* l4_per1 -> i2c1 */
3274static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3275 .master = &dra7xx_l4_per1_hwmod,
3276 .slave = &dra7xx_i2c1_hwmod,
3277 .clk = "l3_iclk_div",
3278 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279};
3280
3281/* l4_per1 -> i2c2 */
3282static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3283 .master = &dra7xx_l4_per1_hwmod,
3284 .slave = &dra7xx_i2c2_hwmod,
3285 .clk = "l3_iclk_div",
3286 .user = OCP_USER_MPU | OCP_USER_SDMA,
3287};
3288
3289/* l4_per1 -> i2c3 */
3290static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3291 .master = &dra7xx_l4_per1_hwmod,
3292 .slave = &dra7xx_i2c3_hwmod,
3293 .clk = "l3_iclk_div",
3294 .user = OCP_USER_MPU | OCP_USER_SDMA,
3295};
3296
3297/* l4_per1 -> i2c4 */
3298static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3299 .master = &dra7xx_l4_per1_hwmod,
3300 .slave = &dra7xx_i2c4_hwmod,
3301 .clk = "l3_iclk_div",
3302 .user = OCP_USER_MPU | OCP_USER_SDMA,
3303};
3304
3305/* l4_per1 -> i2c5 */
3306static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3307 .master = &dra7xx_l4_per1_hwmod,
3308 .slave = &dra7xx_i2c5_hwmod,
3309 .clk = "l3_iclk_div",
3310 .user = OCP_USER_MPU | OCP_USER_SDMA,
3311};
3312
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]3313/* l4_cfg -> mailbox1 */
3314static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3315 .master = &dra7xx_l4_cfg_hwmod,
3316 .slave = &dra7xx_mailbox1_hwmod,
3317 .clk = "l3_iclk_div",
3318 .user = OCP_USER_MPU | OCP_USER_SDMA,
3319};
3320
3321/* l4_per3 -> mailbox2 */
3322static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3323 .master = &dra7xx_l4_per3_hwmod,
3324 .slave = &dra7xx_mailbox2_hwmod,
3325 .clk = "l3_iclk_div",
3326 .user = OCP_USER_MPU | OCP_USER_SDMA,
3327};
3328
3329/* l4_per3 -> mailbox3 */
3330static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3331 .master = &dra7xx_l4_per3_hwmod,
3332 .slave = &dra7xx_mailbox3_hwmod,
3333 .clk = "l3_iclk_div",
3334 .user = OCP_USER_MPU | OCP_USER_SDMA,
3335};
3336
3337/* l4_per3 -> mailbox4 */
3338static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3339 .master = &dra7xx_l4_per3_hwmod,
3340 .slave = &dra7xx_mailbox4_hwmod,
3341 .clk = "l3_iclk_div",
3342 .user = OCP_USER_MPU | OCP_USER_SDMA,
3343};
3344
3345/* l4_per3 -> mailbox5 */
3346static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3347 .master = &dra7xx_l4_per3_hwmod,
3348 .slave = &dra7xx_mailbox5_hwmod,
3349 .clk = "l3_iclk_div",
3350 .user = OCP_USER_MPU | OCP_USER_SDMA,
3351};
3352
3353/* l4_per3 -> mailbox6 */
3354static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3355 .master = &dra7xx_l4_per3_hwmod,
3356 .slave = &dra7xx_mailbox6_hwmod,
3357 .clk = "l3_iclk_div",
3358 .user = OCP_USER_MPU | OCP_USER_SDMA,
3359};
3360
3361/* l4_per3 -> mailbox7 */
3362static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3363 .master = &dra7xx_l4_per3_hwmod,
3364 .slave = &dra7xx_mailbox7_hwmod,
3365 .clk = "l3_iclk_div",
3366 .user = OCP_USER_MPU | OCP_USER_SDMA,
3367};
3368
3369/* l4_per3 -> mailbox8 */
3370static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3371 .master = &dra7xx_l4_per3_hwmod,
3372 .slave = &dra7xx_mailbox8_hwmod,
3373 .clk = "l3_iclk_div",
3374 .user = OCP_USER_MPU | OCP_USER_SDMA,
3375};
3376
3377/* l4_per3 -> mailbox9 */
3378static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3379 .master = &dra7xx_l4_per3_hwmod,
3380 .slave = &dra7xx_mailbox9_hwmod,
3381 .clk = "l3_iclk_div",
3382 .user = OCP_USER_MPU | OCP_USER_SDMA,
3383};
3384
3385/* l4_per3 -> mailbox10 */
3386static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3387 .master = &dra7xx_l4_per3_hwmod,
3388 .slave = &dra7xx_mailbox10_hwmod,
3389 .clk = "l3_iclk_div",
3390 .user = OCP_USER_MPU | OCP_USER_SDMA,
3391};
3392
3393/* l4_per3 -> mailbox11 */
3394static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3395 .master = &dra7xx_l4_per3_hwmod,
3396 .slave = &dra7xx_mailbox11_hwmod,
3397 .clk = "l3_iclk_div",
3398 .user = OCP_USER_MPU | OCP_USER_SDMA,
3399};
3400
3401/* l4_per3 -> mailbox12 */
3402static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3403 .master = &dra7xx_l4_per3_hwmod,
3404 .slave = &dra7xx_mailbox12_hwmod,
3405 .clk = "l3_iclk_div",
3406 .user = OCP_USER_MPU | OCP_USER_SDMA,
3407};
3408
3409/* l4_per3 -> mailbox13 */
3410static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3411 .master = &dra7xx_l4_per3_hwmod,
3412 .slave = &dra7xx_mailbox13_hwmod,
3413 .clk = "l3_iclk_div",
3414 .user = OCP_USER_MPU | OCP_USER_SDMA,
3415};
3416
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3417/* l4_per1 -> mcspi1 */
3418static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3419 .master = &dra7xx_l4_per1_hwmod,
3420 .slave = &dra7xx_mcspi1_hwmod,
3421 .clk = "l3_iclk_div",
3422 .user = OCP_USER_MPU | OCP_USER_SDMA,
3423};
3424
3425/* l4_per1 -> mcspi2 */
3426static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3427 .master = &dra7xx_l4_per1_hwmod,
3428 .slave = &dra7xx_mcspi2_hwmod,
3429 .clk = "l3_iclk_div",
3430 .user = OCP_USER_MPU | OCP_USER_SDMA,
3431};
3432
3433/* l4_per1 -> mcspi3 */
3434static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3435 .master = &dra7xx_l4_per1_hwmod,
3436 .slave = &dra7xx_mcspi3_hwmod,
3437 .clk = "l3_iclk_div",
3438 .user = OCP_USER_MPU | OCP_USER_SDMA,
3439};
3440
3441/* l4_per1 -> mcspi4 */
3442static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3443 .master = &dra7xx_l4_per1_hwmod,
3444 .slave = &dra7xx_mcspi4_hwmod,
3445 .clk = "l3_iclk_div",
3446 .user = OCP_USER_MPU | OCP_USER_SDMA,
3447};
3448
3449/* l4_per1 -> mmc1 */
3450static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3451 .master = &dra7xx_l4_per1_hwmod,
3452 .slave = &dra7xx_mmc1_hwmod,
3453 .clk = "l3_iclk_div",
3454 .user = OCP_USER_MPU | OCP_USER_SDMA,
3455};
3456
3457/* l4_per1 -> mmc2 */
3458static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3459 .master = &dra7xx_l4_per1_hwmod,
3460 .slave = &dra7xx_mmc2_hwmod,
3461 .clk = "l3_iclk_div",
3462 .user = OCP_USER_MPU | OCP_USER_SDMA,
3463};
3464
3465/* l4_per1 -> mmc3 */
3466static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3467 .master = &dra7xx_l4_per1_hwmod,
3468 .slave = &dra7xx_mmc3_hwmod,
3469 .clk = "l3_iclk_div",
3470 .user = OCP_USER_MPU | OCP_USER_SDMA,
3471};
3472
3473/* l4_per1 -> mmc4 */
3474static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3475 .master = &dra7xx_l4_per1_hwmod,
3476 .slave = &dra7xx_mmc4_hwmod,
3477 .clk = "l3_iclk_div",
3478 .user = OCP_USER_MPU | OCP_USER_SDMA,
3479};
3480
3481/* l4_cfg -> mpu */
3482static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3483 .master = &dra7xx_l4_cfg_hwmod,
3484 .slave = &dra7xx_mpu_hwmod,
3485 .clk = "l3_iclk_div",
3486 .user = OCP_USER_MPU | OCP_USER_SDMA,
3487};
3488
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3489/* l4_cfg -> ocp2scp1 */
3490static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3491 .master = &dra7xx_l4_cfg_hwmod,
3492 .slave = &dra7xx_ocp2scp1_hwmod,
3493 .clk = "l4_root_clk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3494 .user = OCP_USER_MPU | OCP_USER_SDMA,
3495};
3496
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]3497/* l4_cfg -> ocp2scp3 */
3498static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3499 .master = &dra7xx_l4_cfg_hwmod,
3500 .slave = &dra7xx_ocp2scp3_hwmod,
3501 .clk = "l4_root_clk_div",
3502 .user = OCP_USER_MPU | OCP_USER_SDMA,
3503};
3504
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3505/* l3_main_1 -> pciess1 */
3506static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3507 .master = &dra7xx_l3_main_1_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3508 .slave = &dra7xx_pciess1_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3509 .clk = "l3_iclk_div",
3510 .user = OCP_USER_MPU | OCP_USER_SDMA,
3511};
3512
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3513/* l4_cfg -> pciess1 */
3514static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3515 .master = &dra7xx_l4_cfg_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3516 .slave = &dra7xx_pciess1_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3517 .clk = "l4_root_clk_div",
3518 .user = OCP_USER_MPU | OCP_USER_SDMA,
3519};
3520
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3521/* l3_main_1 -> pciess2 */
3522static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3523 .master = &dra7xx_l3_main_1_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3524 .slave = &dra7xx_pciess2_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3525 .clk = "l3_iclk_div",
3526 .user = OCP_USER_MPU | OCP_USER_SDMA,
3527};
3528
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3529/* l4_cfg -> pciess2 */
3530static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3531 .master = &dra7xx_l4_cfg_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3532 .slave = &dra7xx_pciess2_hwmod,
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]3533 .clk = "l4_root_clk_div",
3534 .user = OCP_USER_MPU | OCP_USER_SDMA,
3535};
3536
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3537/* l3_main_1 -> qspi */
3538static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3539 .master = &dra7xx_l3_main_1_hwmod,
3540 .slave = &dra7xx_qspi_hwmod,
3541 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3542 .user = OCP_USER_MPU | OCP_USER_SDMA,
3543};
3544
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]3545/* l4_per3 -> rtcss */
3546static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3547 .master = &dra7xx_l4_per3_hwmod,
3548 .slave = &dra7xx_rtcss_hwmod,
3549 .clk = "l4_root_clk_div",
3550 .user = OCP_USER_MPU | OCP_USER_SDMA,
3551};
3552
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3553static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3554 {
3555 .name = "sysc",
3556 .pa_start = 0x4a141100,
3557 .pa_end = 0x4a141107,
3558 .flags = ADDR_TYPE_RT
3559 },
3560 { }
3561};
3562
3563/* l4_cfg -> sata */
3564static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3565 .master = &dra7xx_l4_cfg_hwmod,
3566 .slave = &dra7xx_sata_hwmod,
3567 .clk = "l3_iclk_div",
3568 .addr = dra7xx_sata_addrs,
3569 .user = OCP_USER_MPU | OCP_USER_SDMA,
3570};
3571
3572static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3573 {
3574 .pa_start = 0x4a0dd000,
3575 .pa_end = 0x4a0dd07f,
3576 .flags = ADDR_TYPE_RT
3577 },
3578 { }
3579};
3580
3581/* l4_cfg -> smartreflex_core */
3582static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3583 .master = &dra7xx_l4_cfg_hwmod,
3584 .slave = &dra7xx_smartreflex_core_hwmod,
3585 .clk = "l4_root_clk_div",
3586 .addr = dra7xx_smartreflex_core_addrs,
3587 .user = OCP_USER_MPU | OCP_USER_SDMA,
3588};
3589
3590static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3591 {
3592 .pa_start = 0x4a0d9000,
3593 .pa_end = 0x4a0d907f,
3594 .flags = ADDR_TYPE_RT
3595 },
3596 { }
3597};
3598
3599/* l4_cfg -> smartreflex_mpu */
3600static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3601 .master = &dra7xx_l4_cfg_hwmod,
3602 .slave = &dra7xx_smartreflex_mpu_hwmod,
3603 .clk = "l4_root_clk_div",
3604 .addr = dra7xx_smartreflex_mpu_addrs,
3605 .user = OCP_USER_MPU | OCP_USER_SDMA,
3606};
3607
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3608/* l4_cfg -> spinlock */
3609static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3610 .master = &dra7xx_l4_cfg_hwmod,
3611 .slave = &dra7xx_spinlock_hwmod,
3612 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3613 .user = OCP_USER_MPU | OCP_USER_SDMA,
3614};
3615
3616/* l4_wkup -> timer1 */
3617static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3618 .master = &dra7xx_l4_wkup_hwmod,
3619 .slave = &dra7xx_timer1_hwmod,
3620 .clk = "wkupaon_iclk_mux",
3621 .user = OCP_USER_MPU | OCP_USER_SDMA,
3622};
3623
3624/* l4_per1 -> timer2 */
3625static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3626 .master = &dra7xx_l4_per1_hwmod,
3627 .slave = &dra7xx_timer2_hwmod,
3628 .clk = "l3_iclk_div",
3629 .user = OCP_USER_MPU | OCP_USER_SDMA,
3630};
3631
3632/* l4_per1 -> timer3 */
3633static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3634 .master = &dra7xx_l4_per1_hwmod,
3635 .slave = &dra7xx_timer3_hwmod,
3636 .clk = "l3_iclk_div",
3637 .user = OCP_USER_MPU | OCP_USER_SDMA,
3638};
3639
3640/* l4_per1 -> timer4 */
3641static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3642 .master = &dra7xx_l4_per1_hwmod,
3643 .slave = &dra7xx_timer4_hwmod,
3644 .clk = "l3_iclk_div",
3645 .user = OCP_USER_MPU | OCP_USER_SDMA,
3646};
3647
3648/* l4_per3 -> timer5 */
3649static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3650 .master = &dra7xx_l4_per3_hwmod,
3651 .slave = &dra7xx_timer5_hwmod,
3652 .clk = "l3_iclk_div",
3653 .user = OCP_USER_MPU | OCP_USER_SDMA,
3654};
3655
3656/* l4_per3 -> timer6 */
3657static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3658 .master = &dra7xx_l4_per3_hwmod,
3659 .slave = &dra7xx_timer6_hwmod,
3660 .clk = "l3_iclk_div",
3661 .user = OCP_USER_MPU | OCP_USER_SDMA,
3662};
3663
3664/* l4_per3 -> timer7 */
3665static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3666 .master = &dra7xx_l4_per3_hwmod,
3667 .slave = &dra7xx_timer7_hwmod,
3668 .clk = "l3_iclk_div",
3669 .user = OCP_USER_MPU | OCP_USER_SDMA,
3670};
3671
3672/* l4_per3 -> timer8 */
3673static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3674 .master = &dra7xx_l4_per3_hwmod,
3675 .slave = &dra7xx_timer8_hwmod,
3676 .clk = "l3_iclk_div",
3677 .user = OCP_USER_MPU | OCP_USER_SDMA,
3678};
3679
3680/* l4_per1 -> timer9 */
3681static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3682 .master = &dra7xx_l4_per1_hwmod,
3683 .slave = &dra7xx_timer9_hwmod,
3684 .clk = "l3_iclk_div",
3685 .user = OCP_USER_MPU | OCP_USER_SDMA,
3686};
3687
3688/* l4_per1 -> timer10 */
3689static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3690 .master = &dra7xx_l4_per1_hwmod,
3691 .slave = &dra7xx_timer10_hwmod,
3692 .clk = "l3_iclk_div",
3693 .user = OCP_USER_MPU | OCP_USER_SDMA,
3694};
3695
3696/* l4_per1 -> timer11 */
3697static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3698 .master = &dra7xx_l4_per1_hwmod,
3699 .slave = &dra7xx_timer11_hwmod,
3700 .clk = "l3_iclk_div",
3701 .user = OCP_USER_MPU | OCP_USER_SDMA,
3702};
3703
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]3704/* l4_wkup -> timer12 */
3705static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3706 .master = &dra7xx_l4_wkup_hwmod,
3707 .slave = &dra7xx_timer12_hwmod,
3708 .clk = "wkupaon_iclk_mux",
3709 .user = OCP_USER_MPU | OCP_USER_SDMA,
3710};
3711
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]3712/* l4_per3 -> timer13 */
3713static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3714 .master = &dra7xx_l4_per3_hwmod,
3715 .slave = &dra7xx_timer13_hwmod,
3716 .clk = "l3_iclk_div",
3717 .user = OCP_USER_MPU | OCP_USER_SDMA,
3718};
3719
3720/* l4_per3 -> timer14 */
3721static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3722 .master = &dra7xx_l4_per3_hwmod,
3723 .slave = &dra7xx_timer14_hwmod,
3724 .clk = "l3_iclk_div",
3725 .user = OCP_USER_MPU | OCP_USER_SDMA,
3726};
3727
3728/* l4_per3 -> timer15 */
3729static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3730 .master = &dra7xx_l4_per3_hwmod,
3731 .slave = &dra7xx_timer15_hwmod,
3732 .clk = "l3_iclk_div",
3733 .user = OCP_USER_MPU | OCP_USER_SDMA,
3734};
3735
3736/* l4_per3 -> timer16 */
3737static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3738 .master = &dra7xx_l4_per3_hwmod,
3739 .slave = &dra7xx_timer16_hwmod,
3740 .clk = "l3_iclk_div",
3741 .user = OCP_USER_MPU | OCP_USER_SDMA,
3742};
3743
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3744/* l4_per1 -> uart1 */
3745static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3746 .master = &dra7xx_l4_per1_hwmod,
3747 .slave = &dra7xx_uart1_hwmod,
3748 .clk = "l3_iclk_div",
3749 .user = OCP_USER_MPU | OCP_USER_SDMA,
3750};
3751
3752/* l4_per1 -> uart2 */
3753static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3754 .master = &dra7xx_l4_per1_hwmod,
3755 .slave = &dra7xx_uart2_hwmod,
3756 .clk = "l3_iclk_div",
3757 .user = OCP_USER_MPU | OCP_USER_SDMA,
3758};
3759
3760/* l4_per1 -> uart3 */
3761static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3762 .master = &dra7xx_l4_per1_hwmod,
3763 .slave = &dra7xx_uart3_hwmod,
3764 .clk = "l3_iclk_div",
3765 .user = OCP_USER_MPU | OCP_USER_SDMA,
3766};
3767
3768/* l4_per1 -> uart4 */
3769static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3770 .master = &dra7xx_l4_per1_hwmod,
3771 .slave = &dra7xx_uart4_hwmod,
3772 .clk = "l3_iclk_div",
3773 .user = OCP_USER_MPU | OCP_USER_SDMA,
3774};
3775
3776/* l4_per1 -> uart5 */
3777static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3778 .master = &dra7xx_l4_per1_hwmod,
3779 .slave = &dra7xx_uart5_hwmod,
3780 .clk = "l3_iclk_div",
3781 .user = OCP_USER_MPU | OCP_USER_SDMA,
3782};
3783
3784/* l4_per1 -> uart6 */
3785static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3786 .master = &dra7xx_l4_per1_hwmod,
3787 .slave = &dra7xx_uart6_hwmod,
3788 .clk = "l3_iclk_div",
3789 .user = OCP_USER_MPU | OCP_USER_SDMA,
3790};
3791
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]3792/* l4_per2 -> uart7 */
3793static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3794 .master = &dra7xx_l4_per2_hwmod,
3795 .slave = &dra7xx_uart7_hwmod,
3796 .clk = "l3_iclk_div",
3797 .user = OCP_USER_MPU | OCP_USER_SDMA,
3798};
3799
Joel Fernandesc3118642016-10-18 10:55:21 +0300[diff] [blame]3800/* l4_per1 -> des */
3801static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3802 .master = &dra7xx_l4_per1_hwmod,
3803 .slave = &dra7xx_des_hwmod,
3804 .clk = "l3_iclk_div",
3805 .user = OCP_USER_MPU | OCP_USER_SDMA,
3806};
3807
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]3808/* l4_per2 -> uart8 */
3809static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3810 .master = &dra7xx_l4_per2_hwmod,
3811 .slave = &dra7xx_uart8_hwmod,
3812 .clk = "l3_iclk_div",
3813 .user = OCP_USER_MPU | OCP_USER_SDMA,
3814};
3815
3816/* l4_per2 -> uart9 */
3817static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3818 .master = &dra7xx_l4_per2_hwmod,
3819 .slave = &dra7xx_uart9_hwmod,
3820 .clk = "l3_iclk_div",
3821 .user = OCP_USER_MPU | OCP_USER_SDMA,
3822};
3823
3824/* l4_wkup -> uart10 */
3825static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3826 .master = &dra7xx_l4_wkup_hwmod,
3827 .slave = &dra7xx_uart10_hwmod,
3828 .clk = "wkupaon_iclk_mux",
3829 .user = OCP_USER_MPU | OCP_USER_SDMA,
3830};
3831
Joel Fernandes7a825cc2016-10-18 10:55:24 +0300[diff] [blame]3832/* l4_per1 -> rng */
3833static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3834 .master = &dra7xx_l4_per1_hwmod,
3835 .slave = &dra7xx_rng_hwmod,
3836 .user = OCP_USER_MPU,
3837};
3838
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3839/* l4_per3 -> usb_otg_ss1 */
3840static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3841 .master = &dra7xx_l4_per3_hwmod,
3842 .slave = &dra7xx_usb_otg_ss1_hwmod,
3843 .clk = "dpll_core_h13x2_ck",
3844 .user = OCP_USER_MPU | OCP_USER_SDMA,
3845};
3846
3847/* l4_per3 -> usb_otg_ss2 */
3848static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3849 .master = &dra7xx_l4_per3_hwmod,
3850 .slave = &dra7xx_usb_otg_ss2_hwmod,
3851 .clk = "dpll_core_h13x2_ck",
3852 .user = OCP_USER_MPU | OCP_USER_SDMA,
3853};
3854
3855/* l4_per3 -> usb_otg_ss3 */
3856static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3857 .master = &dra7xx_l4_per3_hwmod,
3858 .slave = &dra7xx_usb_otg_ss3_hwmod,
3859 .clk = "dpll_core_h13x2_ck",
3860 .user = OCP_USER_MPU | OCP_USER_SDMA,
3861};
3862
3863/* l4_per3 -> usb_otg_ss4 */
3864static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3865 .master = &dra7xx_l4_per3_hwmod,
3866 .slave = &dra7xx_usb_otg_ss4_hwmod,
3867 .clk = "dpll_core_h13x2_ck",
3868 .user = OCP_USER_MPU | OCP_USER_SDMA,
3869};
3870
3871/* l3_main_1 -> vcp1 */
3872static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3873 .master = &dra7xx_l3_main_1_hwmod,
3874 .slave = &dra7xx_vcp1_hwmod,
3875 .clk = "l3_iclk_div",
3876 .user = OCP_USER_MPU | OCP_USER_SDMA,
3877};
3878
3879/* l4_per2 -> vcp1 */
3880static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3881 .master = &dra7xx_l4_per2_hwmod,
3882 .slave = &dra7xx_vcp1_hwmod,
3883 .clk = "l3_iclk_div",
3884 .user = OCP_USER_MPU | OCP_USER_SDMA,
3885};
3886
3887/* l3_main_1 -> vcp2 */
3888static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3889 .master = &dra7xx_l3_main_1_hwmod,
3890 .slave = &dra7xx_vcp2_hwmod,
3891 .clk = "l3_iclk_div",
3892 .user = OCP_USER_MPU | OCP_USER_SDMA,
3893};
3894
3895/* l4_per2 -> vcp2 */
3896static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3897 .master = &dra7xx_l4_per2_hwmod,
3898 .slave = &dra7xx_vcp2_hwmod,
3899 .clk = "l3_iclk_div",
3900 .user = OCP_USER_MPU | OCP_USER_SDMA,
3901};
3902
3903/* l4_wkup -> wd_timer2 */
3904static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3905 .master = &dra7xx_l4_wkup_hwmod,
3906 .slave = &dra7xx_wd_timer2_hwmod,
3907 .clk = "wkupaon_iclk_mux",
3908 .user = OCP_USER_MPU | OCP_USER_SDMA,
3909};
3910
Vignesh Rb05ff3c2016-04-10 13:20:09 -0600[diff] [blame]3911/* l4_per2 -> epwmss0 */
3912static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3913 .master = &dra7xx_l4_per2_hwmod,
3914 .slave = &dra7xx_epwmss0_hwmod,
3915 .clk = "l4_root_clk_div",
3916 .user = OCP_USER_MPU,
3917};
3918
3919/* l4_per2 -> epwmss1 */
3920static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3921 .master = &dra7xx_l4_per2_hwmod,
3922 .slave = &dra7xx_epwmss1_hwmod,
3923 .clk = "l4_root_clk_div",
3924 .user = OCP_USER_MPU,
3925};
3926
3927/* l4_per2 -> epwmss2 */
3928static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3929 .master = &dra7xx_l4_per2_hwmod,
3930 .slave = &dra7xx_epwmss2_hwmod,
3931 .clk = "l4_root_clk_div",
3932 .user = OCP_USER_MPU,
3933};
3934
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3935static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
Tomi Valkeinen42121682014-09-15 13:12:18 -0500[diff] [blame]3936 &dra7xx_l3_main_1__dmm,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3937 &dra7xx_l3_main_2__l3_instr,
3938 &dra7xx_l4_cfg__l3_main_1,
3939 &dra7xx_mpu__l3_main_1,
3940 &dra7xx_l3_main_1__l3_main_2,
3941 &dra7xx_l4_cfg__l3_main_2,
3942 &dra7xx_l3_main_1__l4_cfg,
3943 &dra7xx_l3_main_1__l4_per1,
3944 &dra7xx_l3_main_1__l4_per2,
3945 &dra7xx_l3_main_1__l4_per3,
3946 &dra7xx_l3_main_1__l4_wkup,
3947 &dra7xx_l4_per2__atl,
3948 &dra7xx_l3_main_1__bb2d,
3949 &dra7xx_l4_wkup__counter_32k,
3950 &dra7xx_l4_wkup__ctrl_module_wkup,
3951 &dra7xx_l4_wkup__dcan1,
3952 &dra7xx_l4_per2__dcan2,
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]3953 &dra7xx_l4_per2__cpgmac0,
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]3954 &dra7xx_l4_per2__mcasp1,
3955 &dra7xx_l3_main_1__mcasp1,
3956 &dra7xx_l4_per2__mcasp2,
3957 &dra7xx_l3_main_1__mcasp2,
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]3958 &dra7xx_l4_per2__mcasp3,
3959 &dra7xx_l3_main_1__mcasp3,
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]3960 &dra7xx_l4_per2__mcasp4,
3961 &dra7xx_l4_per2__mcasp5,
3962 &dra7xx_l4_per2__mcasp6,
3963 &dra7xx_l4_per2__mcasp7,
3964 &dra7xx_l4_per2__mcasp8,
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]3965 &dra7xx_gmac__mdio,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3966 &dra7xx_l4_cfg__dma_system,
Peter Ujfalusi34b41822016-02-25 16:50:18 +0200[diff] [blame]3967 &dra7xx_l3_main_1__tpcc,
3968 &dra7xx_l3_main_1__tptc0,
3969 &dra7xx_l3_main_1__tptc1,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3970 &dra7xx_l3_main_1__dss,
3971 &dra7xx_l3_main_1__dispc,
3972 &dra7xx_l3_main_1__hdmi,
Joel Fernandes628d7582016-10-18 10:55:22 +0300[diff] [blame]3973 &dra7xx_l3_main_1__aes1,
3974 &dra7xx_l3_main_1__aes2,
Lokesh Vutla7e45f172016-10-18 10:55:23 +0300[diff] [blame]3975 &dra7xx_l3_main_1__sha0,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3976 &dra7xx_l4_per1__elm,
3977 &dra7xx_l4_wkup__gpio1,
3978 &dra7xx_l4_per1__gpio2,
3979 &dra7xx_l4_per1__gpio3,
3980 &dra7xx_l4_per1__gpio4,
3981 &dra7xx_l4_per1__gpio5,
3982 &dra7xx_l4_per1__gpio6,
3983 &dra7xx_l4_per1__gpio7,
3984 &dra7xx_l4_per1__gpio8,
3985 &dra7xx_l3_main_1__gpmc,
3986 &dra7xx_l4_per1__hdq1w,
3987 &dra7xx_l4_per1__i2c1,
3988 &dra7xx_l4_per1__i2c2,
3989 &dra7xx_l4_per1__i2c3,
3990 &dra7xx_l4_per1__i2c4,
3991 &dra7xx_l4_per1__i2c5,
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]3992 &dra7xx_l4_cfg__mailbox1,
3993 &dra7xx_l4_per3__mailbox2,
3994 &dra7xx_l4_per3__mailbox3,
3995 &dra7xx_l4_per3__mailbox4,
3996 &dra7xx_l4_per3__mailbox5,
3997 &dra7xx_l4_per3__mailbox6,
3998 &dra7xx_l4_per3__mailbox7,
3999 &dra7xx_l4_per3__mailbox8,
4000 &dra7xx_l4_per3__mailbox9,
4001 &dra7xx_l4_per3__mailbox10,
4002 &dra7xx_l4_per3__mailbox11,
4003 &dra7xx_l4_per3__mailbox12,
4004 &dra7xx_l4_per3__mailbox13,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4005 &dra7xx_l4_per1__mcspi1,
4006 &dra7xx_l4_per1__mcspi2,
4007 &dra7xx_l4_per1__mcspi3,
4008 &dra7xx_l4_per1__mcspi4,
4009 &dra7xx_l4_per1__mmc1,
4010 &dra7xx_l4_per1__mmc2,
4011 &dra7xx_l4_per1__mmc3,
4012 &dra7xx_l4_per1__mmc4,
4013 &dra7xx_l4_cfg__mpu,
4014 &dra7xx_l4_cfg__ocp2scp1,
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]4015 &dra7xx_l4_cfg__ocp2scp3,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]4016 &dra7xx_l3_main_1__pciess1,
4017 &dra7xx_l4_cfg__pciess1,
4018 &dra7xx_l3_main_1__pciess2,
4019 &dra7xx_l4_cfg__pciess2,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4020 &dra7xx_l3_main_1__qspi,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4021 &dra7xx_l4_cfg__sata,
4022 &dra7xx_l4_cfg__smartreflex_core,
4023 &dra7xx_l4_cfg__smartreflex_mpu,
4024 &dra7xx_l4_cfg__spinlock,
4025 &dra7xx_l4_wkup__timer1,
4026 &dra7xx_l4_per1__timer2,
4027 &dra7xx_l4_per1__timer3,
4028 &dra7xx_l4_per1__timer4,
4029 &dra7xx_l4_per3__timer5,
4030 &dra7xx_l4_per3__timer6,
4031 &dra7xx_l4_per3__timer7,
4032 &dra7xx_l4_per3__timer8,
4033 &dra7xx_l4_per1__timer9,
4034 &dra7xx_l4_per1__timer10,
4035 &dra7xx_l4_per1__timer11,
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]4036 &dra7xx_l4_per3__timer13,
4037 &dra7xx_l4_per3__timer14,
4038 &dra7xx_l4_per3__timer15,
4039 &dra7xx_l4_per3__timer16,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4040 &dra7xx_l4_per1__uart1,
4041 &dra7xx_l4_per1__uart2,
4042 &dra7xx_l4_per1__uart3,
4043 &dra7xx_l4_per1__uart4,
4044 &dra7xx_l4_per1__uart5,
4045 &dra7xx_l4_per1__uart6,
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]4046 &dra7xx_l4_per2__uart7,
4047 &dra7xx_l4_per2__uart8,
4048 &dra7xx_l4_per2__uart9,
4049 &dra7xx_l4_wkup__uart10,
Joel Fernandesc3118642016-10-18 10:55:21 +0300[diff] [blame]4050 &dra7xx_l4_per1__des,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4051 &dra7xx_l4_per3__usb_otg_ss1,
4052 &dra7xx_l4_per3__usb_otg_ss2,
4053 &dra7xx_l4_per3__usb_otg_ss3,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4054 &dra7xx_l3_main_1__vcp1,
4055 &dra7xx_l4_per2__vcp1,
4056 &dra7xx_l3_main_1__vcp2,
4057 &dra7xx_l4_per2__vcp2,
4058 &dra7xx_l4_wkup__wd_timer2,
Vignesh Rb05ff3c2016-04-10 13:20:09 -0600[diff] [blame]4059 &dra7xx_l4_per2__epwmss0,
4060 &dra7xx_l4_per2__epwmss1,
4061 &dra7xx_l4_per2__epwmss2,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4062 NULL,
4063};
4064
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]4065/* GP-only hwmod links */
4066static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4067 &dra7xx_l4_wkup__timer12,
Joel Fernandes7a825cc2016-10-18 10:55:24 +0300[diff] [blame]4068 &dra7xx_l4_per1__rng,
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]4069 NULL,
4070};
4071
4072/* SoC variant specific hwmod links */
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]4073static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4074 &dra7xx_l4_per3__usb_otg_ss4,
4075 NULL,
4076};
4077
4078static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4079 NULL,
4080};
4081
Nishanth Menon6cd9699c2016-10-21 16:08:38 +0530[diff] [blame]4082static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = {
4083 &dra7xx_l4_per3__rtcss,
4084 NULL,
4085};
4086
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4087int __init dra7xx_hwmod_init(void)
4088{
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]4089 int ret;
4090
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4091 omap_hwmod_init();
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]4092 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4093
4094 if (!ret && soc_is_dra74x())
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]4095 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]4096 else if (!ret && soc_is_dra72x())
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]4097 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4098
4099 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4100 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]4101
Nishanth Menon6cd9699c2016-10-21 16:08:38 +0530[diff] [blame]4102 /* now for the IPs *NOT* in dra71 */
4103 if (!ret && !of_machine_is_compatible("ti,dra718"))
4104 ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);
4105
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]4106 return ret;
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]4107}