blob: 109a535b639c98dabc48dcde9a14b3d8fda33617 [file] [log] [blame]
Andrei Konovalovae918c02007-07-17 04:04:11 -07001/*
Andrei Konovalovae918c02007-07-17 04:04:11 -07002 * Xilinx SPI controller driver (master mode only)
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
Grant Likely8fd88212010-10-14 09:04:29 -06007 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
10
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
Andrei Konovalovae918c02007-07-17 04:04:11 -070014 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
Grant Likelyeae6cb32010-10-14 09:32:53 -060019#include <linux/of.h>
Grant Likely8fd88212010-10-14 09:04:29 -060020#include <linux/platform_device.h>
Andrei Konovalovae918c02007-07-17 04:04:11 -070021#include <linux/spi/spi.h>
22#include <linux/spi/spi_bitbang.h>
Richard Röjforsd5af91a2009-11-13 12:28:39 +010023#include <linux/spi/xilinx_spi.h>
Grant Likelyeae6cb32010-10-14 09:32:53 -060024#include <linux/io.h>
Richard Röjforsd5af91a2009-11-13 12:28:39 +010025
David Brownellfc3ba952007-08-30 23:56:24 -070026#define XILINX_SPI_NAME "xilinx_spi"
Andrei Konovalovae918c02007-07-17 04:04:11 -070027
28/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
29 * Product Specification", DS464
30 */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010031#define XSPI_CR_OFFSET 0x60 /* Control Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070032
33#define XSPI_CR_ENABLE 0x02
34#define XSPI_CR_MASTER_MODE 0x04
35#define XSPI_CR_CPOL 0x08
36#define XSPI_CR_CPHA 0x10
37#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
38#define XSPI_CR_TXFIFO_RESET 0x20
39#define XSPI_CR_RXFIFO_RESET 0x40
40#define XSPI_CR_MANUAL_SSELECT 0x80
41#define XSPI_CR_TRANS_INHIBIT 0x100
Richard Röjforsc9da2e12009-11-13 12:28:55 +010042#define XSPI_CR_LSB_FIRST 0x200
Andrei Konovalovae918c02007-07-17 04:04:11 -070043
Richard Röjforsc9da2e12009-11-13 12:28:55 +010044#define XSPI_SR_OFFSET 0x64 /* Status Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070045
46#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
47#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
48#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
49#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
50#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
51
Richard Röjforsc9da2e12009-11-13 12:28:55 +010052#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
53#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070054
55#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
56
57/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
58 * IPIF registers are 32 bit
59 */
60#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
61#define XIPIF_V123B_GINTR_ENABLE 0x80000000
62
63#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
64#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
65
66#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
67#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
68 * disabled */
69#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
70#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
71#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
72#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010073#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
Andrei Konovalovae918c02007-07-17 04:04:11 -070074
75#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
76#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
77
78struct xilinx_spi {
79 /* bitbang has to be first */
80 struct spi_bitbang bitbang;
81 struct completion done;
Richard Röjforsd5af91a2009-11-13 12:28:39 +010082 struct resource mem; /* phys mem */
Andrei Konovalovae918c02007-07-17 04:04:11 -070083 void __iomem *regs; /* virt. address of the control registers */
84
85 u32 irq;
86
Andrei Konovalovae918c02007-07-17 04:04:11 -070087 u8 *rx_ptr; /* pointer in the Tx buffer */
88 const u8 *tx_ptr; /* pointer in the Rx buffer */
89 int remaining_bytes; /* the number of bytes left to transfer */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010090 u8 bits_per_word;
Richard Röjfors86fc5932009-11-13 12:28:49 +010091 unsigned int (*read_fn) (void __iomem *);
92 void (*write_fn) (u32, void __iomem *);
Richard Röjforsc9da2e12009-11-13 12:28:55 +010093 void (*tx_fn) (struct xilinx_spi *);
94 void (*rx_fn) (struct xilinx_spi *);
Andrei Konovalovae918c02007-07-17 04:04:11 -070095};
96
Paul Mundt97782142010-01-20 13:49:45 -070097static void xspi_write32(u32 val, void __iomem *addr)
98{
99 iowrite32(val, addr);
100}
101
102static unsigned int xspi_read32(void __iomem *addr)
103{
104 return ioread32(addr);
105}
106
107static void xspi_write32_be(u32 val, void __iomem *addr)
108{
109 iowrite32be(val, addr);
110}
111
112static unsigned int xspi_read32_be(void __iomem *addr)
113{
114 return ioread32be(addr);
115}
116
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100117static void xspi_tx8(struct xilinx_spi *xspi)
118{
119 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
120 xspi->tx_ptr++;
121}
122
123static void xspi_tx16(struct xilinx_spi *xspi)
124{
125 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
126 xspi->tx_ptr += 2;
127}
128
129static void xspi_tx32(struct xilinx_spi *xspi)
130{
131 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
132 xspi->tx_ptr += 4;
133}
134
135static void xspi_rx8(struct xilinx_spi *xspi)
136{
137 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
138 if (xspi->rx_ptr) {
139 *xspi->rx_ptr = data & 0xff;
140 xspi->rx_ptr++;
141 }
142}
143
144static void xspi_rx16(struct xilinx_spi *xspi)
145{
146 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
147 if (xspi->rx_ptr) {
148 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
149 xspi->rx_ptr += 2;
150 }
151}
152
153static void xspi_rx32(struct xilinx_spi *xspi)
154{
155 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
156 if (xspi->rx_ptr) {
157 *(u32 *)(xspi->rx_ptr) = data;
158 xspi->rx_ptr += 4;
159 }
160}
161
Richard Röjfors86fc5932009-11-13 12:28:49 +0100162static void xspi_init_hw(struct xilinx_spi *xspi)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700163{
Richard Röjfors86fc5932009-11-13 12:28:49 +0100164 void __iomem *regs_base = xspi->regs;
165
Andrei Konovalovae918c02007-07-17 04:04:11 -0700166 /* Reset the SPI device */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100167 xspi->write_fn(XIPIF_V123B_RESET_MASK,
168 regs_base + XIPIF_V123B_RESETR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700169 /* Disable all the interrupts just in case */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100170 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700171 /* Enable the global IPIF interrupt */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100172 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
173 regs_base + XIPIF_V123B_DGIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700174 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100175 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700176 /* Disable the transmitter, enable Manual Slave Select Assertion,
177 * put SPI controller into master mode, and enable it */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100178 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100179 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
180 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700181}
182
183static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
184{
185 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
186
187 if (is_on == BITBANG_CS_INACTIVE) {
188 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100189 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700190 } else if (is_on == BITBANG_CS_ACTIVE) {
191 /* Set the SPI clock phase and polarity */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100192 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700193 & ~XSPI_CR_MODE_MASK;
194 if (spi->mode & SPI_CPHA)
195 cr |= XSPI_CR_CPHA;
196 if (spi->mode & SPI_CPOL)
197 cr |= XSPI_CR_CPOL;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100198 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700199
200 /* We do not check spi->max_speed_hz here as the SPI clock
201 * frequency is not software programmable (the IP block design
202 * parameter)
203 */
204
205 /* Activate the chip select */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100206 xspi->write_fn(~(0x0001 << spi->chip_select),
207 xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700208 }
209}
210
211/* spi_bitbang requires custom setup_transfer() to be defined if there is a
212 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100213 * supports 8 or 16 bits per word which cannot be changed in software.
214 * SPI clock can't be changed in software either.
215 * Check for correct bits per word. Chip select delay calculations could be
Andrei Konovalovae918c02007-07-17 04:04:11 -0700216 * added here as soon as bitbang_work() can be made aware of the delay value.
217 */
218static int xilinx_spi_setup_transfer(struct spi_device *spi,
219 struct spi_transfer *t)
220{
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100221 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700222 u8 bits_per_word;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700223
John Linn1a8d3b72009-09-14 08:17:05 +0000224 bits_per_word = (t && t->bits_per_word)
225 ? t->bits_per_word : spi->bits_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100226 if (bits_per_word != xspi->bits_per_word) {
Andrei Konovalovae918c02007-07-17 04:04:11 -0700227 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
Harvey Harrisonb687d2a2008-04-28 02:14:19 -0700228 __func__, bits_per_word);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700229 return -EINVAL;
230 }
231
Andrei Konovalovae918c02007-07-17 04:04:11 -0700232 return 0;
233}
234
Andrei Konovalovae918c02007-07-17 04:04:11 -0700235static int xilinx_spi_setup(struct spi_device *spi)
236{
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100237 /* always return 0, we can not check the number of bits.
238 * There are cases when SPI setup is called before any driver is
239 * there, in that case the SPI core defaults to 8 bits, which we
240 * do not support in some cases. But if we return an error, the
241 * SPI device would not be registered and no driver can get hold of it
242 * When the driver is there, it will call SPI setup again with the
243 * correct number of bits per transfer.
244 * If a driver setups with the wrong bit number, it will fail when
245 * it tries to do a transfer
246 */
Andrei Konovalovae918c02007-07-17 04:04:11 -0700247 return 0;
248}
249
250static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
251{
252 u8 sr;
253
254 /* Fill the Tx FIFO with as many bytes as possible */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100255 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700256 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
Richard Röjfors86fc5932009-11-13 12:28:49 +0100257 if (xspi->tx_ptr)
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100258 xspi->tx_fn(xspi);
Richard Röjfors86fc5932009-11-13 12:28:49 +0100259 else
260 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100261 xspi->remaining_bytes -= xspi->bits_per_word / 8;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100262 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700263 }
264}
265
266static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
267{
268 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
269 u32 ipif_ier;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700270
271 /* We get here with transmitter inhibited */
272
273 xspi->tx_ptr = t->tx_buf;
274 xspi->rx_ptr = t->rx_buf;
275 xspi->remaining_bytes = t->len;
276 INIT_COMPLETION(xspi->done);
277
Andrei Konovalovae918c02007-07-17 04:04:11 -0700278
279 /* Enable the transmit empty interrupt, which we use to determine
280 * progress on the transmission.
281 */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100282 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
283 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
284 xspi->regs + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700285
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200286 for (;;) {
287 u16 cr;
288 u8 sr;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700289
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200290 xilinx_spi_fill_tx_fifo(xspi);
291
292 /* Start the transfer by not inhibiting the transmitter any
293 * longer
294 */
295 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
296 ~XSPI_CR_TRANS_INHIBIT;
297 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
298
299 wait_for_completion(&xspi->done);
300
301 /* A transmit has just completed. Process received data and
302 * check for more data to transmit. Always inhibit the
303 * transmitter while the Isr refills the transmit register/FIFO,
304 * or make sure it is stopped if we're done.
305 */
306 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
307 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
308 xspi->regs + XSPI_CR_OFFSET);
309
310 /* Read out all the data from the Rx FIFO */
311 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
312 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
313 xspi->rx_fn(xspi);
314 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
315 }
316
317 /* See if there is more data to send */
dan.carpenter@oracle.come33d0852013-06-09 16:07:28 +0300318 if (xspi->remaining_bytes <= 0)
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200319 break;
320 }
Andrei Konovalovae918c02007-07-17 04:04:11 -0700321
322 /* Disable the transmit empty interrupt */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100323 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700324
325 return t->len - xspi->remaining_bytes;
326}
327
328
329/* This driver supports single master mode only. Hence Tx FIFO Empty
330 * is the only interrupt we care about.
331 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
332 * Fault are not to happen.
333 */
334static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
335{
336 struct xilinx_spi *xspi = dev_id;
337 u32 ipif_isr;
338
339 /* Get the IPIF interrupts, and clear them immediately */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100340 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
341 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700342
343 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200344 complete(&xspi->done);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700345 }
346
347 return IRQ_HANDLED;
348}
349
Grant Likelyeae6cb32010-10-14 09:32:53 -0600350static const struct of_device_id xilinx_spi_of_match[] = {
351 { .compatible = "xlnx,xps-spi-2.00.a", },
352 { .compatible = "xlnx,xps-spi-2.00.b", },
353 {}
354};
355MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
Grant Likelyeae6cb32010-10-14 09:32:53 -0600356
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100357struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
Grant Likely91565c42010-10-14 08:54:55 -0600358 u32 irq, s16 bus_num, int num_cs, int little_endian, int bits_per_word)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700359{
Andrei Konovalovae918c02007-07-17 04:04:11 -0700360 struct spi_master *master;
361 struct xilinx_spi *xspi;
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100362 int ret;
John Linnff82c582009-01-09 16:01:53 -0700363
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100364 master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
365 if (!master)
366 return NULL;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700367
David Brownelle7db06b2009-06-17 16:26:04 -0700368 /* the spi->mode bits understood by this driver: */
369 master->mode_bits = SPI_CPOL | SPI_CPHA;
370
Andrei Konovalovae918c02007-07-17 04:04:11 -0700371 xspi = spi_master_get_devdata(master);
372 xspi->bitbang.master = spi_master_get(master);
373 xspi->bitbang.chipselect = xilinx_spi_chipselect;
374 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
375 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
376 xspi->bitbang.master->setup = xilinx_spi_setup;
377 init_completion(&xspi->done);
378
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100379 if (!request_mem_region(mem->start, resource_size(mem),
380 XILINX_SPI_NAME))
Andrei Konovalovae918c02007-07-17 04:04:11 -0700381 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700382
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100383 xspi->regs = ioremap(mem->start, resource_size(mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700384 if (xspi->regs == NULL) {
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100385 dev_warn(dev, "ioremap failure\n");
386 goto map_failed;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700387 }
388
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100389 master->bus_num = bus_num;
Grant Likely91565c42010-10-14 08:54:55 -0600390 master->num_chipselect = num_cs;
Anatolij Gustschin12b15e82010-07-27 22:35:58 +0200391 master->dev.of_node = dev->of_node;
John Linnff82c582009-01-09 16:01:53 -0700392
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100393 xspi->mem = *mem;
394 xspi->irq = irq;
Grant Likely91565c42010-10-14 08:54:55 -0600395 if (little_endian) {
Paul Mundt97782142010-01-20 13:49:45 -0700396 xspi->read_fn = xspi_read32;
397 xspi->write_fn = xspi_write32;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100398 } else {
Paul Mundt97782142010-01-20 13:49:45 -0700399 xspi->read_fn = xspi_read32_be;
400 xspi->write_fn = xspi_write32_be;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100401 }
Grant Likely91565c42010-10-14 08:54:55 -0600402 xspi->bits_per_word = bits_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100403 if (xspi->bits_per_word == 8) {
404 xspi->tx_fn = xspi_tx8;
405 xspi->rx_fn = xspi_rx8;
406 } else if (xspi->bits_per_word == 16) {
407 xspi->tx_fn = xspi_tx16;
408 xspi->rx_fn = xspi_rx16;
409 } else if (xspi->bits_per_word == 32) {
410 xspi->tx_fn = xspi_tx32;
411 xspi->rx_fn = xspi_rx32;
412 } else
413 goto unmap_io;
414
Andrei Konovalovae918c02007-07-17 04:04:11 -0700415
416 /* SPI controller initializations */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100417 xspi_init_hw(xspi);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700418
419 /* Register for SPI Interrupt */
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100420 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
421 if (ret)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700422 goto unmap_io;
423
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100424 ret = spi_bitbang_start(&xspi->bitbang);
425 if (ret) {
426 dev_err(dev, "spi_bitbang_start FAILED\n");
Andrei Konovalovae918c02007-07-17 04:04:11 -0700427 goto free_irq;
428 }
429
Grant Likely920712a2009-11-25 07:23:35 -0700430 dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
431 (unsigned long long)mem->start, xspi->regs, xspi->irq);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100432 return master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700433
434free_irq:
435 free_irq(xspi->irq, xspi);
436unmap_io:
437 iounmap(xspi->regs);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100438map_failed:
439 release_mem_region(mem->start, resource_size(mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700440put_master:
441 spi_master_put(master);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100442 return NULL;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700443}
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100444EXPORT_SYMBOL(xilinx_spi_init);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700445
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100446void xilinx_spi_deinit(struct spi_master *master)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700447{
448 struct xilinx_spi *xspi;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700449
Andrei Konovalovae918c02007-07-17 04:04:11 -0700450 xspi = spi_master_get_devdata(master);
451
452 spi_bitbang_stop(&xspi->bitbang);
453 free_irq(xspi->irq, xspi);
454 iounmap(xspi->regs);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100455
456 release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700457 spi_master_put(xspi->bitbang.master);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700458}
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100459EXPORT_SYMBOL(xilinx_spi_deinit);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700460
Grant Likelyfd4a3192012-12-07 16:57:14 +0000461static int xilinx_spi_probe(struct platform_device *dev)
Grant Likely8fd88212010-10-14 09:04:29 -0600462{
463 struct xspi_platform_data *pdata;
464 struct resource *r;
Grant Likelyeae6cb32010-10-14 09:32:53 -0600465 int irq, num_cs = 0, little_endian = 0, bits_per_word = 8;
Grant Likely8fd88212010-10-14 09:04:29 -0600466 struct spi_master *master;
467 u8 i;
468
Samuel Ortiz3271d382011-04-08 01:23:57 +0200469 pdata = dev->dev.platform_data;
Grant Likelyeae6cb32010-10-14 09:32:53 -0600470 if (pdata) {
471 num_cs = pdata->num_chipselect;
472 little_endian = pdata->little_endian;
473 bits_per_word = pdata->bits_per_word;
474 }
475
476#ifdef CONFIG_OF
477 if (dev->dev.of_node) {
478 const __be32 *prop;
479 int len;
480
481 /* number of slave select bits is required */
482 prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits",
483 &len);
484 if (prop && len >= sizeof(*prop))
485 num_cs = __be32_to_cpup(prop);
486 }
487#endif
488
489 if (!num_cs) {
490 dev_err(&dev->dev, "Missing slave select configuration data\n");
491 return -EINVAL;
492 }
493
Grant Likely8fd88212010-10-14 09:04:29 -0600494
495 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
496 if (!r)
497 return -ENODEV;
498
499 irq = platform_get_irq(dev, 0);
500 if (irq < 0)
501 return -ENXIO;
502
Grant Likelyeae6cb32010-10-14 09:32:53 -0600503 master = xilinx_spi_init(&dev->dev, r, irq, dev->id, num_cs,
504 little_endian, bits_per_word);
Grant Likely8fd88212010-10-14 09:04:29 -0600505 if (!master)
506 return -ENODEV;
507
Grant Likelyeae6cb32010-10-14 09:32:53 -0600508 if (pdata) {
509 for (i = 0; i < pdata->num_devices; i++)
510 spi_new_device(master, pdata->devices + i);
511 }
Grant Likely8fd88212010-10-14 09:04:29 -0600512
513 platform_set_drvdata(dev, master);
514 return 0;
515}
516
Grant Likelyfd4a3192012-12-07 16:57:14 +0000517static int xilinx_spi_remove(struct platform_device *dev)
Grant Likely8fd88212010-10-14 09:04:29 -0600518{
519 xilinx_spi_deinit(platform_get_drvdata(dev));
520 platform_set_drvdata(dev, 0);
521
522 return 0;
523}
524
525/* work with hotplug and coldplug */
526MODULE_ALIAS("platform:" XILINX_SPI_NAME);
527
528static struct platform_driver xilinx_spi_driver = {
529 .probe = xilinx_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000530 .remove = xilinx_spi_remove,
Grant Likely8fd88212010-10-14 09:04:29 -0600531 .driver = {
532 .name = XILINX_SPI_NAME,
533 .owner = THIS_MODULE,
Grant Likelyeae6cb32010-10-14 09:32:53 -0600534 .of_match_table = xilinx_spi_of_match,
Grant Likely8fd88212010-10-14 09:04:29 -0600535 },
536};
Grant Likely940ab882011-10-05 11:29:49 -0600537module_platform_driver(xilinx_spi_driver);
Grant Likely8fd88212010-10-14 09:04:29 -0600538
Andrei Konovalovae918c02007-07-17 04:04:11 -0700539MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
540MODULE_DESCRIPTION("Xilinx SPI driver");
541MODULE_LICENSE("GPL");