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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __ASM_SH_SYSTEM_H
2#define __ASM_SH_SYSTEM_H
3
4/*
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
7 */
8
Tom Rinie4e3b5c2006-09-27 11:28:20 +09009#include <asm/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070010
11/*
12 * switch_to() should switch tasks to task nr n, first
13 */
14
15#define switch_to(prev, next, last) do { \
Ingo Molnar36c8b582006-07-03 00:25:41 -070016 struct task_struct *__last; \
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
18 register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
19 register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
20 register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
21 register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
22 register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
23 __asm__ __volatile__ (".balign 4\n\t" \
24 "stc.l gbr, @-r15\n\t" \
25 "sts.l pr, @-r15\n\t" \
26 "mov.l r8, @-r15\n\t" \
27 "mov.l r9, @-r15\n\t" \
28 "mov.l r10, @-r15\n\t" \
29 "mov.l r11, @-r15\n\t" \
30 "mov.l r12, @-r15\n\t" \
31 "mov.l r13, @-r15\n\t" \
32 "mov.l r14, @-r15\n\t" \
33 "mov.l r15, @r1 ! save SP\n\t" \
34 "mov.l @r6, r15 ! change to new stack\n\t" \
35 "mova 1f, %0\n\t" \
36 "mov.l %0, @r2 ! save PC\n\t" \
37 "mov.l 2f, %0\n\t" \
38 "jmp @%0 ! call __switch_to\n\t" \
39 " lds r7, pr ! with return to new PC\n\t" \
40 ".balign 4\n" \
41 "2:\n\t" \
42 ".long __switch_to\n" \
43 "1:\n\t" \
44 "mov.l @r15+, r14\n\t" \
45 "mov.l @r15+, r13\n\t" \
46 "mov.l @r15+, r12\n\t" \
47 "mov.l @r15+, r11\n\t" \
48 "mov.l @r15+, r10\n\t" \
49 "mov.l @r15+, r9\n\t" \
50 "mov.l @r15+, r8\n\t" \
51 "lds.l @r15+, pr\n\t" \
52 "ldc.l @r15+, gbr\n\t" \
53 : "=z" (__last) \
54 : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
55 "r" (__ts5), "r" (__ts6), "r" (__ts7) \
56 : "r3", "t"); \
57 last = __last; \
58} while (0)
59
Ingo Molnar4dc7a0b2006-01-12 01:05:27 -080060/*
61 * On SMP systems, when the scheduler does migration-cost autodetection,
62 * it needs a way to flush as much of the CPU's caches as possible.
63 *
64 * TODO: fill this in!
65 */
66static inline void sched_cacheflush(void)
67{
68}
69
Linus Torvalds1da177e2005-04-16 15:20:36 -070070#define nop() __asm__ __volatile__ ("nop")
71
72
73#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
74
75static __inline__ unsigned long tas(volatile int *m)
76{ /* #define tas(ptr) (xchg((ptr),1)) */
77 unsigned long retval;
78
79 __asm__ __volatile__ ("tas.b @%1\n\t"
80 "movt %0"
81 : "=r" (retval): "r" (m): "t", "memory");
82 return retval;
83}
84
85extern void __xchg_called_with_bad_pointer(void);
86
87#define mb() __asm__ __volatile__ ("": : :"memory")
88#define rmb() mb()
89#define wmb() __asm__ __volatile__ ("": : :"memory")
90#define read_barrier_depends() do { } while(0)
91
92#ifdef CONFIG_SMP
93#define smp_mb() mb()
94#define smp_rmb() rmb()
95#define smp_wmb() wmb()
96#define smp_read_barrier_depends() read_barrier_depends()
97#else
98#define smp_mb() barrier()
99#define smp_rmb() barrier()
100#define smp_wmb() barrier()
101#define smp_read_barrier_depends() do { } while(0)
102#endif
103
104#define set_mb(var, value) do { xchg(&var, value); } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106/* Interrupt Control */
107static __inline__ void local_irq_enable(void)
108{
109 unsigned long __dummy0, __dummy1;
110
111 __asm__ __volatile__("stc sr, %0\n\t"
112 "and %1, %0\n\t"
113 "stc r6_bank, %1\n\t"
114 "or %1, %0\n\t"
115 "ldc %0, sr"
116 : "=&r" (__dummy0), "=r" (__dummy1)
117 : "1" (~0x000000f0)
118 : "memory");
119}
120
121static __inline__ void local_irq_disable(void)
122{
123 unsigned long __dummy;
124 __asm__ __volatile__("stc sr, %0\n\t"
125 "or #0xf0, %0\n\t"
126 "ldc %0, sr"
127 : "=&z" (__dummy)
128 : /* no inputs */
129 : "memory");
130}
131
132#define local_save_flags(x) \
133 __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
134
135#define irqs_disabled() \
136({ \
137 unsigned long flags; \
138 local_save_flags(flags); \
139 (flags != 0); \
140})
141
142static __inline__ unsigned long local_irq_save(void)
143{
144 unsigned long flags, __dummy;
145
146 __asm__ __volatile__("stc sr, %1\n\t"
147 "mov %1, %0\n\t"
148 "or #0xf0, %0\n\t"
149 "ldc %0, sr\n\t"
150 "mov %1, %0\n\t"
151 "and #0xf0, %0"
152 : "=&z" (flags), "=&r" (__dummy)
153 :/**/
154 : "memory" );
155 return flags;
156}
157
158#ifdef DEBUG_CLI_STI
159static __inline__ void local_irq_restore(unsigned long x)
160{
161 if ((x & 0x000000f0) != 0x000000f0)
162 local_irq_enable();
163 else {
164 unsigned long flags;
165 local_save_flags(flags);
166
167 if (flags == 0) {
168 extern void dump_stack(void);
169 printk(KERN_ERR "BUG!\n");
170 dump_stack();
171 local_irq_disable();
172 }
173 }
174}
175#else
176#define local_irq_restore(x) do { \
177 if ((x & 0x000000f0) != 0x000000f0) \
178 local_irq_enable(); \
179} while (0)
180#endif
181
182#define really_restore_flags(x) do { \
183 if ((x & 0x000000f0) != 0x000000f0) \
184 local_irq_enable(); \
185 else \
186 local_irq_disable(); \
187} while (0)
188
189/*
190 * Jump to P2 area.
191 * When handling TLB or caches, we need to do it from P2 area.
192 */
193#define jump_to_P2() \
194do { \
195 unsigned long __dummy; \
196 __asm__ __volatile__( \
197 "mov.l 1f, %0\n\t" \
198 "or %1, %0\n\t" \
199 "jmp @%0\n\t" \
200 " nop\n\t" \
201 ".balign 4\n" \
202 "1: .long 2f\n" \
203 "2:" \
204 : "=&r" (__dummy) \
205 : "r" (0x20000000)); \
206} while (0)
207
208/*
209 * Back to P1 area.
210 */
211#define back_to_P1() \
212do { \
213 unsigned long __dummy; \
214 __asm__ __volatile__( \
215 "nop;nop;nop;nop;nop;nop;nop\n\t" \
216 "mov.l 1f, %0\n\t" \
217 "jmp @%0\n\t" \
218 " nop\n\t" \
219 ".balign 4\n" \
220 "1: .long 2f\n" \
221 "2:" \
222 : "=&r" (__dummy)); \
223} while (0)
224
225/* For spinlocks etc */
226#define local_irq_save(x) x = local_irq_save()
227
228static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
229{
230 unsigned long flags, retval;
231
232 local_irq_save(flags);
233 retval = *m;
234 *m = val;
235 local_irq_restore(flags);
236 return retval;
237}
238
239static __inline__ unsigned long xchg_u8(volatile unsigned char * m, unsigned long val)
240{
241 unsigned long flags, retval;
242
243 local_irq_save(flags);
244 retval = *m;
245 *m = val & 0xff;
246 local_irq_restore(flags);
247 return retval;
248}
249
250static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
251{
252 switch (size) {
253 case 4:
254 return xchg_u32(ptr, x);
255 break;
256 case 1:
257 return xchg_u8(ptr, x);
258 break;
259 }
260 __xchg_called_with_bad_pointer();
261 return x;
262}
263
Tom Rinie4e3b5c2006-09-27 11:28:20 +0900264static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
265 unsigned long new)
266{
267 __u32 retval;
268 unsigned long flags;
269
270 local_irq_save(flags);
271 retval = *m;
272 if (retval == old)
273 *m = new;
274 local_irq_restore(flags); /* implies memory barrier */
275 return retval;
276}
277
278/* This function doesn't exist, so you'll get a linker error
279 * if something tries to do an invalid cmpxchg(). */
280extern void __cmpxchg_called_with_bad_pointer(void);
281
282#define __HAVE_ARCH_CMPXCHG 1
283
284static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
285 unsigned long new, int size)
286{
287 switch (size) {
288 case 4:
289 return __cmpxchg_u32(ptr, old, new);
290 }
291 __cmpxchg_called_with_bad_pointer();
292 return old;
293}
294
295#define cmpxchg(ptr,o,n) \
296 ({ \
297 __typeof__(*(ptr)) _o_ = (o); \
298 __typeof__(*(ptr)) _n_ = (n); \
299 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
300 (unsigned long)_n_, sizeof(*(ptr))); \
301 })
302
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303/* XXX
304 * disable hlt during certain critical i/o operations
305 */
306#define HAVE_DISABLE_HLT
307void disable_hlt(void);
308void enable_hlt(void);
309
310#define arch_align_stack(x) (x)
311
312#endif