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gerrit-public.fairphone.software / kernel / msm-4.19 / e59bff9af4f8e6093909df605f31400eb8bf6c20 / . / arch / arm / boot / dts / imx28.dtsi
blob: 4e073e8547425ee189a6c91331ade03052e1d999 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Michael Heimpold25fc2282014-03-27 23:51:29 +0100[diff] [blame]12#include <dt-bindings/gpio/gpio.h>
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]13#include "skeleton.dtsi"
14#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]15
16/ {
17 interrupt-parent = <&icoll>;
18
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]19 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]20 ethernet0 = &mac0;
21 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]27 saif0 = &saif0;
28 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]29 serial0 = &auart0;
30 serial1 = &auart1;
31 serial2 = &auart2;
32 serial3 = &auart3;
33 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]34 spi0 = &ssp1;
35 spi1 = &ssp2;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]36 usbphy0 = &usbphy0;
37 usbphy1 = &usbphy1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]38 };
39
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]40 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]41 #address-cells = <0>;
42 #size-cells = <0>;
43
44 cpu {
45 compatible = "arm,arm926ej-s";
46 device_type = "cpu";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]47 };
48 };
49
50 apb@80000000 {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 reg = <0x80000000 0x80000>;
55 ranges;
56
57 apbh@80000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x80000000 0x3c900>;
62 ranges;
63
64 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]65 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x80000000 0x2000>;
69 };
70
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]71 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]72 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]73 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]74 dmas = <&dma_apbh 12>;
75 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]76 status = "disabled";
77 };
78
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]79 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]80 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]81 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]82 interrupts = <82 83 84 85
83 88 88 88 88
84 88 88 88 88
85 87 86 0 0>;
86 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
87 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
88 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
89 "hsadc", "lcdif", "empty", "empty";
90 #dma-cells = <1>;
91 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]92 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]93 };
94
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]95 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]96 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]97 interrupts = <27>;
98 status = "disabled";
99 };
100
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]101 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]102 compatible = "fsl,imx28-gpmi-nand";
103 #address-cells = <1>;
104 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]105 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]106 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]107 interrupts = <41>;
108 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]109 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]110 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]111 dmas = <&dma_apbh 4>;
112 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]113 status = "disabled";
114 };
115
116 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]117 #address-cells = <1>;
118 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]119 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]120 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]121 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]122 dmas = <&dma_apbh 0>;
123 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]124 status = "disabled";
125 };
126
127 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]128 #address-cells = <1>;
129 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]130 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]131 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]132 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]133 dmas = <&dma_apbh 1>;
134 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]135 status = "disabled";
136 };
137
138 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]139 #address-cells = <1>;
140 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]141 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]142 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]143 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]144 dmas = <&dma_apbh 2>;
145 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]146 status = "disabled";
147 };
148
149 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]150 #address-cells = <1>;
151 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]152 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]153 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]154 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]155 dmas = <&dma_apbh 3>;
156 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]157 status = "disabled";
158 };
159
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]160 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]163 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]164 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]165
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]166 gpio0: gpio@0 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupts = <127>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpio1: gpio@1 {
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupts = <126>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
183
184 gpio2: gpio@2 {
185 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
186 interrupts = <125>;
187 gpio-controller;
188 #gpio-cells = <2>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 };
192
193 gpio3: gpio@3 {
194 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
195 interrupts = <124>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 };
201
202 gpio4: gpio@4 {
203 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
204 interrupts = <123>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 };
210
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]211 duart_pins_a: duart@0 {
212 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]213 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]214 MX28_PAD_PWM0__DUART_RX
215 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]216 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]217 fsl,drive-strength = <MXS_DRIVE_4mA>;
218 fsl,voltage = <MXS_VOLTAGE_HIGH>;
219 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]220 };
221
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]222 duart_pins_b: duart@1 {
223 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]224 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]225 MX28_PAD_AUART0_CTS__DUART_RX
226 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]227 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]228 fsl,drive-strength = <MXS_DRIVE_4mA>;
229 fsl,voltage = <MXS_VOLTAGE_HIGH>;
230 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]231 };
232
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]233 duart_4pins_a: duart-4pins@0 {
234 reg = <0>;
235 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]236 MX28_PAD_AUART0_CTS__DUART_RX
237 MX28_PAD_AUART0_RTS__DUART_TX
238 MX28_PAD_AUART0_RX__DUART_CTS
239 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]240 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]241 fsl,drive-strength = <MXS_DRIVE_4mA>;
242 fsl,voltage = <MXS_VOLTAGE_HIGH>;
243 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]244 };
245
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]246 gpmi_pins_a: gpmi-nand@0 {
247 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]248 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]249 MX28_PAD_GPMI_D00__GPMI_D0
250 MX28_PAD_GPMI_D01__GPMI_D1
251 MX28_PAD_GPMI_D02__GPMI_D2
252 MX28_PAD_GPMI_D03__GPMI_D3
253 MX28_PAD_GPMI_D04__GPMI_D4
254 MX28_PAD_GPMI_D05__GPMI_D5
255 MX28_PAD_GPMI_D06__GPMI_D6
256 MX28_PAD_GPMI_D07__GPMI_D7
257 MX28_PAD_GPMI_CE0N__GPMI_CE0N
258 MX28_PAD_GPMI_RDY0__GPMI_READY0
259 MX28_PAD_GPMI_RDN__GPMI_RDN
260 MX28_PAD_GPMI_WRN__GPMI_WRN
261 MX28_PAD_GPMI_ALE__GPMI_ALE
262 MX28_PAD_GPMI_CLE__GPMI_CLE
263 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]264 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]265 fsl,drive-strength = <MXS_DRIVE_4mA>;
266 fsl,voltage = <MXS_VOLTAGE_HIGH>;
267 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]268 };
269
270 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]271 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]272 MX28_PAD_GPMI_RDN__GPMI_RDN
273 MX28_PAD_GPMI_WRN__GPMI_WRN
274 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]275 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]276 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]277 };
278
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]279 auart0_pins_a: auart0@0 {
280 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]281 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]282 MX28_PAD_AUART0_RX__AUART0_RX
283 MX28_PAD_AUART0_TX__AUART0_TX
284 MX28_PAD_AUART0_CTS__AUART0_CTS
285 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]286 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]287 fsl,drive-strength = <MXS_DRIVE_4mA>;
288 fsl,voltage = <MXS_VOLTAGE_HIGH>;
289 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]290 };
291
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]292 auart0_2pins_a: auart0-2pins@0 {
293 reg = <0>;
294 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]295 MX28_PAD_AUART0_RX__AUART0_RX
296 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]297 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]298 fsl,drive-strength = <MXS_DRIVE_4mA>;
299 fsl,voltage = <MXS_VOLTAGE_HIGH>;
300 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]301 };
302
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]303 auart1_pins_a: auart1@0 {
304 reg = <0>;
305 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]306 MX28_PAD_AUART1_RX__AUART1_RX
307 MX28_PAD_AUART1_TX__AUART1_TX
308 MX28_PAD_AUART1_CTS__AUART1_CTS
309 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]310 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]311 fsl,drive-strength = <MXS_DRIVE_4mA>;
312 fsl,voltage = <MXS_VOLTAGE_HIGH>;
313 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]314 };
315
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]316 auart1_2pins_a: auart1-2pins@0 {
317 reg = <0>;
318 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]319 MX28_PAD_AUART1_RX__AUART1_RX
320 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]321 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]322 fsl,drive-strength = <MXS_DRIVE_4mA>;
323 fsl,voltage = <MXS_VOLTAGE_HIGH>;
324 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]325 };
326
327 auart2_2pins_a: auart2-2pins@0 {
328 reg = <0>;
329 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]330 MX28_PAD_SSP2_SCK__AUART2_RX
331 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]332 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]333 fsl,drive-strength = <MXS_DRIVE_4mA>;
334 fsl,voltage = <MXS_VOLTAGE_HIGH>;
335 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]336 };
337
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]338 auart2_2pins_b: auart2-2pins@1 {
339 reg = <1>;
340 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]341 MX28_PAD_AUART2_RX__AUART2_RX
342 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]343 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]344 fsl,drive-strength = <MXS_DRIVE_4mA>;
345 fsl,voltage = <MXS_VOLTAGE_HIGH>;
346 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]347 };
348
Aida Mynzhasovacd0214c2013-10-23 10:58:57 +0400[diff] [blame]349 auart2_pins_a: auart2-pins@0 {
350 reg = <0>;
351 fsl,pinmux-ids = <
352 MX28_PAD_AUART2_RX__AUART2_RX
353 MX28_PAD_AUART2_TX__AUART2_TX
354 MX28_PAD_AUART2_CTS__AUART2_CTS
355 MX28_PAD_AUART2_RTS__AUART2_RTS
356 >;
357 fsl,drive-strength = <MXS_DRIVE_4mA>;
358 fsl,voltage = <MXS_VOLTAGE_HIGH>;
359 fsl,pull-up = <MXS_PULL_DISABLE>;
360 };
361
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]362 auart3_pins_a: auart3@0 {
363 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]364 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]365 MX28_PAD_AUART3_RX__AUART3_RX
366 MX28_PAD_AUART3_TX__AUART3_TX
367 MX28_PAD_AUART3_CTS__AUART3_CTS
368 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]369 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]370 fsl,drive-strength = <MXS_DRIVE_4mA>;
371 fsl,voltage = <MXS_VOLTAGE_HIGH>;
372 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]373 };
374
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]375 auart3_2pins_a: auart3-2pins@0 {
376 reg = <0>;
377 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]378 MX28_PAD_SSP2_MISO__AUART3_RX
379 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]380 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]381 fsl,drive-strength = <MXS_DRIVE_4mA>;
382 fsl,voltage = <MXS_VOLTAGE_HIGH>;
383 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]384 };
385
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]386 auart3_2pins_b: auart3-2pins@1 {
387 reg = <1>;
388 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]389 MX28_PAD_AUART3_RX__AUART3_RX
390 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]391 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]392 fsl,drive-strength = <MXS_DRIVE_4mA>;
393 fsl,voltage = <MXS_VOLTAGE_HIGH>;
394 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]395 };
396
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]397 auart4_2pins_a: auart4@0 {
398 reg = <0>;
399 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]400 MX28_PAD_SSP3_SCK__AUART4_TX
401 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]402 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]403 fsl,drive-strength = <MXS_DRIVE_4mA>;
404 fsl,voltage = <MXS_VOLTAGE_HIGH>;
405 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]406 };
407
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]408 mac0_pins_a: mac0@0 {
409 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]410 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]411 MX28_PAD_ENET0_MDC__ENET0_MDC
412 MX28_PAD_ENET0_MDIO__ENET0_MDIO
413 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
414 MX28_PAD_ENET0_RXD0__ENET0_RXD0
415 MX28_PAD_ENET0_RXD1__ENET0_RXD1
416 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
417 MX28_PAD_ENET0_TXD0__ENET0_TXD0
418 MX28_PAD_ENET0_TXD1__ENET0_TXD1
419 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]420 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]421 fsl,drive-strength = <MXS_DRIVE_8mA>;
422 fsl,voltage = <MXS_VOLTAGE_HIGH>;
423 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]424 };
425
426 mac1_pins_a: mac1@0 {
427 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]428 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]429 MX28_PAD_ENET0_CRS__ENET1_RX_EN
430 MX28_PAD_ENET0_RXD2__ENET1_RXD0
431 MX28_PAD_ENET0_RXD3__ENET1_RXD1
432 MX28_PAD_ENET0_COL__ENET1_TX_EN
433 MX28_PAD_ENET0_TXD2__ENET1_TXD0
434 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]435 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]436 fsl,drive-strength = <MXS_DRIVE_8mA>;
437 fsl,voltage = <MXS_VOLTAGE_HIGH>;
438 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]439 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]440
441 mmc0_8bit_pins_a: mmc0-8bit@0 {
442 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]443 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]444 MX28_PAD_SSP0_DATA0__SSP0_D0
445 MX28_PAD_SSP0_DATA1__SSP0_D1
446 MX28_PAD_SSP0_DATA2__SSP0_D2
447 MX28_PAD_SSP0_DATA3__SSP0_D3
448 MX28_PAD_SSP0_DATA4__SSP0_D4
449 MX28_PAD_SSP0_DATA5__SSP0_D5
450 MX28_PAD_SSP0_DATA6__SSP0_D6
451 MX28_PAD_SSP0_DATA7__SSP0_D7
452 MX28_PAD_SSP0_CMD__SSP0_CMD
453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
454 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]455 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]456 fsl,drive-strength = <MXS_DRIVE_8mA>;
457 fsl,voltage = <MXS_VOLTAGE_HIGH>;
458 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]459 };
460
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]461 mmc0_4bit_pins_a: mmc0-4bit@0 {
462 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]463 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]464 MX28_PAD_SSP0_DATA0__SSP0_D0
465 MX28_PAD_SSP0_DATA1__SSP0_D1
466 MX28_PAD_SSP0_DATA2__SSP0_D2
467 MX28_PAD_SSP0_DATA3__SSP0_D3
468 MX28_PAD_SSP0_CMD__SSP0_CMD
469 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
470 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]471 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]472 fsl,drive-strength = <MXS_DRIVE_8mA>;
473 fsl,voltage = <MXS_VOLTAGE_HIGH>;
474 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]475 };
476
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]477 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]478 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]479 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]480 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]481 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]482 };
483
484 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]485 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]486 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]487 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]488 fsl,drive-strength = <MXS_DRIVE_12mA>;
489 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]490 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]491
Marc Kleine-Budde77d63862014-08-08 11:24:21 +0200[diff] [blame]492 mmc1_4bit_pins_a: mmc1-4bit@0 {
493 reg = <0>;
494 fsl,pinmux-ids = <
495 MX28_PAD_GPMI_D00__SSP1_D0
496 MX28_PAD_GPMI_D01__SSP1_D1
497 MX28_PAD_GPMI_D02__SSP1_D2
498 MX28_PAD_GPMI_D03__SSP1_D3
499 MX28_PAD_GPMI_RDY1__SSP1_CMD
500 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
501 MX28_PAD_GPMI_WRN__SSP1_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_8mA>;
504 fsl,voltage = <MXS_VOLTAGE_HIGH>;
505 fsl,pull-up = <MXS_PULL_ENABLE>;
506 };
507
508 mmc1_cd_cfg: mmc1-cd-cfg {
509 fsl,pinmux-ids = <
510 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
511 >;
512 fsl,pull-up = <MXS_PULL_DISABLE>;
513 };
514
515 mmc1_sck_cfg: mmc1-sck-cfg {
516 fsl,pinmux-ids = <
517 MX28_PAD_GPMI_WRN__SSP1_SCK
518 >;
519 fsl,drive-strength = <MXS_DRIVE_12mA>;
520 fsl,pull-up = <MXS_PULL_DISABLE>;
521 };
522
523
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]524 mmc2_4bit_pins_a: mmc2-4bit@0 {
525 reg = <0>;
526 fsl,pinmux-ids = <
527 MX28_PAD_SSP0_DATA4__SSP2_D0
528 MX28_PAD_SSP1_SCK__SSP2_D1
529 MX28_PAD_SSP1_CMD__SSP2_D2
530 MX28_PAD_SSP0_DATA5__SSP2_D3
531 MX28_PAD_SSP0_DATA6__SSP2_CMD
532 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
533 MX28_PAD_SSP0_DATA7__SSP2_SCK
534 >;
535 fsl,drive-strength = <MXS_DRIVE_8mA>;
536 fsl,voltage = <MXS_VOLTAGE_HIGH>;
537 fsl,pull-up = <MXS_PULL_ENABLE>;
538 };
539
540 mmc2_cd_cfg: mmc2-cd-cfg {
541 fsl,pinmux-ids = <
542 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
543 >;
544 fsl,pull-up = <MXS_PULL_DISABLE>;
545 };
546
547 mmc2_sck_cfg: mmc2-sck-cfg {
548 fsl,pinmux-ids = <
549 MX28_PAD_SSP0_DATA7__SSP2_SCK
550 >;
551 fsl,drive-strength = <MXS_DRIVE_12mA>;
552 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]553 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]554
555 i2c0_pins_a: i2c0@0 {
556 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]557 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]558 MX28_PAD_I2C0_SCL__I2C0_SCL
559 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]560 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]561 fsl,drive-strength = <MXS_DRIVE_8mA>;
562 fsl,voltage = <MXS_VOLTAGE_HIGH>;
563 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]564 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]565
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]566 i2c0_pins_b: i2c0@1 {
567 reg = <1>;
568 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]569 MX28_PAD_AUART0_RX__I2C0_SCL
570 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]571 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]572 fsl,drive-strength = <MXS_DRIVE_8mA>;
573 fsl,voltage = <MXS_VOLTAGE_HIGH>;
574 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]575 };
576
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]577 i2c1_pins_a: i2c1@0 {
578 reg = <0>;
579 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]580 MX28_PAD_PWM0__I2C1_SCL
581 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]582 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]583 fsl,drive-strength = <MXS_DRIVE_8mA>;
584 fsl,voltage = <MXS_VOLTAGE_HIGH>;
585 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]586 };
587
Uwe Kleine-König17c63dd2014-08-08 11:24:22 +0200[diff] [blame]588 i2c1_pins_b: i2c1@1 {
589 reg = <1>;
590 fsl,pinmux-ids = <
591 MX28_PAD_AUART2_CTS__I2C1_SCL
592 MX28_PAD_AUART2_RTS__I2C1_SDA
593 >;
594 fsl,drive-strength = <MXS_DRIVE_8mA>;
595 fsl,voltage = <MXS_VOLTAGE_HIGH>;
596 fsl,pull-up = <MXS_PULL_ENABLE>;
597 };
598
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]599 saif0_pins_a: saif0@0 {
600 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]601 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]602 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
603 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
604 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
605 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]606 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]607 fsl,drive-strength = <MXS_DRIVE_12mA>;
608 fsl,voltage = <MXS_VOLTAGE_HIGH>;
609 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]610 };
611
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]612 saif0_pins_b: saif0@1 {
613 reg = <1>;
614 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]615 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
616 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
617 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]618 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]619 fsl,drive-strength = <MXS_DRIVE_12mA>;
620 fsl,voltage = <MXS_VOLTAGE_HIGH>;
621 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]622 };
623
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]624 saif1_pins_a: saif1@0 {
625 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]626 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]627 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]628 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]629 fsl,drive-strength = <MXS_DRIVE_12mA>;
630 fsl,voltage = <MXS_VOLTAGE_HIGH>;
631 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]632 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]633
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]634 pwm0_pins_a: pwm0@0 {
635 reg = <0>;
636 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]637 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]638 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]639 fsl,drive-strength = <MXS_DRIVE_4mA>;
640 fsl,voltage = <MXS_VOLTAGE_HIGH>;
641 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]642 };
643
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]644 pwm2_pins_a: pwm2@0 {
645 reg = <0>;
646 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]647 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]648 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]649 fsl,drive-strength = <MXS_DRIVE_4mA>;
650 fsl,voltage = <MXS_VOLTAGE_HIGH>;
651 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]652 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]653
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]654 pwm3_pins_a: pwm3@0 {
655 reg = <0>;
656 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]657 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]658 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]659 fsl,drive-strength = <MXS_DRIVE_4mA>;
660 fsl,voltage = <MXS_VOLTAGE_HIGH>;
661 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]662 };
663
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]664 pwm3_pins_b: pwm3@1 {
665 reg = <1>;
666 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]667 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]668 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]669 fsl,drive-strength = <MXS_DRIVE_4mA>;
670 fsl,voltage = <MXS_VOLTAGE_HIGH>;
671 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]672 };
673
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]674 pwm4_pins_a: pwm4@0 {
675 reg = <0>;
676 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]677 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]678 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]679 fsl,drive-strength = <MXS_DRIVE_4mA>;
680 fsl,voltage = <MXS_VOLTAGE_HIGH>;
681 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]682 };
683
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]684 lcdif_24bit_pins_a: lcdif-24bit@0 {
685 reg = <0>;
686 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]687 MX28_PAD_LCD_D00__LCD_D0
688 MX28_PAD_LCD_D01__LCD_D1
689 MX28_PAD_LCD_D02__LCD_D2
690 MX28_PAD_LCD_D03__LCD_D3
691 MX28_PAD_LCD_D04__LCD_D4
692 MX28_PAD_LCD_D05__LCD_D5
693 MX28_PAD_LCD_D06__LCD_D6
694 MX28_PAD_LCD_D07__LCD_D7
695 MX28_PAD_LCD_D08__LCD_D8
696 MX28_PAD_LCD_D09__LCD_D9
697 MX28_PAD_LCD_D10__LCD_D10
698 MX28_PAD_LCD_D11__LCD_D11
699 MX28_PAD_LCD_D12__LCD_D12
700 MX28_PAD_LCD_D13__LCD_D13
701 MX28_PAD_LCD_D14__LCD_D14
702 MX28_PAD_LCD_D15__LCD_D15
703 MX28_PAD_LCD_D16__LCD_D16
704 MX28_PAD_LCD_D17__LCD_D17
705 MX28_PAD_LCD_D18__LCD_D18
706 MX28_PAD_LCD_D19__LCD_D19
707 MX28_PAD_LCD_D20__LCD_D20
708 MX28_PAD_LCD_D21__LCD_D21
709 MX28_PAD_LCD_D22__LCD_D22
710 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]711 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]712 fsl,drive-strength = <MXS_DRIVE_4mA>;
713 fsl,voltage = <MXS_VOLTAGE_HIGH>;
714 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]715 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]716
Denis Carikliec985eb2013-12-05 14:28:04 +0100[diff] [blame]717 lcdif_18bit_pins_a: lcdif-18bit@0 {
718 reg = <0>;
719 fsl,pinmux-ids = <
720 MX28_PAD_LCD_D00__LCD_D0
721 MX28_PAD_LCD_D01__LCD_D1
722 MX28_PAD_LCD_D02__LCD_D2
723 MX28_PAD_LCD_D03__LCD_D3
724 MX28_PAD_LCD_D04__LCD_D4
725 MX28_PAD_LCD_D05__LCD_D5
726 MX28_PAD_LCD_D06__LCD_D6
727 MX28_PAD_LCD_D07__LCD_D7
728 MX28_PAD_LCD_D08__LCD_D8
729 MX28_PAD_LCD_D09__LCD_D9
730 MX28_PAD_LCD_D10__LCD_D10
731 MX28_PAD_LCD_D11__LCD_D11
732 MX28_PAD_LCD_D12__LCD_D12
733 MX28_PAD_LCD_D13__LCD_D13
734 MX28_PAD_LCD_D14__LCD_D14
735 MX28_PAD_LCD_D15__LCD_D15
736 MX28_PAD_LCD_D16__LCD_D16
737 MX28_PAD_LCD_D17__LCD_D17
738 >;
739 fsl,drive-strength = <MXS_DRIVE_4mA>;
740 fsl,voltage = <MXS_VOLTAGE_HIGH>;
741 fsl,pull-up = <MXS_PULL_DISABLE>;
742 };
743
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]744 lcdif_16bit_pins_a: lcdif-16bit@0 {
745 reg = <0>;
746 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]747 MX28_PAD_LCD_D00__LCD_D0
748 MX28_PAD_LCD_D01__LCD_D1
749 MX28_PAD_LCD_D02__LCD_D2
750 MX28_PAD_LCD_D03__LCD_D3
751 MX28_PAD_LCD_D04__LCD_D4
752 MX28_PAD_LCD_D05__LCD_D5
753 MX28_PAD_LCD_D06__LCD_D6
754 MX28_PAD_LCD_D07__LCD_D7
755 MX28_PAD_LCD_D08__LCD_D8
756 MX28_PAD_LCD_D09__LCD_D9
757 MX28_PAD_LCD_D10__LCD_D10
758 MX28_PAD_LCD_D11__LCD_D11
759 MX28_PAD_LCD_D12__LCD_D12
760 MX28_PAD_LCD_D13__LCD_D13
761 MX28_PAD_LCD_D14__LCD_D14
762 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]763 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]764 fsl,drive-strength = <MXS_DRIVE_4mA>;
765 fsl,voltage = <MXS_VOLTAGE_HIGH>;
766 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]767 };
768
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]769 lcdif_sync_pins_a: lcdif-sync@0 {
770 reg = <0>;
771 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]772 MX28_PAD_LCD_RS__LCD_DOTCLK
773 MX28_PAD_LCD_CS__LCD_ENABLE
774 MX28_PAD_LCD_RD_E__LCD_VSYNC
775 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]776 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]777 fsl,drive-strength = <MXS_DRIVE_4mA>;
778 fsl,voltage = <MXS_VOLTAGE_HIGH>;
779 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]780 };
781
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]782 can0_pins_a: can0@0 {
783 reg = <0>;
784 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]785 MX28_PAD_GPMI_RDY2__CAN0_TX
786 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]787 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]788 fsl,drive-strength = <MXS_DRIVE_4mA>;
789 fsl,voltage = <MXS_VOLTAGE_HIGH>;
790 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]791 };
792
793 can1_pins_a: can1@0 {
794 reg = <0>;
795 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]796 MX28_PAD_GPMI_CE2N__CAN1_TX
797 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]798 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]799 fsl,drive-strength = <MXS_DRIVE_4mA>;
800 fsl,voltage = <MXS_VOLTAGE_HIGH>;
801 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]802 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]803
804 spi2_pins_a: spi2@0 {
805 reg = <0>;
806 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]807 MX28_PAD_SSP2_SCK__SSP2_SCK
808 MX28_PAD_SSP2_MOSI__SSP2_CMD
809 MX28_PAD_SSP2_MISO__SSP2_D0
810 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]811 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]812 fsl,drive-strength = <MXS_DRIVE_8mA>;
813 fsl,voltage = <MXS_VOLTAGE_HIGH>;
814 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]815 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]816
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]817 spi3_pins_a: spi3@0 {
818 reg = <0>;
819 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]820 MX28_PAD_AUART2_RX__SSP3_D4
821 MX28_PAD_AUART2_TX__SSP3_D5
822 MX28_PAD_SSP3_SCK__SSP3_SCK
823 MX28_PAD_SSP3_MOSI__SSP3_CMD
824 MX28_PAD_SSP3_MISO__SSP3_D0
825 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]826 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]827 fsl,drive-strength = <MXS_DRIVE_8mA>;
828 fsl,voltage = <MXS_VOLTAGE_HIGH>;
829 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]830 };
831
Uwe Kleine-König8f0b07a2015-03-19 10:55:47 +0100[diff] [blame]832 spi3_pins_b: spi3@1 {
833 reg = <1>;
834 fsl,pinmux-ids = <
835 MX28_PAD_SSP3_SCK__SSP3_SCK
836 MX28_PAD_SSP3_MOSI__SSP3_CMD
837 MX28_PAD_SSP3_MISO__SSP3_D0
838 MX28_PAD_SSP3_SS0__SSP3_D3
839 >;
840 fsl,drive-strength = <MXS_DRIVE_8mA>;
841 fsl,voltage = <MXS_VOLTAGE_HIGH>;
842 fsl,pull-up = <MXS_PULL_ENABLE>;
843 };
844
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]845 usb0_pins_a: usb0@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]846 reg = <0>;
847 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]848 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]849 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]850 fsl,drive-strength = <MXS_DRIVE_12mA>;
851 fsl,voltage = <MXS_VOLTAGE_HIGH>;
852 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]853 };
854
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]855 usb0_pins_b: usb0@1 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]856 reg = <1>;
857 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]858 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]859 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]860 fsl,drive-strength = <MXS_DRIVE_12mA>;
861 fsl,voltage = <MXS_VOLTAGE_HIGH>;
862 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]863 };
864
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]865 usb1_pins_a: usb1@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]866 reg = <0>;
867 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]868 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]869 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]870 fsl,drive-strength = <MXS_DRIVE_12mA>;
871 fsl,voltage = <MXS_VOLTAGE_HIGH>;
872 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]873 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]874
875 usb0_id_pins_a: usb0id@0 {
876 reg = <0>;
877 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]878 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]879 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]880 fsl,drive-strength = <MXS_DRIVE_12mA>;
881 fsl,voltage = <MXS_VOLTAGE_HIGH>;
882 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]883 };
Denis Cariklibb89b8d2013-12-05 14:28:05 +0100[diff] [blame]884
885 usb0_id_pins_b: usb0id1@0 {
886 reg = <0>;
887 fsl,pinmux-ids = <
888 MX28_PAD_PWM2__USB0_ID
889 >;
890 fsl,drive-strength = <MXS_DRIVE_12mA>;
891 fsl,voltage = <MXS_VOLTAGE_HIGH>;
892 fsl,pull-up = <MXS_PULL_ENABLE>;
893 };
894
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]895 };
896
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]897 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]898 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]899 reg = <0x8001c000 0x2000>;
900 interrupts = <89>;
901 status = "disabled";
902 };
903
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]904 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]905 reg = <0x80022000 0x2000>;
906 status = "disabled";
907 };
908
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]909 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]910 compatible = "fsl,imx28-dma-apbx";
911 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]912 interrupts = <78 79 66 0
913 80 81 68 69
914 70 71 72 73
915 74 75 76 77>;
Marek Vasut4ada77e2015-04-24 13:29:47 +0200[diff] [blame]916 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]917 "saif0", "saif1", "i2c0", "i2c1",
918 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
919 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
920 #dma-cells = <1>;
921 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]922 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]923 };
924
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]925 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]926 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]927 reg = <0x80028000 0x2000>;
928 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]929 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]930 };
931
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]932 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]933 reg = <0x8002a000 0x2000>;
934 interrupts = <39>;
935 status = "disabled";
936 };
937
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]938 ocotp: ocotp@8002c000 {
Shawn Guo69d75a02013-03-29 09:59:28 +0800[diff] [blame]939 compatible = "fsl,ocotp";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]940 reg = <0x8002c000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]941 status = "disabled";
942 };
943
944 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]945 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]946 status = "disabled";
947 };
948
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]949 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]950 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]951 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]952 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]953 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]954 dmas = <&dma_apbh 13>;
955 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]956 status = "disabled";
957 };
958
959 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]960 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]961 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]962 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]963 clocks = <&clks 58>, <&clks 58>;
964 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]965 status = "disabled";
966 };
967
968 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]969 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]970 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]971 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]972 clocks = <&clks 59>, <&clks 59>;
973 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]974 status = "disabled";
975 };
976
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]977 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]978 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]979 status = "disabled";
980 };
981
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]982 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]983 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]984 status = "disabled";
985 };
986
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]987 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]988 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]989 status = "disabled";
990 };
991
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]992 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]993 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]994 status = "disabled";
995 };
996
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]997 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]998 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]999 status = "disabled";
1000 };
1001
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1002 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1003 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1004 status = "disabled";
1005 };
1006
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1007 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1008 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1009 status = "disabled";
1010 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]1011 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1012
1013 apbx@80040000 {
1014 compatible = "simple-bus";
1015 #address-cells = <1>;
1016 #size-cells = <1>;
1017 reg = <0x80040000 0x40000>;
1018 ranges;
1019
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1020 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]1021 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1022 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1023 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1024 };
1025
1026 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1027 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1028 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1029 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]1030 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1031 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1032 dmas = <&dma_apbx 4>;
1033 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1034 status = "disabled";
1035 };
1036
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1037 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1038 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1039 status = "disabled";
1040 };
1041
1042 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1043 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1044 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1045 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1046 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1047 dmas = <&dma_apbx 5>;
1048 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1049 status = "disabled";
1050 };
1051
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1052 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1053 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1054 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1055 interrupts = <10 14 15 16 17 18 19
1056 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1057 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]1058 clocks = <&clks 41>;
Alexandre Belloni40dde682013-12-06 21:20:31 +0100[diff] [blame]1059 #io-channel-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1060 };
1061
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1062 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1063 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1064 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1065 dmas = <&dma_apbx 2>;
1066 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1067 status = "disabled";
1068 };
1069
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1070 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1071 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1072 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1073 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1074 };
1075
1076 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1080 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1081 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1082 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1083 dmas = <&dma_apbx 6>;
1084 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1085 status = "disabled";
1086 };
1087
1088 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1092 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1093 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1094 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1095 dmas = <&dma_apbx 7>;
1096 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1097 status = "disabled";
1098 };
1099
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1100 pwm: pwm@80064000 {
1101 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1102 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1103 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1104 #pwm-cells = <2>;
1105 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1106 status = "disabled";
1107 };
1108
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1109 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1110 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1111 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1112 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1113 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1114 };
1115
1116 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1117 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1118 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1119 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1120 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1121 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1122 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1123 status = "disabled";
1124 };
1125
1126 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1127 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1128 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1129 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1130 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1131 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1132 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1133 status = "disabled";
1134 };
1135
1136 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1137 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1138 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1139 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1140 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1141 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1142 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1143 status = "disabled";
1144 };
1145
1146 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1147 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1148 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1149 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1150 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1151 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1152 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1153 status = "disabled";
1154 };
1155
1156 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1157 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1158 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1159 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1160 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1161 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1162 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1163 status = "disabled";
1164 };
1165
1166 duart: serial@80074000 {
1167 compatible = "arm,pl011", "arm,primecell";
1168 reg = <0x80074000 0x1000>;
1169 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1170 clocks = <&clks 45>, <&clks 26>;
1171 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1172 status = "disabled";
1173 };
1174
1175 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1176 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1177 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1178 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1179 status = "disabled";
1180 };
1181
1182 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1183 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1184 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1185 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1186 status = "disabled";
1187 };
1188 };
1189 };
1190
1191 ahb@80080000 {
1192 compatible = "simple-bus";
1193 #address-cells = <1>;
1194 #size-cells = <1>;
1195 reg = <0x80080000 0x80000>;
1196 ranges;
1197
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1198 usb0: usb@80080000 {
1199 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1200 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1201 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1202 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1203 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1204 status = "disabled";
1205 };
1206
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1207 usb1: usb@80090000 {
1208 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1209 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1210 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1211 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1212 fsl,usbphy = <&usbphy1>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]1213 dr_mode = "host";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1214 status = "disabled";
1215 };
1216
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1217 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1218 reg = <0x800c0000 0x10000>;
1219 status = "disabled";
1220 };
1221
1222 mac0: ethernet@800f0000 {
1223 compatible = "fsl,imx28-fec";
1224 reg = <0x800f0000 0x4000>;
1225 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1226 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1227 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1228 status = "disabled";
1229 };
1230
1231 mac1: ethernet@800f4000 {
1232 compatible = "fsl,imx28-fec";
1233 reg = <0x800f4000 0x4000>;
1234 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1235 clocks = <&clks 57>, <&clks 57>;
1236 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1237 status = "disabled";
1238 };
1239
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1240 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1241 reg = <0x800f8000 0x8000>;
1242 status = "disabled";
1243 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1244 };
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1245
1246 iio_hwmon {
1247 compatible = "iio-hwmon";
1248 io-channels = <&lradc 8>;
1249 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1250};