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Olof Johansson03d2bfc2011-01-01 23:52:56 -05001/*
2 * Copyright (C) 2010 Google, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
Lucas Stache5c63d92016-02-29 21:56:25 +010015#include <linux/delay.h>
Olof Johansson03d2bfc2011-01-01 23:52:56 -050016#include <linux/err.h>
Paul Gortmaker96547f52011-07-03 15:15:51 -040017#include <linux/module.h>
Olof Johansson03d2bfc2011-01-01 23:52:56 -050018#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
Stephen Warren55cd65e2011-08-30 13:17:16 -060022#include <linux/of.h>
Stephen Warren3e44a1a2012-02-01 16:30:55 -070023#include <linux/of_device.h>
Olof Johansson03d2bfc2011-01-01 23:52:56 -050024#include <linux/mmc/card.h>
25#include <linux/mmc/host.h>
Lucas Stachc3c23842015-12-22 19:41:02 +010026#include <linux/mmc/mmc.h>
Joseph Lo0aacd232013-03-11 14:44:11 -060027#include <linux/mmc/slot-gpio.h>
Mylene JOSSERAND2391b342015-03-30 23:39:25 +020028#include <linux/gpio/consumer.h>
Olof Johansson03d2bfc2011-01-01 23:52:56 -050029
Olof Johansson03d2bfc2011-01-01 23:52:56 -050030#include "sdhci-pltfm.h"
31
Pavan Kunapulica5879d2012-04-18 18:48:02 +053032/* Tegra SDHOST controller vendor register definitions */
Lucas Stach74cd42b2015-12-22 19:41:01 +010033#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
Lucas Stachc3c23842015-12-22 19:41:02 +010034#define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
35#define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
36#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
Lucas Stach74cd42b2015-12-22 19:41:01 +010037#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
38#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
39
Pavan Kunapulica5879d2012-04-18 18:48:02 +053040#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
Andrew Bresticker31453512014-05-22 08:55:35 -070041#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
42#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
Pavan Kunapulica5879d2012-04-18 18:48:02 +053043#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
Andrew Bresticker31453512014-05-22 08:55:35 -070044#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
Pavan Kunapulica5879d2012-04-18 18:48:02 +053045
Lucas Stache5c63d92016-02-29 21:56:25 +010046#define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
47#define SDHCI_AUTO_CAL_START BIT(31)
48#define SDHCI_AUTO_CAL_ENABLE BIT(29)
49
Stephen Warren3e44a1a2012-02-01 16:30:55 -070050#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
51#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
Pavan Kunapulica5879d2012-04-18 18:48:02 +053052#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
Lucas Stach7ad2ed12015-12-22 19:41:03 +010053#define NVQUIRK_ENABLE_SDR50 BIT(3)
54#define NVQUIRK_ENABLE_SDR104 BIT(4)
55#define NVQUIRK_ENABLE_DDR50 BIT(5)
Lucas Stache5c63d92016-02-29 21:56:25 +010056#define NVQUIRK_HAS_PADCALIB BIT(6)
Stephen Warren3e44a1a2012-02-01 16:30:55 -070057
58struct sdhci_tegra_soc_data {
Lars-Peter Clausen1db5eeb2013-03-13 19:26:03 +010059 const struct sdhci_pltfm_data *pdata;
Stephen Warren3e44a1a2012-02-01 16:30:55 -070060 u32 nvquirks;
61};
62
63struct sdhci_tegra {
Stephen Warren3e44a1a2012-02-01 16:30:55 -070064 const struct sdhci_tegra_soc_data *soc_data;
Mylene JOSSERAND2391b342015-03-30 23:39:25 +020065 struct gpio_desc *power_gpio;
Lucas Stacha8e326a2015-12-22 19:41:00 +010066 bool ddr_signaling;
Lucas Stache5c63d92016-02-29 21:56:25 +010067 bool pad_calib_required;
Stephen Warren3e44a1a2012-02-01 16:30:55 -070068};
69
Olof Johansson03d2bfc2011-01-01 23:52:56 -050070static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
71{
Stephen Warren3e44a1a2012-02-01 16:30:55 -070072 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang0734e792016-02-16 21:08:29 +080073 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
Stephen Warren3e44a1a2012-02-01 16:30:55 -070074 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
75
76 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
77 (reg == SDHCI_HOST_VERSION))) {
Olof Johansson03d2bfc2011-01-01 23:52:56 -050078 /* Erratum: Version register is invalid in HW. */
79 return SDHCI_SPEC_200;
80 }
81
82 return readw(host->ioaddr + reg);
83}
84
Pavan Kunapuli352ee862015-01-28 11:45:16 -050085static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
86{
87 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Pavan Kunapuli352ee862015-01-28 11:45:16 -050088
Rhyland Klein01df7ec2015-02-11 12:55:51 -050089 switch (reg) {
90 case SDHCI_TRANSFER_MODE:
91 /*
92 * Postpone this write, we must do it together with a
93 * command write that is down below.
94 */
95 pltfm_host->xfer_mode_shadow = val;
96 return;
97 case SDHCI_COMMAND:
98 writel((val << 16) | pltfm_host->xfer_mode_shadow,
99 host->ioaddr + SDHCI_TRANSFER_MODE);
100 return;
Pavan Kunapuli352ee862015-01-28 11:45:16 -0500101 }
102
103 writew(val, host->ioaddr + reg);
104}
105
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500106static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
107{
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700108 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang0734e792016-02-16 21:08:29 +0800109 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700110 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
111
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500112 /* Seems like we're getting spurious timeout and crc errors, so
113 * disable signalling of them. In case of real errors software
114 * timers should take care of eventually detecting them.
115 */
116 if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
117 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
118
119 writel(val, host->ioaddr + reg);
120
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700121 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
122 (reg == SDHCI_INT_ENABLE))) {
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500123 /* Erratum: Must enable block gap interrupt detection */
124 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
125 if (val & SDHCI_INT_CARD_INT)
126 gap_ctrl |= 0x8;
127 else
128 gap_ctrl &= ~0x8;
129 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
130 }
131}
132
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700133static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500134{
Joseph Lo0aacd232013-03-11 14:44:11 -0600135 return mmc_gpio_get_ro(host->mmc);
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500136}
137
Russell King03231f92014-04-25 12:57:12 +0100138static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
Pavan Kunapulica5879d2012-04-18 18:48:02 +0530139{
140 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang0734e792016-02-16 21:08:29 +0800141 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
Pavan Kunapulica5879d2012-04-18 18:48:02 +0530142 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
Lucas Stach74cd42b2015-12-22 19:41:01 +0100143 u32 misc_ctrl, clk_ctrl;
Pavan Kunapulica5879d2012-04-18 18:48:02 +0530144
Russell King03231f92014-04-25 12:57:12 +0100145 sdhci_reset(host, mask);
146
Pavan Kunapulica5879d2012-04-18 18:48:02 +0530147 if (!(mask & SDHCI_RESET_ALL))
148 return;
149
Lucas Stach1b84def2015-12-22 19:41:04 +0100150 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
Pavan Kunapulica5879d2012-04-18 18:48:02 +0530151 /* Erratum: Enable SDHCI spec v3.00 support */
Andrew Bresticker31453512014-05-22 08:55:35 -0700152 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
Pavan Kunapulica5879d2012-04-18 18:48:02 +0530153 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
Lucas Stach7ad2ed12015-12-22 19:41:03 +0100154 /* Advertise UHS modes as supported by host */
155 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
156 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
Jon Hunter7bf037d2016-02-26 09:34:17 +0000157 else
158 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
Lucas Stach7ad2ed12015-12-22 19:41:03 +0100159 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
160 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
Jon Hunter7bf037d2016-02-26 09:34:17 +0000161 else
162 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
Lucas Stach7ad2ed12015-12-22 19:41:03 +0100163 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
164 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
Jon Hunter7bf037d2016-02-26 09:34:17 +0000165 else
166 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
Lucas Stach1b84def2015-12-22 19:41:04 +0100167 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
Lucas Stacha8e326a2015-12-22 19:41:00 +0100168
Lucas Stach74cd42b2015-12-22 19:41:01 +0100169 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
170 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
Lucas Stach7ad2ed12015-12-22 19:41:03 +0100171 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
Lucas Stachc3c23842015-12-22 19:41:02 +0100172 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
Lucas Stach74cd42b2015-12-22 19:41:01 +0100173 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
174
Lucas Stache5c63d92016-02-29 21:56:25 +0100175 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
176 tegra_host->pad_calib_required = true;
177
Lucas Stacha8e326a2015-12-22 19:41:00 +0100178 tegra_host->ddr_signaling = false;
Pavan Kunapulica5879d2012-04-18 18:48:02 +0530179}
180
Russell King2317f562014-04-25 12:57:07 +0100181static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500182{
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500183 u32 ctrl;
184
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500185 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Joseph Lo0aacd232013-03-11 14:44:11 -0600186 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
187 (bus_width == MMC_BUS_WIDTH_8)) {
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500188 ctrl &= ~SDHCI_CTRL_4BITBUS;
189 ctrl |= SDHCI_CTRL_8BITBUS;
190 } else {
191 ctrl &= ~SDHCI_CTRL_8BITBUS;
192 if (bus_width == MMC_BUS_WIDTH_4)
193 ctrl |= SDHCI_CTRL_4BITBUS;
194 else
195 ctrl &= ~SDHCI_CTRL_4BITBUS;
196 }
197 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500198}
199
Lucas Stache5c63d92016-02-29 21:56:25 +0100200static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
201{
202 u32 val;
203
204 mdelay(1);
205
206 val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
207 val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
208 sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
209}
210
Lucas Stacha8e326a2015-12-22 19:41:00 +0100211static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
212{
213 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang0734e792016-02-16 21:08:29 +0800214 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
Lucas Stacha8e326a2015-12-22 19:41:00 +0100215 unsigned long host_clk;
216
217 if (!clock)
Lucas Stach3491b692016-02-29 21:56:24 +0100218 return sdhci_set_clock(host, clock);
Lucas Stacha8e326a2015-12-22 19:41:00 +0100219
220 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
221 clk_set_rate(pltfm_host->clk, host_clk);
222 host->max_clk = clk_get_rate(pltfm_host->clk);
223
Lucas Stache5c63d92016-02-29 21:56:25 +0100224 sdhci_set_clock(host, clock);
225
226 if (tegra_host->pad_calib_required) {
227 tegra_sdhci_pad_autocalib(host);
228 tegra_host->pad_calib_required = false;
229 }
Lucas Stacha8e326a2015-12-22 19:41:00 +0100230}
231
232static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
233 unsigned timing)
234{
235 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang0734e792016-02-16 21:08:29 +0800236 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
Lucas Stacha8e326a2015-12-22 19:41:00 +0100237
238 if (timing == MMC_TIMING_UHS_DDR50)
239 tegra_host->ddr_signaling = true;
240
241 return sdhci_set_uhs_signaling(host, timing);
242}
243
244static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
245{
246 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
247
248 /*
249 * DDR modes require the host to run at double the card frequency, so
250 * the maximum rate we can support is half of the module input clock.
251 */
252 return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
253}
254
Lucas Stachc3c23842015-12-22 19:41:02 +0100255static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
256{
257 u32 reg;
258
259 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
260 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
261 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
262 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
263}
264
265static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
266{
267 unsigned int min, max;
268
269 /*
270 * Start search for minimum tap value at 10, as smaller values are
271 * may wrongly be reported as working but fail at higher speeds,
272 * according to the TRM.
273 */
274 min = 10;
275 while (min < 255) {
276 tegra_sdhci_set_tap(host, min);
277 if (!mmc_send_tuning(host->mmc, opcode, NULL))
278 break;
279 min++;
280 }
281
282 /* Find the maximum tap value that still passes. */
283 max = min + 1;
284 while (max < 255) {
285 tegra_sdhci_set_tap(host, max);
286 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
287 max--;
288 break;
289 }
290 max++;
291 }
292
293 /* The TRM states the ideal tap value is at 75% in the passing range. */
294 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
295
296 return mmc_send_tuning(host->mmc, opcode, NULL);
297}
298
Lucas Stache5c63d92016-02-29 21:56:25 +0100299static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
300{
301 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
302 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
303 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
304
305 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
306 tegra_host->pad_calib_required = true;
307}
308
Lars-Peter Clausenc9155682013-03-13 19:26:05 +0100309static const struct sdhci_ops tegra_sdhci_ops = {
Shawn Guo85d65092011-05-27 23:48:12 +0800310 .get_ro = tegra_sdhci_get_ro,
Shawn Guo85d65092011-05-27 23:48:12 +0800311 .read_w = tegra_sdhci_readw,
312 .write_l = tegra_sdhci_writel,
Lucas Stacha8e326a2015-12-22 19:41:00 +0100313 .set_clock = tegra_sdhci_set_clock,
Russell King2317f562014-04-25 12:57:07 +0100314 .set_bus_width = tegra_sdhci_set_bus_width,
Russell King03231f92014-04-25 12:57:12 +0100315 .reset = tegra_sdhci_reset,
Lucas Stachc3c23842015-12-22 19:41:02 +0100316 .platform_execute_tuning = tegra_sdhci_execute_tuning,
Lucas Stacha8e326a2015-12-22 19:41:00 +0100317 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
Lucas Stache5c63d92016-02-29 21:56:25 +0100318 .voltage_switch = tegra_sdhci_voltage_switch,
Lucas Stacha8e326a2015-12-22 19:41:00 +0100319 .get_max_clock = tegra_sdhci_get_max_clock,
Shawn Guo85d65092011-05-27 23:48:12 +0800320};
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500321
Lars-Peter Clausen1db5eeb2013-03-13 19:26:03 +0100322static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
Shawn Guo85d65092011-05-27 23:48:12 +0800323 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
324 SDHCI_QUIRK_SINGLE_POWER_WRITE |
325 SDHCI_QUIRK_NO_HISPD_BIT |
Andrew Brestickerf9260352014-05-22 08:55:36 -0700326 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
327 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
Shawn Guo85d65092011-05-27 23:48:12 +0800328 .ops = &tegra_sdhci_ops,
329};
330
Thierry Redingd49d19c22015-11-16 10:27:14 +0100331static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700332 .pdata = &sdhci_tegra20_pdata,
333 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
334 NVQUIRK_ENABLE_BLOCK_GAP_DET,
335};
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700336
Lars-Peter Clausen1db5eeb2013-03-13 19:26:03 +0100337static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700338 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
339 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
340 SDHCI_QUIRK_SINGLE_POWER_WRITE |
341 SDHCI_QUIRK_NO_HISPD_BIT |
Andrew Brestickerf9260352014-05-22 08:55:36 -0700342 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
343 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
Lucas Stacha8e326a2015-12-22 19:41:00 +0100344 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700345 .ops = &tegra_sdhci_ops,
346};
347
Thierry Redingd49d19c22015-11-16 10:27:14 +0100348static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700349 .pdata = &sdhci_tegra30_pdata,
Andrew Bresticker31453512014-05-22 08:55:35 -0700350 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
Lucas Stach7ad2ed12015-12-22 19:41:03 +0100351 NVQUIRK_ENABLE_SDR50 |
Lucas Stache5c63d92016-02-29 21:56:25 +0100352 NVQUIRK_ENABLE_SDR104 |
353 NVQUIRK_HAS_PADCALIB,
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700354};
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700355
Rhyland Klein01df7ec2015-02-11 12:55:51 -0500356static const struct sdhci_ops tegra114_sdhci_ops = {
357 .get_ro = tegra_sdhci_get_ro,
358 .read_w = tegra_sdhci_readw,
359 .write_w = tegra_sdhci_writew,
360 .write_l = tegra_sdhci_writel,
Lucas Stacha8e326a2015-12-22 19:41:00 +0100361 .set_clock = tegra_sdhci_set_clock,
Rhyland Klein01df7ec2015-02-11 12:55:51 -0500362 .set_bus_width = tegra_sdhci_set_bus_width,
363 .reset = tegra_sdhci_reset,
Lucas Stachc3c23842015-12-22 19:41:02 +0100364 .platform_execute_tuning = tegra_sdhci_execute_tuning,
Lucas Stacha8e326a2015-12-22 19:41:00 +0100365 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
Lucas Stache5c63d92016-02-29 21:56:25 +0100366 .voltage_switch = tegra_sdhci_voltage_switch,
Lucas Stacha8e326a2015-12-22 19:41:00 +0100367 .get_max_clock = tegra_sdhci_get_max_clock,
Rhyland Klein01df7ec2015-02-11 12:55:51 -0500368};
369
Lars-Peter Clausen1db5eeb2013-03-13 19:26:03 +0100370static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
Rhyland Klein5ebf2552013-02-20 13:35:17 -0500371 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
372 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
373 SDHCI_QUIRK_SINGLE_POWER_WRITE |
374 SDHCI_QUIRK_NO_HISPD_BIT |
Andrew Brestickerf9260352014-05-22 08:55:36 -0700375 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
376 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
Lucas Stacha8e326a2015-12-22 19:41:00 +0100377 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
Rhyland Klein01df7ec2015-02-11 12:55:51 -0500378 .ops = &tegra114_sdhci_ops,
Rhyland Klein5ebf2552013-02-20 13:35:17 -0500379};
380
Thierry Redingd49d19c22015-11-16 10:27:14 +0100381static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
Rhyland Klein5ebf2552013-02-20 13:35:17 -0500382 .pdata = &sdhci_tegra114_pdata,
Jon Hunter7bf037d2016-02-26 09:34:17 +0000383};
384
385static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
386 .pdata = &sdhci_tegra114_pdata,
Lucas Stach7ad2ed12015-12-22 19:41:03 +0100387 .nvquirks = NVQUIRK_ENABLE_SDR50 |
388 NVQUIRK_ENABLE_DDR50 |
Lucas Stache5c63d92016-02-29 21:56:25 +0100389 NVQUIRK_ENABLE_SDR104 |
390 NVQUIRK_HAS_PADCALIB,
Rhyland Klein5ebf2552013-02-20 13:35:17 -0500391};
392
Thierry Redingb5a84ec2015-11-16 10:27:15 +0100393static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
394 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
395 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
396 SDHCI_QUIRK_SINGLE_POWER_WRITE |
397 SDHCI_QUIRK_NO_HISPD_BIT |
Lucas Stacha8e326a2015-12-22 19:41:00 +0100398 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
399 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
400 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
Thierry Redingb5a84ec2015-11-16 10:27:15 +0100401 .ops = &tegra114_sdhci_ops,
402};
403
404static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
405 .pdata = &sdhci_tegra210_pdata,
Thierry Redingb5a84ec2015-11-16 10:27:15 +0100406};
407
Bill Pemberton498d83e2012-11-19 13:24:22 -0500408static const struct of_device_id sdhci_tegra_dt_match[] = {
Thierry Redingb5a84ec2015-11-16 10:27:15 +0100409 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
Jon Hunter7bf037d2016-02-26 09:34:17 +0000410 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
Rhyland Klein5ebf2552013-02-20 13:35:17 -0500411 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700412 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700413 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
Grant Likely275173b2011-08-23 12:15:33 -0600414 {}
415};
Arnd Bergmanne4404fa2013-04-23 15:05:57 -0400416MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
Grant Likely275173b2011-08-23 12:15:33 -0600417
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500418static int sdhci_tegra_probe(struct platform_device *pdev)
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500419{
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700420 const struct of_device_id *match;
421 const struct sdhci_tegra_soc_data *soc_data;
422 struct sdhci_host *host;
Shawn Guo85d65092011-05-27 23:48:12 +0800423 struct sdhci_pltfm_host *pltfm_host;
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700424 struct sdhci_tegra *tegra_host;
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500425 struct clk *clk;
426 int rc;
427
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700428 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
Joseph Lob37f9d92012-08-17 15:04:31 +0800429 if (!match)
430 return -EINVAL;
431 soc_data = match->data;
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700432
Jisheng Zhang0734e792016-02-16 21:08:29 +0800433 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
Shawn Guo85d65092011-05-27 23:48:12 +0800434 if (IS_ERR(host))
435 return PTR_ERR(host);
Shawn Guo85d65092011-05-27 23:48:12 +0800436 pltfm_host = sdhci_priv(host);
437
Jisheng Zhang0734e792016-02-16 21:08:29 +0800438 tegra_host = sdhci_pltfm_priv(pltfm_host);
Lucas Stacha8e326a2015-12-22 19:41:00 +0100439 tegra_host->ddr_signaling = false;
Lucas Stache5c63d92016-02-29 21:56:25 +0100440 tegra_host->pad_calib_required = false;
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700441 tegra_host->soc_data = soc_data;
Grant Likely275173b2011-08-23 12:15:33 -0600442
Mylene JOSSERAND2391b342015-03-30 23:39:25 +0200443 rc = mmc_of_parse(host->mmc);
Simon Baatz47caa842013-06-09 22:14:16 +0200444 if (rc)
445 goto err_parse_dt;
Stephen Warren0e786102013-02-15 15:07:19 -0700446
Lucas Stach7ad2ed12015-12-22 19:41:03 +0100447 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
Lucas Stachc3c23842015-12-22 19:41:02 +0100448 host->mmc->caps |= MMC_CAP_1_8V_DDR;
449
Mylene JOSSERAND2391b342015-03-30 23:39:25 +0200450 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
451 GPIOD_OUT_HIGH);
452 if (IS_ERR(tegra_host->power_gpio)) {
453 rc = PTR_ERR(tegra_host->power_gpio);
454 goto err_power_req;
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500455 }
456
Kevin Haoe4f79d92015-02-27 15:47:27 +0800457 clk = devm_clk_get(mmc_dev(host->mmc), NULL);
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500458 if (IS_ERR(clk)) {
459 dev_err(mmc_dev(host->mmc), "clk err\n");
460 rc = PTR_ERR(clk);
Shawn Guo85d65092011-05-27 23:48:12 +0800461 goto err_clk_get;
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500462 }
Prashant Gaikwad1e674bc2012-06-05 09:59:37 +0530463 clk_prepare_enable(clk);
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500464 pltfm_host->clk = clk;
465
Shawn Guo85d65092011-05-27 23:48:12 +0800466 rc = sdhci_add_host(host);
467 if (rc)
468 goto err_add_host;
469
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500470 return 0;
471
Shawn Guo85d65092011-05-27 23:48:12 +0800472err_add_host:
Prashant Gaikwad1e674bc2012-06-05 09:59:37 +0530473 clk_disable_unprepare(pltfm_host->clk);
Shawn Guo85d65092011-05-27 23:48:12 +0800474err_clk_get:
Shawn Guo85d65092011-05-27 23:48:12 +0800475err_power_req:
Simon Baatz47caa842013-06-09 22:14:16 +0200476err_parse_dt:
Shawn Guo85d65092011-05-27 23:48:12 +0800477 sdhci_pltfm_free(pdev);
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500478 return rc;
479}
480
Shawn Guo85d65092011-05-27 23:48:12 +0800481static struct platform_driver sdhci_tegra_driver = {
482 .driver = {
483 .name = "sdhci-tegra",
Grant Likely275173b2011-08-23 12:15:33 -0600484 .of_match_table = sdhci_tegra_dt_match,
Manuel Lauss29495aa2011-11-03 11:09:45 +0100485 .pm = SDHCI_PLTFM_PMOPS,
Shawn Guo85d65092011-05-27 23:48:12 +0800486 },
487 .probe = sdhci_tegra_probe,
Kevin Haocaebcae2015-02-27 15:47:31 +0800488 .remove = sdhci_pltfm_unregister,
Olof Johansson03d2bfc2011-01-01 23:52:56 -0500489};
490
Axel Lind1f81a62011-11-26 12:55:43 +0800491module_platform_driver(sdhci_tegra_driver);
Shawn Guo85d65092011-05-27 23:48:12 +0800492
493MODULE_DESCRIPTION("SDHCI driver for Tegra");
Stephen Warren3e44a1a2012-02-01 16:30:55 -0700494MODULE_AUTHOR("Google, Inc.");
Shawn Guo85d65092011-05-27 23:48:12 +0800495MODULE_LICENSE("GPL v2");