Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010 Google, Inc. |
| 3 | * |
| 4 | * This software is licensed under the terms of the GNU General Public |
| 5 | * License version 2, as published by the Free Software Foundation, and |
| 6 | * may be copied, distributed, and modified under those terms. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 15 | #include <linux/delay.h> |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 16 | #include <linux/err.h> |
Paul Gortmaker | 96547f5 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 17 | #include <linux/module.h> |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 18 | #include <linux/init.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/clk.h> |
| 21 | #include <linux/io.h> |
Stephen Warren | 55cd65e | 2011-08-30 13:17:16 -0600 | [diff] [blame] | 22 | #include <linux/of.h> |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 23 | #include <linux/of_device.h> |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 24 | #include <linux/mmc/card.h> |
| 25 | #include <linux/mmc/host.h> |
Lucas Stach | c3c2384 | 2015-12-22 19:41:02 +0100 | [diff] [blame] | 26 | #include <linux/mmc/mmc.h> |
Joseph Lo | 0aacd23 | 2013-03-11 14:44:11 -0600 | [diff] [blame] | 27 | #include <linux/mmc/slot-gpio.h> |
Mylene JOSSERAND | 2391b34 | 2015-03-30 23:39:25 +0200 | [diff] [blame] | 28 | #include <linux/gpio/consumer.h> |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 29 | |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 30 | #include "sdhci-pltfm.h" |
| 31 | |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 32 | /* Tegra SDHOST controller vendor register definitions */ |
Lucas Stach | 74cd42b | 2015-12-22 19:41:01 +0100 | [diff] [blame] | 33 | #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 |
Lucas Stach | c3c2384 | 2015-12-22 19:41:02 +0100 | [diff] [blame] | 34 | #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 |
| 35 | #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 |
| 36 | #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) |
Lucas Stach | 74cd42b | 2015-12-22 19:41:01 +0100 | [diff] [blame] | 37 | #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) |
| 38 | #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) |
| 39 | |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 40 | #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 |
Andrew Bresticker | 3145351 | 2014-05-22 08:55:35 -0700 | [diff] [blame] | 41 | #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 |
| 42 | #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 43 | #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 |
Andrew Bresticker | 3145351 | 2014-05-22 08:55:35 -0700 | [diff] [blame] | 44 | #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 45 | |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 46 | #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 |
| 47 | #define SDHCI_AUTO_CAL_START BIT(31) |
| 48 | #define SDHCI_AUTO_CAL_ENABLE BIT(29) |
| 49 | |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 50 | #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) |
| 51 | #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 52 | #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) |
Lucas Stach | 7ad2ed1 | 2015-12-22 19:41:03 +0100 | [diff] [blame] | 53 | #define NVQUIRK_ENABLE_SDR50 BIT(3) |
| 54 | #define NVQUIRK_ENABLE_SDR104 BIT(4) |
| 55 | #define NVQUIRK_ENABLE_DDR50 BIT(5) |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 56 | #define NVQUIRK_HAS_PADCALIB BIT(6) |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 57 | |
| 58 | struct sdhci_tegra_soc_data { |
Lars-Peter Clausen | 1db5eeb | 2013-03-13 19:26:03 +0100 | [diff] [blame] | 59 | const struct sdhci_pltfm_data *pdata; |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 60 | u32 nvquirks; |
| 61 | }; |
| 62 | |
| 63 | struct sdhci_tegra { |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 64 | const struct sdhci_tegra_soc_data *soc_data; |
Mylene JOSSERAND | 2391b34 | 2015-03-30 23:39:25 +0200 | [diff] [blame] | 65 | struct gpio_desc *power_gpio; |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 66 | bool ddr_signaling; |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 67 | bool pad_calib_required; |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 68 | }; |
| 69 | |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 70 | static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) |
| 71 | { |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 72 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Jisheng Zhang | 0734e79 | 2016-02-16 21:08:29 +0800 | [diff] [blame] | 73 | struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 74 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
| 75 | |
| 76 | if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && |
| 77 | (reg == SDHCI_HOST_VERSION))) { |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 78 | /* Erratum: Version register is invalid in HW. */ |
| 79 | return SDHCI_SPEC_200; |
| 80 | } |
| 81 | |
| 82 | return readw(host->ioaddr + reg); |
| 83 | } |
| 84 | |
Pavan Kunapuli | 352ee86 | 2015-01-28 11:45:16 -0500 | [diff] [blame] | 85 | static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 86 | { |
| 87 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Pavan Kunapuli | 352ee86 | 2015-01-28 11:45:16 -0500 | [diff] [blame] | 88 | |
Rhyland Klein | 01df7ec | 2015-02-11 12:55:51 -0500 | [diff] [blame] | 89 | switch (reg) { |
| 90 | case SDHCI_TRANSFER_MODE: |
| 91 | /* |
| 92 | * Postpone this write, we must do it together with a |
| 93 | * command write that is down below. |
| 94 | */ |
| 95 | pltfm_host->xfer_mode_shadow = val; |
| 96 | return; |
| 97 | case SDHCI_COMMAND: |
| 98 | writel((val << 16) | pltfm_host->xfer_mode_shadow, |
| 99 | host->ioaddr + SDHCI_TRANSFER_MODE); |
| 100 | return; |
Pavan Kunapuli | 352ee86 | 2015-01-28 11:45:16 -0500 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | writew(val, host->ioaddr + reg); |
| 104 | } |
| 105 | |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 106 | static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 107 | { |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 108 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Jisheng Zhang | 0734e79 | 2016-02-16 21:08:29 +0800 | [diff] [blame] | 109 | struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 110 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
| 111 | |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 112 | /* Seems like we're getting spurious timeout and crc errors, so |
| 113 | * disable signalling of them. In case of real errors software |
| 114 | * timers should take care of eventually detecting them. |
| 115 | */ |
| 116 | if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) |
| 117 | val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); |
| 118 | |
| 119 | writel(val, host->ioaddr + reg); |
| 120 | |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 121 | if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && |
| 122 | (reg == SDHCI_INT_ENABLE))) { |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 123 | /* Erratum: Must enable block gap interrupt detection */ |
| 124 | u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); |
| 125 | if (val & SDHCI_INT_CARD_INT) |
| 126 | gap_ctrl |= 0x8; |
| 127 | else |
| 128 | gap_ctrl &= ~0x8; |
| 129 | writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); |
| 130 | } |
| 131 | } |
| 132 | |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 133 | static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 134 | { |
Joseph Lo | 0aacd23 | 2013-03-11 14:44:11 -0600 | [diff] [blame] | 135 | return mmc_gpio_get_ro(host->mmc); |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 136 | } |
| 137 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 138 | static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 139 | { |
| 140 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Jisheng Zhang | 0734e79 | 2016-02-16 21:08:29 +0800 | [diff] [blame] | 141 | struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 142 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
Lucas Stach | 74cd42b | 2015-12-22 19:41:01 +0100 | [diff] [blame] | 143 | u32 misc_ctrl, clk_ctrl; |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 144 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 145 | sdhci_reset(host, mask); |
| 146 | |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 147 | if (!(mask & SDHCI_RESET_ALL)) |
| 148 | return; |
| 149 | |
Lucas Stach | 1b84def | 2015-12-22 19:41:04 +0100 | [diff] [blame] | 150 | misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 151 | /* Erratum: Enable SDHCI spec v3.00 support */ |
Andrew Bresticker | 3145351 | 2014-05-22 08:55:35 -0700 | [diff] [blame] | 152 | if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 153 | misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; |
Lucas Stach | 7ad2ed1 | 2015-12-22 19:41:03 +0100 | [diff] [blame] | 154 | /* Advertise UHS modes as supported by host */ |
| 155 | if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) |
| 156 | misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; |
Jon Hunter | 7bf037d | 2016-02-26 09:34:17 +0000 | [diff] [blame] | 157 | else |
| 158 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; |
Lucas Stach | 7ad2ed1 | 2015-12-22 19:41:03 +0100 | [diff] [blame] | 159 | if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) |
| 160 | misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; |
Jon Hunter | 7bf037d | 2016-02-26 09:34:17 +0000 | [diff] [blame] | 161 | else |
| 162 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; |
Lucas Stach | 7ad2ed1 | 2015-12-22 19:41:03 +0100 | [diff] [blame] | 163 | if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) |
| 164 | misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; |
Jon Hunter | 7bf037d | 2016-02-26 09:34:17 +0000 | [diff] [blame] | 165 | else |
| 166 | misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; |
Lucas Stach | 1b84def | 2015-12-22 19:41:04 +0100 | [diff] [blame] | 167 | sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 168 | |
Lucas Stach | 74cd42b | 2015-12-22 19:41:01 +0100 | [diff] [blame] | 169 | clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); |
| 170 | clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; |
Lucas Stach | 7ad2ed1 | 2015-12-22 19:41:03 +0100 | [diff] [blame] | 171 | if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) |
Lucas Stach | c3c2384 | 2015-12-22 19:41:02 +0100 | [diff] [blame] | 172 | clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; |
Lucas Stach | 74cd42b | 2015-12-22 19:41:01 +0100 | [diff] [blame] | 173 | sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); |
| 174 | |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 175 | if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) |
| 176 | tegra_host->pad_calib_required = true; |
| 177 | |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 178 | tegra_host->ddr_signaling = false; |
Pavan Kunapuli | ca5879d | 2012-04-18 18:48:02 +0530 | [diff] [blame] | 179 | } |
| 180 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 181 | static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 182 | { |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 183 | u32 ctrl; |
| 184 | |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 185 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Joseph Lo | 0aacd23 | 2013-03-11 14:44:11 -0600 | [diff] [blame] | 186 | if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && |
| 187 | (bus_width == MMC_BUS_WIDTH_8)) { |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 188 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 189 | ctrl |= SDHCI_CTRL_8BITBUS; |
| 190 | } else { |
| 191 | ctrl &= ~SDHCI_CTRL_8BITBUS; |
| 192 | if (bus_width == MMC_BUS_WIDTH_4) |
| 193 | ctrl |= SDHCI_CTRL_4BITBUS; |
| 194 | else |
| 195 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 196 | } |
| 197 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 198 | } |
| 199 | |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 200 | static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) |
| 201 | { |
| 202 | u32 val; |
| 203 | |
| 204 | mdelay(1); |
| 205 | |
| 206 | val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); |
| 207 | val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; |
| 208 | sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); |
| 209 | } |
| 210 | |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 211 | static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
| 212 | { |
| 213 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Jisheng Zhang | 0734e79 | 2016-02-16 21:08:29 +0800 | [diff] [blame] | 214 | struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 215 | unsigned long host_clk; |
| 216 | |
| 217 | if (!clock) |
Lucas Stach | 3491b69 | 2016-02-29 21:56:24 +0100 | [diff] [blame] | 218 | return sdhci_set_clock(host, clock); |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 219 | |
| 220 | host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; |
| 221 | clk_set_rate(pltfm_host->clk, host_clk); |
| 222 | host->max_clk = clk_get_rate(pltfm_host->clk); |
| 223 | |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 224 | sdhci_set_clock(host, clock); |
| 225 | |
| 226 | if (tegra_host->pad_calib_required) { |
| 227 | tegra_sdhci_pad_autocalib(host); |
| 228 | tegra_host->pad_calib_required = false; |
| 229 | } |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 230 | } |
| 231 | |
| 232 | static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, |
| 233 | unsigned timing) |
| 234 | { |
| 235 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Jisheng Zhang | 0734e79 | 2016-02-16 21:08:29 +0800 | [diff] [blame] | 236 | struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 237 | |
| 238 | if (timing == MMC_TIMING_UHS_DDR50) |
| 239 | tegra_host->ddr_signaling = true; |
| 240 | |
| 241 | return sdhci_set_uhs_signaling(host, timing); |
| 242 | } |
| 243 | |
| 244 | static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) |
| 245 | { |
| 246 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 247 | |
| 248 | /* |
| 249 | * DDR modes require the host to run at double the card frequency, so |
| 250 | * the maximum rate we can support is half of the module input clock. |
| 251 | */ |
| 252 | return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2; |
| 253 | } |
| 254 | |
Lucas Stach | c3c2384 | 2015-12-22 19:41:02 +0100 | [diff] [blame] | 255 | static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) |
| 256 | { |
| 257 | u32 reg; |
| 258 | |
| 259 | reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); |
| 260 | reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; |
| 261 | reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; |
| 262 | sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); |
| 263 | } |
| 264 | |
| 265 | static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) |
| 266 | { |
| 267 | unsigned int min, max; |
| 268 | |
| 269 | /* |
| 270 | * Start search for minimum tap value at 10, as smaller values are |
| 271 | * may wrongly be reported as working but fail at higher speeds, |
| 272 | * according to the TRM. |
| 273 | */ |
| 274 | min = 10; |
| 275 | while (min < 255) { |
| 276 | tegra_sdhci_set_tap(host, min); |
| 277 | if (!mmc_send_tuning(host->mmc, opcode, NULL)) |
| 278 | break; |
| 279 | min++; |
| 280 | } |
| 281 | |
| 282 | /* Find the maximum tap value that still passes. */ |
| 283 | max = min + 1; |
| 284 | while (max < 255) { |
| 285 | tegra_sdhci_set_tap(host, max); |
| 286 | if (mmc_send_tuning(host->mmc, opcode, NULL)) { |
| 287 | max--; |
| 288 | break; |
| 289 | } |
| 290 | max++; |
| 291 | } |
| 292 | |
| 293 | /* The TRM states the ideal tap value is at 75% in the passing range. */ |
| 294 | tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); |
| 295 | |
| 296 | return mmc_send_tuning(host->mmc, opcode, NULL); |
| 297 | } |
| 298 | |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 299 | static void tegra_sdhci_voltage_switch(struct sdhci_host *host) |
| 300 | { |
| 301 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 302 | struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); |
| 303 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
| 304 | |
| 305 | if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) |
| 306 | tegra_host->pad_calib_required = true; |
| 307 | } |
| 308 | |
Lars-Peter Clausen | c915568 | 2013-03-13 19:26:05 +0100 | [diff] [blame] | 309 | static const struct sdhci_ops tegra_sdhci_ops = { |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 310 | .get_ro = tegra_sdhci_get_ro, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 311 | .read_w = tegra_sdhci_readw, |
| 312 | .write_l = tegra_sdhci_writel, |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 313 | .set_clock = tegra_sdhci_set_clock, |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 314 | .set_bus_width = tegra_sdhci_set_bus_width, |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 315 | .reset = tegra_sdhci_reset, |
Lucas Stach | c3c2384 | 2015-12-22 19:41:02 +0100 | [diff] [blame] | 316 | .platform_execute_tuning = tegra_sdhci_execute_tuning, |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 317 | .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 318 | .voltage_switch = tegra_sdhci_voltage_switch, |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 319 | .get_max_clock = tegra_sdhci_get_max_clock, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 320 | }; |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 321 | |
Lars-Peter Clausen | 1db5eeb | 2013-03-13 19:26:03 +0100 | [diff] [blame] | 322 | static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 323 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
| 324 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
| 325 | SDHCI_QUIRK_NO_HISPD_BIT | |
Andrew Bresticker | f926035 | 2014-05-22 08:55:36 -0700 | [diff] [blame] | 326 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
| 327 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 328 | .ops = &tegra_sdhci_ops, |
| 329 | }; |
| 330 | |
Thierry Reding | d49d19c2 | 2015-11-16 10:27:14 +0100 | [diff] [blame] | 331 | static const struct sdhci_tegra_soc_data soc_data_tegra20 = { |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 332 | .pdata = &sdhci_tegra20_pdata, |
| 333 | .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | |
| 334 | NVQUIRK_ENABLE_BLOCK_GAP_DET, |
| 335 | }; |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 336 | |
Lars-Peter Clausen | 1db5eeb | 2013-03-13 19:26:03 +0100 | [diff] [blame] | 337 | static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 338 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
| 339 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
| 340 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
| 341 | SDHCI_QUIRK_NO_HISPD_BIT | |
Andrew Bresticker | f926035 | 2014-05-22 08:55:36 -0700 | [diff] [blame] | 342 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
| 343 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 344 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 345 | .ops = &tegra_sdhci_ops, |
| 346 | }; |
| 347 | |
Thierry Reding | d49d19c2 | 2015-11-16 10:27:14 +0100 | [diff] [blame] | 348 | static const struct sdhci_tegra_soc_data soc_data_tegra30 = { |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 349 | .pdata = &sdhci_tegra30_pdata, |
Andrew Bresticker | 3145351 | 2014-05-22 08:55:35 -0700 | [diff] [blame] | 350 | .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | |
Lucas Stach | 7ad2ed1 | 2015-12-22 19:41:03 +0100 | [diff] [blame] | 351 | NVQUIRK_ENABLE_SDR50 | |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 352 | NVQUIRK_ENABLE_SDR104 | |
| 353 | NVQUIRK_HAS_PADCALIB, |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 354 | }; |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 355 | |
Rhyland Klein | 01df7ec | 2015-02-11 12:55:51 -0500 | [diff] [blame] | 356 | static const struct sdhci_ops tegra114_sdhci_ops = { |
| 357 | .get_ro = tegra_sdhci_get_ro, |
| 358 | .read_w = tegra_sdhci_readw, |
| 359 | .write_w = tegra_sdhci_writew, |
| 360 | .write_l = tegra_sdhci_writel, |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 361 | .set_clock = tegra_sdhci_set_clock, |
Rhyland Klein | 01df7ec | 2015-02-11 12:55:51 -0500 | [diff] [blame] | 362 | .set_bus_width = tegra_sdhci_set_bus_width, |
| 363 | .reset = tegra_sdhci_reset, |
Lucas Stach | c3c2384 | 2015-12-22 19:41:02 +0100 | [diff] [blame] | 364 | .platform_execute_tuning = tegra_sdhci_execute_tuning, |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 365 | .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 366 | .voltage_switch = tegra_sdhci_voltage_switch, |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 367 | .get_max_clock = tegra_sdhci_get_max_clock, |
Rhyland Klein | 01df7ec | 2015-02-11 12:55:51 -0500 | [diff] [blame] | 368 | }; |
| 369 | |
Lars-Peter Clausen | 1db5eeb | 2013-03-13 19:26:03 +0100 | [diff] [blame] | 370 | static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { |
Rhyland Klein | 5ebf255 | 2013-02-20 13:35:17 -0500 | [diff] [blame] | 371 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
| 372 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
| 373 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
| 374 | SDHCI_QUIRK_NO_HISPD_BIT | |
Andrew Bresticker | f926035 | 2014-05-22 08:55:36 -0700 | [diff] [blame] | 375 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
| 376 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 377 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, |
Rhyland Klein | 01df7ec | 2015-02-11 12:55:51 -0500 | [diff] [blame] | 378 | .ops = &tegra114_sdhci_ops, |
Rhyland Klein | 5ebf255 | 2013-02-20 13:35:17 -0500 | [diff] [blame] | 379 | }; |
| 380 | |
Thierry Reding | d49d19c2 | 2015-11-16 10:27:14 +0100 | [diff] [blame] | 381 | static const struct sdhci_tegra_soc_data soc_data_tegra114 = { |
Rhyland Klein | 5ebf255 | 2013-02-20 13:35:17 -0500 | [diff] [blame] | 382 | .pdata = &sdhci_tegra114_pdata, |
Jon Hunter | 7bf037d | 2016-02-26 09:34:17 +0000 | [diff] [blame] | 383 | }; |
| 384 | |
| 385 | static const struct sdhci_tegra_soc_data soc_data_tegra124 = { |
| 386 | .pdata = &sdhci_tegra114_pdata, |
Lucas Stach | 7ad2ed1 | 2015-12-22 19:41:03 +0100 | [diff] [blame] | 387 | .nvquirks = NVQUIRK_ENABLE_SDR50 | |
| 388 | NVQUIRK_ENABLE_DDR50 | |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 389 | NVQUIRK_ENABLE_SDR104 | |
| 390 | NVQUIRK_HAS_PADCALIB, |
Rhyland Klein | 5ebf255 | 2013-02-20 13:35:17 -0500 | [diff] [blame] | 391 | }; |
| 392 | |
Thierry Reding | b5a84ec | 2015-11-16 10:27:15 +0100 | [diff] [blame] | 393 | static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { |
| 394 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
| 395 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
| 396 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
| 397 | SDHCI_QUIRK_NO_HISPD_BIT | |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 398 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
| 399 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
| 400 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, |
Thierry Reding | b5a84ec | 2015-11-16 10:27:15 +0100 | [diff] [blame] | 401 | .ops = &tegra114_sdhci_ops, |
| 402 | }; |
| 403 | |
| 404 | static const struct sdhci_tegra_soc_data soc_data_tegra210 = { |
| 405 | .pdata = &sdhci_tegra210_pdata, |
Thierry Reding | b5a84ec | 2015-11-16 10:27:15 +0100 | [diff] [blame] | 406 | }; |
| 407 | |
Bill Pemberton | 498d83e | 2012-11-19 13:24:22 -0500 | [diff] [blame] | 408 | static const struct of_device_id sdhci_tegra_dt_match[] = { |
Thierry Reding | b5a84ec | 2015-11-16 10:27:15 +0100 | [diff] [blame] | 409 | { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, |
Jon Hunter | 7bf037d | 2016-02-26 09:34:17 +0000 | [diff] [blame] | 410 | { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, |
Rhyland Klein | 5ebf255 | 2013-02-20 13:35:17 -0500 | [diff] [blame] | 411 | { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 412 | { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 413 | { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, |
Grant Likely | 275173b | 2011-08-23 12:15:33 -0600 | [diff] [blame] | 414 | {} |
| 415 | }; |
Arnd Bergmann | e4404fa | 2013-04-23 15:05:57 -0400 | [diff] [blame] | 416 | MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); |
Grant Likely | 275173b | 2011-08-23 12:15:33 -0600 | [diff] [blame] | 417 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 418 | static int sdhci_tegra_probe(struct platform_device *pdev) |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 419 | { |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 420 | const struct of_device_id *match; |
| 421 | const struct sdhci_tegra_soc_data *soc_data; |
| 422 | struct sdhci_host *host; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 423 | struct sdhci_pltfm_host *pltfm_host; |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 424 | struct sdhci_tegra *tegra_host; |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 425 | struct clk *clk; |
| 426 | int rc; |
| 427 | |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 428 | match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); |
Joseph Lo | b37f9d9 | 2012-08-17 15:04:31 +0800 | [diff] [blame] | 429 | if (!match) |
| 430 | return -EINVAL; |
| 431 | soc_data = match->data; |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 432 | |
Jisheng Zhang | 0734e79 | 2016-02-16 21:08:29 +0800 | [diff] [blame] | 433 | host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 434 | if (IS_ERR(host)) |
| 435 | return PTR_ERR(host); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 436 | pltfm_host = sdhci_priv(host); |
| 437 | |
Jisheng Zhang | 0734e79 | 2016-02-16 21:08:29 +0800 | [diff] [blame] | 438 | tegra_host = sdhci_pltfm_priv(pltfm_host); |
Lucas Stach | a8e326a | 2015-12-22 19:41:00 +0100 | [diff] [blame] | 439 | tegra_host->ddr_signaling = false; |
Lucas Stach | e5c63d9 | 2016-02-29 21:56:25 +0100 | [diff] [blame^] | 440 | tegra_host->pad_calib_required = false; |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 441 | tegra_host->soc_data = soc_data; |
Grant Likely | 275173b | 2011-08-23 12:15:33 -0600 | [diff] [blame] | 442 | |
Mylene JOSSERAND | 2391b34 | 2015-03-30 23:39:25 +0200 | [diff] [blame] | 443 | rc = mmc_of_parse(host->mmc); |
Simon Baatz | 47caa84 | 2013-06-09 22:14:16 +0200 | [diff] [blame] | 444 | if (rc) |
| 445 | goto err_parse_dt; |
Stephen Warren | 0e78610 | 2013-02-15 15:07:19 -0700 | [diff] [blame] | 446 | |
Lucas Stach | 7ad2ed1 | 2015-12-22 19:41:03 +0100 | [diff] [blame] | 447 | if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) |
Lucas Stach | c3c2384 | 2015-12-22 19:41:02 +0100 | [diff] [blame] | 448 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
| 449 | |
Mylene JOSSERAND | 2391b34 | 2015-03-30 23:39:25 +0200 | [diff] [blame] | 450 | tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", |
| 451 | GPIOD_OUT_HIGH); |
| 452 | if (IS_ERR(tegra_host->power_gpio)) { |
| 453 | rc = PTR_ERR(tegra_host->power_gpio); |
| 454 | goto err_power_req; |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 455 | } |
| 456 | |
Kevin Hao | e4f79d9 | 2015-02-27 15:47:27 +0800 | [diff] [blame] | 457 | clk = devm_clk_get(mmc_dev(host->mmc), NULL); |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 458 | if (IS_ERR(clk)) { |
| 459 | dev_err(mmc_dev(host->mmc), "clk err\n"); |
| 460 | rc = PTR_ERR(clk); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 461 | goto err_clk_get; |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 462 | } |
Prashant Gaikwad | 1e674bc | 2012-06-05 09:59:37 +0530 | [diff] [blame] | 463 | clk_prepare_enable(clk); |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 464 | pltfm_host->clk = clk; |
| 465 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 466 | rc = sdhci_add_host(host); |
| 467 | if (rc) |
| 468 | goto err_add_host; |
| 469 | |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 470 | return 0; |
| 471 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 472 | err_add_host: |
Prashant Gaikwad | 1e674bc | 2012-06-05 09:59:37 +0530 | [diff] [blame] | 473 | clk_disable_unprepare(pltfm_host->clk); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 474 | err_clk_get: |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 475 | err_power_req: |
Simon Baatz | 47caa84 | 2013-06-09 22:14:16 +0200 | [diff] [blame] | 476 | err_parse_dt: |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 477 | sdhci_pltfm_free(pdev); |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 478 | return rc; |
| 479 | } |
| 480 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 481 | static struct platform_driver sdhci_tegra_driver = { |
| 482 | .driver = { |
| 483 | .name = "sdhci-tegra", |
Grant Likely | 275173b | 2011-08-23 12:15:33 -0600 | [diff] [blame] | 484 | .of_match_table = sdhci_tegra_dt_match, |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 485 | .pm = SDHCI_PLTFM_PMOPS, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 486 | }, |
| 487 | .probe = sdhci_tegra_probe, |
Kevin Hao | caebcae | 2015-02-27 15:47:31 +0800 | [diff] [blame] | 488 | .remove = sdhci_pltfm_unregister, |
Olof Johansson | 03d2bfc | 2011-01-01 23:52:56 -0500 | [diff] [blame] | 489 | }; |
| 490 | |
Axel Lin | d1f81a6 | 2011-11-26 12:55:43 +0800 | [diff] [blame] | 491 | module_platform_driver(sdhci_tegra_driver); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 492 | |
| 493 | MODULE_DESCRIPTION("SDHCI driver for Tegra"); |
Stephen Warren | 3e44a1a | 2012-02-01 16:30:55 -0700 | [diff] [blame] | 494 | MODULE_AUTHOR("Google, Inc."); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 495 | MODULE_LICENSE("GPL v2"); |