| Sergei Shtylyov | 371b53e0 | 2009-09-25 22:24:57 +0400 | [diff] [blame^] | 1 | /* |
| 2 | * USB related definitions |
| 3 | * |
| 4 | * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_ARCH_USB_H |
| 12 | #define __ASM_ARCH_USB_H |
| 13 | |
| 14 | /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ |
| 15 | #define CFGCHIP2_PHYCLKGD (1 << 17) |
| 16 | #define CFGCHIP2_VBUSSENSE (1 << 16) |
| 17 | #define CFGCHIP2_RESET (1 << 15) |
| 18 | #define CFGCHIP2_OTGMODE (3 << 13) |
| 19 | #define CFGCHIP2_NO_OVERRIDE (0 << 13) |
| 20 | #define CFGCHIP2_FORCE_HOST (1 << 13) |
| 21 | #define CFGCHIP2_FORCE_DEVICE (2 << 13) |
| 22 | #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) |
| 23 | #define CFGCHIP2_USB1PHYCLKMUX (1 << 12) |
| 24 | #define CFGCHIP2_USB2PHYCLKMUX (1 << 11) |
| 25 | #define CFGCHIP2_PHYPWRDN (1 << 10) |
| 26 | #define CFGCHIP2_OTGPWRDN (1 << 9) |
| 27 | #define CFGCHIP2_DATPOL (1 << 8) |
| 28 | #define CFGCHIP2_USB1SUSPENDM (1 << 7) |
| 29 | #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ |
| 30 | #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ |
| 31 | #define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ |
| 32 | #define CFGCHIP2_REFFREQ (0xf << 0) |
| 33 | #define CFGCHIP2_REFFREQ_12MHZ (1 << 0) |
| 34 | #define CFGCHIP2_REFFREQ_24MHZ (2 << 0) |
| 35 | #define CFGCHIP2_REFFREQ_48MHZ (3 << 0) |
| 36 | |
| 37 | #endif /* ifndef __ASM_ARCH_USB_H */ |