| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * DTC controller, taken from T128 driver by... |
| 3 | * Copyright 1993, Drew Eckhardt |
| 4 | * Visionary Computing |
| 5 | * (Unix and Linux consulting and custom programming) |
| 6 | * drew@colorado.edu |
| 7 | * +1 (303) 440-4894 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef DTC3280_H |
| 11 | #define DTC3280_H |
| 12 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #define NCR5380_implementation_fields \ |
| 14 | void __iomem *base |
| 15 | |
| Finn Thain | 54d8fe4 | 2016-01-03 16:05:06 +1100 | [diff] [blame] | 16 | #define DTC_address(reg) \ |
| 17 | (((struct NCR5380_hostdata *)shost_priv(instance))->base + DTC_5380_OFFSET + reg) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #define NCR5380_read(reg) (readb(DTC_address(reg))) |
| 20 | #define NCR5380_write(reg, value) (writeb(value, DTC_address(reg))) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | |
| Finn Thain | ff3d457 | 2016-01-03 16:05:25 +1100 | [diff] [blame] | 22 | #define NCR5380_dma_xfer_len(instance, cmd, phase) \ |
| 23 | dtc_dma_xfer_len(cmd) |
| 24 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #define NCR5380_intr dtc_intr |
| 26 | #define NCR5380_queue_command dtc_queue_command |
| 27 | #define NCR5380_abort dtc_abort |
| 28 | #define NCR5380_bus_reset dtc_bus_reset |
| Finn Thain | 8c32513 | 2014-11-12 16:11:58 +1100 | [diff] [blame] | 29 | #define NCR5380_info dtc_info |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
| Finn Thain | e5d55d1 | 2016-03-23 21:10:16 +1100 | [diff] [blame^] | 31 | #define NCR5380_io_delay(x) udelay(x) |
| 32 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | /* 15 12 11 10 |
| 34 | 1001 1100 0000 0000 */ |
| 35 | |
| 36 | #define DTC_IRQS 0x9c00 |
| 37 | |
| 38 | |
| 39 | #endif /* DTC3280_H */ |