Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
| 3 | * http://www.samsung.com |
| 4 | * |
| 5 | * Common Codes for EXYNOS |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/irq.h> |
| 15 | #include <linux/io.h> |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 16 | #include <linux/device.h> |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 17 | #include <linux/gpio.h> |
| 18 | #include <linux/sched.h> |
| 19 | #include <linux/serial_core.h> |
Arnd Bergmann | 237c78b | 2012-01-07 12:30:20 +0000 | [diff] [blame] | 20 | #include <linux/of.h> |
| 21 | #include <linux/of_irq.h> |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 22 | |
| 23 | #include <asm/proc-fns.h> |
Arnd Bergmann | 40ba95f | 2012-01-07 11:51:28 +0000 | [diff] [blame] | 24 | #include <asm/exception.h> |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 25 | #include <asm/hardware/cache-l2x0.h> |
| 26 | #include <asm/hardware/gic.h> |
| 27 | #include <asm/mach/map.h> |
| 28 | #include <asm/mach/irq.h> |
| 29 | |
| 30 | #include <mach/regs-irq.h> |
| 31 | #include <mach/regs-pmu.h> |
| 32 | #include <mach/regs-gpio.h> |
| 33 | |
| 34 | #include <plat/cpu.h> |
| 35 | #include <plat/clock.h> |
| 36 | #include <plat/devs.h> |
| 37 | #include <plat/pm.h> |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 38 | #include <plat/sdhci.h> |
| 39 | #include <plat/gpio-cfg.h> |
| 40 | #include <plat/adc-core.h> |
| 41 | #include <plat/fb-core.h> |
| 42 | #include <plat/fimc-core.h> |
| 43 | #include <plat/iic-core.h> |
| 44 | #include <plat/tv-core.h> |
| 45 | #include <plat/regs-serial.h> |
| 46 | |
| 47 | #include "common.h" |
| 48 | |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 49 | static const char name_exynos4210[] = "EXYNOS4210"; |
| 50 | static const char name_exynos4212[] = "EXYNOS4212"; |
| 51 | static const char name_exynos4412[] = "EXYNOS4412"; |
| 52 | |
| 53 | static struct cpu_table cpu_ids[] __initdata = { |
| 54 | { |
| 55 | .idcode = EXYNOS4210_CPU_ID, |
| 56 | .idmask = EXYNOS4_CPU_MASK, |
| 57 | .map_io = exynos4_map_io, |
| 58 | .init_clocks = exynos4_init_clocks, |
| 59 | .init_uarts = exynos4_init_uarts, |
| 60 | .init = exynos_init, |
| 61 | .name = name_exynos4210, |
| 62 | }, { |
| 63 | .idcode = EXYNOS4212_CPU_ID, |
| 64 | .idmask = EXYNOS4_CPU_MASK, |
| 65 | .map_io = exynos4_map_io, |
| 66 | .init_clocks = exynos4_init_clocks, |
| 67 | .init_uarts = exynos4_init_uarts, |
| 68 | .init = exynos_init, |
| 69 | .name = name_exynos4212, |
| 70 | }, { |
| 71 | .idcode = EXYNOS4412_CPU_ID, |
| 72 | .idmask = EXYNOS4_CPU_MASK, |
| 73 | .map_io = exynos4_map_io, |
| 74 | .init_clocks = exynos4_init_clocks, |
| 75 | .init_uarts = exynos4_init_uarts, |
| 76 | .init = exynos_init, |
| 77 | .name = name_exynos4412, |
| 78 | }, |
| 79 | }; |
| 80 | |
| 81 | /* Initial IO mappings */ |
| 82 | |
| 83 | static struct map_desc exynos_iodesc[] __initdata = { |
| 84 | { |
| 85 | .virtual = (unsigned long)S5P_VA_CHIPID, |
| 86 | .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID), |
| 87 | .length = SZ_4K, |
| 88 | .type = MT_DEVICE, |
| 89 | }, { |
| 90 | .virtual = (unsigned long)S3C_VA_SYS, |
| 91 | .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), |
| 92 | .length = SZ_64K, |
| 93 | .type = MT_DEVICE, |
| 94 | }, { |
| 95 | .virtual = (unsigned long)S3C_VA_TIMER, |
| 96 | .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER), |
| 97 | .length = SZ_16K, |
| 98 | .type = MT_DEVICE, |
| 99 | }, { |
| 100 | .virtual = (unsigned long)S3C_VA_WATCHDOG, |
| 101 | .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG), |
| 102 | .length = SZ_4K, |
| 103 | .type = MT_DEVICE, |
| 104 | }, { |
| 105 | .virtual = (unsigned long)S5P_VA_SROMC, |
| 106 | .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), |
| 107 | .length = SZ_4K, |
| 108 | .type = MT_DEVICE, |
| 109 | }, { |
| 110 | .virtual = (unsigned long)S5P_VA_SYSTIMER, |
| 111 | .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), |
| 112 | .length = SZ_4K, |
| 113 | .type = MT_DEVICE, |
| 114 | }, { |
| 115 | .virtual = (unsigned long)S5P_VA_PMU, |
| 116 | .pfn = __phys_to_pfn(EXYNOS4_PA_PMU), |
| 117 | .length = SZ_64K, |
| 118 | .type = MT_DEVICE, |
| 119 | }, { |
| 120 | .virtual = (unsigned long)S5P_VA_COMBINER_BASE, |
| 121 | .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), |
| 122 | .length = SZ_4K, |
| 123 | .type = MT_DEVICE, |
| 124 | }, { |
| 125 | .virtual = (unsigned long)S5P_VA_GIC_CPU, |
| 126 | .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), |
| 127 | .length = SZ_64K, |
| 128 | .type = MT_DEVICE, |
| 129 | }, { |
| 130 | .virtual = (unsigned long)S5P_VA_GIC_DIST, |
| 131 | .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), |
| 132 | .length = SZ_64K, |
| 133 | .type = MT_DEVICE, |
| 134 | }, { |
| 135 | .virtual = (unsigned long)S3C_VA_UART, |
| 136 | .pfn = __phys_to_pfn(EXYNOS4_PA_UART), |
| 137 | .length = SZ_512K, |
| 138 | .type = MT_DEVICE, |
| 139 | }, |
| 140 | }; |
| 141 | |
| 142 | static struct map_desc exynos4_iodesc[] __initdata = { |
| 143 | { |
| 144 | .virtual = (unsigned long)S5P_VA_CMU, |
| 145 | .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), |
| 146 | .length = SZ_128K, |
| 147 | .type = MT_DEVICE, |
| 148 | }, { |
| 149 | .virtual = (unsigned long)S5P_VA_COREPERI_BASE, |
| 150 | .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI), |
| 151 | .length = SZ_8K, |
| 152 | .type = MT_DEVICE, |
| 153 | }, { |
| 154 | .virtual = (unsigned long)S5P_VA_L2CC, |
| 155 | .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC), |
| 156 | .length = SZ_4K, |
| 157 | .type = MT_DEVICE, |
| 158 | }, { |
| 159 | .virtual = (unsigned long)S5P_VA_GPIO1, |
| 160 | .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1), |
| 161 | .length = SZ_4K, |
| 162 | .type = MT_DEVICE, |
| 163 | }, { |
| 164 | .virtual = (unsigned long)S5P_VA_GPIO2, |
| 165 | .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2), |
| 166 | .length = SZ_4K, |
| 167 | .type = MT_DEVICE, |
| 168 | }, { |
| 169 | .virtual = (unsigned long)S5P_VA_GPIO3, |
| 170 | .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3), |
| 171 | .length = SZ_256, |
| 172 | .type = MT_DEVICE, |
| 173 | }, { |
| 174 | .virtual = (unsigned long)S5P_VA_DMC0, |
| 175 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), |
| 176 | .length = SZ_4K, |
| 177 | .type = MT_DEVICE, |
| 178 | }, { |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 179 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, |
| 180 | .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), |
| 181 | .length = SZ_4K, |
| 182 | .type = MT_DEVICE, |
| 183 | }, |
| 184 | }; |
| 185 | |
| 186 | static struct map_desc exynos4_iodesc0[] __initdata = { |
| 187 | { |
| 188 | .virtual = (unsigned long)S5P_VA_SYSRAM, |
| 189 | .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0), |
| 190 | .length = SZ_4K, |
| 191 | .type = MT_DEVICE, |
| 192 | }, |
| 193 | }; |
| 194 | |
| 195 | static struct map_desc exynos4_iodesc1[] __initdata = { |
| 196 | { |
| 197 | .virtual = (unsigned long)S5P_VA_SYSRAM, |
| 198 | .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1), |
| 199 | .length = SZ_4K, |
| 200 | .type = MT_DEVICE, |
| 201 | }, |
| 202 | }; |
| 203 | |
| 204 | static void exynos_idle(void) |
| 205 | { |
| 206 | if (!need_resched()) |
| 207 | cpu_do_idle(); |
| 208 | |
| 209 | local_irq_enable(); |
| 210 | } |
| 211 | |
Russell King | 9eb4859 | 2012-01-03 11:56:53 +0100 | [diff] [blame] | 212 | void exynos4_restart(char mode, const char *cmd) |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 213 | { |
| 214 | __raw_writel(0x1, S5P_SWRESET); |
| 215 | } |
| 216 | |
| 217 | /* |
| 218 | * exynos_map_io |
| 219 | * |
| 220 | * register the standard cpu IO areas |
| 221 | */ |
| 222 | |
| 223 | void __init exynos_init_io(struct map_desc *mach_desc, int size) |
| 224 | { |
| 225 | /* initialize the io descriptors we need for initialization */ |
| 226 | iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); |
| 227 | if (mach_desc) |
| 228 | iotable_init(mach_desc, size); |
| 229 | |
| 230 | /* detect cpu id and rev. */ |
| 231 | s5p_init_cpu(S5P_VA_CHIPID); |
| 232 | |
| 233 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); |
| 234 | } |
| 235 | |
| 236 | void __init exynos4_map_io(void) |
| 237 | { |
| 238 | iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); |
| 239 | |
| 240 | if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) |
| 241 | iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0)); |
| 242 | else |
| 243 | iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1)); |
| 244 | |
| 245 | /* initialize device information early */ |
| 246 | exynos4_default_sdhci0(); |
| 247 | exynos4_default_sdhci1(); |
| 248 | exynos4_default_sdhci2(); |
| 249 | exynos4_default_sdhci3(); |
| 250 | |
| 251 | s3c_adc_setname("samsung-adc-v3"); |
| 252 | |
| 253 | s3c_fimc_setname(0, "exynos4-fimc"); |
| 254 | s3c_fimc_setname(1, "exynos4-fimc"); |
| 255 | s3c_fimc_setname(2, "exynos4-fimc"); |
| 256 | s3c_fimc_setname(3, "exynos4-fimc"); |
| 257 | |
| 258 | /* The I2C bus controllers are directly compatible with s3c2440 */ |
| 259 | s3c_i2c0_setname("s3c2440-i2c"); |
| 260 | s3c_i2c1_setname("s3c2440-i2c"); |
| 261 | s3c_i2c2_setname("s3c2440-i2c"); |
| 262 | |
| 263 | s5p_fb_setname(0, "exynos4-fb"); |
| 264 | s5p_hdmi_setname("exynos4-hdmi"); |
| 265 | } |
| 266 | |
| 267 | void __init exynos4_init_clocks(int xtal) |
| 268 | { |
| 269 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); |
| 270 | |
| 271 | s3c24xx_register_baseclocks(xtal); |
| 272 | s5p_register_clocks(xtal); |
| 273 | |
| 274 | if (soc_is_exynos4210()) |
| 275 | exynos4210_register_clocks(); |
| 276 | else if (soc_is_exynos4212() || soc_is_exynos4412()) |
| 277 | exynos4212_register_clocks(); |
| 278 | |
| 279 | exynos4_register_clocks(); |
| 280 | exynos4_setup_clocks(); |
| 281 | } |
| 282 | |
| 283 | #define COMBINER_ENABLE_SET 0x0 |
| 284 | #define COMBINER_ENABLE_CLEAR 0x4 |
| 285 | #define COMBINER_INT_STATUS 0xC |
| 286 | |
| 287 | static DEFINE_SPINLOCK(irq_controller_lock); |
| 288 | |
| 289 | struct combiner_chip_data { |
| 290 | unsigned int irq_offset; |
| 291 | unsigned int irq_mask; |
| 292 | void __iomem *base; |
| 293 | }; |
| 294 | |
| 295 | static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; |
| 296 | |
| 297 | static inline void __iomem *combiner_base(struct irq_data *data) |
| 298 | { |
| 299 | struct combiner_chip_data *combiner_data = |
| 300 | irq_data_get_irq_chip_data(data); |
| 301 | |
| 302 | return combiner_data->base; |
| 303 | } |
| 304 | |
| 305 | static void combiner_mask_irq(struct irq_data *data) |
| 306 | { |
| 307 | u32 mask = 1 << (data->irq % 32); |
| 308 | |
| 309 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); |
| 310 | } |
| 311 | |
| 312 | static void combiner_unmask_irq(struct irq_data *data) |
| 313 | { |
| 314 | u32 mask = 1 << (data->irq % 32); |
| 315 | |
| 316 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); |
| 317 | } |
| 318 | |
| 319 | static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
| 320 | { |
| 321 | struct combiner_chip_data *chip_data = irq_get_handler_data(irq); |
| 322 | struct irq_chip *chip = irq_get_chip(irq); |
| 323 | unsigned int cascade_irq, combiner_irq; |
| 324 | unsigned long status; |
| 325 | |
| 326 | chained_irq_enter(chip, desc); |
| 327 | |
| 328 | spin_lock(&irq_controller_lock); |
| 329 | status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); |
| 330 | spin_unlock(&irq_controller_lock); |
| 331 | status &= chip_data->irq_mask; |
| 332 | |
| 333 | if (status == 0) |
| 334 | goto out; |
| 335 | |
| 336 | combiner_irq = __ffs(status); |
| 337 | |
| 338 | cascade_irq = combiner_irq + (chip_data->irq_offset & ~31); |
| 339 | if (unlikely(cascade_irq >= NR_IRQS)) |
| 340 | do_bad_IRQ(cascade_irq, desc); |
| 341 | else |
| 342 | generic_handle_irq(cascade_irq); |
| 343 | |
| 344 | out: |
| 345 | chained_irq_exit(chip, desc); |
| 346 | } |
| 347 | |
| 348 | static struct irq_chip combiner_chip = { |
| 349 | .name = "COMBINER", |
| 350 | .irq_mask = combiner_mask_irq, |
| 351 | .irq_unmask = combiner_unmask_irq, |
| 352 | }; |
| 353 | |
| 354 | static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) |
| 355 | { |
| 356 | if (combiner_nr >= MAX_COMBINER_NR) |
| 357 | BUG(); |
| 358 | if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) |
| 359 | BUG(); |
| 360 | irq_set_chained_handler(irq, combiner_handle_cascade_irq); |
| 361 | } |
| 362 | |
| 363 | static void __init combiner_init(unsigned int combiner_nr, void __iomem *base, |
| 364 | unsigned int irq_start) |
| 365 | { |
| 366 | unsigned int i; |
| 367 | |
| 368 | if (combiner_nr >= MAX_COMBINER_NR) |
| 369 | BUG(); |
| 370 | |
| 371 | combiner_data[combiner_nr].base = base; |
| 372 | combiner_data[combiner_nr].irq_offset = irq_start; |
| 373 | combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); |
| 374 | |
| 375 | /* Disable all interrupts */ |
| 376 | |
| 377 | __raw_writel(combiner_data[combiner_nr].irq_mask, |
| 378 | base + COMBINER_ENABLE_CLEAR); |
| 379 | |
| 380 | /* Setup the Linux IRQ subsystem */ |
| 381 | |
| 382 | for (i = irq_start; i < combiner_data[combiner_nr].irq_offset |
| 383 | + MAX_IRQ_IN_COMBINER; i++) { |
| 384 | irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq); |
| 385 | irq_set_chip_data(i, &combiner_data[combiner_nr]); |
| 386 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 387 | } |
| 388 | } |
| 389 | |
Arnd Bergmann | 237c78b | 2012-01-07 12:30:20 +0000 | [diff] [blame] | 390 | #ifdef CONFIG_OF |
| 391 | static const struct of_device_id exynos4_dt_irq_match[] = { |
| 392 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, |
| 393 | {}, |
| 394 | }; |
| 395 | #endif |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 396 | |
| 397 | void __init exynos4_init_irq(void) |
| 398 | { |
| 399 | int irq; |
Arnd Bergmann | 40ba95f | 2012-01-07 11:51:28 +0000 | [diff] [blame] | 400 | unsigned int gic_bank_offset; |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 401 | |
| 402 | gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; |
| 403 | |
Arnd Bergmann | 237c78b | 2012-01-07 12:30:20 +0000 | [diff] [blame] | 404 | if (!of_have_populated_dt()) |
| 405 | gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset); |
| 406 | #ifdef CONFIG_OF |
| 407 | else |
| 408 | of_irq_init(exynos4_dt_irq_match); |
| 409 | #endif |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 410 | |
| 411 | for (irq = 0; irq < MAX_COMBINER_NR; irq++) { |
| 412 | |
| 413 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), |
| 414 | COMBINER_IRQ(irq, 0)); |
| 415 | combiner_cascade_irq(irq, IRQ_SPI(irq)); |
| 416 | } |
| 417 | |
| 418 | /* |
| 419 | * The parameters of s5p_init_irq() are for VIC init. |
| 420 | * Theses parameters should be NULL and 0 because EXYNOS4 |
| 421 | * uses GIC instead of VIC. |
| 422 | */ |
| 423 | s5p_init_irq(NULL, 0); |
| 424 | } |
| 425 | |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 426 | struct bus_type exynos4_subsys = { |
| 427 | .name = "exynos4-core", |
| 428 | .dev_name = "exynos4-core", |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 429 | }; |
| 430 | |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 431 | static struct device exynos4_dev = { |
| 432 | .bus = &exynos4_subsys, |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 433 | }; |
| 434 | |
| 435 | static int __init exynos4_core_init(void) |
| 436 | { |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 437 | return subsys_system_register(&exynos4_subsys, NULL); |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 438 | } |
| 439 | core_initcall(exynos4_core_init); |
| 440 | |
| 441 | #ifdef CONFIG_CACHE_L2X0 |
| 442 | static int __init exynos4_l2x0_cache_init(void) |
| 443 | { |
| 444 | /* TAG, Data Latency Control: 2cycle */ |
| 445 | __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); |
| 446 | |
| 447 | if (soc_is_exynos4210()) |
| 448 | __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); |
| 449 | else if (soc_is_exynos4212() || soc_is_exynos4412()) |
| 450 | __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); |
| 451 | |
| 452 | /* L2X0 Prefetch Control */ |
| 453 | __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); |
| 454 | |
| 455 | /* L2X0 Power Control */ |
| 456 | __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, |
| 457 | S5P_VA_L2CC + L2X0_POWER_CTRL); |
| 458 | |
| 459 | l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); |
| 460 | |
| 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | early_initcall(exynos4_l2x0_cache_init); |
| 465 | #endif |
| 466 | |
| 467 | int __init exynos_init(void) |
| 468 | { |
| 469 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); |
| 470 | |
| 471 | /* set idle function */ |
| 472 | pm_idle = exynos_idle; |
| 473 | |
Linus Torvalds | 7affca3 | 2012-01-07 12:03:30 -0800 | [diff] [blame] | 474 | return device_register(&exynos4_dev); |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 475 | } |
| 476 | |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 477 | /* uart registration process */ |
| 478 | |
| 479 | void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
| 480 | { |
| 481 | struct s3c2410_uartcfg *tcfg = cfg; |
| 482 | u32 ucnt; |
| 483 | |
Arnd Bergmann | 237c78b | 2012-01-07 12:30:20 +0000 | [diff] [blame] | 484 | for (ucnt = 0; ucnt < no; ucnt++, tcfg++) |
| 485 | tcfg->has_fracval = 1; |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 486 | |
Arnd Bergmann | 237c78b | 2012-01-07 12:30:20 +0000 | [diff] [blame] | 487 | s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no); |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 488 | } |
| 489 | |
| 490 | static DEFINE_SPINLOCK(eint_lock); |
| 491 | |
| 492 | static unsigned int eint0_15_data[16]; |
| 493 | |
| 494 | static unsigned int exynos4_get_irq_nr(unsigned int number) |
| 495 | { |
| 496 | u32 ret = 0; |
| 497 | |
| 498 | switch (number) { |
| 499 | case 0 ... 3: |
| 500 | ret = (number + IRQ_EINT0); |
| 501 | break; |
| 502 | case 4 ... 7: |
| 503 | ret = (number + (IRQ_EINT4 - 4)); |
| 504 | break; |
| 505 | case 8 ... 15: |
| 506 | ret = (number + (IRQ_EINT8 - 8)); |
| 507 | break; |
| 508 | default: |
| 509 | printk(KERN_ERR "number available : %d\n", number); |
| 510 | } |
| 511 | |
| 512 | return ret; |
| 513 | } |
| 514 | |
| 515 | static inline void exynos4_irq_eint_mask(struct irq_data *data) |
| 516 | { |
| 517 | u32 mask; |
| 518 | |
| 519 | spin_lock(&eint_lock); |
| 520 | mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); |
| 521 | mask |= eint_irq_to_bit(data->irq); |
| 522 | __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); |
| 523 | spin_unlock(&eint_lock); |
| 524 | } |
| 525 | |
| 526 | static void exynos4_irq_eint_unmask(struct irq_data *data) |
| 527 | { |
| 528 | u32 mask; |
| 529 | |
| 530 | spin_lock(&eint_lock); |
| 531 | mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); |
| 532 | mask &= ~(eint_irq_to_bit(data->irq)); |
| 533 | __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); |
| 534 | spin_unlock(&eint_lock); |
| 535 | } |
| 536 | |
| 537 | static inline void exynos4_irq_eint_ack(struct irq_data *data) |
| 538 | { |
| 539 | __raw_writel(eint_irq_to_bit(data->irq), |
| 540 | S5P_EINT_PEND(EINT_REG_NR(data->irq))); |
| 541 | } |
| 542 | |
| 543 | static void exynos4_irq_eint_maskack(struct irq_data *data) |
| 544 | { |
| 545 | exynos4_irq_eint_mask(data); |
| 546 | exynos4_irq_eint_ack(data); |
| 547 | } |
| 548 | |
| 549 | static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type) |
| 550 | { |
| 551 | int offs = EINT_OFFSET(data->irq); |
| 552 | int shift; |
| 553 | u32 ctrl, mask; |
| 554 | u32 newvalue = 0; |
| 555 | |
| 556 | switch (type) { |
| 557 | case IRQ_TYPE_EDGE_RISING: |
| 558 | newvalue = S5P_IRQ_TYPE_EDGE_RISING; |
| 559 | break; |
| 560 | |
| 561 | case IRQ_TYPE_EDGE_FALLING: |
| 562 | newvalue = S5P_IRQ_TYPE_EDGE_FALLING; |
| 563 | break; |
| 564 | |
| 565 | case IRQ_TYPE_EDGE_BOTH: |
| 566 | newvalue = S5P_IRQ_TYPE_EDGE_BOTH; |
| 567 | break; |
| 568 | |
| 569 | case IRQ_TYPE_LEVEL_LOW: |
| 570 | newvalue = S5P_IRQ_TYPE_LEVEL_LOW; |
| 571 | break; |
| 572 | |
| 573 | case IRQ_TYPE_LEVEL_HIGH: |
| 574 | newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; |
| 575 | break; |
| 576 | |
| 577 | default: |
| 578 | printk(KERN_ERR "No such irq type %d", type); |
| 579 | return -EINVAL; |
| 580 | } |
| 581 | |
| 582 | shift = (offs & 0x7) * 4; |
| 583 | mask = 0x7 << shift; |
| 584 | |
| 585 | spin_lock(&eint_lock); |
| 586 | ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq))); |
| 587 | ctrl &= ~mask; |
| 588 | ctrl |= newvalue << shift; |
| 589 | __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq))); |
| 590 | spin_unlock(&eint_lock); |
| 591 | |
| 592 | switch (offs) { |
| 593 | case 0 ... 7: |
| 594 | s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); |
| 595 | break; |
| 596 | case 8 ... 15: |
| 597 | s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE); |
| 598 | break; |
| 599 | case 16 ... 23: |
| 600 | s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE); |
| 601 | break; |
| 602 | case 24 ... 31: |
| 603 | s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE); |
| 604 | break; |
| 605 | default: |
| 606 | printk(KERN_ERR "No such irq number %d", offs); |
| 607 | } |
| 608 | |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | static struct irq_chip exynos4_irq_eint = { |
| 613 | .name = "exynos4-eint", |
| 614 | .irq_mask = exynos4_irq_eint_mask, |
| 615 | .irq_unmask = exynos4_irq_eint_unmask, |
| 616 | .irq_mask_ack = exynos4_irq_eint_maskack, |
| 617 | .irq_ack = exynos4_irq_eint_ack, |
| 618 | .irq_set_type = exynos4_irq_eint_set_type, |
| 619 | #ifdef CONFIG_PM |
| 620 | .irq_set_wake = s3c_irqext_wake, |
| 621 | #endif |
| 622 | }; |
| 623 | |
| 624 | /* |
| 625 | * exynos4_irq_demux_eint |
| 626 | * |
| 627 | * This function demuxes the IRQ from from EINTs 16 to 31. |
| 628 | * It is designed to be inlined into the specific handler |
| 629 | * s5p_irq_demux_eintX_Y. |
| 630 | * |
| 631 | * Each EINT pend/mask registers handle eight of them. |
| 632 | */ |
| 633 | static inline void exynos4_irq_demux_eint(unsigned int start) |
| 634 | { |
| 635 | unsigned int irq; |
| 636 | |
| 637 | u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); |
| 638 | u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); |
| 639 | |
| 640 | status &= ~mask; |
| 641 | status &= 0xff; |
| 642 | |
| 643 | while (status) { |
| 644 | irq = fls(status) - 1; |
| 645 | generic_handle_irq(irq + start); |
| 646 | status &= ~(1 << irq); |
| 647 | } |
| 648 | } |
| 649 | |
| 650 | static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) |
| 651 | { |
| 652 | struct irq_chip *chip = irq_get_chip(irq); |
| 653 | chained_irq_enter(chip, desc); |
| 654 | exynos4_irq_demux_eint(IRQ_EINT(16)); |
| 655 | exynos4_irq_demux_eint(IRQ_EINT(24)); |
| 656 | chained_irq_exit(chip, desc); |
| 657 | } |
| 658 | |
| 659 | static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) |
| 660 | { |
| 661 | u32 *irq_data = irq_get_handler_data(irq); |
| 662 | struct irq_chip *chip = irq_get_chip(irq); |
| 663 | |
| 664 | chained_irq_enter(chip, desc); |
| 665 | chip->irq_mask(&desc->irq_data); |
| 666 | |
| 667 | if (chip->irq_ack) |
| 668 | chip->irq_ack(&desc->irq_data); |
| 669 | |
| 670 | generic_handle_irq(*irq_data); |
| 671 | |
| 672 | chip->irq_unmask(&desc->irq_data); |
| 673 | chained_irq_exit(chip, desc); |
| 674 | } |
| 675 | |
| 676 | int __init exynos4_init_irq_eint(void) |
| 677 | { |
| 678 | int irq; |
| 679 | |
| 680 | for (irq = 0 ; irq <= 31 ; irq++) { |
| 681 | irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, |
| 682 | handle_level_irq); |
| 683 | set_irq_flags(IRQ_EINT(irq), IRQF_VALID); |
| 684 | } |
| 685 | |
| 686 | irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); |
| 687 | |
| 688 | for (irq = 0 ; irq <= 15 ; irq++) { |
| 689 | eint0_15_data[irq] = IRQ_EINT(irq); |
| 690 | |
| 691 | irq_set_handler_data(exynos4_get_irq_nr(irq), |
| 692 | &eint0_15_data[irq]); |
| 693 | irq_set_chained_handler(exynos4_get_irq_nr(irq), |
| 694 | exynos4_irq_eint0_15); |
| 695 | } |
| 696 | |
| 697 | return 0; |
| 698 | } |
| 699 | arch_initcall(exynos4_init_irq_eint); |