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Sathya Perla6b7c5b92009-03-11 23:32:03 -07001/*
Ajit Khaparded2145cd2011-03-16 08:20:46 +00002 * Copyright (C) 2005 - 2011 Emulex
Sathya Perla6b7c5b92009-03-11 23:32:03 -07003 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
Ajit Khaparded2145cd2011-03-16 08:20:46 +000011 * linux-drivers@emulex.com
Sathya Perla6b7c5b92009-03-11 23:32:03 -070012 *
Ajit Khaparded2145cd2011-03-16 08:20:46 +000013 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
Sathya Perla6b7c5b92009-03-11 23:32:03 -070016 */
17
18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
Sathya Perla6b7c5b92009-03-11 23:32:03 -070023#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
Ajit Khaparde84517482009-09-04 03:12:16 +000030#include <linux/firmware.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Sathya Perlaab1594e2011-07-25 19:10:15 +000032#include <linux/u64_stats_sync.h>
Sathya Perla6b7c5b92009-03-11 23:32:03 -070033
34#include "be_hw.h"
Parav Pandit045508a2012-03-26 14:27:13 +000035#include "be_roce.h"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070036
Sathya Perla20d5ec42012-06-05 19:37:23 +000037#define DRV_VER "4.2.248.0u"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070038#define DRV_NAME "be2net"
39#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070040#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
Ajit Khapardec4ca2372009-05-18 15:38:55 -070041#define OC_NAME "Emulex OneConnect 10Gbps NIC"
Sathya Perlafe6d2a32010-11-21 23:25:50 +000042#define OC_NAME_BE OC_NAME "(be3)"
43#define OC_NAME_LANCER OC_NAME "(Lancer)"
Ajit Khapardeecedb6a2011-12-15 06:31:38 +000044#define OC_NAME_SH OC_NAME "(Skyhawk)"
Ajit Khaparde35ecf032010-02-09 01:38:06 +000045#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070046
Ajit Khapardec4ca2372009-05-18 15:38:55 -070047#define BE_VENDOR_ID 0x19a2
Sathya Perlafe6d2a32010-11-21 23:25:50 +000048#define EMULEX_VENDOR_ID 0x10df
Ajit Khapardec4ca2372009-05-18 15:38:55 -070049#define BE_DEVICE_ID1 0x211
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070050#define BE_DEVICE_ID2 0x221
Sathya Perlafe6d2a32010-11-21 23:25:50 +000051#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
52#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
53#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
Mammatha Edhala12f4d0a2011-05-18 03:26:22 +000054#define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
Ajit Khapardeecedb6a2011-12-15 06:31:38 +000055#define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
Ajit Khaparde4762f6c2012-03-18 06:23:11 +000056#define OC_SUBSYS_DEVICE_ID1 0xE602
57#define OC_SUBSYS_DEVICE_ID2 0xE642
58#define OC_SUBSYS_DEVICE_ID3 0xE612
59#define OC_SUBSYS_DEVICE_ID4 0xE652
Ajit Khapardec4ca2372009-05-18 15:38:55 -070060
61static inline char *nic_name(struct pci_dev *pdev)
62{
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070063 switch (pdev->device) {
64 case OC_DEVICE_ID1:
Ajit Khapardec4ca2372009-05-18 15:38:55 -070065 return OC_NAME;
Ajit Khapardee254f6e2010-02-09 01:28:35 +000066 case OC_DEVICE_ID2:
Sathya Perlafe6d2a32010-11-21 23:25:50 +000067 return OC_NAME_BE;
68 case OC_DEVICE_ID3:
Mammatha Edhala12f4d0a2011-05-18 03:26:22 +000069 case OC_DEVICE_ID4:
Sathya Perlafe6d2a32010-11-21 23:25:50 +000070 return OC_NAME_LANCER;
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070071 case BE_DEVICE_ID2:
72 return BE3_NAME;
Ajit Khapardeecedb6a2011-12-15 06:31:38 +000073 case OC_DEVICE_ID5:
74 return OC_NAME_SH;
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070075 default:
Ajit Khapardec4ca2372009-05-18 15:38:55 -070076 return BE_NAME;
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070077 }
Ajit Khapardec4ca2372009-05-18 15:38:55 -070078}
79
Sathya Perla6b7c5b92009-03-11 23:32:03 -070080/* Number of bytes of an RX frame that are copied to skb->data */
Sathya Perla2e588f82011-03-11 02:49:26 +000081#define BE_HDR_LEN ((u16) 64)
Eric Dumazetbb349bb2012-01-25 03:56:30 +000082/* allocate extra space to allow tunneling decapsulation without head reallocation */
83#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
84
Sathya Perla6b7c5b92009-03-11 23:32:03 -070085#define BE_MAX_JUMBO_FRAME_SIZE 9018
86#define BE_MIN_MTU 256
87
88#define BE_NUM_VLANS_SUPPORTED 64
Sathya Perla10ef9ab2012-02-09 18:05:27 +000089#define BE_MAX_EQD 96u
Sathya Perla6b7c5b92009-03-11 23:32:03 -070090#define BE_MAX_TX_FRAG_COUNT 30
91
92#define EVNT_Q_LEN 1024
93#define TX_Q_LEN 2048
94#define TX_CQ_LEN 1024
95#define RX_Q_LEN 1024 /* Does not support any other value */
96#define RX_CQ_LEN 1024
Sathya Perla5fb379e2009-06-18 00:02:59 +000097#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070098#define MCC_CQ_LEN 256
99
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000100#define BE3_MAX_RSS_QS 8
101#define BE2_MAX_RSS_QS 4
102#define MAX_RSS_QS BE3_MAX_RSS_QS
Sathya Perlaac6a0c42011-03-21 20:49:25 +0000103#define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000104
Sathya Perla3c8def92011-06-12 20:01:58 +0000105#define MAX_TX_QS 8
Parav Pandit045508a2012-03-26 14:27:13 +0000106#define MAX_ROCE_EQS 5
107#define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS) /* RSS qs + RoCE */
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000108#define BE_TX_BUDGET 256
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700109#define BE_NAPI_WEIGHT 64
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000110#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700111#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
112
Sathya Perla8788fdc2009-07-27 22:52:03 +0000113#define FW_VER_LEN 32
114
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700115struct be_dma_mem {
116 void *va;
117 dma_addr_t dma;
118 u32 size;
119};
120
121struct be_queue_info {
122 struct be_dma_mem dma_mem;
123 u16 len;
124 u16 entry_size; /* Size of an element in the queue */
125 u16 id;
126 u16 tail, head;
127 bool created;
128 atomic_t used; /* Number of valid elements in the queue */
129};
130
Sathya Perla5fb379e2009-06-18 00:02:59 +0000131static inline u32 MODULO(u16 val, u16 limit)
132{
133 BUG_ON(limit & (limit - 1));
134 return val & (limit - 1);
135}
136
137static inline void index_adv(u16 *index, u16 val, u16 limit)
138{
139 *index = MODULO((*index + val), limit);
140}
141
142static inline void index_inc(u16 *index, u16 limit)
143{
144 *index = MODULO((*index + 1), limit);
145}
146
147static inline void *queue_head_node(struct be_queue_info *q)
148{
149 return q->dma_mem.va + q->head * q->entry_size;
150}
151
152static inline void *queue_tail_node(struct be_queue_info *q)
153{
154 return q->dma_mem.va + q->tail * q->entry_size;
155}
156
Somnath Kotur3de09452011-09-30 07:25:05 +0000157static inline void *queue_index_node(struct be_queue_info *q, u16 index)
158{
159 return q->dma_mem.va + index * q->entry_size;
160}
161
Sathya Perla5fb379e2009-06-18 00:02:59 +0000162static inline void queue_head_inc(struct be_queue_info *q)
163{
164 index_inc(&q->head, q->len);
165}
166
Padmanabh Ratnakar652bf642012-04-25 01:47:03 +0000167static inline void index_dec(u16 *index, u16 limit)
168{
169 *index = MODULO((*index - 1), limit);
170}
171
Sathya Perla5fb379e2009-06-18 00:02:59 +0000172static inline void queue_tail_inc(struct be_queue_info *q)
173{
174 index_inc(&q->tail, q->len);
175}
176
Sathya Perla5fb379e2009-06-18 00:02:59 +0000177struct be_eq_obj {
178 struct be_queue_info q;
179 char desc[32];
180
181 /* Adaptive interrupt coalescing (AIC) info */
182 bool enable_aic;
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000183 u32 min_eqd; /* in usecs */
184 u32 max_eqd; /* in usecs */
185 u32 eqd; /* configured val when aic is off */
186 u32 cur_eqd; /* in usecs */
Sathya Perla5fb379e2009-06-18 00:02:59 +0000187
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000188 u8 idx; /* array index */
189 u16 tx_budget;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000190 struct napi_struct napi;
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000191 struct be_adapter *adapter;
192} ____cacheline_aligned_in_smp;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000193
194struct be_mcc_obj {
195 struct be_queue_info q;
196 struct be_queue_info cq;
Sathya Perla7a1e9b22010-02-17 01:35:11 +0000197 bool rearm_cq;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000198};
199
Sathya Perla3abcded2010-10-03 22:12:27 -0700200struct be_tx_stats {
Sathya Perlaac124ff2011-07-25 19:10:14 +0000201 u64 tx_bytes;
202 u64 tx_pkts;
203 u64 tx_reqs;
204 u64 tx_wrbs;
205 u64 tx_compl;
206 ulong tx_jiffies;
207 u32 tx_stops;
Sathya Perlaab1594e2011-07-25 19:10:15 +0000208 struct u64_stats_sync sync;
209 struct u64_stats_sync sync_compl;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700210};
211
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700212struct be_tx_obj {
213 struct be_queue_info q;
214 struct be_queue_info cq;
215 /* Remember the skbs that were transmitted */
216 struct sk_buff *sent_skb_list[TX_Q_LEN];
Sathya Perla3c8def92011-06-12 20:01:58 +0000217 struct be_tx_stats stats;
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000218} ____cacheline_aligned_in_smp;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700219
220/* Struct to remember the pages posted for rx frags */
221struct be_rx_page_info {
222 struct page *page;
FUJITA Tomonorifac6da52010-04-01 16:53:22 +0000223 DEFINE_DMA_UNMAP_ADDR(bus);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700224 u16 page_offset;
225 bool last_page_user;
226};
227
Sathya Perla3abcded2010-10-03 22:12:27 -0700228struct be_rx_stats {
Sathya Perla3abcded2010-10-03 22:12:27 -0700229 u64 rx_bytes;
Sathya Perla3abcded2010-10-03 22:12:27 -0700230 u64 rx_pkts;
Sathya Perlaac124ff2011-07-25 19:10:14 +0000231 u64 rx_pkts_prev;
232 ulong rx_jiffies;
233 u32 rx_drops_no_skbs; /* skb allocation errors */
234 u32 rx_drops_no_frags; /* HW has no fetched frags */
235 u32 rx_post_fail; /* page post alloc failures */
Sathya Perlaac124ff2011-07-25 19:10:14 +0000236 u32 rx_compl;
Sathya Perla3abcded2010-10-03 22:12:27 -0700237 u32 rx_mcast_pkts;
Sathya Perlaac124ff2011-07-25 19:10:14 +0000238 u32 rx_compl_err; /* completions with err set */
239 u32 rx_pps; /* pkts per second */
Sathya Perlaab1594e2011-07-25 19:10:15 +0000240 struct u64_stats_sync sync;
Sathya Perla3abcded2010-10-03 22:12:27 -0700241};
242
Sathya Perla2e588f82011-03-11 02:49:26 +0000243struct be_rx_compl_info {
244 u32 rss_hash;
Somnath Kotur6709d952011-05-04 22:40:46 +0000245 u16 vlan_tag;
Sathya Perla2e588f82011-03-11 02:49:26 +0000246 u16 pkt_size;
247 u16 rxq_idx;
Sathya Perla12004ae2011-08-02 19:57:46 +0000248 u16 port;
Sathya Perla2e588f82011-03-11 02:49:26 +0000249 u8 vlanf;
250 u8 num_rcvd;
251 u8 err;
252 u8 ipf;
253 u8 tcpf;
254 u8 udpf;
255 u8 ip_csum;
256 u8 l4_csum;
257 u8 ipv6;
258 u8 vtm;
259 u8 pkt_type;
260};
261
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700262struct be_rx_obj {
Sathya Perla3abcded2010-10-03 22:12:27 -0700263 struct be_adapter *adapter;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700264 struct be_queue_info q;
265 struct be_queue_info cq;
Sathya Perla2e588f82011-03-11 02:49:26 +0000266 struct be_rx_compl_info rxcp;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700267 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
Sathya Perla3abcded2010-10-03 22:12:27 -0700268 struct be_rx_stats stats;
269 u8 rss_id;
270 bool rx_post_starved; /* Zero rx frags have been posted to BE */
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000271} ____cacheline_aligned_in_smp;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700272
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000273struct be_drv_stats {
Somnath Kotur9ae081c2011-09-30 07:23:35 +0000274 u32 be_on_die_temperature;
Sathya Perlaac124ff2011-07-25 19:10:14 +0000275 u32 eth_red_drops;
276 u32 rx_drops_no_pbuf;
277 u32 rx_drops_no_txpb;
278 u32 rx_drops_no_erx_descr;
279 u32 rx_drops_no_tpre_descr;
280 u32 rx_drops_too_many_frags;
Sathya Perlaac124ff2011-07-25 19:10:14 +0000281 u32 forwarded_packets;
282 u32 rx_drops_mtu;
283 u32 rx_crc_errors;
284 u32 rx_alignment_symbol_errors;
285 u32 rx_pause_frames;
286 u32 rx_priority_pause_frames;
287 u32 rx_control_frames;
288 u32 rx_in_range_errors;
289 u32 rx_out_range_errors;
290 u32 rx_frame_too_long;
Sathya Perlad45b9d32012-01-29 20:17:39 +0000291 u32 rx_address_mismatch_drops;
Sathya Perlaac124ff2011-07-25 19:10:14 +0000292 u32 rx_dropped_too_small;
293 u32 rx_dropped_too_short;
294 u32 rx_dropped_header_too_small;
295 u32 rx_dropped_tcp_length;
296 u32 rx_dropped_runt;
297 u32 rx_ip_checksum_errs;
298 u32 rx_tcp_checksum_errs;
299 u32 rx_udp_checksum_errs;
300 u32 tx_pauseframes;
301 u32 tx_priority_pauseframes;
302 u32 tx_controlframes;
303 u32 rxpp_fifo_overflow_drop;
304 u32 rx_input_fifo_overflow_drop;
305 u32 pmem_fifo_overflow_drop;
306 u32 jabber_events;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000307};
308
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000309struct be_vf_cfg {
Sathya Perla11ac75e2011-12-13 00:58:50 +0000310 unsigned char mac_addr[ETH_ALEN];
311 int if_handle;
312 int pmac_id;
Ajit Khapardef1f3ee12012-03-18 06:23:41 +0000313 u16 def_vid;
Sathya Perla11ac75e2011-12-13 00:58:50 +0000314 u16 vlan_tag;
315 u32 tx_rate;
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000316};
317
Sathya Perla39f1d942012-05-08 19:41:24 +0000318enum vf_state {
319 ENABLED = 0,
320 ASSIGNED = 1
321};
322
Ajit Khapardeb236916a2011-12-30 12:15:40 +0000323#define BE_FLAGS_LINK_STATUS_INIT 1
Sathya Perla191eb752012-02-23 18:50:13 +0000324#define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
Ajit Khapardefbc13f02012-03-18 06:23:21 +0000325#define BE_UC_PMAC_COUNT 30
326#define BE_VF_UC_PMAC_COUNT 2
Ajit Khapardeb236916a2011-12-30 12:15:40 +0000327
Ajit Khaparde42f11cf2012-04-21 18:53:22 +0000328struct phy_info {
329 u8 transceiver;
330 u8 autoneg;
331 u8 fc_autoneg;
332 u8 port_type;
333 u16 phy_type;
334 u16 interface_type;
335 u32 misc_params;
336 u16 auto_speeds_supported;
337 u16 fixed_speeds_supported;
338 int link_speed;
339 int forced_port_speed;
340 u32 dac_cable_len;
341 u32 advertising;
342 u32 supported;
343};
344
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700345struct be_adapter {
346 struct pci_dev *pdev;
347 struct net_device *netdev;
348
Sathya Perla8788fdc2009-07-27 22:52:03 +0000349 u8 __iomem *csr;
350 u8 __iomem *db; /* Door Bell */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000351
Ivan Vecera29849612010-12-14 05:43:19 +0000352 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000353 struct be_dma_mem mbox_mem;
354 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
355 * is stored for freeing purpose */
356 struct be_dma_mem mbox_mem_alloced;
357
358 struct be_mcc_obj mcc_obj;
359 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
360 spinlock_t mcc_cq_lock;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700361
Sathya Perlaac6a0c42011-03-21 20:49:25 +0000362 u32 num_msix_vec;
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000363 u32 num_evt_qs;
364 struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
365 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700366 bool isr_registered;
367
368 /* TX Rings */
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000369 u32 num_tx_qs;
Sathya Perla3c8def92011-06-12 20:01:58 +0000370 struct be_tx_obj tx_obj[MAX_TX_QS];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700371
372 /* Rx rings */
Sathya Perla3abcded2010-10-03 22:12:27 -0700373 u32 num_rx_qs;
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000374 struct be_rx_obj rx_obj[MAX_RX_QS];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700375 u32 big_page_size; /* Compounded page size shared by rx wrbs */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700376
Padmanabh Ratnakarecd62102011-04-03 01:54:11 +0000377 u8 eq_next_idx;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000378 struct be_drv_stats drv_stats;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000379
Ajit Khaparde82903e42010-02-09 01:34:57 +0000380 u16 vlans_added;
381 u16 max_vlans; /* Number of vlans supported */
Jesse Grossb7381272010-10-20 13:56:02 +0000382 u8 vlan_tag[VLAN_N_VID];
Somnath Koturcc4ce022010-10-21 07:11:14 -0700383 u8 vlan_prio_bmap; /* Available Priority BitMap */
384 u16 recommended_prio; /* Recommended Priority */
Sathya Perla5b8821b2011-08-02 19:57:44 +0000385 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700386
Sathya Perla3abcded2010-10-03 22:12:27 -0700387 struct be_dma_mem stats_cmd;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700388 /* Work queue used to perform periodic tasks like getting statistics */
389 struct delayed_work work;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000390 u16 work_counter;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700391
Ajit Khapardeb236916a2011-12-30 12:15:40 +0000392 u32 flags;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700393 /* Ethtool knobs and info */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700394 char fw_ver[FW_VER_LEN];
Sathya Perla30128032011-11-10 19:17:57 +0000395 int if_handle; /* Used to configure filtering */
Ajit Khapardefbc13f02012-03-18 06:23:21 +0000396 u32 *pmac_id; /* MAC addr handle used by BE card */
stephen hemminger1a642462011-04-04 11:06:40 +0000397 u32 beacon_state; /* for set_phys_id */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700398
Sathya Perlacf588472010-02-14 21:22:01 +0000399 bool eeh_err;
Sathya Perla6589ade2011-11-10 19:18:00 +0000400 bool ue_detected;
401 bool fw_timeout;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700402 u32 port_num;
Sathya Perla24307ee2009-06-18 00:09:25 +0000403 bool promiscuous;
Ajit Khaparde3486be22010-07-23 02:04:54 +0000404 u32 function_mode;
Sathya Perla3abcded2010-10-03 22:12:27 -0700405 u32 function_caps;
Ajit Khaparde9e90c962009-11-06 02:06:59 +0000406 u32 rx_fc; /* Rx flow control */
407 u32 tx_fc; /* Tx flow control */
Ajit Khapardeb2aebe62011-02-20 11:41:39 +0000408 bool stats_cmd_sent;
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000409 u8 generation; /* BladeEngine ASIC generation */
Parav Pandit045508a2012-03-26 14:27:13 +0000410 u32 if_type;
411 struct {
412 u8 __iomem *base; /* Door Bell */
413 u32 size;
414 u32 total_size;
415 u64 io_addr;
416 } roce_db;
417 u32 num_msix_roce_vec;
418 struct ocrdma_dev *ocrdma_dev;
419 struct list_head entry;
420
Sarveshwar Bandidd131e72010-05-25 16:16:32 -0700421 u32 flash_status;
422 struct completion flash_compl;
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000423
Sathya Perla39f1d942012-05-08 19:41:24 +0000424 u32 num_vfs; /* Number of VFs provisioned by PF driver */
425 u32 dev_num_vfs; /* Number of VFs supported by HW */
426 u8 virtfn;
Sathya Perla11ac75e2011-12-13 00:58:50 +0000427 struct be_vf_cfg *vf_cfg;
428 bool be3_native;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000429 u32 sli_family;
Ajit Khaparde9e1453c2011-02-20 11:42:22 +0000430 u8 hba_port_num;
Ajit Khaparde3968fa12011-02-20 11:41:53 +0000431 u16 pvid;
Ajit Khaparde42f11cf2012-04-21 18:53:22 +0000432 struct phy_info phy;
Ajit Khaparde4762f6c2012-03-18 06:23:11 +0000433 u8 wol_cap;
434 bool wol;
Ajit Khapardefbc13f02012-03-18 06:23:21 +0000435 u32 max_pmac_cnt; /* Max secondary UC MACs programmable */
436 u32 uc_macs; /* Count of secondary UC MAC programmed */
Somnath Kotur941a77d2012-05-17 22:59:03 +0000437 u32 msg_enable;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700438};
439
Sathya Perla39f1d942012-05-08 19:41:24 +0000440#define be_physfn(adapter) (!adapter->virtfn)
Sathya Perla11ac75e2011-12-13 00:58:50 +0000441#define sriov_enabled(adapter) (adapter->num_vfs > 0)
Sathya Perla39f1d942012-05-08 19:41:24 +0000442#define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
443 be_physfn(adapter))
Sathya Perla11ac75e2011-12-13 00:58:50 +0000444#define for_all_vfs(adapter, vf_cfg, i) \
445 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
446 i++, vf_cfg++)
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000447
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000448/* BladeEngine Generation numbers */
449#define BE_GEN2 2
450#define BE_GEN3 3
451
Sathya Perla5b8821b2011-08-02 19:57:44 +0000452#define ON 1
453#define OFF 0
Mammatha Edhala12f4d0a2011-05-18 03:26:22 +0000454#define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \
455 (adapter->pdev->device == OC_DEVICE_ID4))
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000456
Parav Pandit045508a2012-03-26 14:27:13 +0000457#define be_roce_supported(adapter) ((adapter->if_type == SLI_INTF_TYPE_3 || \
458 adapter->sli_family == SKYHAWK_SLI_FAMILY) && \
459 (adapter->function_mode & RDMA_ENABLED))
460
Stephen Hemminger0fc0b732009-09-02 01:03:33 -0700461extern const struct ethtool_ops be_ethtool_ops;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700462
Sathya Perlaac6a0c42011-03-21 20:49:25 +0000463#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000464#define num_irqs(adapter) (msix_enabled(adapter) ? \
465 adapter->num_msix_vec : 1)
466#define tx_stats(txo) (&(txo)->stats)
467#define rx_stats(rxo) (&(rxo)->stats)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700468
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000469/* The default RXQ is the last RXQ */
470#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700471
Sathya Perla3abcded2010-10-03 22:12:27 -0700472#define for_all_rx_queues(adapter, rxo, i) \
473 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
474 i++, rxo++)
475
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000476/* Skip the default non-rss queue (last one)*/
Sathya Perla3abcded2010-10-03 22:12:27 -0700477#define for_all_rss_queues(adapter, rxo, i) \
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000478 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
Sathya Perla3abcded2010-10-03 22:12:27 -0700479 i++, rxo++)
480
Sathya Perla3c8def92011-06-12 20:01:58 +0000481#define for_all_tx_queues(adapter, txo, i) \
482 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
483 i++, txo++)
484
Sathya Perla10ef9ab2012-02-09 18:05:27 +0000485#define for_all_evt_queues(adapter, eqo, i) \
486 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
487 i++, eqo++)
488
489#define is_mcc_eqo(eqo) (eqo->idx == 0)
490#define mcc_eqo(adapter) (&adapter->eq_obj[0])
491
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700492#define PAGE_SHIFT_4K 12
493#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
494
495/* Returns number of pages spanned by the data starting at the given addr */
496#define PAGES_4K_SPANNED(_address, size) \
497 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
498 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
499
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700500/* Returns bit offset within a DWORD of a bitfield */
501#define AMAP_BIT_OFFSET(_struct, field) \
502 (((size_t)&(((_struct *)0)->field))%32)
503
504/* Returns the bit mask of the field that is NOT shifted into location. */
505static inline u32 amap_mask(u32 bitsize)
506{
507 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
508}
509
510static inline void
511amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
512{
513 u32 *dw = (u32 *) ptr + dw_offset;
514 *dw &= ~(mask << offset);
515 *dw |= (mask & value) << offset;
516}
517
518#define AMAP_SET_BITS(_struct, field, ptr, val) \
519 amap_set(ptr, \
520 offsetof(_struct, field)/32, \
521 amap_mask(sizeof(((_struct *)0)->field)), \
522 AMAP_BIT_OFFSET(_struct, field), \
523 val)
524
525static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
526{
527 u32 *dw = (u32 *) ptr;
528 return mask & (*(dw + dw_offset) >> offset);
529}
530
531#define AMAP_GET_BITS(_struct, field, ptr) \
532 amap_get(ptr, \
533 offsetof(_struct, field)/32, \
534 amap_mask(sizeof(((_struct *)0)->field)), \
535 AMAP_BIT_OFFSET(_struct, field))
536
537#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
538#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
539static inline void swap_dws(void *wrb, int len)
540{
541#ifdef __BIG_ENDIAN
542 u32 *dw = wrb;
543 BUG_ON(len % 4);
544 do {
545 *dw = cpu_to_le32(*dw);
546 dw++;
547 len -= 4;
548 } while (len);
549#endif /* __BIG_ENDIAN */
550}
551
552static inline u8 is_tcp_pkt(struct sk_buff *skb)
553{
554 u8 val = 0;
555
556 if (ip_hdr(skb)->version == 4)
557 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
558 else if (ip_hdr(skb)->version == 6)
559 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
560
561 return val;
562}
563
564static inline u8 is_udp_pkt(struct sk_buff *skb)
565{
566 u8 val = 0;
567
568 if (ip_hdr(skb)->version == 4)
569 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
570 else if (ip_hdr(skb)->version == 6)
571 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
572
573 return val;
574}
575
Somnath Kotur93040ae2012-06-26 22:32:10 +0000576static inline bool is_ipv4_pkt(struct sk_buff *skb)
577{
578 return skb->protocol == ntohs(ETH_P_IP) && ip_hdr(skb)->version == 4;
579}
580
Ajit Khaparde6d87f5c2010-08-25 00:32:33 +0000581static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
582{
583 u32 addr;
584
585 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
586
587 mac[5] = (u8)(addr & 0xFF);
588 mac[4] = (u8)((addr >> 8) & 0xFF);
589 mac[3] = (u8)((addr >> 16) & 0xFF);
Ajit Khaparde7a2414a2011-02-11 13:36:18 +0000590 /* Use the OUI from the current MAC address */
591 memcpy(mac, adapter->netdev->dev_addr, 3);
Ajit Khaparde6d87f5c2010-08-25 00:32:33 +0000592}
593
Ajit Khaparde4b972912011-04-06 18:07:43 +0000594static inline bool be_multi_rxq(const struct be_adapter *adapter)
595{
596 return adapter->num_rx_qs > 1;
597}
598
Sathya Perla6589ade2011-11-10 19:18:00 +0000599static inline bool be_error(struct be_adapter *adapter)
600{
601 return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout;
602}
603
Ajit Khaparde4762f6c2012-03-18 06:23:11 +0000604static inline bool be_is_wol_excluded(struct be_adapter *adapter)
605{
606 struct pci_dev *pdev = adapter->pdev;
607
608 if (!be_physfn(adapter))
609 return true;
610
611 switch (pdev->subsystem_device) {
612 case OC_SUBSYS_DEVICE_ID1:
613 case OC_SUBSYS_DEVICE_ID2:
614 case OC_SUBSYS_DEVICE_ID3:
615 case OC_SUBSYS_DEVICE_ID4:
616 return true;
617 default:
618 return false;
619 }
620}
621
Parav Pandit045508a2012-03-26 14:27:13 +0000622static inline bool be_type_2_3(struct be_adapter *adapter)
623{
624 return (adapter->if_type == SLI_INTF_TYPE_2 ||
625 adapter->if_type == SLI_INTF_TYPE_3) ? true : false;
626}
627
Sathya Perla8788fdc2009-07-27 22:52:03 +0000628extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
Sathya Perla5fb379e2009-06-18 00:02:59 +0000629 u16 num_popped);
Ajit Khapardeb236916a2011-12-30 12:15:40 +0000630extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
Ajit Khaparde89a88ab2011-05-16 07:36:18 +0000631extern void be_parse_stats(struct be_adapter *adapter);
Ajit Khaparde84517482009-09-04 03:12:16 +0000632extern int be_load_fw(struct be_adapter *adapter, u8 *func);
Ajit Khaparde4762f6c2012-03-18 06:23:11 +0000633extern bool be_is_wol_supported(struct be_adapter *adapter);
Ajit Khaparde42f11cf2012-04-21 18:53:22 +0000634extern bool be_pause_supported(struct be_adapter *adapter);
Somnath Kotur941a77d2012-05-17 22:59:03 +0000635extern u32 be_get_fw_log_level(struct be_adapter *adapter);
636
Parav Pandit045508a2012-03-26 14:27:13 +0000637/*
638 * internal function to initialize-cleanup roce device.
639 */
640extern void be_roce_dev_add(struct be_adapter *);
641extern void be_roce_dev_remove(struct be_adapter *);
642
643/*
644 * internal function to open-close roce device during ifup-ifdown.
645 */
646extern void be_roce_dev_open(struct be_adapter *);
647extern void be_roce_dev_close(struct be_adapter *);
648
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700649#endif /* BE_H */