Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xHCI host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2008 Intel Corp. |
| 5 | * |
| 6 | * Author: Sarah Sharp |
| 7 | * Some code borrowed from the Linux EHCI driver. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software Foundation, |
| 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Ring initialization rules: |
| 25 | * 1. Each segment is initialized to zero, except for link TRBs. |
| 26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or |
| 27 | * Consumer Cycle State (CCS), depending on ring function. |
| 28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. |
| 29 | * |
| 30 | * Ring behavior rules: |
| 31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at |
| 32 | * least one free TRB in the ring. This is useful if you want to turn that |
| 33 | * into a link TRB and expand the ring. |
| 34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a |
| 35 | * link TRB, then load the pointer with the address in the link TRB. If the |
| 36 | * link TRB had its toggle bit set, you may need to update the ring cycle |
| 37 | * state (see cycle bit rules). You may have to do this multiple times |
| 38 | * until you reach a non-link TRB. |
| 39 | * 3. A ring is full if enqueue++ (for the definition of increment above) |
| 40 | * equals the dequeue pointer. |
| 41 | * |
| 42 | * Cycle bit rules: |
| 43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit |
| 44 | * in a link TRB, it must toggle the ring cycle state. |
| 45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit |
| 46 | * in a link TRB, it must toggle the ring cycle state. |
| 47 | * |
| 48 | * Producer rules: |
| 49 | * 1. Check if ring is full before you enqueue. |
| 50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. |
| 51 | * Update enqueue pointer between each write (which may update the ring |
| 52 | * cycle state). |
| 53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command |
| 54 | * and endpoint rings. If HC is the producer for the event ring, |
| 55 | * and it generates an interrupt according to interrupt modulation rules. |
| 56 | * |
| 57 | * Consumer rules: |
| 58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, |
| 59 | * the TRB is owned by the consumer. |
| 60 | * 2. Update dequeue pointer (which may update the ring cycle state) and |
| 61 | * continue processing TRBs until you reach a TRB which is not owned by you. |
| 62 | * 3. Notify the producer. SW is the consumer for the event ring, and it |
| 63 | * updates event ring dequeue pointer. HC is the consumer for the command and |
| 64 | * endpoint rings; it generates events on the event ring for these. |
| 65 | */ |
| 66 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 67 | #include <linux/scatterlist.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 68 | #include <linux/slab.h> |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 69 | #include "xhci.h" |
| 70 | |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 71 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, |
| 72 | struct xhci_virt_device *virt_dev, |
| 73 | struct xhci_event_cmd *event); |
| 74 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 75 | /* |
| 76 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA |
| 77 | * address of the TRB. |
| 78 | */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 79 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 80 | union xhci_trb *trb) |
| 81 | { |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 82 | unsigned long segment_offset; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 83 | |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 84 | if (!seg || !trb || trb < seg->trbs) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 85 | return 0; |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 86 | /* offset in TRBs */ |
| 87 | segment_offset = trb - seg->trbs; |
| 88 | if (segment_offset > TRBS_PER_SEGMENT) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 89 | return 0; |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 90 | return seg->dma + (segment_offset * sizeof(*trb)); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | /* Does this link TRB point to the first segment in a ring, |
| 94 | * or was the previous TRB the last TRB on the last segment in the ERST? |
| 95 | */ |
Dmitry Torokhov | 575688e | 2011-03-20 02:15:16 -0700 | [diff] [blame] | 96 | static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 97 | struct xhci_segment *seg, union xhci_trb *trb) |
| 98 | { |
| 99 | if (ring == xhci->event_ring) |
| 100 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && |
| 101 | (seg->next == xhci->event_ring->first_seg); |
| 102 | else |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 103 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring |
| 107 | * segment? I.e. would the updated event TRB pointer step off the end of the |
| 108 | * event seg? |
| 109 | */ |
Dmitry Torokhov | 575688e | 2011-03-20 02:15:16 -0700 | [diff] [blame] | 110 | static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 111 | struct xhci_segment *seg, union xhci_trb *trb) |
| 112 | { |
| 113 | if (ring == xhci->event_ring) |
| 114 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; |
| 115 | else |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 116 | return TRB_TYPE_LINK_LE32(trb->link.control); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 117 | } |
| 118 | |
Dmitry Torokhov | 575688e | 2011-03-20 02:15:16 -0700 | [diff] [blame] | 119 | static int enqueue_is_link_trb(struct xhci_ring *ring) |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 120 | { |
| 121 | struct xhci_link_trb *link = &ring->enqueue->link; |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 122 | return TRB_TYPE_LINK_LE32(link->control); |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 123 | } |
| 124 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 125 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
| 126 | * TRB is in a new segment. This does not skip over link TRBs, and it does not |
| 127 | * effect the ring dequeue or enqueue pointers. |
| 128 | */ |
| 129 | static void next_trb(struct xhci_hcd *xhci, |
| 130 | struct xhci_ring *ring, |
| 131 | struct xhci_segment **seg, |
| 132 | union xhci_trb **trb) |
| 133 | { |
| 134 | if (last_trb(xhci, ring, *seg, *trb)) { |
| 135 | *seg = (*seg)->next; |
| 136 | *trb = ((*seg)->trbs); |
| 137 | } else { |
John Youn | a1669b2 | 2010-08-09 13:56:11 -0700 | [diff] [blame] | 138 | (*trb)++; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 139 | } |
| 140 | } |
| 141 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 142 | /* |
| 143 | * See Cycle bit rules. SW is the consumer for the event ring only. |
| 144 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. |
| 145 | */ |
| 146 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) |
| 147 | { |
| 148 | union xhci_trb *next = ++(ring->dequeue); |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 149 | unsigned long long addr; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 150 | |
| 151 | ring->deq_updates++; |
| 152 | /* Update the dequeue pointer further if that was a link TRB or we're at |
| 153 | * the end of an event ring segment (which doesn't have link TRBS) |
| 154 | */ |
| 155 | while (last_trb(xhci, ring, ring->deq_seg, next)) { |
| 156 | if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) { |
| 157 | ring->cycle_state = (ring->cycle_state ? 0 : 1); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 158 | } |
| 159 | ring->deq_seg = ring->deq_seg->next; |
| 160 | ring->dequeue = ring->deq_seg->trbs; |
| 161 | next = ring->dequeue; |
| 162 | } |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 163 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | /* |
| 167 | * See Cycle bit rules. SW is the consumer for the event ring only. |
| 168 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. |
| 169 | * |
| 170 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the |
| 171 | * chain bit is set), then set the chain bit in all the following link TRBs. |
| 172 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs |
| 173 | * have their chain bit cleared (so that each Link TRB is a separate TD). |
| 174 | * |
| 175 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit |
Sarah Sharp | b0567b3 | 2009-08-07 14:04:36 -0700 | [diff] [blame] | 176 | * set, but other sections talk about dealing with the chain bit set. This was |
| 177 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 |
| 178 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 179 | * |
| 180 | * @more_trbs_coming: Will you enqueue more TRBs before calling |
| 181 | * prepare_transfer()? |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 182 | */ |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 183 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 184 | bool consumer, bool more_trbs_coming, bool isoc) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 185 | { |
| 186 | u32 chain; |
| 187 | union xhci_trb *next; |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 188 | unsigned long long addr; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 189 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 190 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 191 | next = ++(ring->enqueue); |
| 192 | |
| 193 | ring->enq_updates++; |
| 194 | /* Update the dequeue pointer further if that was a link TRB or we're at |
| 195 | * the end of an event ring segment (which doesn't have link TRBS) |
| 196 | */ |
| 197 | while (last_trb(xhci, ring, ring->enq_seg, next)) { |
| 198 | if (!consumer) { |
| 199 | if (ring != xhci->event_ring) { |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 200 | /* |
| 201 | * If the caller doesn't plan on enqueueing more |
| 202 | * TDs before ringing the doorbell, then we |
| 203 | * don't want to give the link TRB to the |
| 204 | * hardware just yet. We'll give the link TRB |
| 205 | * back in prepare_ring() just before we enqueue |
| 206 | * the TD at the top of the ring. |
| 207 | */ |
| 208 | if (!chain && !more_trbs_coming) |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 209 | break; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 210 | |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 211 | /* If we're not dealing with 0.95 hardware or |
| 212 | * isoc rings on AMD 0.96 host, |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 213 | * carry over the chain bit of the previous TRB |
| 214 | * (which may mean the chain bit is cleared). |
| 215 | */ |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 216 | if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST)) |
| 217 | && !xhci_link_trb_quirk(xhci)) { |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 218 | next->link.control &= |
| 219 | cpu_to_le32(~TRB_CHAIN); |
| 220 | next->link.control |= |
| 221 | cpu_to_le32(chain); |
Sarah Sharp | b0567b3 | 2009-08-07 14:04:36 -0700 | [diff] [blame] | 222 | } |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 223 | /* Give this link TRB to the hardware */ |
| 224 | wmb(); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 225 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 226 | } |
| 227 | /* Toggle the cycle bit after the last ring segment. */ |
| 228 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { |
| 229 | ring->cycle_state = (ring->cycle_state ? 0 : 1); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 230 | } |
| 231 | } |
| 232 | ring->enq_seg = ring->enq_seg->next; |
| 233 | ring->enqueue = ring->enq_seg->trbs; |
| 234 | next = ring->enqueue; |
| 235 | } |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 236 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | /* |
| 240 | * Check to see if there's room to enqueue num_trbs on the ring. See rules |
| 241 | * above. |
| 242 | * FIXME: this would be simpler and faster if we just kept track of the number |
| 243 | * of free TRBs in a ring. |
| 244 | */ |
| 245 | static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
| 246 | unsigned int num_trbs) |
| 247 | { |
| 248 | int i; |
| 249 | union xhci_trb *enq = ring->enqueue; |
| 250 | struct xhci_segment *enq_seg = ring->enq_seg; |
Sarah Sharp | 44ebd03 | 2010-05-18 16:05:26 -0700 | [diff] [blame] | 251 | struct xhci_segment *cur_seg; |
| 252 | unsigned int left_on_ring; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 253 | |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 254 | /* If we are currently pointing to a link TRB, advance the |
| 255 | * enqueue pointer before checking for space */ |
| 256 | while (last_trb(xhci, ring, enq_seg, enq)) { |
| 257 | enq_seg = enq_seg->next; |
| 258 | enq = enq_seg->trbs; |
| 259 | } |
| 260 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 261 | /* Check if ring is empty */ |
Sarah Sharp | 44ebd03 | 2010-05-18 16:05:26 -0700 | [diff] [blame] | 262 | if (enq == ring->dequeue) { |
| 263 | /* Can't use link trbs */ |
| 264 | left_on_ring = TRBS_PER_SEGMENT - 1; |
| 265 | for (cur_seg = enq_seg->next; cur_seg != enq_seg; |
| 266 | cur_seg = cur_seg->next) |
| 267 | left_on_ring += TRBS_PER_SEGMENT - 1; |
| 268 | |
| 269 | /* Always need one TRB free in the ring. */ |
| 270 | left_on_ring -= 1; |
| 271 | if (num_trbs > left_on_ring) { |
| 272 | xhci_warn(xhci, "Not enough room on ring; " |
| 273 | "need %u TRBs, %u TRBs left\n", |
| 274 | num_trbs, left_on_ring); |
| 275 | return 0; |
| 276 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 277 | return 1; |
Sarah Sharp | 44ebd03 | 2010-05-18 16:05:26 -0700 | [diff] [blame] | 278 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 279 | /* Make sure there's an extra empty TRB available */ |
| 280 | for (i = 0; i <= num_trbs; ++i) { |
| 281 | if (enq == ring->dequeue) |
| 282 | return 0; |
| 283 | enq++; |
| 284 | while (last_trb(xhci, ring, enq_seg, enq)) { |
| 285 | enq_seg = enq_seg->next; |
| 286 | enq = enq_seg->trbs; |
| 287 | } |
| 288 | } |
| 289 | return 1; |
| 290 | } |
| 291 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 292 | /* Ring the host controller doorbell after placing a command on the ring */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 293 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 294 | { |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 295 | xhci_dbg(xhci, "// Ding dong!\n"); |
Matthew Wilcox | 50d64676 | 2010-12-15 14:18:11 -0500 | [diff] [blame] | 296 | xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 297 | /* Flush PCI posted writes */ |
| 298 | xhci_readl(xhci, &xhci->dba->doorbell[0]); |
| 299 | } |
| 300 | |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 301 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 302 | unsigned int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 303 | unsigned int ep_index, |
| 304 | unsigned int stream_id) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 305 | { |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 306 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
Matthew Wilcox | 50d64676 | 2010-12-15 14:18:11 -0500 | [diff] [blame] | 307 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 308 | unsigned int ep_state = ep->ep_state; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 309 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 310 | /* Don't ring the doorbell for this endpoint if there are pending |
Matthew Wilcox | 50d64676 | 2010-12-15 14:18:11 -0500 | [diff] [blame] | 311 | * cancellations because we don't want to interrupt processing. |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 312 | * We don't want to restart any stream rings if there's a set dequeue |
| 313 | * pointer command pending because the device can choose to start any |
| 314 | * stream once the endpoint is on the HW schedule. |
| 315 | * FIXME - check all the stream rings for pending cancellations. |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 316 | */ |
Matthew Wilcox | 50d64676 | 2010-12-15 14:18:11 -0500 | [diff] [blame] | 317 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
| 318 | (ep_state & EP_HALTED)) |
| 319 | return; |
| 320 | xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr); |
| 321 | /* The CPU has better things to do at this point than wait for a |
| 322 | * write-posting flush. It'll get there soon enough. |
| 323 | */ |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 324 | } |
| 325 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 326 | /* Ring the doorbell for any rings with pending URBs */ |
| 327 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, |
| 328 | unsigned int slot_id, |
| 329 | unsigned int ep_index) |
| 330 | { |
| 331 | unsigned int stream_id; |
| 332 | struct xhci_virt_ep *ep; |
| 333 | |
| 334 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 335 | |
| 336 | /* A ring has pending URBs if its TD list is not empty */ |
| 337 | if (!(ep->ep_state & EP_HAS_STREAMS)) { |
| 338 | if (!(list_empty(&ep->ring->td_list))) |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 339 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 340 | return; |
| 341 | } |
| 342 | |
| 343 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; |
| 344 | stream_id++) { |
| 345 | struct xhci_stream_info *stream_info = ep->stream_info; |
| 346 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 347 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
| 348 | stream_id); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 349 | } |
| 350 | } |
| 351 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 352 | /* |
| 353 | * Find the segment that trb is in. Start searching in start_seg. |
| 354 | * If we must move past a segment that has a link TRB with a toggle cycle state |
| 355 | * bit set, then we will toggle the value pointed at by cycle_state. |
| 356 | */ |
| 357 | static struct xhci_segment *find_trb_seg( |
| 358 | struct xhci_segment *start_seg, |
| 359 | union xhci_trb *trb, int *cycle_state) |
| 360 | { |
| 361 | struct xhci_segment *cur_seg = start_seg; |
| 362 | struct xhci_generic_trb *generic_trb; |
| 363 | |
| 364 | while (cur_seg->trbs > trb || |
| 365 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { |
| 366 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 367 | if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE)) |
Sarah Sharp | ba0a4d9 | 2011-02-23 18:13:43 -0800 | [diff] [blame] | 368 | *cycle_state ^= 0x1; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 369 | cur_seg = cur_seg->next; |
| 370 | if (cur_seg == start_seg) |
| 371 | /* Looped over the entire list. Oops! */ |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 372 | return NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 373 | } |
| 374 | return cur_seg; |
| 375 | } |
| 376 | |
Sarah Sharp | 021bff9 | 2010-07-29 22:12:20 -0700 | [diff] [blame] | 377 | |
| 378 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, |
| 379 | unsigned int slot_id, unsigned int ep_index, |
| 380 | unsigned int stream_id) |
| 381 | { |
| 382 | struct xhci_virt_ep *ep; |
| 383 | |
| 384 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 385 | /* Common case: no streams */ |
| 386 | if (!(ep->ep_state & EP_HAS_STREAMS)) |
| 387 | return ep->ring; |
| 388 | |
| 389 | if (stream_id == 0) { |
| 390 | xhci_warn(xhci, |
| 391 | "WARN: Slot ID %u, ep index %u has streams, " |
| 392 | "but URB has no stream ID.\n", |
| 393 | slot_id, ep_index); |
| 394 | return NULL; |
| 395 | } |
| 396 | |
| 397 | if (stream_id < ep->stream_info->num_streams) |
| 398 | return ep->stream_info->stream_rings[stream_id]; |
| 399 | |
| 400 | xhci_warn(xhci, |
| 401 | "WARN: Slot ID %u, ep index %u has " |
| 402 | "stream IDs 1 to %u allocated, " |
| 403 | "but stream ID %u is requested.\n", |
| 404 | slot_id, ep_index, |
| 405 | ep->stream_info->num_streams - 1, |
| 406 | stream_id); |
| 407 | return NULL; |
| 408 | } |
| 409 | |
| 410 | /* Get the right ring for the given URB. |
| 411 | * If the endpoint supports streams, boundary check the URB's stream ID. |
| 412 | * If the endpoint doesn't support streams, return the singular endpoint ring. |
| 413 | */ |
| 414 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, |
| 415 | struct urb *urb) |
| 416 | { |
| 417 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, |
| 418 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); |
| 419 | } |
| 420 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 421 | /* |
| 422 | * Move the xHC's endpoint ring dequeue pointer past cur_td. |
| 423 | * Record the new state of the xHC's endpoint ring dequeue segment, |
| 424 | * dequeue pointer, and new consumer cycle state in state. |
| 425 | * Update our internal representation of the ring's dequeue pointer. |
| 426 | * |
| 427 | * We do this in three jumps: |
| 428 | * - First we update our new ring state to be the same as when the xHC stopped. |
| 429 | * - Then we traverse the ring to find the segment that contains |
| 430 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass |
| 431 | * any link TRBs with the toggle cycle bit set. |
| 432 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit |
| 433 | * if we've moved it past a link TRB with the toggle cycle bit set. |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 434 | * |
| 435 | * Some of the uses of xhci_generic_trb are grotty, but if they're done |
| 436 | * with correct __le32 accesses they should work fine. Only users of this are |
| 437 | * in here. |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 438 | */ |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 439 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 440 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 441 | unsigned int stream_id, struct xhci_td *cur_td, |
| 442 | struct xhci_dequeue_state *state) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 443 | { |
| 444 | struct xhci_virt_device *dev = xhci->devs[slot_id]; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 445 | struct xhci_ring *ep_ring; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 446 | struct xhci_generic_trb *trb; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 447 | struct xhci_ep_ctx *ep_ctx; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 448 | dma_addr_t addr; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 449 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 450 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
| 451 | ep_index, stream_id); |
| 452 | if (!ep_ring) { |
| 453 | xhci_warn(xhci, "WARN can't find new dequeue state " |
| 454 | "for invalid stream ID %u.\n", |
| 455 | stream_id); |
| 456 | return; |
| 457 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 458 | state->new_cycle_state = 0; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 459 | xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 460 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 461 | dev->eps[ep_index].stopped_trb, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 462 | &state->new_cycle_state); |
Paul Zimmerman | 68e41c5 | 2011-02-12 14:06:06 -0800 | [diff] [blame] | 463 | if (!state->new_deq_seg) { |
| 464 | WARN_ON(1); |
| 465 | return; |
| 466 | } |
| 467 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 468 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 469 | xhci_dbg(xhci, "Finding endpoint context\n"); |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 470 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 471 | state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 472 | |
| 473 | state->new_deq_ptr = cur_td->last_trb; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 474 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 475 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
| 476 | state->new_deq_ptr, |
| 477 | &state->new_cycle_state); |
Paul Zimmerman | 68e41c5 | 2011-02-12 14:06:06 -0800 | [diff] [blame] | 478 | if (!state->new_deq_seg) { |
| 479 | WARN_ON(1); |
| 480 | return; |
| 481 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 482 | |
| 483 | trb = &state->new_deq_ptr->generic; |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 484 | if (TRB_TYPE_LINK_LE32(trb->field[3]) && |
| 485 | (trb->field[3] & cpu_to_le32(LINK_TOGGLE))) |
Sarah Sharp | ba0a4d9 | 2011-02-23 18:13:43 -0800 | [diff] [blame] | 486 | state->new_cycle_state ^= 0x1; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 487 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); |
| 488 | |
Sarah Sharp | 01a1fdb | 2011-02-23 18:12:29 -0800 | [diff] [blame] | 489 | /* |
| 490 | * If there is only one segment in a ring, find_trb_seg()'s while loop |
| 491 | * will not run, and it will return before it has a chance to see if it |
| 492 | * needs to toggle the cycle bit. It can't tell if the stalled transfer |
| 493 | * ended just before the link TRB on a one-segment ring, or if the TD |
| 494 | * wrapped around the top of the ring, because it doesn't have the TD in |
| 495 | * question. Look for the one-segment case where stalled TRB's address |
| 496 | * is greater than the new dequeue pointer address. |
| 497 | */ |
| 498 | if (ep_ring->first_seg == ep_ring->first_seg->next && |
| 499 | state->new_deq_ptr < dev->eps[ep_index].stopped_trb) |
| 500 | state->new_cycle_state ^= 0x1; |
| 501 | xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state); |
| 502 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 503 | /* Don't update the ring cycle state for the producer (us). */ |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 504 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
| 505 | state->new_deq_seg); |
| 506 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); |
| 507 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", |
| 508 | (unsigned long long) addr); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 509 | } |
| 510 | |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 511 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
| 512 | * (The last TRB actually points to the ring enqueue pointer, which is not part |
| 513 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. |
| 514 | */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 515 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 516 | struct xhci_td *cur_td, bool flip_cycle) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 517 | { |
| 518 | struct xhci_segment *cur_seg; |
| 519 | union xhci_trb *cur_trb; |
| 520 | |
| 521 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; |
| 522 | true; |
| 523 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 524 | if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 525 | /* Unchain any chained Link TRBs, but |
| 526 | * leave the pointers intact. |
| 527 | */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 528 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 529 | /* Flip the cycle bit (link TRBs can't be the first |
| 530 | * or last TRB). |
| 531 | */ |
| 532 | if (flip_cycle) |
| 533 | cur_trb->generic.field[3] ^= |
| 534 | cpu_to_le32(TRB_CYCLE); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 535 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 536 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
| 537 | "in seg %p (0x%llx dma)\n", |
| 538 | cur_trb, |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 539 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 540 | cur_seg, |
| 541 | (unsigned long long)cur_seg->dma); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 542 | } else { |
| 543 | cur_trb->generic.field[0] = 0; |
| 544 | cur_trb->generic.field[1] = 0; |
| 545 | cur_trb->generic.field[2] = 0; |
| 546 | /* Preserve only the cycle bit of this TRB */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 547 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 548 | /* Flip the cycle bit except on the first or last TRB */ |
| 549 | if (flip_cycle && cur_trb != cur_td->first_trb && |
| 550 | cur_trb != cur_td->last_trb) |
| 551 | cur_trb->generic.field[3] ^= |
| 552 | cpu_to_le32(TRB_CYCLE); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 553 | cur_trb->generic.field[3] |= cpu_to_le32( |
| 554 | TRB_TYPE(TRB_TR_NOOP)); |
Sarah Sharp | 79688ac | 2011-12-19 16:56:04 -0800 | [diff] [blame] | 555 | xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n", |
| 556 | (unsigned long long) |
| 557 | xhci_trb_virt_to_dma(cur_seg, cur_trb)); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 558 | } |
| 559 | if (cur_trb == cur_td->last_trb) |
| 560 | break; |
| 561 | } |
| 562 | } |
| 563 | |
| 564 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 565 | unsigned int ep_index, unsigned int stream_id, |
| 566 | struct xhci_segment *deq_seg, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 567 | union xhci_trb *deq_ptr, u32 cycle_state); |
| 568 | |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 569 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 570 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 571 | unsigned int stream_id, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 572 | struct xhci_dequeue_state *deq_state) |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 573 | { |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 574 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 575 | |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 576 | xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " |
| 577 | "new deq ptr = %p (0x%llx dma), new cycle = %u\n", |
| 578 | deq_state->new_deq_seg, |
| 579 | (unsigned long long)deq_state->new_deq_seg->dma, |
| 580 | deq_state->new_deq_ptr, |
| 581 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), |
| 582 | deq_state->new_cycle_state); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 583 | queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 584 | deq_state->new_deq_seg, |
| 585 | deq_state->new_deq_ptr, |
| 586 | (u32) deq_state->new_cycle_state); |
| 587 | /* Stop the TD queueing code from ringing the doorbell until |
| 588 | * this command completes. The HC won't set the dequeue pointer |
| 589 | * if the ring is running, and ringing the doorbell starts the |
| 590 | * ring running. |
| 591 | */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 592 | ep->ep_state |= SET_DEQ_PENDING; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 593 | } |
| 594 | |
Dmitry Torokhov | 575688e | 2011-03-20 02:15:16 -0700 | [diff] [blame] | 595 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 596 | struct xhci_virt_ep *ep) |
| 597 | { |
| 598 | ep->ep_state &= ~EP_HALT_PENDING; |
| 599 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the |
| 600 | * timer is running on another CPU, we don't decrement stop_cmds_pending |
| 601 | * (since we didn't successfully stop the watchdog timer). |
| 602 | */ |
| 603 | if (del_timer(&ep->stop_cmd_timer)) |
| 604 | ep->stop_cmds_pending--; |
| 605 | } |
| 606 | |
| 607 | /* Must be called with xhci->lock held in interrupt context */ |
| 608 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
| 609 | struct xhci_td *cur_td, int status, char *adjective) |
| 610 | { |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 611 | struct usb_hcd *hcd; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 612 | struct urb *urb; |
| 613 | struct urb_priv *urb_priv; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 614 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 615 | urb = cur_td->urb; |
| 616 | urb_priv = urb->hcpriv; |
| 617 | urb_priv->td_cnt++; |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 618 | hcd = bus_to_hcd(urb->dev->bus); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 619 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 620 | /* Only giveback urb when this is the last td in urb */ |
| 621 | if (urb_priv->td_cnt == urb_priv->length) { |
Andiry Xu | c41136b | 2011-03-22 17:08:14 +0800 | [diff] [blame] | 622 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
| 623 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; |
| 624 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
| 625 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
| 626 | usb_amd_quirk_pll_enable(); |
| 627 | } |
| 628 | } |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 629 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 630 | |
| 631 | spin_unlock(&xhci->lock); |
| 632 | usb_hcd_giveback_urb(hcd, urb, status); |
| 633 | xhci_urb_free_priv(xhci, urb_priv); |
| 634 | spin_lock(&xhci->lock); |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 635 | } |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 636 | } |
| 637 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 638 | /* |
| 639 | * When we get a command completion for a Stop Endpoint Command, we need to |
| 640 | * unlink any cancelled TDs from the ring. There are two ways to do that: |
| 641 | * |
| 642 | * 1. If the HW was in the middle of processing the TD that needs to be |
| 643 | * cancelled, then we must move the ring's dequeue pointer past the last TRB |
| 644 | * in the TD with a Set Dequeue Pointer Command. |
| 645 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain |
| 646 | * bit cleared) so that the HW will skip over them. |
| 647 | */ |
| 648 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 649 | union xhci_trb *trb, struct xhci_event_cmd *event) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 650 | { |
| 651 | unsigned int slot_id; |
| 652 | unsigned int ep_index; |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 653 | struct xhci_virt_device *virt_dev; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 654 | struct xhci_ring *ep_ring; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 655 | struct xhci_virt_ep *ep; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 656 | struct list_head *entry; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 657 | struct xhci_td *cur_td = NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 658 | struct xhci_td *last_unlinked_td; |
| 659 | |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 660 | struct xhci_dequeue_state deq_state; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 661 | |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 662 | if (unlikely(TRB_TO_SUSPEND_PORT( |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 663 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) { |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 664 | slot_id = TRB_TO_SLOT_ID( |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 665 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 666 | virt_dev = xhci->devs[slot_id]; |
| 667 | if (virt_dev) |
| 668 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, |
| 669 | event); |
| 670 | else |
| 671 | xhci_warn(xhci, "Stop endpoint command " |
| 672 | "completion for disabled slot %u\n", |
| 673 | slot_id); |
| 674 | return; |
| 675 | } |
| 676 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 677 | memset(&deq_state, 0, sizeof(deq_state)); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 678 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
| 679 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 680 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 681 | |
Sarah Sharp | 678539c | 2009-10-27 10:55:52 -0700 | [diff] [blame] | 682 | if (list_empty(&ep->cancelled_td_list)) { |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 683 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
Sarah Sharp | 0714a57 | 2011-05-24 11:53:29 -0700 | [diff] [blame] | 684 | ep->stopped_td = NULL; |
| 685 | ep->stopped_trb = NULL; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 686 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 687 | return; |
Sarah Sharp | 678539c | 2009-10-27 10:55:52 -0700 | [diff] [blame] | 688 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 689 | |
| 690 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. |
| 691 | * We have the xHCI lock, so nothing can modify this list until we drop |
| 692 | * it. We're also in the event handler, so we can't get re-interrupted |
| 693 | * if another Stop Endpoint command completes |
| 694 | */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 695 | list_for_each(entry, &ep->cancelled_td_list) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 696 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
Sarah Sharp | 79688ac | 2011-12-19 16:56:04 -0800 | [diff] [blame] | 697 | xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n", |
| 698 | (unsigned long long)xhci_trb_virt_to_dma( |
| 699 | cur_td->start_seg, cur_td->first_trb)); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 700 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
| 701 | if (!ep_ring) { |
| 702 | /* This shouldn't happen unless a driver is mucking |
| 703 | * with the stream ID after submission. This will |
| 704 | * leave the TD on the hardware ring, and the hardware |
| 705 | * will try to execute it, and may access a buffer |
| 706 | * that has already been freed. In the best case, the |
| 707 | * hardware will execute it, and the event handler will |
| 708 | * ignore the completion event for that TD, since it was |
| 709 | * removed from the td_list for that endpoint. In |
| 710 | * short, don't muck with the stream ID after |
| 711 | * submission. |
| 712 | */ |
| 713 | xhci_warn(xhci, "WARN Cancelled URB %p " |
| 714 | "has invalid stream ID %u.\n", |
| 715 | cur_td->urb, |
| 716 | cur_td->urb->stream_id); |
| 717 | goto remove_finished_td; |
| 718 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 719 | /* |
| 720 | * If we stopped on the TD we need to cancel, then we have to |
| 721 | * move the xHC endpoint ring dequeue pointer past this TD. |
| 722 | */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 723 | if (cur_td == ep->stopped_td) |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 724 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
| 725 | cur_td->urb->stream_id, |
| 726 | cur_td, &deq_state); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 727 | else |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 728 | td_to_noop(xhci, ep_ring, cur_td, false); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 729 | remove_finished_td: |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 730 | /* |
| 731 | * The event handler won't see a completion for this TD anymore, |
| 732 | * so remove it from the endpoint ring's TD list. Keep it in |
| 733 | * the cancelled TD list for URB completion later. |
| 734 | */ |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 735 | list_del_init(&cur_td->td_list); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 736 | } |
| 737 | last_unlinked_td = cur_td; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 738 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 739 | |
| 740 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ |
| 741 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 742 | xhci_queue_new_dequeue_state(xhci, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 743 | slot_id, ep_index, |
| 744 | ep->stopped_td->urb->stream_id, |
| 745 | &deq_state); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 746 | xhci_ring_cmd_db(xhci); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 747 | } else { |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 748 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
| 749 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 750 | } |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 751 | ep->stopped_td = NULL; |
| 752 | ep->stopped_trb = NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 753 | |
| 754 | /* |
| 755 | * Drop the lock and complete the URBs in the cancelled TD list. |
| 756 | * New TDs to be cancelled might be added to the end of the list before |
| 757 | * we can complete all the URBs for the TDs we already unlinked. |
| 758 | * So stop when we've completed the URB for the last TD we unlinked. |
| 759 | */ |
| 760 | do { |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 761 | cur_td = list_entry(ep->cancelled_td_list.next, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 762 | struct xhci_td, cancelled_td_list); |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 763 | list_del_init(&cur_td->cancelled_td_list); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 764 | |
| 765 | /* Clean up the cancelled URB */ |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 766 | /* Doesn't matter what we pass for status, since the core will |
| 767 | * just overwrite it (because the URB has been unlinked). |
| 768 | */ |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 769 | xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 770 | |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 771 | /* Stop processing the cancelled list if the watchdog timer is |
| 772 | * running. |
| 773 | */ |
| 774 | if (xhci->xhc_state & XHCI_STATE_DYING) |
| 775 | return; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 776 | } while (cur_td != last_unlinked_td); |
| 777 | |
| 778 | /* Return to the event handler with xhci->lock re-acquired */ |
| 779 | } |
| 780 | |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 781 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
| 782 | * In this case, we assume the host controller is broken or dying or dead. The |
| 783 | * host may still be completing some other events, so we have to be careful to |
| 784 | * let the event ring handler and the URB dequeueing/enqueueing functions know |
| 785 | * through xhci->state. |
| 786 | * |
| 787 | * The timer may also fire if the host takes a very long time to respond to the |
| 788 | * command, and the stop endpoint command completion handler cannot delete the |
| 789 | * timer before the timer function is called. Another endpoint cancellation may |
| 790 | * sneak in before the timer function can grab the lock, and that may queue |
| 791 | * another stop endpoint command and add the timer back. So we cannot use a |
| 792 | * simple flag to say whether there is a pending stop endpoint command for a |
| 793 | * particular endpoint. |
| 794 | * |
| 795 | * Instead we use a combination of that flag and a counter for the number of |
| 796 | * pending stop endpoint commands. If the timer is the tail end of the last |
| 797 | * stop endpoint command, and the endpoint's command is still pending, we assume |
| 798 | * the host is dying. |
| 799 | */ |
| 800 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) |
| 801 | { |
| 802 | struct xhci_hcd *xhci; |
| 803 | struct xhci_virt_ep *ep; |
| 804 | struct xhci_virt_ep *temp_ep; |
| 805 | struct xhci_ring *ring; |
| 806 | struct xhci_td *cur_td; |
| 807 | int ret, i, j; |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 808 | unsigned long flags; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 809 | |
| 810 | ep = (struct xhci_virt_ep *) arg; |
| 811 | xhci = ep->xhci; |
| 812 | |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 813 | spin_lock_irqsave(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 814 | |
| 815 | ep->stop_cmds_pending--; |
| 816 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
| 817 | xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " |
| 818 | "xHCI as DYING, exiting.\n"); |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 819 | spin_unlock_irqrestore(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 820 | return; |
| 821 | } |
| 822 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { |
| 823 | xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " |
| 824 | "exiting.\n"); |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 825 | spin_unlock_irqrestore(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 826 | return; |
| 827 | } |
| 828 | |
| 829 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); |
| 830 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); |
| 831 | /* Oops, HC is dead or dying or at least not responding to the stop |
| 832 | * endpoint command. |
| 833 | */ |
| 834 | xhci->xhc_state |= XHCI_STATE_DYING; |
| 835 | /* Disable interrupts from the host controller and start halting it */ |
| 836 | xhci_quiesce(xhci); |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 837 | spin_unlock_irqrestore(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 838 | |
| 839 | ret = xhci_halt(xhci); |
| 840 | |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 841 | spin_lock_irqsave(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 842 | if (ret < 0) { |
| 843 | /* This is bad; the host is not responding to commands and it's |
| 844 | * not allowing itself to be halted. At least interrupts are |
Sarah Sharp | ac04e6f | 2011-03-11 08:47:33 -0800 | [diff] [blame] | 845 | * disabled. If we call usb_hc_died(), it will attempt to |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 846 | * disconnect all device drivers under this host. Those |
| 847 | * disconnect() methods will wait for all URBs to be unlinked, |
| 848 | * so we must complete them. |
| 849 | */ |
| 850 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); |
| 851 | xhci_warn(xhci, "Completing active URBs anyway.\n"); |
| 852 | /* We could turn all TDs on the rings to no-ops. This won't |
| 853 | * help if the host has cached part of the ring, and is slow if |
| 854 | * we want to preserve the cycle bit. Skip it and hope the host |
| 855 | * doesn't touch the memory. |
| 856 | */ |
| 857 | } |
| 858 | for (i = 0; i < MAX_HC_SLOTS; i++) { |
| 859 | if (!xhci->devs[i]) |
| 860 | continue; |
| 861 | for (j = 0; j < 31; j++) { |
| 862 | temp_ep = &xhci->devs[i]->eps[j]; |
| 863 | ring = temp_ep->ring; |
| 864 | if (!ring) |
| 865 | continue; |
| 866 | xhci_dbg(xhci, "Killing URBs for slot ID %u, " |
| 867 | "ep index %u\n", i, j); |
| 868 | while (!list_empty(&ring->td_list)) { |
| 869 | cur_td = list_first_entry(&ring->td_list, |
| 870 | struct xhci_td, |
| 871 | td_list); |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 872 | list_del_init(&cur_td->td_list); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 873 | if (!list_empty(&cur_td->cancelled_td_list)) |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 874 | list_del_init(&cur_td->cancelled_td_list); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 875 | xhci_giveback_urb_in_irq(xhci, cur_td, |
| 876 | -ESHUTDOWN, "killed"); |
| 877 | } |
| 878 | while (!list_empty(&temp_ep->cancelled_td_list)) { |
| 879 | cur_td = list_first_entry( |
| 880 | &temp_ep->cancelled_td_list, |
| 881 | struct xhci_td, |
| 882 | cancelled_td_list); |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 883 | list_del_init(&cur_td->cancelled_td_list); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 884 | xhci_giveback_urb_in_irq(xhci, cur_td, |
| 885 | -ESHUTDOWN, "killed"); |
| 886 | } |
| 887 | } |
| 888 | } |
Don Zickus | f43d623 | 2011-10-20 23:52:14 -0400 | [diff] [blame] | 889 | spin_unlock_irqrestore(&xhci->lock, flags); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 890 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 891 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 892 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); |
| 893 | } |
| 894 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 895 | /* |
| 896 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, |
| 897 | * we need to clear the set deq pending flag in the endpoint ring state, so that |
| 898 | * the TD queueing code can ring the doorbell again. We also need to ring the |
| 899 | * endpoint doorbell to restart the ring, but only if there aren't more |
| 900 | * cancellations pending. |
| 901 | */ |
| 902 | static void handle_set_deq_completion(struct xhci_hcd *xhci, |
| 903 | struct xhci_event_cmd *event, |
| 904 | union xhci_trb *trb) |
| 905 | { |
| 906 | unsigned int slot_id; |
| 907 | unsigned int ep_index; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 908 | unsigned int stream_id; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 909 | struct xhci_ring *ep_ring; |
| 910 | struct xhci_virt_device *dev; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 911 | struct xhci_ep_ctx *ep_ctx; |
| 912 | struct xhci_slot_ctx *slot_ctx; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 913 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 914 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
| 915 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
| 916 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 917 | dev = xhci->devs[slot_id]; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 918 | |
| 919 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); |
| 920 | if (!ep_ring) { |
| 921 | xhci_warn(xhci, "WARN Set TR deq ptr command for " |
| 922 | "freed stream ID %u\n", |
| 923 | stream_id); |
| 924 | /* XXX: Harmless??? */ |
| 925 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
| 926 | return; |
| 927 | } |
| 928 | |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 929 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
| 930 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 931 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 932 | if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 933 | unsigned int ep_state; |
| 934 | unsigned int slot_state; |
| 935 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 936 | switch (GET_COMP_CODE(le32_to_cpu(event->status))) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 937 | case COMP_TRB_ERR: |
| 938 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " |
| 939 | "of stream ID configuration\n"); |
| 940 | break; |
| 941 | case COMP_CTX_STATE: |
| 942 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " |
| 943 | "to incorrect slot or ep state.\n"); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 944 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 945 | ep_state &= EP_STATE_MASK; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 946 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 947 | slot_state = GET_SLOT_STATE(slot_state); |
| 948 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", |
| 949 | slot_state, ep_state); |
| 950 | break; |
| 951 | case COMP_EBADSLT: |
| 952 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " |
| 953 | "slot %u was not enabled.\n", slot_id); |
| 954 | break; |
| 955 | default: |
| 956 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " |
| 957 | "completion code of %u.\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 958 | GET_COMP_CODE(le32_to_cpu(event->status))); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 959 | break; |
| 960 | } |
| 961 | /* OK what do we do now? The endpoint state is hosed, and we |
| 962 | * should never get to this point if the synchronization between |
| 963 | * queueing, and endpoint state are correct. This might happen |
| 964 | * if the device gets disconnected after we've finished |
| 965 | * cancelling URBs, which might not be an error... |
| 966 | */ |
| 967 | } else { |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 968 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 969 | le64_to_cpu(ep_ctx->deq)); |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 970 | if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg, |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 971 | dev->eps[ep_index].queued_deq_ptr) == |
| 972 | (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) { |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 973 | /* Update the ring's dequeue segment and dequeue pointer |
| 974 | * to reflect the new position. |
| 975 | */ |
| 976 | ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg; |
| 977 | ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr; |
| 978 | } else { |
| 979 | xhci_warn(xhci, "Mismatch between completed Set TR Deq " |
| 980 | "Ptr command & xHCI internal state.\n"); |
| 981 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
| 982 | dev->eps[ep_index].queued_deq_seg, |
| 983 | dev->eps[ep_index].queued_deq_ptr); |
| 984 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 985 | } |
| 986 | |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 987 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 988 | dev->eps[ep_index].queued_deq_seg = NULL; |
| 989 | dev->eps[ep_index].queued_deq_ptr = NULL; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 990 | /* Restart any rings with pending URBs */ |
| 991 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 992 | } |
| 993 | |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 994 | static void handle_reset_ep_completion(struct xhci_hcd *xhci, |
| 995 | struct xhci_event_cmd *event, |
| 996 | union xhci_trb *trb) |
| 997 | { |
| 998 | int slot_id; |
| 999 | unsigned int ep_index; |
| 1000 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1001 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
| 1002 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1003 | /* This command will only fail if the endpoint wasn't halted, |
| 1004 | * but we don't care. |
| 1005 | */ |
| 1006 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 1007 | GET_COMP_CODE(le32_to_cpu(event->status))); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1008 | |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1009 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
| 1010 | * command complete before the endpoint can be used. Queue that here |
| 1011 | * because the HW can't handle two commands being queued in a row. |
| 1012 | */ |
| 1013 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { |
| 1014 | xhci_dbg(xhci, "Queueing configure endpoint command\n"); |
| 1015 | xhci_queue_configure_endpoint(xhci, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1016 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
| 1017 | false); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1018 | xhci_ring_cmd_db(xhci); |
| 1019 | } else { |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1020 | /* Clear our internal halted state and restart the ring(s) */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1021 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1022 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1023 | } |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1024 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1025 | |
Sarah Sharp | a50c8aa | 2009-09-04 10:53:15 -0700 | [diff] [blame] | 1026 | /* Check to see if a command in the device's command queue matches this one. |
| 1027 | * Signal the completion or free the command, and return 1. Return 0 if the |
| 1028 | * completed command isn't at the head of the command list. |
| 1029 | */ |
| 1030 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, |
| 1031 | struct xhci_virt_device *virt_dev, |
| 1032 | struct xhci_event_cmd *event) |
| 1033 | { |
| 1034 | struct xhci_command *command; |
| 1035 | |
| 1036 | if (list_empty(&virt_dev->cmd_list)) |
| 1037 | return 0; |
| 1038 | |
| 1039 | command = list_entry(virt_dev->cmd_list.next, |
| 1040 | struct xhci_command, cmd_list); |
| 1041 | if (xhci->cmd_ring->dequeue != command->command_trb) |
| 1042 | return 0; |
| 1043 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1044 | command->status = GET_COMP_CODE(le32_to_cpu(event->status)); |
Sarah Sharp | a50c8aa | 2009-09-04 10:53:15 -0700 | [diff] [blame] | 1045 | list_del(&command->cmd_list); |
| 1046 | if (command->completion) |
| 1047 | complete(command->completion); |
| 1048 | else |
| 1049 | xhci_free_command(xhci, command); |
| 1050 | return 1; |
| 1051 | } |
| 1052 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1053 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
| 1054 | struct xhci_event_cmd *event) |
| 1055 | { |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1056 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1057 | u64 cmd_dma; |
| 1058 | dma_addr_t cmd_dequeue_dma; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1059 | struct xhci_input_control_ctx *ctrl_ctx; |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1060 | struct xhci_virt_device *virt_dev; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1061 | unsigned int ep_index; |
| 1062 | struct xhci_ring *ep_ring; |
| 1063 | unsigned int ep_state; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1064 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1065 | cmd_dma = le64_to_cpu(event->cmd_trb); |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1066 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1067 | xhci->cmd_ring->dequeue); |
| 1068 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
| 1069 | if (cmd_dequeue_dma == 0) { |
| 1070 | xhci->error_bitmask |= 1 << 4; |
| 1071 | return; |
| 1072 | } |
| 1073 | /* Does the DMA address match our internal dequeue pointer address? */ |
| 1074 | if (cmd_dma != (u64) cmd_dequeue_dma) { |
| 1075 | xhci->error_bitmask |= 1 << 5; |
| 1076 | return; |
| 1077 | } |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1078 | switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]) |
| 1079 | & TRB_TYPE_BITMASK) { |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1080 | case TRB_TYPE(TRB_ENABLE_SLOT): |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1081 | if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1082 | xhci->slot_id = slot_id; |
| 1083 | else |
| 1084 | xhci->slot_id = 0; |
| 1085 | complete(&xhci->addr_dev); |
| 1086 | break; |
| 1087 | case TRB_TYPE(TRB_DISABLE_SLOT): |
Sarah Sharp | 2cf95c1 | 2011-05-11 16:14:58 -0700 | [diff] [blame] | 1088 | if (xhci->devs[slot_id]) { |
| 1089 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) |
| 1090 | /* Delete default control endpoint resources */ |
| 1091 | xhci_free_device_endpoint_resources(xhci, |
| 1092 | xhci->devs[slot_id], true); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1093 | xhci_free_virt_device(xhci, slot_id); |
Sarah Sharp | 2cf95c1 | 2011-05-11 16:14:58 -0700 | [diff] [blame] | 1094 | } |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1095 | break; |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1096 | case TRB_TYPE(TRB_CONFIG_EP): |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1097 | virt_dev = xhci->devs[slot_id]; |
Sarah Sharp | a50c8aa | 2009-09-04 10:53:15 -0700 | [diff] [blame] | 1098 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1099 | break; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1100 | /* |
| 1101 | * Configure endpoint commands can come from the USB core |
| 1102 | * configuration or alt setting changes, or because the HW |
| 1103 | * needed an extra configure endpoint command after a reset |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 1104 | * endpoint command or streams were being configured. |
| 1105 | * If the command was for a halted endpoint, the xHCI driver |
| 1106 | * is not waiting on the configure endpoint command. |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1107 | */ |
| 1108 | ctrl_ctx = xhci_get_input_control_ctx(xhci, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1109 | virt_dev->in_ctx); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1110 | /* Input ctx add_flags are the endpoint index plus one */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1111 | ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1; |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1112 | /* A usb_set_interface() call directly after clearing a halted |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1113 | * condition may race on this quirky hardware. Not worth |
| 1114 | * worrying about, since this is prototype hardware. Not sure |
| 1115 | * if this will work for streams, but streams support was |
| 1116 | * untested on this prototype. |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1117 | */ |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1118 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1119 | ep_index != (unsigned int) -1 && |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1120 | le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG == |
| 1121 | le32_to_cpu(ctrl_ctx->drop_flags)) { |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1122 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
| 1123 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; |
| 1124 | if (!(ep_state & EP_HALTED)) |
| 1125 | goto bandwidth_change; |
| 1126 | xhci_dbg(xhci, "Completed config ep cmd - " |
| 1127 | "last ep index = %d, state = %d\n", |
| 1128 | ep_index, ep_state); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1129 | /* Clear internal halted state and restart ring(s) */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1130 | xhci->devs[slot_id]->eps[ep_index].ep_state &= |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1131 | ~EP_HALTED; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1132 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1133 | break; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1134 | } |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1135 | bandwidth_change: |
| 1136 | xhci_dbg(xhci, "Completed config ep cmd\n"); |
| 1137 | xhci->devs[slot_id]->cmd_status = |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1138 | GET_COMP_CODE(le32_to_cpu(event->status)); |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1139 | complete(&xhci->devs[slot_id]->cmd_completion); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1140 | break; |
Sarah Sharp | 2d3f1fa | 2009-08-07 14:04:49 -0700 | [diff] [blame] | 1141 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
Sarah Sharp | ac1c1b7 | 2009-09-04 10:53:20 -0700 | [diff] [blame] | 1142 | virt_dev = xhci->devs[slot_id]; |
| 1143 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
| 1144 | break; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1145 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); |
Sarah Sharp | 2d3f1fa | 2009-08-07 14:04:49 -0700 | [diff] [blame] | 1146 | complete(&xhci->devs[slot_id]->cmd_completion); |
| 1147 | break; |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1148 | case TRB_TYPE(TRB_ADDR_DEV): |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1149 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1150 | complete(&xhci->addr_dev); |
| 1151 | break; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1152 | case TRB_TYPE(TRB_STOP_RING): |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 1153 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1154 | break; |
| 1155 | case TRB_TYPE(TRB_SET_DEQ): |
| 1156 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); |
| 1157 | break; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1158 | case TRB_TYPE(TRB_CMD_NOOP): |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1159 | break; |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1160 | case TRB_TYPE(TRB_RESET_EP): |
| 1161 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); |
| 1162 | break; |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 1163 | case TRB_TYPE(TRB_RESET_DEV): |
| 1164 | xhci_dbg(xhci, "Completed reset device command.\n"); |
| 1165 | slot_id = TRB_TO_SLOT_ID( |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1166 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 1167 | virt_dev = xhci->devs[slot_id]; |
| 1168 | if (virt_dev) |
| 1169 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); |
| 1170 | else |
| 1171 | xhci_warn(xhci, "Reset device command completion " |
| 1172 | "for disabled slot %u\n", slot_id); |
| 1173 | break; |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1174 | case TRB_TYPE(TRB_NEC_GET_FW): |
| 1175 | if (!(xhci->quirks & XHCI_NEC_HOST)) { |
| 1176 | xhci->error_bitmask |= 1 << 6; |
| 1177 | break; |
| 1178 | } |
| 1179 | xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1180 | NEC_FW_MAJOR(le32_to_cpu(event->status)), |
| 1181 | NEC_FW_MINOR(le32_to_cpu(event->status))); |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1182 | break; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1183 | default: |
| 1184 | /* Skip over unknown commands on the event ring */ |
| 1185 | xhci->error_bitmask |= 1 << 6; |
| 1186 | break; |
| 1187 | } |
| 1188 | inc_deq(xhci, xhci->cmd_ring, false); |
| 1189 | } |
| 1190 | |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1191 | static void handle_vendor_event(struct xhci_hcd *xhci, |
| 1192 | union xhci_trb *event) |
| 1193 | { |
| 1194 | u32 trb_type; |
| 1195 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1196 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1197 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
| 1198 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) |
| 1199 | handle_cmd_completion(xhci, &event->event_cmd); |
| 1200 | } |
| 1201 | |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1202 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
| 1203 | * port registers -- USB 3.0 and USB 2.0). |
| 1204 | * |
| 1205 | * Returns a zero-based port number, which is suitable for indexing into each of |
| 1206 | * the split roothubs' port arrays and bus state arrays. |
| 1207 | */ |
| 1208 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, |
| 1209 | struct xhci_hcd *xhci, u32 port_id) |
| 1210 | { |
| 1211 | unsigned int i; |
| 1212 | unsigned int num_similar_speed_ports = 0; |
| 1213 | |
| 1214 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], |
| 1215 | * and usb2_ports are 0-based indexes. Count the number of similar |
| 1216 | * speed ports, up to 1 port before this port. |
| 1217 | */ |
| 1218 | for (i = 0; i < (port_id - 1); i++) { |
| 1219 | u8 port_speed = xhci->port_array[i]; |
| 1220 | |
| 1221 | /* |
| 1222 | * Skip ports that don't have known speeds, or have duplicate |
| 1223 | * Extended Capabilities port speed entries. |
| 1224 | */ |
Dan Carpenter | 22e0487 | 2011-03-17 22:39:49 +0300 | [diff] [blame] | 1225 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1226 | continue; |
| 1227 | |
| 1228 | /* |
| 1229 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and |
| 1230 | * 1.1 ports are under the USB 2.0 hub. If the port speed |
| 1231 | * matches the device speed, it's a similar speed port. |
| 1232 | */ |
| 1233 | if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) |
| 1234 | num_similar_speed_ports++; |
| 1235 | } |
| 1236 | return num_similar_speed_ports; |
| 1237 | } |
| 1238 | |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1239 | static void handle_port_status(struct xhci_hcd *xhci, |
| 1240 | union xhci_trb *event) |
| 1241 | { |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1242 | struct usb_hcd *hcd; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1243 | u32 port_id; |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1244 | u32 temp, temp1; |
Sarah Sharp | 518e848 | 2010-12-15 11:56:29 -0800 | [diff] [blame] | 1245 | int max_ports; |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1246 | int slot_id; |
Sarah Sharp | 5308a91 | 2010-12-01 11:34:59 -0800 | [diff] [blame] | 1247 | unsigned int faked_port_index; |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1248 | u8 major_revision; |
Sarah Sharp | 20b67cf | 2010-12-15 12:47:14 -0800 | [diff] [blame] | 1249 | struct xhci_bus_state *bus_state; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1250 | __le32 __iomem **port_array; |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1251 | bool bogus_port_status = false; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1252 | |
| 1253 | /* Port status change events always have a successful completion code */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1254 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1255 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
| 1256 | xhci->error_bitmask |= 1 << 8; |
| 1257 | } |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1258 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1259 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
| 1260 | |
Sarah Sharp | 518e848 | 2010-12-15 11:56:29 -0800 | [diff] [blame] | 1261 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
| 1262 | if ((port_id <= 0) || (port_id > max_ports)) { |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1263 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1264 | bogus_port_status = true; |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1265 | goto cleanup; |
| 1266 | } |
| 1267 | |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1268 | /* Figure out which usb_hcd this port is attached to: |
| 1269 | * is it a USB 3.0 port or a USB 2.0/1.1 port? |
| 1270 | */ |
| 1271 | major_revision = xhci->port_array[port_id - 1]; |
| 1272 | if (major_revision == 0) { |
| 1273 | xhci_warn(xhci, "Event for port %u not in " |
| 1274 | "Extended Capabilities, ignoring.\n", |
| 1275 | port_id); |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1276 | bogus_port_status = true; |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1277 | goto cleanup; |
| 1278 | } |
Dan Carpenter | 22e0487 | 2011-03-17 22:39:49 +0300 | [diff] [blame] | 1279 | if (major_revision == DUPLICATE_ENTRY) { |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1280 | xhci_warn(xhci, "Event for port %u duplicated in" |
| 1281 | "Extended Capabilities, ignoring.\n", |
| 1282 | port_id); |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1283 | bogus_port_status = true; |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1284 | goto cleanup; |
Sarah Sharp | 5308a91 | 2010-12-01 11:34:59 -0800 | [diff] [blame] | 1285 | } |
| 1286 | |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1287 | /* |
| 1288 | * Hardware port IDs reported by a Port Status Change Event include USB |
| 1289 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a |
| 1290 | * resume event, but we first need to translate the hardware port ID |
| 1291 | * into the index into the ports on the correct split roothub, and the |
| 1292 | * correct bus_state structure. |
| 1293 | */ |
| 1294 | /* Find the right roothub. */ |
| 1295 | hcd = xhci_to_hcd(xhci); |
| 1296 | if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) |
| 1297 | hcd = xhci->shared_hcd; |
| 1298 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
| 1299 | if (hcd->speed == HCD_USB3) |
| 1300 | port_array = xhci->usb3_ports; |
| 1301 | else |
| 1302 | port_array = xhci->usb2_ports; |
| 1303 | /* Find the faked port hub number */ |
| 1304 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, |
| 1305 | port_id); |
| 1306 | |
Sarah Sharp | 5308a91 | 2010-12-01 11:34:59 -0800 | [diff] [blame] | 1307 | temp = xhci_readl(xhci, port_array[faked_port_index]); |
Sarah Sharp | 7111ebc | 2010-12-14 13:24:55 -0800 | [diff] [blame] | 1308 | if (hcd->state == HC_STATE_SUSPENDED) { |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1309 | xhci_dbg(xhci, "resume root hub\n"); |
| 1310 | usb_hcd_resume_root_hub(hcd); |
| 1311 | } |
| 1312 | |
| 1313 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { |
| 1314 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); |
| 1315 | |
| 1316 | temp1 = xhci_readl(xhci, &xhci->op_regs->command); |
| 1317 | if (!(temp1 & CMD_RUN)) { |
| 1318 | xhci_warn(xhci, "xHC is not running.\n"); |
| 1319 | goto cleanup; |
| 1320 | } |
| 1321 | |
| 1322 | if (DEV_SUPERSPEED(temp)) { |
| 1323 | xhci_dbg(xhci, "resume SS port %d\n", port_id); |
Andiry Xu | c9682df | 2011-09-23 14:19:48 -0700 | [diff] [blame] | 1324 | xhci_set_link_state(xhci, port_array, faked_port_index, |
| 1325 | XDEV_U0); |
Sarah Sharp | 5233630 | 2010-12-16 10:49:09 -0800 | [diff] [blame] | 1326 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
| 1327 | faked_port_index); |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1328 | if (!slot_id) { |
| 1329 | xhci_dbg(xhci, "slot_id is zero\n"); |
| 1330 | goto cleanup; |
| 1331 | } |
| 1332 | xhci_ring_device(xhci, slot_id); |
| 1333 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
| 1334 | /* Clear PORT_PLC */ |
Andiry Xu | d2f52c9 | 2011-09-23 14:19:49 -0700 | [diff] [blame] | 1335 | xhci_test_and_clear_bit(xhci, port_array, |
| 1336 | faked_port_index, PORT_PLC); |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1337 | } else { |
| 1338 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1339 | bus_state->resume_done[faked_port_index] = jiffies + |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1340 | msecs_to_jiffies(20); |
| 1341 | mod_timer(&hcd->rh_timer, |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1342 | bus_state->resume_done[faked_port_index]); |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1343 | /* Do the rest in GetPortStatus */ |
| 1344 | } |
| 1345 | } |
| 1346 | |
Andiry Xu | 6fd4562 | 2011-09-23 14:19:50 -0700 | [diff] [blame] | 1347 | if (hcd->speed != HCD_USB3) |
| 1348 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, |
| 1349 | PORT_PLC); |
| 1350 | |
Andiry Xu | 5619253 | 2010-10-14 07:23:00 -0700 | [diff] [blame] | 1351 | cleanup: |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1352 | /* Update event ring dequeue pointer before dropping the lock */ |
| 1353 | inc_deq(xhci, xhci->event_ring, true); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1354 | |
Sarah Sharp | 386139d | 2011-03-24 08:02:58 -0700 | [diff] [blame] | 1355 | /* Don't make the USB core poll the roothub if we got a bad port status |
| 1356 | * change event. Besides, at that point we can't tell which roothub |
| 1357 | * (USB 2.0 or USB 3.0) to kick. |
| 1358 | */ |
| 1359 | if (bogus_port_status) |
| 1360 | return; |
| 1361 | |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1362 | spin_unlock(&xhci->lock); |
| 1363 | /* Pass this up to the core */ |
Sarah Sharp | f6ff0ac | 2010-12-16 11:21:10 -0800 | [diff] [blame] | 1364 | usb_hcd_poll_rh_status(hcd); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1365 | spin_lock(&xhci->lock); |
| 1366 | } |
| 1367 | |
| 1368 | /* |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1369 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending |
| 1370 | * at end_trb, which may be in another segment. If the suspect DMA address is a |
| 1371 | * TRB in this TD, this function returns that TRB's segment. Otherwise it |
| 1372 | * returns 0. |
| 1373 | */ |
Sarah Sharp | 6648f29 | 2009-11-09 13:35:23 -0800 | [diff] [blame] | 1374 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1375 | union xhci_trb *start_trb, |
| 1376 | union xhci_trb *end_trb, |
| 1377 | dma_addr_t suspect_dma) |
| 1378 | { |
| 1379 | dma_addr_t start_dma; |
| 1380 | dma_addr_t end_seg_dma; |
| 1381 | dma_addr_t end_trb_dma; |
| 1382 | struct xhci_segment *cur_seg; |
| 1383 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1384 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1385 | cur_seg = start_seg; |
| 1386 | |
| 1387 | do { |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1388 | if (start_dma == 0) |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1389 | return NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1390 | /* We may get an event for a Link TRB in the middle of a TD */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1391 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1392 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1393 | /* If the end TRB isn't in this segment, this is set to 0 */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1394 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1395 | |
| 1396 | if (end_trb_dma > 0) { |
| 1397 | /* The end TRB is in this segment, so suspect should be here */ |
| 1398 | if (start_dma <= end_trb_dma) { |
| 1399 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) |
| 1400 | return cur_seg; |
| 1401 | } else { |
| 1402 | /* Case for one segment with |
| 1403 | * a TD wrapped around to the top |
| 1404 | */ |
| 1405 | if ((suspect_dma >= start_dma && |
| 1406 | suspect_dma <= end_seg_dma) || |
| 1407 | (suspect_dma >= cur_seg->dma && |
| 1408 | suspect_dma <= end_trb_dma)) |
| 1409 | return cur_seg; |
| 1410 | } |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1411 | return NULL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1412 | } else { |
| 1413 | /* Might still be somewhere in this segment */ |
| 1414 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) |
| 1415 | return cur_seg; |
| 1416 | } |
| 1417 | cur_seg = cur_seg->next; |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1418 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1419 | } while (cur_seg != start_seg); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1420 | |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1421 | return NULL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1422 | } |
| 1423 | |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1424 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
| 1425 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1426 | unsigned int stream_id, |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1427 | struct xhci_td *td, union xhci_trb *event_trb) |
| 1428 | { |
| 1429 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 1430 | ep->ep_state |= EP_HALTED; |
| 1431 | ep->stopped_td = td; |
| 1432 | ep->stopped_trb = event_trb; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1433 | ep->stopped_stream = stream_id; |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1434 | |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1435 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
| 1436 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1437 | |
| 1438 | ep->stopped_td = NULL; |
| 1439 | ep->stopped_trb = NULL; |
Sarah Sharp | 5e5cf6f | 2010-05-06 13:40:18 -0700 | [diff] [blame] | 1440 | ep->stopped_stream = 0; |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1441 | |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1442 | xhci_ring_cmd_db(xhci); |
| 1443 | } |
| 1444 | |
| 1445 | /* Check if an error has halted the endpoint ring. The class driver will |
| 1446 | * cleanup the halt for a non-default control endpoint if we indicate a stall. |
| 1447 | * However, a babble and other errors also halt the endpoint ring, and the class |
| 1448 | * driver won't clear the halt in that case, so we need to issue a Set Transfer |
| 1449 | * Ring Dequeue Pointer command manually. |
| 1450 | */ |
| 1451 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, |
| 1452 | struct xhci_ep_ctx *ep_ctx, |
| 1453 | unsigned int trb_comp_code) |
| 1454 | { |
| 1455 | /* TRB completion codes that may require a manual halt cleanup */ |
| 1456 | if (trb_comp_code == COMP_TX_ERR || |
| 1457 | trb_comp_code == COMP_BABBLE || |
| 1458 | trb_comp_code == COMP_SPLIT_ERR) |
| 1459 | /* The 0.96 spec says a babbling control endpoint |
| 1460 | * is not halted. The 0.96 spec says it is. Some HW |
| 1461 | * claims to be 0.95 compliant, but it halts the control |
| 1462 | * endpoint anyway. Check if a babble halted the |
| 1463 | * endpoint. |
| 1464 | */ |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 1465 | if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
| 1466 | cpu_to_le32(EP_STATE_HALTED)) |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1467 | return 1; |
| 1468 | |
| 1469 | return 0; |
| 1470 | } |
| 1471 | |
Sarah Sharp | b45b506 | 2009-12-09 15:59:06 -0800 | [diff] [blame] | 1472 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
| 1473 | { |
| 1474 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { |
| 1475 | /* Vendor defined "informational" completion code, |
| 1476 | * treat as not-an-error. |
| 1477 | */ |
| 1478 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", |
| 1479 | trb_comp_code); |
| 1480 | xhci_dbg(xhci, "Treating code as success.\n"); |
| 1481 | return 1; |
| 1482 | } |
| 1483 | return 0; |
| 1484 | } |
| 1485 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1486 | /* |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1487 | * Finish the td processing, remove the td from td list; |
| 1488 | * Return 1 if the urb can be given back. |
| 1489 | */ |
| 1490 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1491 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1492 | struct xhci_virt_ep *ep, int *status, bool skip) |
| 1493 | { |
| 1494 | struct xhci_virt_device *xdev; |
| 1495 | struct xhci_ring *ep_ring; |
| 1496 | unsigned int slot_id; |
| 1497 | int ep_index; |
| 1498 | struct urb *urb = NULL; |
| 1499 | struct xhci_ep_ctx *ep_ctx; |
| 1500 | int ret = 0; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1501 | struct urb_priv *urb_priv; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1502 | u32 trb_comp_code; |
| 1503 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1504 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1505 | xdev = xhci->devs[slot_id]; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1506 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
| 1507 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1508 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1509 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1510 | |
| 1511 | if (skip) |
| 1512 | goto td_cleanup; |
| 1513 | |
| 1514 | if (trb_comp_code == COMP_STOP_INVAL || |
| 1515 | trb_comp_code == COMP_STOP) { |
| 1516 | /* The Endpoint Stop Command completion will take care of any |
| 1517 | * stopped TDs. A stopped TD may be restarted, so don't update |
| 1518 | * the ring dequeue pointer or take this TD off any lists yet. |
| 1519 | */ |
| 1520 | ep->stopped_td = td; |
| 1521 | ep->stopped_trb = event_trb; |
| 1522 | return 0; |
| 1523 | } else { |
| 1524 | if (trb_comp_code == COMP_STALL) { |
| 1525 | /* The transfer is completed from the driver's |
| 1526 | * perspective, but we need to issue a set dequeue |
| 1527 | * command for this stalled endpoint to move the dequeue |
| 1528 | * pointer past the TD. We can't do that here because |
| 1529 | * the halt condition must be cleared first. Let the |
| 1530 | * USB class driver clear the stall later. |
| 1531 | */ |
| 1532 | ep->stopped_td = td; |
| 1533 | ep->stopped_trb = event_trb; |
| 1534 | ep->stopped_stream = ep_ring->stream_id; |
| 1535 | } else if (xhci_requires_manual_halt_cleanup(xhci, |
| 1536 | ep_ctx, trb_comp_code)) { |
| 1537 | /* Other types of errors halt the endpoint, but the |
| 1538 | * class driver doesn't call usb_reset_endpoint() unless |
| 1539 | * the error is -EPIPE. Clear the halted status in the |
| 1540 | * xHCI hardware manually. |
| 1541 | */ |
| 1542 | xhci_cleanup_halted_endpoint(xhci, |
| 1543 | slot_id, ep_index, ep_ring->stream_id, |
| 1544 | td, event_trb); |
| 1545 | } else { |
| 1546 | /* Update ring dequeue pointer */ |
| 1547 | while (ep_ring->dequeue != td->last_trb) |
| 1548 | inc_deq(xhci, ep_ring, false); |
| 1549 | inc_deq(xhci, ep_ring, false); |
| 1550 | } |
| 1551 | |
| 1552 | td_cleanup: |
| 1553 | /* Clean up the endpoint's TD list */ |
| 1554 | urb = td->urb; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1555 | urb_priv = urb->hcpriv; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1556 | |
| 1557 | /* Do one last check of the actual transfer length. |
| 1558 | * If the host controller said we transferred more data than |
| 1559 | * the buffer length, urb->actual_length will be a very big |
| 1560 | * number (since it's unsigned). Play it safe and say we didn't |
| 1561 | * transfer anything. |
| 1562 | */ |
| 1563 | if (urb->actual_length > urb->transfer_buffer_length) { |
| 1564 | xhci_warn(xhci, "URB transfer length is wrong, " |
| 1565 | "xHC issue? req. len = %u, " |
| 1566 | "act. len = %u\n", |
| 1567 | urb->transfer_buffer_length, |
| 1568 | urb->actual_length); |
| 1569 | urb->actual_length = 0; |
| 1570 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1571 | *status = -EREMOTEIO; |
| 1572 | else |
| 1573 | *status = 0; |
| 1574 | } |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 1575 | list_del_init(&td->td_list); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1576 | /* Was this TD slated to be cancelled but completed anyway? */ |
| 1577 | if (!list_empty(&td->cancelled_td_list)) |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 1578 | list_del_init(&td->cancelled_td_list); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1579 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1580 | urb_priv->td_cnt++; |
| 1581 | /* Giveback the urb when all the tds are completed */ |
Andiry Xu | c41136b | 2011-03-22 17:08:14 +0800 | [diff] [blame] | 1582 | if (urb_priv->td_cnt == urb_priv->length) { |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1583 | ret = 1; |
Andiry Xu | c41136b | 2011-03-22 17:08:14 +0800 | [diff] [blame] | 1584 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
| 1585 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; |
| 1586 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs |
| 1587 | == 0) { |
| 1588 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
| 1589 | usb_amd_quirk_pll_enable(); |
| 1590 | } |
| 1591 | } |
| 1592 | } |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1593 | } |
| 1594 | |
| 1595 | return ret; |
| 1596 | } |
| 1597 | |
| 1598 | /* |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1599 | * Process control tds, update urb status and actual_length. |
| 1600 | */ |
| 1601 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1602 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1603 | struct xhci_virt_ep *ep, int *status) |
| 1604 | { |
| 1605 | struct xhci_virt_device *xdev; |
| 1606 | struct xhci_ring *ep_ring; |
| 1607 | unsigned int slot_id; |
| 1608 | int ep_index; |
| 1609 | struct xhci_ep_ctx *ep_ctx; |
| 1610 | u32 trb_comp_code; |
| 1611 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1612 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1613 | xdev = xhci->devs[slot_id]; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1614 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
| 1615 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1616 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1617 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1618 | |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1619 | switch (trb_comp_code) { |
| 1620 | case COMP_SUCCESS: |
| 1621 | if (event_trb == ep_ring->dequeue) { |
| 1622 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " |
| 1623 | "without IOC set??\n"); |
| 1624 | *status = -ESHUTDOWN; |
| 1625 | } else if (event_trb != td->last_trb) { |
| 1626 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " |
| 1627 | "without IOC set??\n"); |
| 1628 | *status = -ESHUTDOWN; |
| 1629 | } else { |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1630 | *status = 0; |
| 1631 | } |
| 1632 | break; |
| 1633 | case COMP_SHORT_TX: |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1634 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1635 | *status = -EREMOTEIO; |
| 1636 | else |
| 1637 | *status = 0; |
| 1638 | break; |
Sarah Sharp | 3abeca9 | 2011-05-05 19:08:09 -0700 | [diff] [blame] | 1639 | case COMP_STOP_INVAL: |
| 1640 | case COMP_STOP: |
| 1641 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1642 | default: |
| 1643 | if (!xhci_requires_manual_halt_cleanup(xhci, |
| 1644 | ep_ctx, trb_comp_code)) |
| 1645 | break; |
| 1646 | xhci_dbg(xhci, "TRB error code %u, " |
| 1647 | "halted endpoint index = %u\n", |
| 1648 | trb_comp_code, ep_index); |
| 1649 | /* else fall through */ |
| 1650 | case COMP_STALL: |
| 1651 | /* Did we transfer part of the data (middle) phase? */ |
| 1652 | if (event_trb != ep_ring->dequeue && |
| 1653 | event_trb != td->last_trb) |
| 1654 | td->urb->actual_length = |
| 1655 | td->urb->transfer_buffer_length |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1656 | - TRB_LEN(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1657 | else |
| 1658 | td->urb->actual_length = 0; |
| 1659 | |
| 1660 | xhci_cleanup_halted_endpoint(xhci, |
| 1661 | slot_id, ep_index, 0, td, event_trb); |
| 1662 | return finish_td(xhci, td, event_trb, event, ep, status, true); |
| 1663 | } |
| 1664 | /* |
| 1665 | * Did we transfer any data, despite the errors that might have |
| 1666 | * happened? I.e. did we get past the setup stage? |
| 1667 | */ |
| 1668 | if (event_trb != ep_ring->dequeue) { |
| 1669 | /* The event was for the status stage */ |
| 1670 | if (event_trb == td->last_trb) { |
| 1671 | if (td->urb->actual_length != 0) { |
| 1672 | /* Don't overwrite a previously set error code |
| 1673 | */ |
| 1674 | if ((*status == -EINPROGRESS || *status == 0) && |
| 1675 | (td->urb->transfer_flags |
| 1676 | & URB_SHORT_NOT_OK)) |
| 1677 | /* Did we already see a short data |
| 1678 | * stage? */ |
| 1679 | *status = -EREMOTEIO; |
| 1680 | } else { |
| 1681 | td->urb->actual_length = |
| 1682 | td->urb->transfer_buffer_length; |
| 1683 | } |
| 1684 | } else { |
| 1685 | /* Maybe the event was for the data stage? */ |
Sarah Sharp | 3abeca9 | 2011-05-05 19:08:09 -0700 | [diff] [blame] | 1686 | td->urb->actual_length = |
| 1687 | td->urb->transfer_buffer_length - |
| 1688 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
| 1689 | xhci_dbg(xhci, "Waiting for status " |
| 1690 | "stage event\n"); |
| 1691 | return 0; |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1692 | } |
| 1693 | } |
| 1694 | |
| 1695 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 1696 | } |
| 1697 | |
| 1698 | /* |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1699 | * Process isochronous tds, update urb packet status and actual_length. |
| 1700 | */ |
| 1701 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1702 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1703 | struct xhci_virt_ep *ep, int *status) |
| 1704 | { |
| 1705 | struct xhci_ring *ep_ring; |
| 1706 | struct urb_priv *urb_priv; |
| 1707 | int idx; |
| 1708 | int len = 0; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1709 | union xhci_trb *cur_trb; |
| 1710 | struct xhci_segment *cur_seg; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1711 | struct usb_iso_packet_descriptor *frame; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1712 | u32 trb_comp_code; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1713 | bool skip_td = false; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1714 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1715 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
| 1716 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1717 | urb_priv = td->urb->hcpriv; |
| 1718 | idx = urb_priv->td_cnt; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1719 | frame = &td->urb->iso_frame_desc[idx]; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1720 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1721 | /* handle completion code */ |
| 1722 | switch (trb_comp_code) { |
| 1723 | case COMP_SUCCESS: |
| 1724 | frame->status = 0; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1725 | break; |
| 1726 | case COMP_SHORT_TX: |
| 1727 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? |
| 1728 | -EREMOTEIO : 0; |
| 1729 | break; |
| 1730 | case COMP_BW_OVER: |
| 1731 | frame->status = -ECOMM; |
| 1732 | skip_td = true; |
| 1733 | break; |
| 1734 | case COMP_BUFF_OVER: |
| 1735 | case COMP_BABBLE: |
| 1736 | frame->status = -EOVERFLOW; |
| 1737 | skip_td = true; |
| 1738 | break; |
Alex He | f6ba6fe | 2011-06-08 18:34:06 +0800 | [diff] [blame] | 1739 | case COMP_DEV_ERR: |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1740 | case COMP_STALL: |
| 1741 | frame->status = -EPROTO; |
| 1742 | skip_td = true; |
| 1743 | break; |
| 1744 | case COMP_STOP: |
| 1745 | case COMP_STOP_INVAL: |
| 1746 | break; |
| 1747 | default: |
| 1748 | frame->status = -1; |
| 1749 | break; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1750 | } |
| 1751 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1752 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
| 1753 | frame->actual_length = frame->length; |
| 1754 | td->urb->actual_length += frame->length; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1755 | } else { |
| 1756 | for (cur_trb = ep_ring->dequeue, |
| 1757 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; |
| 1758 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 1759 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
| 1760 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1761 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1762 | } |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1763 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
| 1764 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1765 | |
| 1766 | if (trb_comp_code != COMP_STOP_INVAL) { |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1767 | frame->actual_length = len; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1768 | td->urb->actual_length += len; |
| 1769 | } |
| 1770 | } |
| 1771 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1772 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 1773 | } |
| 1774 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1775 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1776 | struct xhci_transfer_event *event, |
| 1777 | struct xhci_virt_ep *ep, int *status) |
| 1778 | { |
| 1779 | struct xhci_ring *ep_ring; |
| 1780 | struct urb_priv *urb_priv; |
| 1781 | struct usb_iso_packet_descriptor *frame; |
| 1782 | int idx; |
| 1783 | |
Matt Evans | f697531 | 2011-06-01 13:01:01 +1000 | [diff] [blame] | 1784 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1785 | urb_priv = td->urb->hcpriv; |
| 1786 | idx = urb_priv->td_cnt; |
| 1787 | frame = &td->urb->iso_frame_desc[idx]; |
| 1788 | |
Sarah Sharp | b3df3f9 | 2011-06-15 19:57:46 -0700 | [diff] [blame] | 1789 | /* The transfer is partly done. */ |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 1790 | frame->status = -EXDEV; |
| 1791 | |
| 1792 | /* calc actual length */ |
| 1793 | frame->actual_length = 0; |
| 1794 | |
| 1795 | /* Update ring dequeue pointer */ |
| 1796 | while (ep_ring->dequeue != td->last_trb) |
| 1797 | inc_deq(xhci, ep_ring, false); |
| 1798 | inc_deq(xhci, ep_ring, false); |
| 1799 | |
| 1800 | return finish_td(xhci, td, NULL, event, ep, status, true); |
| 1801 | } |
| 1802 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1803 | /* |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1804 | * Process bulk and interrupt tds, update urb status and actual_length. |
| 1805 | */ |
| 1806 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1807 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1808 | struct xhci_virt_ep *ep, int *status) |
| 1809 | { |
| 1810 | struct xhci_ring *ep_ring; |
| 1811 | union xhci_trb *cur_trb; |
| 1812 | struct xhci_segment *cur_seg; |
| 1813 | u32 trb_comp_code; |
| 1814 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1815 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
| 1816 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1817 | |
| 1818 | switch (trb_comp_code) { |
| 1819 | case COMP_SUCCESS: |
| 1820 | /* Double check that the HW transferred everything. */ |
| 1821 | if (event_trb != td->last_trb) { |
| 1822 | xhci_warn(xhci, "WARN Successful completion " |
| 1823 | "on short TX\n"); |
| 1824 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1825 | *status = -EREMOTEIO; |
| 1826 | else |
| 1827 | *status = 0; |
| 1828 | } else { |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1829 | *status = 0; |
| 1830 | } |
| 1831 | break; |
| 1832 | case COMP_SHORT_TX: |
| 1833 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1834 | *status = -EREMOTEIO; |
| 1835 | else |
| 1836 | *status = 0; |
| 1837 | break; |
| 1838 | default: |
| 1839 | /* Others already handled above */ |
| 1840 | break; |
| 1841 | } |
Sarah Sharp | f444ff2 | 2011-04-05 15:53:47 -0700 | [diff] [blame] | 1842 | if (trb_comp_code == COMP_SHORT_TX) |
| 1843 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " |
| 1844 | "%d bytes untransferred\n", |
| 1845 | td->urb->ep->desc.bEndpointAddress, |
| 1846 | td->urb->transfer_buffer_length, |
| 1847 | TRB_LEN(le32_to_cpu(event->transfer_len))); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1848 | /* Fast path - was this the last TRB in the TD for this URB? */ |
| 1849 | if (event_trb == td->last_trb) { |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1850 | if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1851 | td->urb->actual_length = |
| 1852 | td->urb->transfer_buffer_length - |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1853 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1854 | if (td->urb->transfer_buffer_length < |
| 1855 | td->urb->actual_length) { |
| 1856 | xhci_warn(xhci, "HC gave bad length " |
| 1857 | "of %d bytes left\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1858 | TRB_LEN(le32_to_cpu(event->transfer_len))); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1859 | td->urb->actual_length = 0; |
| 1860 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1861 | *status = -EREMOTEIO; |
| 1862 | else |
| 1863 | *status = 0; |
| 1864 | } |
| 1865 | /* Don't overwrite a previously set error code */ |
| 1866 | if (*status == -EINPROGRESS) { |
| 1867 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1868 | *status = -EREMOTEIO; |
| 1869 | else |
| 1870 | *status = 0; |
| 1871 | } |
| 1872 | } else { |
| 1873 | td->urb->actual_length = |
| 1874 | td->urb->transfer_buffer_length; |
| 1875 | /* Ignore a short packet completion if the |
| 1876 | * untransferred length was zero. |
| 1877 | */ |
| 1878 | if (*status == -EREMOTEIO) |
| 1879 | *status = 0; |
| 1880 | } |
| 1881 | } else { |
| 1882 | /* Slow path - walk the list, starting from the dequeue |
| 1883 | * pointer, to get the actual length transferred. |
| 1884 | */ |
| 1885 | td->urb->actual_length = 0; |
| 1886 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; |
| 1887 | cur_trb != event_trb; |
| 1888 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 1889 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
| 1890 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1891 | td->urb->actual_length += |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1892 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1893 | } |
| 1894 | /* If the ring didn't stop on a Link or No-op TRB, add |
| 1895 | * in the actual bytes transferred from the Normal TRB |
| 1896 | */ |
| 1897 | if (trb_comp_code != COMP_STOP_INVAL) |
| 1898 | td->urb->actual_length += |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1899 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
| 1900 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1901 | } |
| 1902 | |
| 1903 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 1904 | } |
| 1905 | |
| 1906 | /* |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1907 | * If this function returns an error condition, it means it got a Transfer |
| 1908 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. |
| 1909 | * At this point, the host controller is probably hosed and should be reset. |
| 1910 | */ |
| 1911 | static int handle_tx_event(struct xhci_hcd *xhci, |
| 1912 | struct xhci_transfer_event *event) |
| 1913 | { |
| 1914 | struct xhci_virt_device *xdev; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1915 | struct xhci_virt_ep *ep; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1916 | struct xhci_ring *ep_ring; |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 1917 | unsigned int slot_id; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1918 | int ep_index; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1919 | struct xhci_td *td = NULL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1920 | dma_addr_t event_dma; |
| 1921 | struct xhci_segment *event_seg; |
| 1922 | union xhci_trb *event_trb; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1923 | struct urb *urb = NULL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1924 | int status = -EINPROGRESS; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1925 | struct urb_priv *urb_priv; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 1926 | struct xhci_ep_ctx *ep_ctx; |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 1927 | struct list_head *tmp; |
Sarah Sharp | 66d1eeb | 2009-08-27 14:35:53 -0700 | [diff] [blame] | 1928 | u32 trb_comp_code; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1929 | int ret = 0; |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 1930 | int td_num = 0; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1931 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1932 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 1933 | xdev = xhci->devs[slot_id]; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1934 | if (!xdev) { |
| 1935 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); |
Sarah Sharp | 9258c0b | 2011-12-01 14:50:30 -0800 | [diff] [blame] | 1936 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
Sarah Sharp | e910b44 | 2012-01-04 16:54:12 -0800 | [diff] [blame^] | 1937 | (unsigned long long) xhci_trb_virt_to_dma( |
| 1938 | xhci->event_ring->deq_seg, |
Sarah Sharp | 9258c0b | 2011-12-01 14:50:30 -0800 | [diff] [blame] | 1939 | xhci->event_ring->dequeue), |
| 1940 | lower_32_bits(le64_to_cpu(event->buffer)), |
| 1941 | upper_32_bits(le64_to_cpu(event->buffer)), |
| 1942 | le32_to_cpu(event->transfer_len), |
| 1943 | le32_to_cpu(event->flags)); |
| 1944 | xhci_dbg(xhci, "Event ring:\n"); |
| 1945 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1946 | return -ENODEV; |
| 1947 | } |
| 1948 | |
| 1949 | /* Endpoint ID is 1 based, our index is zero based */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1950 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1951 | ep = &xdev->eps[ep_index]; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1952 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 1953 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1954 | if (!ep_ring || |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1955 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
| 1956 | EP_STATE_DISABLED) { |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1957 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
| 1958 | "or incorrect stream ring\n"); |
Sarah Sharp | 9258c0b | 2011-12-01 14:50:30 -0800 | [diff] [blame] | 1959 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
Sarah Sharp | e910b44 | 2012-01-04 16:54:12 -0800 | [diff] [blame^] | 1960 | (unsigned long long) xhci_trb_virt_to_dma( |
| 1961 | xhci->event_ring->deq_seg, |
Sarah Sharp | 9258c0b | 2011-12-01 14:50:30 -0800 | [diff] [blame] | 1962 | xhci->event_ring->dequeue), |
| 1963 | lower_32_bits(le64_to_cpu(event->buffer)), |
| 1964 | upper_32_bits(le64_to_cpu(event->buffer)), |
| 1965 | le32_to_cpu(event->transfer_len), |
| 1966 | le32_to_cpu(event->flags)); |
| 1967 | xhci_dbg(xhci, "Event ring:\n"); |
| 1968 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1969 | return -ENODEV; |
| 1970 | } |
| 1971 | |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 1972 | /* Count current td numbers if ep->skip is set */ |
| 1973 | if (ep->skip) { |
| 1974 | list_for_each(tmp, &ep_ring->td_list) |
| 1975 | td_num++; |
| 1976 | } |
| 1977 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 1978 | event_dma = le64_to_cpu(event->buffer); |
| 1979 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1980 | /* Look for common error cases */ |
Sarah Sharp | 66d1eeb | 2009-08-27 14:35:53 -0700 | [diff] [blame] | 1981 | switch (trb_comp_code) { |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1982 | /* Skip codes that require special handling depending on |
| 1983 | * transfer type |
| 1984 | */ |
| 1985 | case COMP_SUCCESS: |
| 1986 | case COMP_SHORT_TX: |
| 1987 | break; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1988 | case COMP_STOP: |
| 1989 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); |
| 1990 | break; |
| 1991 | case COMP_STOP_INVAL: |
| 1992 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); |
| 1993 | break; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1994 | case COMP_STALL: |
Sarah Sharp | 2a9227a | 2011-10-25 13:55:30 +0200 | [diff] [blame] | 1995 | xhci_dbg(xhci, "Stalled endpoint\n"); |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1996 | ep->ep_state |= EP_HALTED; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1997 | status = -EPIPE; |
| 1998 | break; |
| 1999 | case COMP_TRB_ERR: |
| 2000 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); |
| 2001 | status = -EILSEQ; |
| 2002 | break; |
Sarah Sharp | ec74e40 | 2009-11-11 10:28:36 -0800 | [diff] [blame] | 2003 | case COMP_SPLIT_ERR: |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2004 | case COMP_TX_ERR: |
Sarah Sharp | 2a9227a | 2011-10-25 13:55:30 +0200 | [diff] [blame] | 2005 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2006 | status = -EPROTO; |
| 2007 | break; |
Sarah Sharp | 4a73143 | 2009-07-27 12:04:32 -0700 | [diff] [blame] | 2008 | case COMP_BABBLE: |
Sarah Sharp | 2a9227a | 2011-10-25 13:55:30 +0200 | [diff] [blame] | 2009 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
Sarah Sharp | 4a73143 | 2009-07-27 12:04:32 -0700 | [diff] [blame] | 2010 | status = -EOVERFLOW; |
| 2011 | break; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2012 | case COMP_DB_ERR: |
| 2013 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); |
| 2014 | status = -ENOSR; |
| 2015 | break; |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2016 | case COMP_BW_OVER: |
| 2017 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); |
| 2018 | break; |
| 2019 | case COMP_BUFF_OVER: |
| 2020 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); |
| 2021 | break; |
| 2022 | case COMP_UNDERRUN: |
| 2023 | /* |
| 2024 | * When the Isoch ring is empty, the xHC will generate |
| 2025 | * a Ring Overrun Event for IN Isoch endpoint or Ring |
| 2026 | * Underrun Event for OUT Isoch endpoint. |
| 2027 | */ |
| 2028 | xhci_dbg(xhci, "underrun event on endpoint\n"); |
| 2029 | if (!list_empty(&ep_ring->td_list)) |
| 2030 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " |
| 2031 | "still with TDs queued?\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2032 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
| 2033 | ep_index); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2034 | goto cleanup; |
| 2035 | case COMP_OVERRUN: |
| 2036 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
| 2037 | if (!list_empty(&ep_ring->td_list)) |
| 2038 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " |
| 2039 | "still with TDs queued?\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2040 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
| 2041 | ep_index); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2042 | goto cleanup; |
Alex He | f6ba6fe | 2011-06-08 18:34:06 +0800 | [diff] [blame] | 2043 | case COMP_DEV_ERR: |
| 2044 | xhci_warn(xhci, "WARN: detect an incompatible device"); |
| 2045 | status = -EPROTO; |
| 2046 | break; |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2047 | case COMP_MISSED_INT: |
| 2048 | /* |
| 2049 | * When encounter missed service error, one or more isoc tds |
| 2050 | * may be missed by xHC. |
| 2051 | * Set skip flag of the ep_ring; Complete the missed tds as |
| 2052 | * short transfer when process the ep_ring next time. |
| 2053 | */ |
| 2054 | ep->skip = true; |
| 2055 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); |
| 2056 | goto cleanup; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2057 | default: |
Sarah Sharp | b45b506 | 2009-12-09 15:59:06 -0800 | [diff] [blame] | 2058 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
Sarah Sharp | 5ad6a52 | 2009-11-11 10:28:40 -0800 | [diff] [blame] | 2059 | status = 0; |
| 2060 | break; |
| 2061 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2062 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably " |
| 2063 | "busted\n"); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2064 | goto cleanup; |
| 2065 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2066 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2067 | do { |
| 2068 | /* This TRB should be in the TD at the head of this ring's |
| 2069 | * TD list. |
| 2070 | */ |
| 2071 | if (list_empty(&ep_ring->td_list)) { |
| 2072 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " |
| 2073 | "with no TDs queued?\n", |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2074 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
| 2075 | ep_index); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2076 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 2077 | (le32_to_cpu(event->flags) & |
| 2078 | TRB_TYPE_BITMASK)>>10); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2079 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); |
| 2080 | if (ep->skip) { |
| 2081 | ep->skip = false; |
| 2082 | xhci_dbg(xhci, "td_list is empty while skip " |
| 2083 | "flag set. Clear skip flag.\n"); |
| 2084 | } |
| 2085 | ret = 0; |
| 2086 | goto cleanup; |
| 2087 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2088 | |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 2089 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
| 2090 | if (ep->skip && td_num == 0) { |
| 2091 | ep->skip = false; |
| 2092 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " |
| 2093 | "Clear skip flag.\n"); |
| 2094 | ret = 0; |
| 2095 | goto cleanup; |
| 2096 | } |
| 2097 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2098 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
Andiry Xu | c2d7b49 | 2011-09-19 16:05:12 -0700 | [diff] [blame] | 2099 | if (ep->skip) |
| 2100 | td_num--; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2101 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2102 | /* Is this a TRB in the currently executing TD? */ |
| 2103 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, |
| 2104 | td->last_trb, event_dma); |
Alex He | e1cf486 | 2011-06-03 15:58:25 +0800 | [diff] [blame] | 2105 | |
| 2106 | /* |
| 2107 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE |
| 2108 | * is not in the current TD pointed by ep_ring->dequeue because |
| 2109 | * that the hardware dequeue pointer still at the previous TRB |
| 2110 | * of the current TD. The previous TRB maybe a Link TD or the |
| 2111 | * last TRB of the previous TD. The command completion handle |
| 2112 | * will take care the rest. |
| 2113 | */ |
| 2114 | if (!event_seg && trb_comp_code == COMP_STOP_INVAL) { |
| 2115 | ret = 0; |
| 2116 | goto cleanup; |
| 2117 | } |
| 2118 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2119 | if (!event_seg) { |
| 2120 | if (!ep->skip || |
| 2121 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { |
Sarah Sharp | ad80833 | 2011-05-25 10:43:56 -0700 | [diff] [blame] | 2122 | /* Some host controllers give a spurious |
| 2123 | * successful event after a short transfer. |
| 2124 | * Ignore it. |
| 2125 | */ |
| 2126 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
| 2127 | ep_ring->last_td_was_short) { |
| 2128 | ep_ring->last_td_was_short = false; |
| 2129 | ret = 0; |
| 2130 | goto cleanup; |
| 2131 | } |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2132 | /* HC is busted, give up! */ |
| 2133 | xhci_err(xhci, |
| 2134 | "ERROR Transfer event TRB DMA ptr not " |
| 2135 | "part of current TD\n"); |
| 2136 | return -ESHUTDOWN; |
| 2137 | } |
| 2138 | |
| 2139 | ret = skip_isoc_td(xhci, td, event, ep, &status); |
| 2140 | goto cleanup; |
| 2141 | } |
Sarah Sharp | ad80833 | 2011-05-25 10:43:56 -0700 | [diff] [blame] | 2142 | if (trb_comp_code == COMP_SHORT_TX) |
| 2143 | ep_ring->last_td_was_short = true; |
| 2144 | else |
| 2145 | ep_ring->last_td_was_short = false; |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2146 | |
| 2147 | if (ep->skip) { |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2148 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
| 2149 | ep->skip = false; |
| 2150 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 2151 | |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2152 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
| 2153 | sizeof(*event_trb)]; |
| 2154 | /* |
| 2155 | * No-op TRB should not trigger interrupts. |
| 2156 | * If event_trb is a no-op TRB, it means the |
| 2157 | * corresponding TD has been cancelled. Just ignore |
| 2158 | * the TD. |
| 2159 | */ |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 2160 | if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { |
Dmitry Torokhov | 926008c | 2011-03-23 20:47:05 -0700 | [diff] [blame] | 2161 | xhci_dbg(xhci, |
| 2162 | "event_trb is a no-op TRB. Skip it\n"); |
| 2163 | goto cleanup; |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2164 | } |
| 2165 | |
| 2166 | /* Now update the urb's actual_length and give back to |
| 2167 | * the core |
| 2168 | */ |
| 2169 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
| 2170 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, |
| 2171 | &status); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2172 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
| 2173 | ret = process_isoc_td(xhci, td, event_trb, event, ep, |
| 2174 | &status); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2175 | else |
| 2176 | ret = process_bulk_intr_td(xhci, td, event_trb, event, |
| 2177 | ep, &status); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 2178 | |
| 2179 | cleanup: |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2180 | /* |
| 2181 | * Do not update event ring dequeue pointer if ep->skip is set. |
| 2182 | * Will roll back to continue process missed tds. |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 2183 | */ |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2184 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { |
| 2185 | inc_deq(xhci, xhci->event_ring, true); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2186 | } |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2187 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2188 | if (ret) { |
| 2189 | urb = td->urb; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2190 | urb_priv = urb->hcpriv; |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2191 | /* Leave the TD around for the reset endpoint function |
| 2192 | * to use(but only if it's not a control endpoint, |
| 2193 | * since we already queued the Set TR dequeue pointer |
| 2194 | * command for stalled control endpoints). |
| 2195 | */ |
| 2196 | if (usb_endpoint_xfer_control(&urb->ep->desc) || |
| 2197 | (trb_comp_code != COMP_STALL && |
| 2198 | trb_comp_code != COMP_BABBLE)) |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2199 | xhci_urb_free_priv(xhci, urb_priv); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2200 | |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 2201 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
Sarah Sharp | f444ff2 | 2011-04-05 15:53:47 -0700 | [diff] [blame] | 2202 | if ((urb->actual_length != urb->transfer_buffer_length && |
| 2203 | (urb->transfer_flags & |
| 2204 | URB_SHORT_NOT_OK)) || |
Sarah Sharp | fd984d2 | 2011-09-02 11:05:56 -0700 | [diff] [blame] | 2205 | (status != 0 && |
| 2206 | !usb_endpoint_xfer_isoc(&urb->ep->desc))) |
Sarah Sharp | f444ff2 | 2011-04-05 15:53:47 -0700 | [diff] [blame] | 2207 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
| 2208 | "expected = %x, status = %d\n", |
| 2209 | urb, urb->actual_length, |
| 2210 | urb->transfer_buffer_length, |
| 2211 | status); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2212 | spin_unlock(&xhci->lock); |
Sarah Sharp | b3df3f9 | 2011-06-15 19:57:46 -0700 | [diff] [blame] | 2213 | /* EHCI, UHCI, and OHCI always unconditionally set the |
| 2214 | * urb->status of an isochronous endpoint to 0. |
| 2215 | */ |
| 2216 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) |
| 2217 | status = 0; |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 2218 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 2219 | spin_lock(&xhci->lock); |
| 2220 | } |
| 2221 | |
| 2222 | /* |
| 2223 | * If ep->skip is set, it means there are missed tds on the |
| 2224 | * endpoint ring need to take care of. |
| 2225 | * Process them as short transfer until reach the td pointed by |
| 2226 | * the event. |
| 2227 | */ |
| 2228 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); |
| 2229 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2230 | return 0; |
| 2231 | } |
| 2232 | |
| 2233 | /* |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2234 | * This function handles all OS-owned events on the event ring. It may drop |
| 2235 | * xhci->lock between event processing (e.g. to pass up port status changes). |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2236 | * Returns >0 for "possibly more events to process" (caller should call again), |
| 2237 | * otherwise 0 if done. In future, <0 returns should indicate error code. |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2238 | */ |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2239 | static int xhci_handle_event(struct xhci_hcd *xhci) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2240 | { |
| 2241 | union xhci_trb *event; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2242 | int update_ptrs = 1; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2243 | int ret; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2244 | |
| 2245 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
| 2246 | xhci->error_bitmask |= 1 << 1; |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2247 | return 0; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2248 | } |
| 2249 | |
| 2250 | event = xhci->event_ring->dequeue; |
| 2251 | /* Does the HC or OS own the TRB? */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2252 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
| 2253 | xhci->event_ring->cycle_state) { |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2254 | xhci->error_bitmask |= 1 << 2; |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2255 | return 0; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2256 | } |
| 2257 | |
Matt Evans | 92a3da4 | 2011-03-29 13:40:51 +1100 | [diff] [blame] | 2258 | /* |
| 2259 | * Barrier between reading the TRB_CYCLE (valid) flag above and any |
| 2260 | * speculative reads of the event's flags/data below. |
| 2261 | */ |
| 2262 | rmb(); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2263 | /* FIXME: Handle more event types. */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2264 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2265 | case TRB_TYPE(TRB_COMPLETION): |
| 2266 | handle_cmd_completion(xhci, &event->event_cmd); |
| 2267 | break; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2268 | case TRB_TYPE(TRB_PORT_STATUS): |
| 2269 | handle_port_status(xhci, event); |
| 2270 | update_ptrs = 0; |
| 2271 | break; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2272 | case TRB_TYPE(TRB_TRANSFER): |
| 2273 | ret = handle_tx_event(xhci, &event->trans_event); |
| 2274 | if (ret < 0) |
| 2275 | xhci->error_bitmask |= 1 << 9; |
| 2276 | else |
| 2277 | update_ptrs = 0; |
| 2278 | break; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2279 | default: |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2280 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
| 2281 | TRB_TYPE(48)) |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 2282 | handle_vendor_event(xhci, event); |
| 2283 | else |
| 2284 | xhci->error_bitmask |= 1 << 3; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2285 | } |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 2286 | /* Any of the above functions may drop and re-acquire the lock, so check |
| 2287 | * to make sure a watchdog timer didn't mark the host as non-responsive. |
| 2288 | */ |
| 2289 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
| 2290 | xhci_dbg(xhci, "xHCI host dying, returning from " |
| 2291 | "event handler.\n"); |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2292 | return 0; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 2293 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2294 | |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2295 | if (update_ptrs) |
| 2296 | /* Update SW event ring dequeue pointer */ |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2297 | inc_deq(xhci, xhci->event_ring, true); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2298 | |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2299 | /* Are there more items on the event ring? Caller will call us again to |
| 2300 | * check. |
| 2301 | */ |
| 2302 | return 1; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2303 | } |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2304 | |
| 2305 | /* |
| 2306 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, |
| 2307 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of |
| 2308 | * indicators of an event TRB error, but we check the status *first* to be safe. |
| 2309 | */ |
| 2310 | irqreturn_t xhci_irq(struct usb_hcd *hcd) |
| 2311 | { |
| 2312 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2313 | u32 status; |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2314 | union xhci_trb *trb; |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2315 | u64 temp_64; |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2316 | union xhci_trb *event_ring_deq; |
| 2317 | dma_addr_t deq; |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2318 | |
| 2319 | spin_lock(&xhci->lock); |
| 2320 | trb = xhci->event_ring->dequeue; |
| 2321 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2322 | status = xhci_readl(xhci, &xhci->op_regs->status); |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2323 | if (status == 0xffffffff) |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2324 | goto hw_died; |
| 2325 | |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2326 | if (!(status & STS_EINT)) { |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2327 | spin_unlock(&xhci->lock); |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2328 | return IRQ_NONE; |
| 2329 | } |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2330 | if (status & STS_FATAL) { |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2331 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
| 2332 | xhci_halt(xhci); |
| 2333 | hw_died: |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2334 | spin_unlock(&xhci->lock); |
| 2335 | return -ESHUTDOWN; |
| 2336 | } |
| 2337 | |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2338 | /* |
| 2339 | * Clear the op reg interrupt status first, |
| 2340 | * so we can receive interrupts from other MSI-X interrupters. |
| 2341 | * Write 1 to clear the interrupt status. |
| 2342 | */ |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2343 | status |= STS_EINT; |
| 2344 | xhci_writel(xhci, status, &xhci->op_regs->status); |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2345 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
| 2346 | /* Clear the MSI-X event interrupt status */ |
| 2347 | |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame] | 2348 | if (hcd->irq != -1) { |
| 2349 | u32 irq_pending; |
| 2350 | /* Acknowledge the PCI interrupt */ |
| 2351 | irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 2352 | irq_pending |= 0x3; |
| 2353 | xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending); |
| 2354 | } |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2355 | |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2356 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2357 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
| 2358 | "Shouldn't IRQs be disabled?\n"); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2359 | /* Clear the event handler busy flag (RW1C); |
| 2360 | * the event ring should be empty. |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2361 | */ |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2362 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
| 2363 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
| 2364 | &xhci->ir_set->erst_dequeue); |
| 2365 | spin_unlock(&xhci->lock); |
| 2366 | |
| 2367 | return IRQ_HANDLED; |
| 2368 | } |
| 2369 | |
| 2370 | event_ring_deq = xhci->event_ring->dequeue; |
| 2371 | /* FIXME this should be a delayed service routine |
| 2372 | * that clears the EHB. |
| 2373 | */ |
Matt Evans | 9dee9a2 | 2011-03-29 13:41:02 +1100 | [diff] [blame] | 2374 | while (xhci_handle_event(xhci) > 0) {} |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2375 | |
| 2376 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
| 2377 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
| 2378 | if (event_ring_deq != xhci->event_ring->dequeue) { |
| 2379 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, |
| 2380 | xhci->event_ring->dequeue); |
| 2381 | if (deq == 0) |
| 2382 | xhci_warn(xhci, "WARN something wrong with SW event " |
| 2383 | "ring dequeue ptr.\n"); |
| 2384 | /* Update HC event ring dequeue pointer */ |
| 2385 | temp_64 &= ERST_PTR_MASK; |
| 2386 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); |
| 2387 | } |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2388 | |
| 2389 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2390 | temp_64 |= ERST_EHB; |
| 2391 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
| 2392 | |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2393 | spin_unlock(&xhci->lock); |
| 2394 | |
| 2395 | return IRQ_HANDLED; |
| 2396 | } |
| 2397 | |
| 2398 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) |
| 2399 | { |
Alan Stern | 968b822 | 2011-11-03 12:03:38 -0400 | [diff] [blame] | 2400 | return xhci_irq(hcd); |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2401 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2402 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2403 | /**** Endpoint Ring Operations ****/ |
| 2404 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2405 | /* |
| 2406 | * Generic function for queueing a TRB on a ring. |
| 2407 | * The caller must have checked to make sure there's room on the ring. |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2408 | * |
| 2409 | * @more_trbs_coming: Will you enqueue more TRBs before calling |
| 2410 | * prepare_transfer()? |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2411 | */ |
| 2412 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2413 | bool consumer, bool more_trbs_coming, bool isoc, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2414 | u32 field1, u32 field2, u32 field3, u32 field4) |
| 2415 | { |
| 2416 | struct xhci_generic_trb *trb; |
| 2417 | |
| 2418 | trb = &ring->enqueue->generic; |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2419 | trb->field[0] = cpu_to_le32(field1); |
| 2420 | trb->field[1] = cpu_to_le32(field2); |
| 2421 | trb->field[2] = cpu_to_le32(field3); |
| 2422 | trb->field[3] = cpu_to_le32(field4); |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2423 | inc_enq(xhci, ring, consumer, more_trbs_coming, isoc); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2424 | } |
| 2425 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2426 | /* |
| 2427 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. |
| 2428 | * FIXME allocate segments if the ring is full. |
| 2429 | */ |
| 2430 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2431 | u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags) |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2432 | { |
| 2433 | /* Make sure the endpoint has been added to xHC schedule */ |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2434 | switch (ep_state) { |
| 2435 | case EP_STATE_DISABLED: |
| 2436 | /* |
| 2437 | * USB core changed config/interfaces without notifying us, |
| 2438 | * or hardware is reporting the wrong state. |
| 2439 | */ |
| 2440 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); |
| 2441 | return -ENOENT; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2442 | case EP_STATE_ERROR: |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 2443 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2444 | /* FIXME event handling code for error needs to clear it */ |
| 2445 | /* XXX not sure if this should be -ENOENT or not */ |
| 2446 | return -EINVAL; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 2447 | case EP_STATE_HALTED: |
| 2448 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2449 | case EP_STATE_STOPPED: |
| 2450 | case EP_STATE_RUNNING: |
| 2451 | break; |
| 2452 | default: |
| 2453 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); |
| 2454 | /* |
| 2455 | * FIXME issue Configure Endpoint command to try to get the HC |
| 2456 | * back into a known state. |
| 2457 | */ |
| 2458 | return -EINVAL; |
| 2459 | } |
| 2460 | if (!room_on_ring(xhci, ep_ring, num_trbs)) { |
| 2461 | /* FIXME allocate more room */ |
| 2462 | xhci_err(xhci, "ERROR no room on ep ring\n"); |
| 2463 | return -ENOMEM; |
| 2464 | } |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2465 | |
| 2466 | if (enqueue_is_link_trb(ep_ring)) { |
| 2467 | struct xhci_ring *ring = ep_ring; |
| 2468 | union xhci_trb *next; |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2469 | |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2470 | next = ring->enqueue; |
| 2471 | |
| 2472 | while (last_trb(xhci, ring, ring->enq_seg, next)) { |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2473 | /* If we're not dealing with 0.95 hardware or isoc rings |
| 2474 | * on AMD 0.96 host, clear the chain bit. |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2475 | */ |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2476 | if (!xhci_link_trb_quirk(xhci) && !(isoc && |
| 2477 | (xhci->quirks & XHCI_AMD_0x96_HOST))) |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2478 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2479 | else |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2480 | next->link.control |= cpu_to_le32(TRB_CHAIN); |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2481 | |
| 2482 | wmb(); |
Matt Evans | f5960b6 | 2011-06-01 10:22:55 +1000 | [diff] [blame] | 2483 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2484 | |
| 2485 | /* Toggle the cycle bit after the last ring segment. */ |
| 2486 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { |
| 2487 | ring->cycle_state = (ring->cycle_state ? 0 : 1); |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2488 | } |
| 2489 | ring->enq_seg = ring->enq_seg->next; |
| 2490 | ring->enqueue = ring->enq_seg->trbs; |
| 2491 | next = ring->enqueue; |
| 2492 | } |
| 2493 | } |
| 2494 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2495 | return 0; |
| 2496 | } |
| 2497 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2498 | static int prepare_transfer(struct xhci_hcd *xhci, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2499 | struct xhci_virt_device *xdev, |
| 2500 | unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2501 | unsigned int stream_id, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2502 | unsigned int num_trbs, |
| 2503 | struct urb *urb, |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2504 | unsigned int td_index, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2505 | bool isoc, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2506 | gfp_t mem_flags) |
| 2507 | { |
| 2508 | int ret; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2509 | struct urb_priv *urb_priv; |
| 2510 | struct xhci_td *td; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2511 | struct xhci_ring *ep_ring; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 2512 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2513 | |
| 2514 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); |
| 2515 | if (!ep_ring) { |
| 2516 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", |
| 2517 | stream_id); |
| 2518 | return -EINVAL; |
| 2519 | } |
| 2520 | |
| 2521 | ret = prepare_ring(xhci, ep_ring, |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2522 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2523 | num_trbs, isoc, mem_flags); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2524 | if (ret) |
| 2525 | return ret; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2526 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2527 | urb_priv = urb->hcpriv; |
| 2528 | td = urb_priv->td[td_index]; |
| 2529 | |
| 2530 | INIT_LIST_HEAD(&td->td_list); |
| 2531 | INIT_LIST_HEAD(&td->cancelled_td_list); |
| 2532 | |
| 2533 | if (td_index == 0) { |
Sarah Sharp | 214f76f | 2010-10-26 11:22:02 -0700 | [diff] [blame] | 2534 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
Sarah Sharp | d13565c | 2011-07-22 14:34:34 -0700 | [diff] [blame] | 2535 | if (unlikely(ret)) |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2536 | return ret; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2537 | } |
| 2538 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2539 | td->urb = urb; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2540 | /* Add this TD to the tail of the endpoint ring's TD list */ |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2541 | list_add_tail(&td->td_list, &ep_ring->td_list); |
| 2542 | td->start_seg = ep_ring->enq_seg; |
| 2543 | td->first_trb = ep_ring->enqueue; |
| 2544 | |
| 2545 | urb_priv->td[td_index] = td; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2546 | |
| 2547 | return 0; |
| 2548 | } |
| 2549 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2550 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2551 | { |
| 2552 | int num_sgs, num_trbs, running_total, temp, i; |
| 2553 | struct scatterlist *sg; |
| 2554 | |
| 2555 | sg = NULL; |
Clemens Ladisch | bc677d5 | 2011-12-03 23:41:31 +0100 | [diff] [blame] | 2556 | num_sgs = urb->num_mapped_sgs; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2557 | temp = urb->transfer_buffer_length; |
| 2558 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2559 | num_trbs = 0; |
Matthew Wilcox | 910f8d0 | 2010-05-01 12:20:01 -0600 | [diff] [blame] | 2560 | for_each_sg(urb->sg, sg, num_sgs, i) { |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2561 | unsigned int len = sg_dma_len(sg); |
| 2562 | |
| 2563 | /* Scatter gather list entries may cross 64KB boundaries */ |
| 2564 | running_total = TRB_MAX_BUFF_SIZE - |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 2565 | (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); |
Paul Zimmerman | 5807795 | 2011-02-12 14:07:20 -0800 | [diff] [blame] | 2566 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2567 | if (running_total != 0) |
| 2568 | num_trbs++; |
| 2569 | |
| 2570 | /* How many more 64KB chunks to transfer, how many more TRBs? */ |
Paul Zimmerman | bcd2fde | 2011-02-12 14:07:57 -0800 | [diff] [blame] | 2571 | while (running_total < sg_dma_len(sg) && running_total < temp) { |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2572 | num_trbs++; |
| 2573 | running_total += TRB_MAX_BUFF_SIZE; |
| 2574 | } |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2575 | len = min_t(int, len, temp); |
| 2576 | temp -= len; |
| 2577 | if (temp == 0) |
| 2578 | break; |
| 2579 | } |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2580 | return num_trbs; |
| 2581 | } |
| 2582 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2583 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2584 | { |
| 2585 | if (num_trbs != 0) |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 2586 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2587 | "TRBs, %d left\n", __func__, |
| 2588 | urb->ep->desc.bEndpointAddress, num_trbs); |
| 2589 | if (running_total != urb->transfer_buffer_length) |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 2590 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2591 | "queued %#x (%d), asked for %#x (%d)\n", |
| 2592 | __func__, |
| 2593 | urb->ep->desc.bEndpointAddress, |
| 2594 | running_total, running_total, |
| 2595 | urb->transfer_buffer_length, |
| 2596 | urb->transfer_buffer_length); |
| 2597 | } |
| 2598 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2599 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2600 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 2601 | struct xhci_generic_trb *start_trb) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2602 | { |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2603 | /* |
| 2604 | * Pass all the TRBs to the hardware at once and make sure this write |
| 2605 | * isn't reordered. |
| 2606 | */ |
| 2607 | wmb(); |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 2608 | if (start_cycle) |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2609 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 2610 | else |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2611 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 2612 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2613 | } |
| 2614 | |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 2615 | /* |
| 2616 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt |
| 2617 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD |
| 2618 | * (comprised of sg list entries) can take several service intervals to |
| 2619 | * transmit. |
| 2620 | */ |
| 2621 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 2622 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2623 | { |
| 2624 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, |
| 2625 | xhci->devs[slot_id]->out_ctx, ep_index); |
| 2626 | int xhci_interval; |
| 2627 | int ep_interval; |
| 2628 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 2629 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 2630 | ep_interval = urb->interval; |
| 2631 | /* Convert to microframes */ |
| 2632 | if (urb->dev->speed == USB_SPEED_LOW || |
| 2633 | urb->dev->speed == USB_SPEED_FULL) |
| 2634 | ep_interval *= 8; |
| 2635 | /* FIXME change this to a warning and a suggestion to use the new API |
| 2636 | * to set the polling interval (once the API is added). |
| 2637 | */ |
| 2638 | if (xhci_interval != ep_interval) { |
Andiry Xu | 7961acd | 2010-12-20 17:14:20 +0800 | [diff] [blame] | 2639 | if (printk_ratelimit()) |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 2640 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
| 2641 | " (%d microframe%s) than xHCI " |
| 2642 | "(%d microframe%s)\n", |
| 2643 | ep_interval, |
| 2644 | ep_interval == 1 ? "" : "s", |
| 2645 | xhci_interval, |
| 2646 | xhci_interval == 1 ? "" : "s"); |
| 2647 | urb->interval = xhci_interval; |
| 2648 | /* Convert back to frames for LS/FS devices */ |
| 2649 | if (urb->dev->speed == USB_SPEED_LOW || |
| 2650 | urb->dev->speed == USB_SPEED_FULL) |
| 2651 | urb->interval /= 8; |
| 2652 | } |
| 2653 | return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); |
| 2654 | } |
| 2655 | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2656 | /* |
| 2657 | * The TD size is the number of bytes remaining in the TD (including this TRB), |
| 2658 | * right shifted by 10. |
| 2659 | * It must fit in bits 21:17, so it can't be bigger than 31. |
| 2660 | */ |
| 2661 | static u32 xhci_td_remainder(unsigned int remainder) |
| 2662 | { |
| 2663 | u32 max = (1 << (21 - 17 + 1)) - 1; |
| 2664 | |
| 2665 | if ((remainder >> 10) >= max) |
| 2666 | return max << 17; |
| 2667 | else |
| 2668 | return (remainder >> 10) << 17; |
| 2669 | } |
| 2670 | |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2671 | /* |
| 2672 | * For xHCI 1.0 host controllers, TD size is the number of packets remaining in |
| 2673 | * the TD (*not* including this TRB). |
| 2674 | * |
| 2675 | * Total TD packet count = total_packet_count = |
| 2676 | * roundup(TD size in bytes / wMaxPacketSize) |
| 2677 | * |
| 2678 | * Packets transferred up to and including this TRB = packets_transferred = |
| 2679 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) |
| 2680 | * |
| 2681 | * TD size = total_packet_count - packets_transferred |
| 2682 | * |
| 2683 | * It must fit in bits 21:17, so it can't be bigger than 31. |
| 2684 | */ |
| 2685 | |
| 2686 | static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len, |
| 2687 | unsigned int total_packet_count, struct urb *urb) |
| 2688 | { |
| 2689 | int packets_transferred; |
| 2690 | |
Sarah Sharp | 48df4a6 | 2011-08-12 10:23:01 -0700 | [diff] [blame] | 2691 | /* One TRB with a zero-length data packet. */ |
| 2692 | if (running_total == 0 && trb_buff_len == 0) |
| 2693 | return 0; |
| 2694 | |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2695 | /* All the TRB queueing functions don't count the current TRB in |
| 2696 | * running_total. |
| 2697 | */ |
| 2698 | packets_transferred = (running_total + trb_buff_len) / |
Kuninori Morimoto | 29cc889 | 2011-08-23 03:12:03 -0700 | [diff] [blame] | 2699 | usb_endpoint_maxp(&urb->ep->desc); |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2700 | |
| 2701 | return xhci_td_remainder(total_packet_count - packets_transferred); |
| 2702 | } |
| 2703 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2704 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2705 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2706 | { |
| 2707 | struct xhci_ring *ep_ring; |
| 2708 | unsigned int num_trbs; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2709 | struct urb_priv *urb_priv; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2710 | struct xhci_td *td; |
| 2711 | struct scatterlist *sg; |
| 2712 | int num_sgs; |
| 2713 | int trb_buff_len, this_sg_len, running_total; |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2714 | unsigned int total_packet_count; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2715 | bool first_trb; |
| 2716 | u64 addr; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2717 | bool more_trbs_coming; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2718 | |
| 2719 | struct xhci_generic_trb *start_trb; |
| 2720 | int start_cycle; |
| 2721 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2722 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 2723 | if (!ep_ring) |
| 2724 | return -EINVAL; |
| 2725 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2726 | num_trbs = count_sg_trbs_needed(xhci, urb); |
Clemens Ladisch | bc677d5 | 2011-12-03 23:41:31 +0100 | [diff] [blame] | 2727 | num_sgs = urb->num_mapped_sgs; |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2728 | total_packet_count = roundup(urb->transfer_buffer_length, |
Kuninori Morimoto | 29cc889 | 2011-08-23 03:12:03 -0700 | [diff] [blame] | 2729 | usb_endpoint_maxp(&urb->ep->desc)); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2730 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2731 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2732 | ep_index, urb->stream_id, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2733 | num_trbs, urb, 0, false, mem_flags); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2734 | if (trb_buff_len < 0) |
| 2735 | return trb_buff_len; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2736 | |
| 2737 | urb_priv = urb->hcpriv; |
| 2738 | td = urb_priv->td[0]; |
| 2739 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2740 | /* |
| 2741 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 2742 | * until we've finished creating all the other TRBs. The ring's cycle |
| 2743 | * state may change as we enqueue the other TRBs, so save it too. |
| 2744 | */ |
| 2745 | start_trb = &ep_ring->enqueue->generic; |
| 2746 | start_cycle = ep_ring->cycle_state; |
| 2747 | |
| 2748 | running_total = 0; |
| 2749 | /* |
| 2750 | * How much data is in the first TRB? |
| 2751 | * |
| 2752 | * There are three forces at work for TRB buffer pointers and lengths: |
| 2753 | * 1. We don't want to walk off the end of this sg-list entry buffer. |
| 2754 | * 2. The transfer length that the driver requested may be smaller than |
| 2755 | * the amount of memory allocated for this scatter-gather list. |
| 2756 | * 3. TRBs buffers can't cross 64KB boundaries. |
| 2757 | */ |
Matthew Wilcox | 910f8d0 | 2010-05-01 12:20:01 -0600 | [diff] [blame] | 2758 | sg = urb->sg; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2759 | addr = (u64) sg_dma_address(sg); |
| 2760 | this_sg_len = sg_dma_len(sg); |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 2761 | trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2762 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
| 2763 | if (trb_buff_len > urb->transfer_buffer_length) |
| 2764 | trb_buff_len = urb->transfer_buffer_length; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2765 | |
| 2766 | first_trb = true; |
| 2767 | /* Queue the first TRB, even if it's zero-length */ |
| 2768 | do { |
| 2769 | u32 field = 0; |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2770 | u32 length_field = 0; |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2771 | u32 remainder = 0; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2772 | |
| 2773 | /* Don't change the cycle bit of the first TRB until later */ |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 2774 | if (first_trb) { |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2775 | first_trb = false; |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 2776 | if (start_cycle == 0) |
| 2777 | field |= 0x1; |
| 2778 | } else |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2779 | field |= ep_ring->cycle_state; |
| 2780 | |
| 2781 | /* Chain all the TRBs together; clear the chain bit in the last |
| 2782 | * TRB to indicate it's the last TRB in the chain. |
| 2783 | */ |
| 2784 | if (num_trbs > 1) { |
| 2785 | field |= TRB_CHAIN; |
| 2786 | } else { |
| 2787 | /* FIXME - add check for ZERO_PACKET flag before this */ |
| 2788 | td->last_trb = ep_ring->enqueue; |
| 2789 | field |= TRB_IOC; |
| 2790 | } |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 2791 | |
| 2792 | /* Only set interrupt on short packet for IN endpoints */ |
| 2793 | if (usb_urb_dir_in(urb)) |
| 2794 | field |= TRB_ISP; |
| 2795 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2796 | if (TRB_MAX_BUFF_SIZE - |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 2797 | (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2798 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
| 2799 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", |
| 2800 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), |
| 2801 | (unsigned int) addr + trb_buff_len); |
| 2802 | } |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2803 | |
| 2804 | /* Set the TRB length, TD size, and interrupter fields. */ |
| 2805 | if (xhci->hci_version < 0x100) { |
| 2806 | remainder = xhci_td_remainder( |
| 2807 | urb->transfer_buffer_length - |
| 2808 | running_total); |
| 2809 | } else { |
| 2810 | remainder = xhci_v1_0_td_remainder(running_total, |
| 2811 | trb_buff_len, total_packet_count, urb); |
| 2812 | } |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2813 | length_field = TRB_LEN(trb_buff_len) | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2814 | remainder | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2815 | TRB_INTR_TARGET(0); |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2816 | |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2817 | if (num_trbs > 1) |
| 2818 | more_trbs_coming = true; |
| 2819 | else |
| 2820 | more_trbs_coming = false; |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2821 | queue_trb(xhci, ep_ring, false, more_trbs_coming, false, |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 2822 | lower_32_bits(addr), |
| 2823 | upper_32_bits(addr), |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2824 | length_field, |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 2825 | field | TRB_TYPE(TRB_NORMAL)); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2826 | --num_trbs; |
| 2827 | running_total += trb_buff_len; |
| 2828 | |
| 2829 | /* Calculate length for next transfer -- |
| 2830 | * Are we done queueing all the TRBs for this sg entry? |
| 2831 | */ |
| 2832 | this_sg_len -= trb_buff_len; |
| 2833 | if (this_sg_len == 0) { |
| 2834 | --num_sgs; |
| 2835 | if (num_sgs == 0) |
| 2836 | break; |
| 2837 | sg = sg_next(sg); |
| 2838 | addr = (u64) sg_dma_address(sg); |
| 2839 | this_sg_len = sg_dma_len(sg); |
| 2840 | } else { |
| 2841 | addr += trb_buff_len; |
| 2842 | } |
| 2843 | |
| 2844 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 2845 | (addr & (TRB_MAX_BUFF_SIZE - 1)); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2846 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
| 2847 | if (running_total + trb_buff_len > urb->transfer_buffer_length) |
| 2848 | trb_buff_len = |
| 2849 | urb->transfer_buffer_length - running_total; |
| 2850 | } while (running_total < urb->transfer_buffer_length); |
| 2851 | |
| 2852 | check_trb_math(urb, num_trbs, running_total); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2853 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 2854 | start_cycle, start_trb); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2855 | return 0; |
| 2856 | } |
| 2857 | |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2858 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2859 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2860 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2861 | { |
| 2862 | struct xhci_ring *ep_ring; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2863 | struct urb_priv *urb_priv; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2864 | struct xhci_td *td; |
| 2865 | int num_trbs; |
| 2866 | struct xhci_generic_trb *start_trb; |
| 2867 | bool first_trb; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2868 | bool more_trbs_coming; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2869 | int start_cycle; |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2870 | u32 field, length_field; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2871 | |
| 2872 | int running_total, trb_buff_len, ret; |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2873 | unsigned int total_packet_count; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2874 | u64 addr; |
| 2875 | |
Alan Stern | ff9c895 | 2010-04-02 13:27:28 -0400 | [diff] [blame] | 2876 | if (urb->num_sgs) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2877 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
| 2878 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2879 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 2880 | if (!ep_ring) |
| 2881 | return -EINVAL; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2882 | |
| 2883 | num_trbs = 0; |
| 2884 | /* How much data is (potentially) left before the 64KB boundary? */ |
| 2885 | running_total = TRB_MAX_BUFF_SIZE - |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 2886 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
Paul Zimmerman | 5807795 | 2011-02-12 14:07:20 -0800 | [diff] [blame] | 2887 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2888 | |
| 2889 | /* If there's some data on this 64KB chunk, or we have to send a |
| 2890 | * zero-length transfer, we need at least one TRB |
| 2891 | */ |
| 2892 | if (running_total != 0 || urb->transfer_buffer_length == 0) |
| 2893 | num_trbs++; |
| 2894 | /* How many more 64KB chunks to transfer, how many more TRBs? */ |
| 2895 | while (running_total < urb->transfer_buffer_length) { |
| 2896 | num_trbs++; |
| 2897 | running_total += TRB_MAX_BUFF_SIZE; |
| 2898 | } |
| 2899 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ |
| 2900 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2901 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
| 2902 | ep_index, urb->stream_id, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2903 | num_trbs, urb, 0, false, mem_flags); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2904 | if (ret < 0) |
| 2905 | return ret; |
| 2906 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2907 | urb_priv = urb->hcpriv; |
| 2908 | td = urb_priv->td[0]; |
| 2909 | |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2910 | /* |
| 2911 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 2912 | * until we've finished creating all the other TRBs. The ring's cycle |
| 2913 | * state may change as we enqueue the other TRBs, so save it too. |
| 2914 | */ |
| 2915 | start_trb = &ep_ring->enqueue->generic; |
| 2916 | start_cycle = ep_ring->cycle_state; |
| 2917 | |
| 2918 | running_total = 0; |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2919 | total_packet_count = roundup(urb->transfer_buffer_length, |
Kuninori Morimoto | 29cc889 | 2011-08-23 03:12:03 -0700 | [diff] [blame] | 2920 | usb_endpoint_maxp(&urb->ep->desc)); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2921 | /* How much data is in the first TRB? */ |
| 2922 | addr = (u64) urb->transfer_dma; |
| 2923 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
Paul Zimmerman | a249018 | 2011-02-12 14:06:44 -0800 | [diff] [blame] | 2924 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
| 2925 | if (trb_buff_len > urb->transfer_buffer_length) |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2926 | trb_buff_len = urb->transfer_buffer_length; |
| 2927 | |
| 2928 | first_trb = true; |
| 2929 | |
| 2930 | /* Queue the first TRB, even if it's zero-length */ |
| 2931 | do { |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2932 | u32 remainder = 0; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2933 | field = 0; |
| 2934 | |
| 2935 | /* Don't change the cycle bit of the first TRB until later */ |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 2936 | if (first_trb) { |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2937 | first_trb = false; |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 2938 | if (start_cycle == 0) |
| 2939 | field |= 0x1; |
| 2940 | } else |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2941 | field |= ep_ring->cycle_state; |
| 2942 | |
| 2943 | /* Chain all the TRBs together; clear the chain bit in the last |
| 2944 | * TRB to indicate it's the last TRB in the chain. |
| 2945 | */ |
| 2946 | if (num_trbs > 1) { |
| 2947 | field |= TRB_CHAIN; |
| 2948 | } else { |
| 2949 | /* FIXME - add check for ZERO_PACKET flag before this */ |
| 2950 | td->last_trb = ep_ring->enqueue; |
| 2951 | field |= TRB_IOC; |
| 2952 | } |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 2953 | |
| 2954 | /* Only set interrupt on short packet for IN endpoints */ |
| 2955 | if (usb_urb_dir_in(urb)) |
| 2956 | field |= TRB_ISP; |
| 2957 | |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2958 | /* Set the TRB length, TD size, and interrupter fields. */ |
| 2959 | if (xhci->hci_version < 0x100) { |
| 2960 | remainder = xhci_td_remainder( |
| 2961 | urb->transfer_buffer_length - |
| 2962 | running_total); |
| 2963 | } else { |
| 2964 | remainder = xhci_v1_0_td_remainder(running_total, |
| 2965 | trb_buff_len, total_packet_count, urb); |
| 2966 | } |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2967 | length_field = TRB_LEN(trb_buff_len) | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2968 | remainder | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2969 | TRB_INTR_TARGET(0); |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 2970 | |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2971 | if (num_trbs > 1) |
| 2972 | more_trbs_coming = true; |
| 2973 | else |
| 2974 | more_trbs_coming = false; |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 2975 | queue_trb(xhci, ep_ring, false, more_trbs_coming, false, |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 2976 | lower_32_bits(addr), |
| 2977 | upper_32_bits(addr), |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2978 | length_field, |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 2979 | field | TRB_TYPE(TRB_NORMAL)); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2980 | --num_trbs; |
| 2981 | running_total += trb_buff_len; |
| 2982 | |
| 2983 | /* Calculate length for next transfer */ |
| 2984 | addr += trb_buff_len; |
| 2985 | trb_buff_len = urb->transfer_buffer_length - running_total; |
| 2986 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) |
| 2987 | trb_buff_len = TRB_MAX_BUFF_SIZE; |
| 2988 | } while (running_total < urb->transfer_buffer_length); |
| 2989 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2990 | check_trb_math(urb, num_trbs, running_total); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2991 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 2992 | start_cycle, start_trb); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2993 | return 0; |
| 2994 | } |
| 2995 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2996 | /* Caller must have locked xhci->lock */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2997 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2998 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2999 | { |
| 3000 | struct xhci_ring *ep_ring; |
| 3001 | int num_trbs; |
| 3002 | int ret; |
| 3003 | struct usb_ctrlrequest *setup; |
| 3004 | struct xhci_generic_trb *start_trb; |
| 3005 | int start_cycle; |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3006 | u32 field, length_field; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 3007 | struct urb_priv *urb_priv; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3008 | struct xhci_td *td; |
| 3009 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3010 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 3011 | if (!ep_ring) |
| 3012 | return -EINVAL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3013 | |
| 3014 | /* |
| 3015 | * Need to copy setup packet into setup TRB, so we can't use the setup |
| 3016 | * DMA address. |
| 3017 | */ |
| 3018 | if (!urb->setup_packet) |
| 3019 | return -EINVAL; |
| 3020 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3021 | /* 1 TRB for setup, 1 for status */ |
| 3022 | num_trbs = 2; |
| 3023 | /* |
| 3024 | * Don't need to check if we need additional event data and normal TRBs, |
| 3025 | * since data in control transfers will never get bigger than 16MB |
| 3026 | * XXX: can we get a buffer that crosses 64KB boundaries? |
| 3027 | */ |
| 3028 | if (urb->transfer_buffer_length > 0) |
| 3029 | num_trbs++; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3030 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
| 3031 | ep_index, urb->stream_id, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3032 | num_trbs, urb, 0, false, mem_flags); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3033 | if (ret < 0) |
| 3034 | return ret; |
| 3035 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 3036 | urb_priv = urb->hcpriv; |
| 3037 | td = urb_priv->td[0]; |
| 3038 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3039 | /* |
| 3040 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 3041 | * until we've finished creating all the other TRBs. The ring's cycle |
| 3042 | * state may change as we enqueue the other TRBs, so save it too. |
| 3043 | */ |
| 3044 | start_trb = &ep_ring->enqueue->generic; |
| 3045 | start_cycle = ep_ring->cycle_state; |
| 3046 | |
| 3047 | /* Queue setup TRB - see section 6.4.1.2.1 */ |
| 3048 | /* FIXME better way to translate setup_packet into two u32 fields? */ |
| 3049 | setup = (struct usb_ctrlrequest *) urb->setup_packet; |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 3050 | field = 0; |
| 3051 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); |
| 3052 | if (start_cycle == 0) |
| 3053 | field |= 0x1; |
Andiry Xu | b83cdc8 | 2011-05-05 18:13:56 +0800 | [diff] [blame] | 3054 | |
| 3055 | /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ |
| 3056 | if (xhci->hci_version == 0x100) { |
| 3057 | if (urb->transfer_buffer_length > 0) { |
| 3058 | if (setup->bRequestType & USB_DIR_IN) |
| 3059 | field |= TRB_TX_TYPE(TRB_DATA_IN); |
| 3060 | else |
| 3061 | field |= TRB_TX_TYPE(TRB_DATA_OUT); |
| 3062 | } |
| 3063 | } |
| 3064 | |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3065 | queue_trb(xhci, ep_ring, false, true, false, |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 3066 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
| 3067 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, |
| 3068 | TRB_LEN(8) | TRB_INTR_TARGET(0), |
| 3069 | /* Immediate data in pointer */ |
| 3070 | field); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3071 | |
| 3072 | /* If there's data, queue data TRBs */ |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3073 | /* Only set interrupt on short packet for IN endpoints */ |
| 3074 | if (usb_urb_dir_in(urb)) |
| 3075 | field = TRB_ISP | TRB_TYPE(TRB_DATA); |
| 3076 | else |
| 3077 | field = TRB_TYPE(TRB_DATA); |
| 3078 | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3079 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 3080 | xhci_td_remainder(urb->transfer_buffer_length) | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3081 | TRB_INTR_TARGET(0); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3082 | if (urb->transfer_buffer_length > 0) { |
| 3083 | if (setup->bRequestType & USB_DIR_IN) |
| 3084 | field |= TRB_DIR_IN; |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3085 | queue_trb(xhci, ep_ring, false, true, false, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3086 | lower_32_bits(urb->transfer_dma), |
| 3087 | upper_32_bits(urb->transfer_dma), |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 3088 | length_field, |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3089 | field | ep_ring->cycle_state); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3090 | } |
| 3091 | |
| 3092 | /* Save the DMA address of the last TRB in the TD */ |
| 3093 | td->last_trb = ep_ring->enqueue; |
| 3094 | |
| 3095 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ |
| 3096 | /* If the device sent data, the status stage is an OUT transfer */ |
| 3097 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) |
| 3098 | field = 0; |
| 3099 | else |
| 3100 | field = TRB_DIR_IN; |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3101 | queue_trb(xhci, ep_ring, false, false, false, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3102 | 0, |
| 3103 | 0, |
| 3104 | TRB_INTR_TARGET(0), |
| 3105 | /* Event on completion */ |
| 3106 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); |
| 3107 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3108 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 3109 | start_cycle, start_trb); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3110 | return 0; |
| 3111 | } |
| 3112 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3113 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
| 3114 | struct urb *urb, int i) |
| 3115 | { |
| 3116 | int num_trbs = 0; |
Sarah Sharp | 48df4a6 | 2011-08-12 10:23:01 -0700 | [diff] [blame] | 3117 | u64 addr, td_len; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3118 | |
| 3119 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); |
| 3120 | td_len = urb->iso_frame_desc[i].length; |
| 3121 | |
Sarah Sharp | 48df4a6 | 2011-08-12 10:23:01 -0700 | [diff] [blame] | 3122 | num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)), |
| 3123 | TRB_MAX_BUFF_SIZE); |
| 3124 | if (num_trbs == 0) |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3125 | num_trbs++; |
| 3126 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3127 | return num_trbs; |
| 3128 | } |
| 3129 | |
Sarah Sharp | 5cd43e3 | 2011-04-08 09:37:29 -0700 | [diff] [blame] | 3130 | /* |
| 3131 | * The transfer burst count field of the isochronous TRB defines the number of |
| 3132 | * bursts that are required to move all packets in this TD. Only SuperSpeed |
| 3133 | * devices can burst up to bMaxBurst number of packets per service interval. |
| 3134 | * This field is zero based, meaning a value of zero in the field means one |
| 3135 | * burst. Basically, for everything but SuperSpeed devices, this field will be |
| 3136 | * zero. Only xHCI 1.0 host controllers support this field. |
| 3137 | */ |
| 3138 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, |
| 3139 | struct usb_device *udev, |
| 3140 | struct urb *urb, unsigned int total_packet_count) |
| 3141 | { |
| 3142 | unsigned int max_burst; |
| 3143 | |
| 3144 | if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER) |
| 3145 | return 0; |
| 3146 | |
| 3147 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; |
| 3148 | return roundup(total_packet_count, max_burst + 1) - 1; |
| 3149 | } |
| 3150 | |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3151 | /* |
| 3152 | * Returns the number of packets in the last "burst" of packets. This field is |
| 3153 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so |
| 3154 | * the last burst packet count is equal to the total number of packets in the |
| 3155 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst |
| 3156 | * must contain (bMaxBurst + 1) number of packets, but the last burst can |
| 3157 | * contain 1 to (bMaxBurst + 1) packets. |
| 3158 | */ |
| 3159 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, |
| 3160 | struct usb_device *udev, |
| 3161 | struct urb *urb, unsigned int total_packet_count) |
| 3162 | { |
| 3163 | unsigned int max_burst; |
| 3164 | unsigned int residue; |
| 3165 | |
| 3166 | if (xhci->hci_version < 0x100) |
| 3167 | return 0; |
| 3168 | |
| 3169 | switch (udev->speed) { |
| 3170 | case USB_SPEED_SUPER: |
| 3171 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
| 3172 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; |
| 3173 | residue = total_packet_count % (max_burst + 1); |
| 3174 | /* If residue is zero, the last burst contains (max_burst + 1) |
| 3175 | * number of packets, but the TLBPC field is zero-based. |
| 3176 | */ |
| 3177 | if (residue == 0) |
| 3178 | return max_burst; |
| 3179 | return residue - 1; |
| 3180 | default: |
| 3181 | if (total_packet_count == 0) |
| 3182 | return 0; |
| 3183 | return total_packet_count - 1; |
| 3184 | } |
| 3185 | } |
| 3186 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3187 | /* This is for isoc transfer */ |
| 3188 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 3189 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 3190 | { |
| 3191 | struct xhci_ring *ep_ring; |
| 3192 | struct urb_priv *urb_priv; |
| 3193 | struct xhci_td *td; |
| 3194 | int num_tds, trbs_per_td; |
| 3195 | struct xhci_generic_trb *start_trb; |
| 3196 | bool first_trb; |
| 3197 | int start_cycle; |
| 3198 | u32 field, length_field; |
| 3199 | int running_total, trb_buff_len, td_len, td_remain_len, ret; |
| 3200 | u64 start_addr, addr; |
| 3201 | int i, j; |
Andiry Xu | 47cbf69 | 2010-12-20 14:49:48 +0800 | [diff] [blame] | 3202 | bool more_trbs_coming; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3203 | |
| 3204 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
| 3205 | |
| 3206 | num_tds = urb->number_of_packets; |
| 3207 | if (num_tds < 1) { |
| 3208 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); |
| 3209 | return -EINVAL; |
| 3210 | } |
| 3211 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3212 | start_addr = (u64) urb->transfer_dma; |
| 3213 | start_trb = &ep_ring->enqueue->generic; |
| 3214 | start_cycle = ep_ring->cycle_state; |
| 3215 | |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3216 | urb_priv = urb->hcpriv; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3217 | /* Queue the first TRB, even if it's zero-length */ |
| 3218 | for (i = 0; i < num_tds; i++) { |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3219 | unsigned int total_packet_count; |
Sarah Sharp | 5cd43e3 | 2011-04-08 09:37:29 -0700 | [diff] [blame] | 3220 | unsigned int burst_count; |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3221 | unsigned int residue; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3222 | |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3223 | first_trb = true; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3224 | running_total = 0; |
| 3225 | addr = start_addr + urb->iso_frame_desc[i].offset; |
| 3226 | td_len = urb->iso_frame_desc[i].length; |
| 3227 | td_remain_len = td_len; |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3228 | total_packet_count = roundup(td_len, |
Kuninori Morimoto | 29cc889 | 2011-08-23 03:12:03 -0700 | [diff] [blame] | 3229 | usb_endpoint_maxp(&urb->ep->desc)); |
Sarah Sharp | 48df4a6 | 2011-08-12 10:23:01 -0700 | [diff] [blame] | 3230 | /* A zero-length transfer still involves at least one packet. */ |
| 3231 | if (total_packet_count == 0) |
| 3232 | total_packet_count++; |
Sarah Sharp | 5cd43e3 | 2011-04-08 09:37:29 -0700 | [diff] [blame] | 3233 | burst_count = xhci_get_burst_count(xhci, urb->dev, urb, |
| 3234 | total_packet_count); |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3235 | residue = xhci_get_last_burst_packet_count(xhci, |
| 3236 | urb->dev, urb, total_packet_count); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3237 | |
| 3238 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); |
| 3239 | |
| 3240 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3241 | urb->stream_id, trbs_per_td, urb, i, true, |
| 3242 | mem_flags); |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3243 | if (ret < 0) { |
| 3244 | if (i == 0) |
| 3245 | return ret; |
| 3246 | goto cleanup; |
| 3247 | } |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3248 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3249 | td = urb_priv->td[i]; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3250 | for (j = 0; j < trbs_per_td; j++) { |
| 3251 | u32 remainder = 0; |
Sarah Sharp | b61d378 | 2011-04-19 17:43:33 -0700 | [diff] [blame] | 3252 | field = TRB_TBC(burst_count) | TRB_TLBPC(residue); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3253 | |
| 3254 | if (first_trb) { |
| 3255 | /* Queue the isoc TRB */ |
| 3256 | field |= TRB_TYPE(TRB_ISOC); |
| 3257 | /* Assume URB_ISO_ASAP is set */ |
| 3258 | field |= TRB_SIA; |
Andiry Xu | 50f7b52 | 2010-12-20 15:09:34 +0800 | [diff] [blame] | 3259 | if (i == 0) { |
| 3260 | if (start_cycle == 0) |
| 3261 | field |= 0x1; |
| 3262 | } else |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3263 | field |= ep_ring->cycle_state; |
| 3264 | first_trb = false; |
| 3265 | } else { |
| 3266 | /* Queue other normal TRBs */ |
| 3267 | field |= TRB_TYPE(TRB_NORMAL); |
| 3268 | field |= ep_ring->cycle_state; |
| 3269 | } |
| 3270 | |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3271 | /* Only set interrupt on short packet for IN EPs */ |
| 3272 | if (usb_urb_dir_in(urb)) |
| 3273 | field |= TRB_ISP; |
| 3274 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3275 | /* Chain all the TRBs together; clear the chain bit in |
| 3276 | * the last TRB to indicate it's the last TRB in the |
| 3277 | * chain. |
| 3278 | */ |
| 3279 | if (j < trbs_per_td - 1) { |
| 3280 | field |= TRB_CHAIN; |
Andiry Xu | 47cbf69 | 2010-12-20 14:49:48 +0800 | [diff] [blame] | 3281 | more_trbs_coming = true; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3282 | } else { |
| 3283 | td->last_trb = ep_ring->enqueue; |
| 3284 | field |= TRB_IOC; |
Andiry Xu | ad106f2 | 2011-05-05 18:14:02 +0800 | [diff] [blame] | 3285 | if (xhci->hci_version == 0x100) { |
| 3286 | /* Set BEI bit except for the last td */ |
| 3287 | if (i < num_tds - 1) |
| 3288 | field |= TRB_BEI; |
| 3289 | } |
Andiry Xu | 47cbf69 | 2010-12-20 14:49:48 +0800 | [diff] [blame] | 3290 | more_trbs_coming = false; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3291 | } |
| 3292 | |
| 3293 | /* Calculate TRB length */ |
| 3294 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
| 3295 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); |
| 3296 | if (trb_buff_len > td_remain_len) |
| 3297 | trb_buff_len = td_remain_len; |
| 3298 | |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3299 | /* Set the TRB length, TD size, & interrupter fields. */ |
| 3300 | if (xhci->hci_version < 0x100) { |
| 3301 | remainder = xhci_td_remainder( |
| 3302 | td_len - running_total); |
| 3303 | } else { |
| 3304 | remainder = xhci_v1_0_td_remainder( |
| 3305 | running_total, trb_buff_len, |
| 3306 | total_packet_count, urb); |
| 3307 | } |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3308 | length_field = TRB_LEN(trb_buff_len) | |
| 3309 | remainder | |
| 3310 | TRB_INTR_TARGET(0); |
Sarah Sharp | 4da6e6f | 2011-04-01 14:01:30 -0700 | [diff] [blame] | 3311 | |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3312 | queue_trb(xhci, ep_ring, false, more_trbs_coming, true, |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3313 | lower_32_bits(addr), |
| 3314 | upper_32_bits(addr), |
| 3315 | length_field, |
Sarah Sharp | af8b9e6 | 2011-03-23 16:26:26 -0700 | [diff] [blame] | 3316 | field); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3317 | running_total += trb_buff_len; |
| 3318 | |
| 3319 | addr += trb_buff_len; |
| 3320 | td_remain_len -= trb_buff_len; |
| 3321 | } |
| 3322 | |
| 3323 | /* Check TD length */ |
| 3324 | if (running_total != td_len) { |
| 3325 | xhci_err(xhci, "ISOC TD length unmatch\n"); |
| 3326 | return -EINVAL; |
| 3327 | } |
| 3328 | } |
| 3329 | |
Andiry Xu | c41136b | 2011-03-22 17:08:14 +0800 | [diff] [blame] | 3330 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
| 3331 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
| 3332 | usb_amd_quirk_pll_disable(); |
| 3333 | } |
| 3334 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; |
| 3335 | |
Andiry Xu | e1eab2e | 2011-01-04 16:30:39 -0800 | [diff] [blame] | 3336 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
| 3337 | start_cycle, start_trb); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3338 | return 0; |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3339 | cleanup: |
| 3340 | /* Clean up a partially enqueued isoc transfer. */ |
| 3341 | |
| 3342 | for (i--; i >= 0; i--) |
Sarah Sharp | 585df1d | 2011-08-02 15:43:40 -0700 | [diff] [blame] | 3343 | list_del_init(&urb_priv->td[i]->td_list); |
Sarah Sharp | 522989a | 2011-07-29 12:44:32 -0700 | [diff] [blame] | 3344 | |
| 3345 | /* Use the first TD as a temporary variable to turn the TDs we've queued |
| 3346 | * into No-ops with a software-owned cycle bit. That way the hardware |
| 3347 | * won't accidentally start executing bogus TDs when we partially |
| 3348 | * overwrite them. td->first_trb and td->start_seg are already set. |
| 3349 | */ |
| 3350 | urb_priv->td[0]->last_trb = ep_ring->enqueue; |
| 3351 | /* Every TRB except the first & last will have its cycle bit flipped. */ |
| 3352 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); |
| 3353 | |
| 3354 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ |
| 3355 | ep_ring->enqueue = urb_priv->td[0]->first_trb; |
| 3356 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; |
| 3357 | ep_ring->cycle_state = start_cycle; |
| 3358 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
| 3359 | return ret; |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3360 | } |
| 3361 | |
| 3362 | /* |
| 3363 | * Check transfer ring to guarantee there is enough room for the urb. |
| 3364 | * Update ISO URB start_frame and interval. |
| 3365 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to |
| 3366 | * update the urb->start_frame by now. |
| 3367 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. |
| 3368 | */ |
| 3369 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 3370 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 3371 | { |
| 3372 | struct xhci_virt_device *xdev; |
| 3373 | struct xhci_ring *ep_ring; |
| 3374 | struct xhci_ep_ctx *ep_ctx; |
| 3375 | int start_frame; |
| 3376 | int xhci_interval; |
| 3377 | int ep_interval; |
| 3378 | int num_tds, num_trbs, i; |
| 3379 | int ret; |
| 3380 | |
| 3381 | xdev = xhci->devs[slot_id]; |
| 3382 | ep_ring = xdev->eps[ep_index].ring; |
| 3383 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
| 3384 | |
| 3385 | num_trbs = 0; |
| 3386 | num_tds = urb->number_of_packets; |
| 3387 | for (i = 0; i < num_tds; i++) |
| 3388 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); |
| 3389 | |
| 3390 | /* Check the ring to guarantee there is enough room for the whole urb. |
| 3391 | * Do not insert any td of the urb to the ring if the check failed. |
| 3392 | */ |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 3393 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3394 | num_trbs, true, mem_flags); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3395 | if (ret) |
| 3396 | return ret; |
| 3397 | |
| 3398 | start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index); |
| 3399 | start_frame &= 0x3fff; |
| 3400 | |
| 3401 | urb->start_frame = start_frame; |
| 3402 | if (urb->dev->speed == USB_SPEED_LOW || |
| 3403 | urb->dev->speed == USB_SPEED_FULL) |
| 3404 | urb->start_frame >>= 3; |
| 3405 | |
Matt Evans | 28ccd29 | 2011-03-29 13:40:46 +1100 | [diff] [blame] | 3406 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3407 | ep_interval = urb->interval; |
| 3408 | /* Convert to microframes */ |
| 3409 | if (urb->dev->speed == USB_SPEED_LOW || |
| 3410 | urb->dev->speed == USB_SPEED_FULL) |
| 3411 | ep_interval *= 8; |
| 3412 | /* FIXME change this to a warning and a suggestion to use the new API |
| 3413 | * to set the polling interval (once the API is added). |
| 3414 | */ |
| 3415 | if (xhci_interval != ep_interval) { |
Andiry Xu | 7961acd | 2010-12-20 17:14:20 +0800 | [diff] [blame] | 3416 | if (printk_ratelimit()) |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 3417 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
| 3418 | " (%d microframe%s) than xHCI " |
| 3419 | "(%d microframe%s)\n", |
| 3420 | ep_interval, |
| 3421 | ep_interval == 1 ? "" : "s", |
| 3422 | xhci_interval, |
| 3423 | xhci_interval == 1 ? "" : "s"); |
| 3424 | urb->interval = xhci_interval; |
| 3425 | /* Convert back to frames for LS/FS devices */ |
| 3426 | if (urb->dev->speed == USB_SPEED_LOW || |
| 3427 | urb->dev->speed == USB_SPEED_FULL) |
| 3428 | urb->interval /= 8; |
| 3429 | } |
| 3430 | return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); |
| 3431 | } |
| 3432 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3433 | /**** Command Ring Operations ****/ |
| 3434 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3435 | /* Generic function for queueing a command TRB on the command ring. |
| 3436 | * Check to make sure there's room on the command ring for one command TRB. |
| 3437 | * Also check that there's room reserved for commands that must not fail. |
| 3438 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, |
| 3439 | * then only check for the number of reserved spots. |
| 3440 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB |
| 3441 | * because the command event handler may want to resubmit a failed command. |
| 3442 | */ |
| 3443 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, |
| 3444 | u32 field3, u32 field4, bool command_must_succeed) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3445 | { |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3446 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 3447 | int ret; |
| 3448 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3449 | if (!command_must_succeed) |
| 3450 | reserved_trbs++; |
| 3451 | |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 3452 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3453 | reserved_trbs, false, GFP_ATOMIC); |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 3454 | if (ret < 0) { |
| 3455 | xhci_err(xhci, "ERR: No room for command on command ring\n"); |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3456 | if (command_must_succeed) |
| 3457 | xhci_err(xhci, "ERR: Reserved TRB counting for " |
| 3458 | "unfailable commands failed.\n"); |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 3459 | return ret; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3460 | } |
Andiry Xu | 7e393a8 | 2011-09-23 14:19:54 -0700 | [diff] [blame] | 3461 | queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2, |
| 3462 | field3, field4 | xhci->cmd_ring->cycle_state); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3463 | return 0; |
| 3464 | } |
| 3465 | |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3466 | /* Queue a slot enable or disable request on the command ring */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3467 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3468 | { |
| 3469 | return queue_command(xhci, 0, 0, 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3470 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3471 | } |
| 3472 | |
| 3473 | /* Queue an address device command TRB */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3474 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
| 3475 | u32 slot_id) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3476 | { |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 3477 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
| 3478 | upper_32_bits(in_ctx_ptr), 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3479 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), |
| 3480 | false); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3481 | } |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 3482 | |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 3483 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
| 3484 | u32 field1, u32 field2, u32 field3, u32 field4) |
| 3485 | { |
| 3486 | return queue_command(xhci, field1, field2, field3, field4, false); |
| 3487 | } |
| 3488 | |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 3489 | /* Queue a reset device command TRB */ |
| 3490 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) |
| 3491 | { |
| 3492 | return queue_command(xhci, 0, 0, 0, |
| 3493 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
| 3494 | false); |
| 3495 | } |
| 3496 | |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 3497 | /* Queue a configure endpoint command TRB */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3498 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3499 | u32 slot_id, bool command_must_succeed) |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 3500 | { |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 3501 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
| 3502 | upper_32_bits(in_ctx_ptr), 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3503 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
| 3504 | command_must_succeed); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 3505 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3506 | |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 3507 | /* Queue an evaluate context command TRB */ |
| 3508 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
| 3509 | u32 slot_id) |
| 3510 | { |
| 3511 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
| 3512 | upper_32_bits(in_ctx_ptr), 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3513 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
| 3514 | false); |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 3515 | } |
| 3516 | |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 3517 | /* |
| 3518 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop |
| 3519 | * activity on an endpoint that is about to be suspended. |
| 3520 | */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3521 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 3522 | unsigned int ep_index, int suspend) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3523 | { |
| 3524 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 3525 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
| 3526 | u32 type = TRB_TYPE(TRB_STOP_RING); |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 3527 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3528 | |
| 3529 | return queue_command(xhci, 0, 0, 0, |
Andiry Xu | be88fe4 | 2010-10-14 07:22:57 -0700 | [diff] [blame] | 3530 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3531 | } |
| 3532 | |
| 3533 | /* Set Transfer Ring Dequeue Pointer command. |
| 3534 | * This should not be used for endpoints that have streams enabled. |
| 3535 | */ |
| 3536 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3537 | unsigned int ep_index, unsigned int stream_id, |
| 3538 | struct xhci_segment *deq_seg, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3539 | union xhci_trb *deq_ptr, u32 cycle_state) |
| 3540 | { |
| 3541 | dma_addr_t addr; |
| 3542 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 3543 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3544 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3545 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 3546 | struct xhci_virt_ep *ep; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3547 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3548 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 3549 | if (addr == 0) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3550 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 3551 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
| 3552 | deq_seg, deq_ptr); |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 3553 | return 0; |
| 3554 | } |
Sarah Sharp | bf161e8 | 2011-02-23 15:46:42 -0800 | [diff] [blame] | 3555 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 3556 | if ((ep->ep_state & SET_DEQ_PENDING)) { |
| 3557 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
| 3558 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); |
| 3559 | return 0; |
| 3560 | } |
| 3561 | ep->queued_deq_seg = deq_seg; |
| 3562 | ep->queued_deq_ptr = deq_ptr; |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 3563 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3564 | upper_32_bits(addr), trb_stream_id, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3565 | trb_slot_id | trb_ep_index | type, false); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3566 | } |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 3567 | |
| 3568 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, |
| 3569 | unsigned int ep_index) |
| 3570 | { |
| 3571 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 3572 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
| 3573 | u32 type = TRB_TYPE(TRB_RESET_EP); |
| 3574 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3575 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
| 3576 | false); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 3577 | } |