Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Pinctrl data for the NVIDIA Tegra124 pinmux |
| 3 | * |
Stephen Warren | 0ffdd4b | 2014-03-12 15:35:47 -0600 | [diff] [blame] | 4 | * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/pinctrl/pinctrl.h> |
| 20 | #include <linux/pinctrl/pinmux.h> |
| 21 | |
| 22 | #include "pinctrl-tegra.h" |
| 23 | |
| 24 | /* |
| 25 | * Most pins affected by the pinmux can also be GPIOs. Define these first. |
| 26 | * These must match how the GPIO driver names/numbers its pins. |
| 27 | */ |
| 28 | #define _GPIO(offset) (offset) |
| 29 | |
| 30 | #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0) |
| 31 | #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1) |
| 32 | #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2) |
| 33 | #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3) |
| 34 | #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4) |
| 35 | #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5) |
| 36 | #define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6) |
| 37 | #define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7) |
| 38 | #define TEGRA_PIN_PB0 _GPIO(8) |
| 39 | #define TEGRA_PIN_PB1 _GPIO(9) |
| 40 | #define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12) |
| 41 | #define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13) |
| 42 | #define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14) |
| 43 | #define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15) |
| 44 | #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16) |
| 45 | #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18) |
| 46 | #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19) |
| 47 | #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20) |
| 48 | #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21) |
| 49 | #define TEGRA_PIN_PC7 _GPIO(23) |
| 50 | #define TEGRA_PIN_PG0 _GPIO(48) |
| 51 | #define TEGRA_PIN_PG1 _GPIO(49) |
| 52 | #define TEGRA_PIN_PG2 _GPIO(50) |
| 53 | #define TEGRA_PIN_PG3 _GPIO(51) |
| 54 | #define TEGRA_PIN_PG4 _GPIO(52) |
| 55 | #define TEGRA_PIN_PG5 _GPIO(53) |
| 56 | #define TEGRA_PIN_PG6 _GPIO(54) |
| 57 | #define TEGRA_PIN_PG7 _GPIO(55) |
| 58 | #define TEGRA_PIN_PH0 _GPIO(56) |
| 59 | #define TEGRA_PIN_PH1 _GPIO(57) |
| 60 | #define TEGRA_PIN_PH2 _GPIO(58) |
| 61 | #define TEGRA_PIN_PH3 _GPIO(59) |
| 62 | #define TEGRA_PIN_PH4 _GPIO(60) |
| 63 | #define TEGRA_PIN_PH5 _GPIO(61) |
| 64 | #define TEGRA_PIN_PH6 _GPIO(62) |
| 65 | #define TEGRA_PIN_PH7 _GPIO(63) |
| 66 | #define TEGRA_PIN_PI0 _GPIO(64) |
| 67 | #define TEGRA_PIN_PI1 _GPIO(65) |
| 68 | #define TEGRA_PIN_PI2 _GPIO(66) |
| 69 | #define TEGRA_PIN_PI3 _GPIO(67) |
| 70 | #define TEGRA_PIN_PI4 _GPIO(68) |
| 71 | #define TEGRA_PIN_PI5 _GPIO(69) |
| 72 | #define TEGRA_PIN_PI6 _GPIO(70) |
| 73 | #define TEGRA_PIN_PI7 _GPIO(71) |
| 74 | #define TEGRA_PIN_PJ0 _GPIO(72) |
| 75 | #define TEGRA_PIN_PJ2 _GPIO(74) |
| 76 | #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77) |
| 77 | #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78) |
| 78 | #define TEGRA_PIN_PJ7 _GPIO(79) |
| 79 | #define TEGRA_PIN_PK0 _GPIO(80) |
| 80 | #define TEGRA_PIN_PK1 _GPIO(81) |
| 81 | #define TEGRA_PIN_PK2 _GPIO(82) |
| 82 | #define TEGRA_PIN_PK3 _GPIO(83) |
| 83 | #define TEGRA_PIN_PK4 _GPIO(84) |
| 84 | #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85) |
| 85 | #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86) |
| 86 | #define TEGRA_PIN_PK7 _GPIO(87) |
| 87 | #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104) |
| 88 | #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105) |
| 89 | #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106) |
| 90 | #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107) |
| 91 | #define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108) |
| 92 | #define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109) |
| 93 | #define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111) |
| 94 | #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112) |
| 95 | #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113) |
| 96 | #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114) |
| 97 | #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115) |
| 98 | #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116) |
| 99 | #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117) |
| 100 | #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118) |
| 101 | #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119) |
| 102 | #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120) |
| 103 | #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121) |
| 104 | #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122) |
| 105 | #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123) |
| 106 | #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124) |
| 107 | #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125) |
| 108 | #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126) |
| 109 | #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127) |
| 110 | #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128) |
| 111 | #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129) |
| 112 | #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130) |
| 113 | #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131) |
| 114 | #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132) |
| 115 | #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133) |
| 116 | #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134) |
| 117 | #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135) |
| 118 | #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136) |
| 119 | #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137) |
| 120 | #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138) |
| 121 | #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139) |
| 122 | #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140) |
| 123 | #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141) |
| 124 | #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142) |
| 125 | #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143) |
| 126 | #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144) |
| 127 | #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145) |
| 128 | #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146) |
| 129 | #define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147) |
| 130 | #define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148) |
| 131 | #define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149) |
| 132 | #define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150) |
| 133 | #define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151) |
| 134 | #define TEGRA_PIN_KB_ROW16_PT0 _GPIO(152) |
| 135 | #define TEGRA_PIN_KB_ROW17_PT1 _GPIO(153) |
| 136 | #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157) |
| 137 | #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158) |
| 138 | #define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159) |
| 139 | #define TEGRA_PIN_PU0 _GPIO(160) |
| 140 | #define TEGRA_PIN_PU1 _GPIO(161) |
| 141 | #define TEGRA_PIN_PU2 _GPIO(162) |
| 142 | #define TEGRA_PIN_PU3 _GPIO(163) |
| 143 | #define TEGRA_PIN_PU4 _GPIO(164) |
| 144 | #define TEGRA_PIN_PU5 _GPIO(165) |
| 145 | #define TEGRA_PIN_PU6 _GPIO(166) |
| 146 | #define TEGRA_PIN_PV0 _GPIO(168) |
| 147 | #define TEGRA_PIN_PV1 _GPIO(169) |
| 148 | #define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170) |
| 149 | #define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171) |
| 150 | #define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172) |
| 151 | #define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173) |
| 152 | #define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178) |
| 153 | #define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179) |
| 154 | #define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180) |
| 155 | #define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181) |
| 156 | #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182) |
| 157 | #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183) |
| 158 | #define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184) |
| 159 | #define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185) |
| 160 | #define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186) |
| 161 | #define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187) |
| 162 | #define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188) |
| 163 | #define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189) |
| 164 | #define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190) |
| 165 | #define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191) |
| 166 | #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192) |
| 167 | #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193) |
| 168 | #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194) |
| 169 | #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195) |
| 170 | #define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196) |
| 171 | #define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197) |
| 172 | #define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198) |
| 173 | #define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199) |
| 174 | #define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200) |
| 175 | #define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201) |
| 176 | #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206) |
| 177 | #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207) |
| 178 | #define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208) |
| 179 | #define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209) |
| 180 | #define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210) |
| 181 | #define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211) |
| 182 | #define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212) |
| 183 | #define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213) |
| 184 | #define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214) |
| 185 | #define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215) |
| 186 | #define TEGRA_PIN_PBB0 _GPIO(216) |
| 187 | #define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217) |
| 188 | #define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218) |
| 189 | #define TEGRA_PIN_PBB3 _GPIO(219) |
| 190 | #define TEGRA_PIN_PBB4 _GPIO(220) |
| 191 | #define TEGRA_PIN_PBB5 _GPIO(221) |
| 192 | #define TEGRA_PIN_PBB6 _GPIO(222) |
| 193 | #define TEGRA_PIN_PBB7 _GPIO(223) |
| 194 | #define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224) |
| 195 | #define TEGRA_PIN_PCC1 _GPIO(225) |
| 196 | #define TEGRA_PIN_PCC2 _GPIO(226) |
| 197 | #define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228) |
| 198 | #define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229) |
| 199 | #define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233) |
| 200 | #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234) |
| 201 | #define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235) |
| 202 | #define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237) |
| 203 | #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238) |
| 204 | #define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240) |
| 205 | #define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241) |
| 206 | #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2 _GPIO(242) |
| 207 | #define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243) |
| 208 | #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244) |
| 209 | #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245) |
| 210 | #define TEGRA_PIN_DP_HPD_PFF0 _GPIO(248) |
| 211 | #define TEGRA_PIN_USB_VBUS_EN2_PFF1 _GPIO(249) |
| 212 | #define TEGRA_PIN_PFF2 _GPIO(250) |
| 213 | |
| 214 | /* All non-GPIO pins follow */ |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 215 | #define NUM_GPIOS (TEGRA_PIN_PFF2 + 1) |
| 216 | #define _PIN(offset) (NUM_GPIOS + (offset)) |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 217 | |
| 218 | /* Non-GPIO pins */ |
| 219 | #define TEGRA_PIN_CORE_PWR_REQ _PIN(0) |
| 220 | #define TEGRA_PIN_CPU_PWR_REQ _PIN(1) |
| 221 | #define TEGRA_PIN_PWR_INT_N _PIN(2) |
| 222 | #define TEGRA_PIN_GMI_CLK_LB _PIN(3) |
| 223 | #define TEGRA_PIN_RESET_OUT_N _PIN(4) |
| 224 | #define TEGRA_PIN_OWR _PIN(5) |
| 225 | #define TEGRA_PIN_CLK_32K_IN _PIN(6) |
| 226 | #define TEGRA_PIN_JTAG_RTCK _PIN(7) |
Sean Paul | 3ccc11f | 2014-09-09 15:58:45 -0400 | [diff] [blame] | 227 | #define TEGRA_PIN_DSI_B_CLK_P _PIN(8) |
| 228 | #define TEGRA_PIN_DSI_B_CLK_N _PIN(9) |
| 229 | #define TEGRA_PIN_DSI_B_D0_P _PIN(10) |
| 230 | #define TEGRA_PIN_DSI_B_D0_N _PIN(11) |
| 231 | #define TEGRA_PIN_DSI_B_D1_P _PIN(12) |
| 232 | #define TEGRA_PIN_DSI_B_D1_N _PIN(13) |
| 233 | #define TEGRA_PIN_DSI_B_D2_P _PIN(14) |
| 234 | #define TEGRA_PIN_DSI_B_D2_N _PIN(15) |
| 235 | #define TEGRA_PIN_DSI_B_D3_P _PIN(16) |
| 236 | #define TEGRA_PIN_DSI_B_D3_N _PIN(17) |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 237 | |
| 238 | static const struct pinctrl_pin_desc tegra124_pins[] = { |
| 239 | PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), |
| 240 | PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"), |
| 241 | PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"), |
| 242 | PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"), |
| 243 | PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"), |
| 244 | PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"), |
| 245 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"), |
| 246 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"), |
| 247 | PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"), |
| 248 | PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"), |
| 249 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"), |
| 250 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"), |
| 251 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"), |
| 252 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"), |
| 253 | PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"), |
| 254 | PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"), |
| 255 | PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"), |
| 256 | PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"), |
| 257 | PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"), |
| 258 | PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"), |
| 259 | PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"), |
| 260 | PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"), |
| 261 | PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"), |
| 262 | PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"), |
| 263 | PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"), |
| 264 | PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"), |
| 265 | PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"), |
| 266 | PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"), |
| 267 | PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"), |
| 268 | PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"), |
| 269 | PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"), |
| 270 | PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"), |
| 271 | PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"), |
| 272 | PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"), |
| 273 | PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"), |
| 274 | PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"), |
| 275 | PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"), |
| 276 | PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"), |
| 277 | PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"), |
| 278 | PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"), |
| 279 | PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"), |
| 280 | PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"), |
| 281 | PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"), |
| 282 | PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"), |
| 283 | PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"), |
| 284 | PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"), |
| 285 | PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"), |
| 286 | PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"), |
| 287 | PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"), |
| 288 | PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"), |
| 289 | PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"), |
| 290 | PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"), |
| 291 | PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"), |
| 292 | PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"), |
| 293 | PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"), |
| 294 | PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"), |
| 295 | PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"), |
| 296 | PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"), |
| 297 | PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"), |
| 298 | PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"), |
| 299 | PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"), |
| 300 | PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"), |
| 301 | PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"), |
| 302 | PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"), |
| 303 | PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"), |
| 304 | PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"), |
| 305 | PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"), |
| 306 | PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"), |
| 307 | PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"), |
| 308 | PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"), |
| 309 | PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"), |
| 310 | PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"), |
| 311 | PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"), |
| 312 | PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"), |
| 313 | PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"), |
| 314 | PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"), |
| 315 | PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"), |
| 316 | PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"), |
| 317 | PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"), |
| 318 | PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"), |
| 319 | PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"), |
| 320 | PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"), |
| 321 | PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"), |
| 322 | PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"), |
| 323 | PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"), |
| 324 | PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"), |
| 325 | PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"), |
| 326 | PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"), |
| 327 | PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"), |
| 328 | PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"), |
| 329 | PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"), |
| 330 | PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"), |
| 331 | PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"), |
| 332 | PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"), |
| 333 | PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"), |
| 334 | PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"), |
| 335 | PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"), |
| 336 | PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"), |
| 337 | PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"), |
Stephen Warren | a76cbd7 | 2014-03-05 14:53:32 -0700 | [diff] [blame] | 338 | PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"), |
| 339 | PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"), |
| 340 | PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"), |
| 341 | PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"), |
| 342 | PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"), |
| 343 | PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"), |
| 344 | PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 345 | PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"), |
| 346 | PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"), |
| 347 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"), |
| 348 | PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"), |
| 349 | PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"), |
| 350 | PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"), |
| 351 | PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"), |
| 352 | PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"), |
| 353 | PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"), |
| 354 | PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"), |
| 355 | PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"), |
| 356 | PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"), |
| 357 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"), |
| 358 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"), |
| 359 | PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"), |
| 360 | PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"), |
| 361 | PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"), |
| 362 | PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"), |
| 363 | PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"), |
| 364 | PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"), |
| 365 | PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"), |
| 366 | PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"), |
| 367 | PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"), |
| 368 | PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"), |
| 369 | PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"), |
| 370 | PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"), |
| 371 | PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"), |
| 372 | PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"), |
| 373 | PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"), |
| 374 | PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"), |
| 375 | PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"), |
| 376 | PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"), |
| 377 | PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"), |
| 378 | PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"), |
| 379 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"), |
| 380 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"), |
| 381 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"), |
| 382 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"), |
| 383 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"), |
| 384 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"), |
| 385 | PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"), |
| 386 | PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"), |
| 387 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"), |
| 388 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"), |
| 389 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"), |
| 390 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"), |
| 391 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"), |
| 392 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"), |
| 393 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"), |
| 394 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"), |
| 395 | PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"), |
| 396 | PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"), |
| 397 | PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"), |
| 398 | PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"), |
| 399 | PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"), |
| 400 | PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"), |
| 401 | PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"), |
| 402 | PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"), |
| 403 | PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"), |
| 404 | PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"), |
| 405 | PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"), |
| 406 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"), |
| 407 | PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"), |
| 408 | PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"), |
| 409 | PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"), |
| 410 | PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"), |
| 411 | PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"), |
| 412 | PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"), |
| 413 | PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"), |
| 414 | PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"), |
| 415 | PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"), |
| 416 | PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"), |
| 417 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"), |
| 418 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 419 | PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"), |
| 420 | PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"), |
| 421 | PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"), |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 422 | PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), |
| 423 | PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), |
| 424 | PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 425 | PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"), |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 426 | PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"), |
| 427 | PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"), |
| 428 | PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 429 | PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), |
Sean Paul | 3ccc11f | 2014-09-09 15:58:45 -0400 | [diff] [blame] | 430 | PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"), |
| 431 | PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"), |
| 432 | PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"), |
| 433 | PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"), |
| 434 | PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"), |
| 435 | PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"), |
| 436 | PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"), |
| 437 | PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"), |
| 438 | PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"), |
| 439 | PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 440 | }; |
| 441 | |
| 442 | static const unsigned clk_32k_out_pa0_pins[] = { |
| 443 | TEGRA_PIN_CLK_32K_OUT_PA0, |
| 444 | }; |
| 445 | |
| 446 | static const unsigned uart3_cts_n_pa1_pins[] = { |
| 447 | TEGRA_PIN_UART3_CTS_N_PA1, |
| 448 | }; |
| 449 | |
| 450 | static const unsigned dap2_fs_pa2_pins[] = { |
| 451 | TEGRA_PIN_DAP2_FS_PA2, |
| 452 | }; |
| 453 | |
| 454 | static const unsigned dap2_sclk_pa3_pins[] = { |
| 455 | TEGRA_PIN_DAP2_SCLK_PA3, |
| 456 | }; |
| 457 | |
| 458 | static const unsigned dap2_din_pa4_pins[] = { |
| 459 | TEGRA_PIN_DAP2_DIN_PA4, |
| 460 | }; |
| 461 | |
| 462 | static const unsigned dap2_dout_pa5_pins[] = { |
| 463 | TEGRA_PIN_DAP2_DOUT_PA5, |
| 464 | }; |
| 465 | |
| 466 | static const unsigned sdmmc3_clk_pa6_pins[] = { |
| 467 | TEGRA_PIN_SDMMC3_CLK_PA6, |
| 468 | }; |
| 469 | |
| 470 | static const unsigned sdmmc3_cmd_pa7_pins[] = { |
| 471 | TEGRA_PIN_SDMMC3_CMD_PA7, |
| 472 | }; |
| 473 | |
| 474 | static const unsigned pb0_pins[] = { |
| 475 | TEGRA_PIN_PB0, |
| 476 | }; |
| 477 | |
| 478 | static const unsigned pb1_pins[] = { |
| 479 | TEGRA_PIN_PB1, |
| 480 | }; |
| 481 | |
| 482 | static const unsigned sdmmc3_dat3_pb4_pins[] = { |
| 483 | TEGRA_PIN_SDMMC3_DAT3_PB4, |
| 484 | }; |
| 485 | |
| 486 | static const unsigned sdmmc3_dat2_pb5_pins[] = { |
| 487 | TEGRA_PIN_SDMMC3_DAT2_PB5, |
| 488 | }; |
| 489 | |
| 490 | static const unsigned sdmmc3_dat1_pb6_pins[] = { |
| 491 | TEGRA_PIN_SDMMC3_DAT1_PB6, |
| 492 | }; |
| 493 | |
| 494 | static const unsigned sdmmc3_dat0_pb7_pins[] = { |
| 495 | TEGRA_PIN_SDMMC3_DAT0_PB7, |
| 496 | }; |
| 497 | |
| 498 | static const unsigned uart3_rts_n_pc0_pins[] = { |
| 499 | TEGRA_PIN_UART3_RTS_N_PC0, |
| 500 | }; |
| 501 | |
| 502 | static const unsigned uart2_txd_pc2_pins[] = { |
| 503 | TEGRA_PIN_UART2_TXD_PC2, |
| 504 | }; |
| 505 | |
| 506 | static const unsigned uart2_rxd_pc3_pins[] = { |
| 507 | TEGRA_PIN_UART2_RXD_PC3, |
| 508 | }; |
| 509 | |
| 510 | static const unsigned gen1_i2c_scl_pc4_pins[] = { |
| 511 | TEGRA_PIN_GEN1_I2C_SCL_PC4, |
| 512 | }; |
| 513 | |
| 514 | static const unsigned gen1_i2c_sda_pc5_pins[] = { |
| 515 | TEGRA_PIN_GEN1_I2C_SDA_PC5, |
| 516 | }; |
| 517 | |
| 518 | static const unsigned pc7_pins[] = { |
| 519 | TEGRA_PIN_PC7, |
| 520 | }; |
| 521 | |
| 522 | static const unsigned pg0_pins[] = { |
| 523 | TEGRA_PIN_PG0, |
| 524 | }; |
| 525 | |
| 526 | static const unsigned pg1_pins[] = { |
| 527 | TEGRA_PIN_PG1, |
| 528 | }; |
| 529 | |
| 530 | static const unsigned pg2_pins[] = { |
| 531 | TEGRA_PIN_PG2, |
| 532 | }; |
| 533 | |
| 534 | static const unsigned pg3_pins[] = { |
| 535 | TEGRA_PIN_PG3, |
| 536 | }; |
| 537 | |
| 538 | static const unsigned pg4_pins[] = { |
| 539 | TEGRA_PIN_PG4, |
| 540 | }; |
| 541 | |
| 542 | static const unsigned pg5_pins[] = { |
| 543 | TEGRA_PIN_PG5, |
| 544 | }; |
| 545 | |
| 546 | static const unsigned pg6_pins[] = { |
| 547 | TEGRA_PIN_PG6, |
| 548 | }; |
| 549 | |
| 550 | static const unsigned pg7_pins[] = { |
| 551 | TEGRA_PIN_PG7, |
| 552 | }; |
| 553 | |
| 554 | static const unsigned ph0_pins[] = { |
| 555 | TEGRA_PIN_PH0, |
| 556 | }; |
| 557 | |
| 558 | static const unsigned ph1_pins[] = { |
| 559 | TEGRA_PIN_PH1, |
| 560 | }; |
| 561 | |
| 562 | static const unsigned ph2_pins[] = { |
| 563 | TEGRA_PIN_PH2, |
| 564 | }; |
| 565 | |
| 566 | static const unsigned ph3_pins[] = { |
| 567 | TEGRA_PIN_PH3, |
| 568 | }; |
| 569 | |
| 570 | static const unsigned ph4_pins[] = { |
| 571 | TEGRA_PIN_PH4, |
| 572 | }; |
| 573 | |
| 574 | static const unsigned ph5_pins[] = { |
| 575 | TEGRA_PIN_PH5, |
| 576 | }; |
| 577 | |
| 578 | static const unsigned ph6_pins[] = { |
| 579 | TEGRA_PIN_PH6, |
| 580 | }; |
| 581 | |
| 582 | static const unsigned ph7_pins[] = { |
| 583 | TEGRA_PIN_PH7, |
| 584 | }; |
| 585 | |
| 586 | static const unsigned pi0_pins[] = { |
| 587 | TEGRA_PIN_PI0, |
| 588 | }; |
| 589 | |
| 590 | static const unsigned pi1_pins[] = { |
| 591 | TEGRA_PIN_PI1, |
| 592 | }; |
| 593 | |
| 594 | static const unsigned pi2_pins[] = { |
| 595 | TEGRA_PIN_PI2, |
| 596 | }; |
| 597 | |
| 598 | static const unsigned pi3_pins[] = { |
| 599 | TEGRA_PIN_PI3, |
| 600 | }; |
| 601 | |
| 602 | static const unsigned pi4_pins[] = { |
| 603 | TEGRA_PIN_PI4, |
| 604 | }; |
| 605 | |
| 606 | static const unsigned pi5_pins[] = { |
| 607 | TEGRA_PIN_PI5, |
| 608 | }; |
| 609 | |
| 610 | static const unsigned pi6_pins[] = { |
| 611 | TEGRA_PIN_PI6, |
| 612 | }; |
| 613 | |
| 614 | static const unsigned pi7_pins[] = { |
| 615 | TEGRA_PIN_PI7, |
| 616 | }; |
| 617 | |
| 618 | static const unsigned pj0_pins[] = { |
| 619 | TEGRA_PIN_PJ0, |
| 620 | }; |
| 621 | |
| 622 | static const unsigned pj2_pins[] = { |
| 623 | TEGRA_PIN_PJ2, |
| 624 | }; |
| 625 | |
| 626 | static const unsigned uart2_cts_n_pj5_pins[] = { |
| 627 | TEGRA_PIN_UART2_CTS_N_PJ5, |
| 628 | }; |
| 629 | |
| 630 | static const unsigned uart2_rts_n_pj6_pins[] = { |
| 631 | TEGRA_PIN_UART2_RTS_N_PJ6, |
| 632 | }; |
| 633 | |
| 634 | static const unsigned pj7_pins[] = { |
| 635 | TEGRA_PIN_PJ7, |
| 636 | }; |
| 637 | |
| 638 | static const unsigned pk0_pins[] = { |
| 639 | TEGRA_PIN_PK0, |
| 640 | }; |
| 641 | |
| 642 | static const unsigned pk1_pins[] = { |
| 643 | TEGRA_PIN_PK1, |
| 644 | }; |
| 645 | |
| 646 | static const unsigned pk2_pins[] = { |
| 647 | TEGRA_PIN_PK2, |
| 648 | }; |
| 649 | |
| 650 | static const unsigned pk3_pins[] = { |
| 651 | TEGRA_PIN_PK3, |
| 652 | }; |
| 653 | |
| 654 | static const unsigned pk4_pins[] = { |
| 655 | TEGRA_PIN_PK4, |
| 656 | }; |
| 657 | |
| 658 | static const unsigned spdif_out_pk5_pins[] = { |
| 659 | TEGRA_PIN_SPDIF_OUT_PK5, |
| 660 | }; |
| 661 | |
| 662 | static const unsigned spdif_in_pk6_pins[] = { |
| 663 | TEGRA_PIN_SPDIF_IN_PK6, |
| 664 | }; |
| 665 | |
| 666 | static const unsigned pk7_pins[] = { |
| 667 | TEGRA_PIN_PK7, |
| 668 | }; |
| 669 | |
| 670 | static const unsigned dap1_fs_pn0_pins[] = { |
| 671 | TEGRA_PIN_DAP1_FS_PN0, |
| 672 | }; |
| 673 | |
| 674 | static const unsigned dap1_din_pn1_pins[] = { |
| 675 | TEGRA_PIN_DAP1_DIN_PN1, |
| 676 | }; |
| 677 | |
| 678 | static const unsigned dap1_dout_pn2_pins[] = { |
| 679 | TEGRA_PIN_DAP1_DOUT_PN2, |
| 680 | }; |
| 681 | |
| 682 | static const unsigned dap1_sclk_pn3_pins[] = { |
| 683 | TEGRA_PIN_DAP1_SCLK_PN3, |
| 684 | }; |
| 685 | |
| 686 | static const unsigned usb_vbus_en0_pn4_pins[] = { |
| 687 | TEGRA_PIN_USB_VBUS_EN0_PN4, |
| 688 | }; |
| 689 | |
| 690 | static const unsigned usb_vbus_en1_pn5_pins[] = { |
| 691 | TEGRA_PIN_USB_VBUS_EN1_PN5, |
| 692 | }; |
| 693 | |
| 694 | static const unsigned hdmi_int_pn7_pins[] = { |
| 695 | TEGRA_PIN_HDMI_INT_PN7, |
| 696 | }; |
| 697 | |
| 698 | static const unsigned ulpi_data7_po0_pins[] = { |
| 699 | TEGRA_PIN_ULPI_DATA7_PO0, |
| 700 | }; |
| 701 | |
| 702 | static const unsigned ulpi_data0_po1_pins[] = { |
| 703 | TEGRA_PIN_ULPI_DATA0_PO1, |
| 704 | }; |
| 705 | |
| 706 | static const unsigned ulpi_data1_po2_pins[] = { |
| 707 | TEGRA_PIN_ULPI_DATA1_PO2, |
| 708 | }; |
| 709 | |
| 710 | static const unsigned ulpi_data2_po3_pins[] = { |
| 711 | TEGRA_PIN_ULPI_DATA2_PO3, |
| 712 | }; |
| 713 | |
| 714 | static const unsigned ulpi_data3_po4_pins[] = { |
| 715 | TEGRA_PIN_ULPI_DATA3_PO4, |
| 716 | }; |
| 717 | |
| 718 | static const unsigned ulpi_data4_po5_pins[] = { |
| 719 | TEGRA_PIN_ULPI_DATA4_PO5, |
| 720 | }; |
| 721 | |
| 722 | static const unsigned ulpi_data5_po6_pins[] = { |
| 723 | TEGRA_PIN_ULPI_DATA5_PO6, |
| 724 | }; |
| 725 | |
| 726 | static const unsigned ulpi_data6_po7_pins[] = { |
| 727 | TEGRA_PIN_ULPI_DATA6_PO7, |
| 728 | }; |
| 729 | |
| 730 | static const unsigned dap3_fs_pp0_pins[] = { |
| 731 | TEGRA_PIN_DAP3_FS_PP0, |
| 732 | }; |
| 733 | |
| 734 | static const unsigned dap3_din_pp1_pins[] = { |
| 735 | TEGRA_PIN_DAP3_DIN_PP1, |
| 736 | }; |
| 737 | |
| 738 | static const unsigned dap3_dout_pp2_pins[] = { |
| 739 | TEGRA_PIN_DAP3_DOUT_PP2, |
| 740 | }; |
| 741 | |
| 742 | static const unsigned dap3_sclk_pp3_pins[] = { |
| 743 | TEGRA_PIN_DAP3_SCLK_PP3, |
| 744 | }; |
| 745 | |
| 746 | static const unsigned dap4_fs_pp4_pins[] = { |
| 747 | TEGRA_PIN_DAP4_FS_PP4, |
| 748 | }; |
| 749 | |
| 750 | static const unsigned dap4_din_pp5_pins[] = { |
| 751 | TEGRA_PIN_DAP4_DIN_PP5, |
| 752 | }; |
| 753 | |
| 754 | static const unsigned dap4_dout_pp6_pins[] = { |
| 755 | TEGRA_PIN_DAP4_DOUT_PP6, |
| 756 | }; |
| 757 | |
| 758 | static const unsigned dap4_sclk_pp7_pins[] = { |
| 759 | TEGRA_PIN_DAP4_SCLK_PP7, |
| 760 | }; |
| 761 | |
| 762 | static const unsigned kb_col0_pq0_pins[] = { |
| 763 | TEGRA_PIN_KB_COL0_PQ0, |
| 764 | }; |
| 765 | |
| 766 | static const unsigned kb_col1_pq1_pins[] = { |
| 767 | TEGRA_PIN_KB_COL1_PQ1, |
| 768 | }; |
| 769 | |
| 770 | static const unsigned kb_col2_pq2_pins[] = { |
| 771 | TEGRA_PIN_KB_COL2_PQ2, |
| 772 | }; |
| 773 | |
| 774 | static const unsigned kb_col3_pq3_pins[] = { |
| 775 | TEGRA_PIN_KB_COL3_PQ3, |
| 776 | }; |
| 777 | |
| 778 | static const unsigned kb_col4_pq4_pins[] = { |
| 779 | TEGRA_PIN_KB_COL4_PQ4, |
| 780 | }; |
| 781 | |
| 782 | static const unsigned kb_col5_pq5_pins[] = { |
| 783 | TEGRA_PIN_KB_COL5_PQ5, |
| 784 | }; |
| 785 | |
| 786 | static const unsigned kb_col6_pq6_pins[] = { |
| 787 | TEGRA_PIN_KB_COL6_PQ6, |
| 788 | }; |
| 789 | |
| 790 | static const unsigned kb_col7_pq7_pins[] = { |
| 791 | TEGRA_PIN_KB_COL7_PQ7, |
| 792 | }; |
| 793 | |
| 794 | static const unsigned kb_row0_pr0_pins[] = { |
| 795 | TEGRA_PIN_KB_ROW0_PR0, |
| 796 | }; |
| 797 | |
| 798 | static const unsigned kb_row1_pr1_pins[] = { |
| 799 | TEGRA_PIN_KB_ROW1_PR1, |
| 800 | }; |
| 801 | |
| 802 | static const unsigned kb_row2_pr2_pins[] = { |
| 803 | TEGRA_PIN_KB_ROW2_PR2, |
| 804 | }; |
| 805 | |
| 806 | static const unsigned kb_row3_pr3_pins[] = { |
| 807 | TEGRA_PIN_KB_ROW3_PR3, |
| 808 | }; |
| 809 | |
| 810 | static const unsigned kb_row4_pr4_pins[] = { |
| 811 | TEGRA_PIN_KB_ROW4_PR4, |
| 812 | }; |
| 813 | |
| 814 | static const unsigned kb_row5_pr5_pins[] = { |
| 815 | TEGRA_PIN_KB_ROW5_PR5, |
| 816 | }; |
| 817 | |
| 818 | static const unsigned kb_row6_pr6_pins[] = { |
| 819 | TEGRA_PIN_KB_ROW6_PR6, |
| 820 | }; |
| 821 | |
| 822 | static const unsigned kb_row7_pr7_pins[] = { |
| 823 | TEGRA_PIN_KB_ROW7_PR7, |
| 824 | }; |
| 825 | |
| 826 | static const unsigned kb_row8_ps0_pins[] = { |
| 827 | TEGRA_PIN_KB_ROW8_PS0, |
| 828 | }; |
| 829 | |
| 830 | static const unsigned kb_row9_ps1_pins[] = { |
| 831 | TEGRA_PIN_KB_ROW9_PS1, |
| 832 | }; |
| 833 | |
| 834 | static const unsigned kb_row10_ps2_pins[] = { |
| 835 | TEGRA_PIN_KB_ROW10_PS2, |
| 836 | }; |
| 837 | |
| 838 | static const unsigned kb_row11_ps3_pins[] = { |
| 839 | TEGRA_PIN_KB_ROW11_PS3, |
| 840 | }; |
| 841 | |
| 842 | static const unsigned kb_row12_ps4_pins[] = { |
| 843 | TEGRA_PIN_KB_ROW12_PS4, |
| 844 | }; |
| 845 | |
| 846 | static const unsigned kb_row13_ps5_pins[] = { |
| 847 | TEGRA_PIN_KB_ROW13_PS5, |
| 848 | }; |
| 849 | |
| 850 | static const unsigned kb_row14_ps6_pins[] = { |
| 851 | TEGRA_PIN_KB_ROW14_PS6, |
| 852 | }; |
| 853 | |
| 854 | static const unsigned kb_row15_ps7_pins[] = { |
| 855 | TEGRA_PIN_KB_ROW15_PS7, |
| 856 | }; |
| 857 | |
| 858 | static const unsigned kb_row16_pt0_pins[] = { |
| 859 | TEGRA_PIN_KB_ROW16_PT0, |
| 860 | }; |
| 861 | |
| 862 | static const unsigned kb_row17_pt1_pins[] = { |
| 863 | TEGRA_PIN_KB_ROW17_PT1, |
| 864 | }; |
| 865 | |
| 866 | static const unsigned gen2_i2c_scl_pt5_pins[] = { |
| 867 | TEGRA_PIN_GEN2_I2C_SCL_PT5, |
| 868 | }; |
| 869 | |
| 870 | static const unsigned gen2_i2c_sda_pt6_pins[] = { |
| 871 | TEGRA_PIN_GEN2_I2C_SDA_PT6, |
| 872 | }; |
| 873 | |
| 874 | static const unsigned sdmmc4_cmd_pt7_pins[] = { |
| 875 | TEGRA_PIN_SDMMC4_CMD_PT7, |
| 876 | }; |
| 877 | |
| 878 | static const unsigned pu0_pins[] = { |
| 879 | TEGRA_PIN_PU0, |
| 880 | }; |
| 881 | |
| 882 | static const unsigned pu1_pins[] = { |
| 883 | TEGRA_PIN_PU1, |
| 884 | }; |
| 885 | |
| 886 | static const unsigned pu2_pins[] = { |
| 887 | TEGRA_PIN_PU2, |
| 888 | }; |
| 889 | |
| 890 | static const unsigned pu3_pins[] = { |
| 891 | TEGRA_PIN_PU3, |
| 892 | }; |
| 893 | |
| 894 | static const unsigned pu4_pins[] = { |
| 895 | TEGRA_PIN_PU4, |
| 896 | }; |
| 897 | |
| 898 | static const unsigned pu5_pins[] = { |
| 899 | TEGRA_PIN_PU5, |
| 900 | }; |
| 901 | |
| 902 | static const unsigned pu6_pins[] = { |
| 903 | TEGRA_PIN_PU6, |
| 904 | }; |
| 905 | |
| 906 | static const unsigned pv0_pins[] = { |
| 907 | TEGRA_PIN_PV0, |
| 908 | }; |
| 909 | |
| 910 | static const unsigned pv1_pins[] = { |
| 911 | TEGRA_PIN_PV1, |
| 912 | }; |
| 913 | |
| 914 | static const unsigned sdmmc3_cd_n_pv2_pins[] = { |
| 915 | TEGRA_PIN_SDMMC3_CD_N_PV2, |
| 916 | }; |
| 917 | |
| 918 | static const unsigned sdmmc1_wp_n_pv3_pins[] = { |
| 919 | TEGRA_PIN_SDMMC1_WP_N_PV3, |
| 920 | }; |
| 921 | |
| 922 | static const unsigned ddc_scl_pv4_pins[] = { |
| 923 | TEGRA_PIN_DDC_SCL_PV4, |
| 924 | }; |
| 925 | |
| 926 | static const unsigned ddc_sda_pv5_pins[] = { |
| 927 | TEGRA_PIN_DDC_SDA_PV5, |
| 928 | }; |
| 929 | |
| 930 | static const unsigned gpio_w2_aud_pw2_pins[] = { |
| 931 | TEGRA_PIN_GPIO_W2_AUD_PW2, |
| 932 | }; |
| 933 | |
| 934 | static const unsigned gpio_w3_aud_pw3_pins[] = { |
| 935 | TEGRA_PIN_GPIO_W3_AUD_PW3, |
| 936 | }; |
| 937 | |
| 938 | static const unsigned dap_mclk1_pw4_pins[] = { |
| 939 | TEGRA_PIN_DAP_MCLK1_PW4, |
| 940 | }; |
| 941 | |
| 942 | static const unsigned clk2_out_pw5_pins[] = { |
| 943 | TEGRA_PIN_CLK2_OUT_PW5, |
| 944 | }; |
| 945 | |
| 946 | static const unsigned uart3_txd_pw6_pins[] = { |
| 947 | TEGRA_PIN_UART3_TXD_PW6, |
| 948 | }; |
| 949 | |
| 950 | static const unsigned uart3_rxd_pw7_pins[] = { |
| 951 | TEGRA_PIN_UART3_RXD_PW7, |
| 952 | }; |
| 953 | |
| 954 | static const unsigned dvfs_pwm_px0_pins[] = { |
| 955 | TEGRA_PIN_DVFS_PWM_PX0, |
| 956 | }; |
| 957 | |
| 958 | static const unsigned gpio_x1_aud_px1_pins[] = { |
| 959 | TEGRA_PIN_GPIO_X1_AUD_PX1, |
| 960 | }; |
| 961 | |
| 962 | static const unsigned dvfs_clk_px2_pins[] = { |
| 963 | TEGRA_PIN_DVFS_CLK_PX2, |
| 964 | }; |
| 965 | |
| 966 | static const unsigned gpio_x3_aud_px3_pins[] = { |
| 967 | TEGRA_PIN_GPIO_X3_AUD_PX3, |
| 968 | }; |
| 969 | |
| 970 | static const unsigned gpio_x4_aud_px4_pins[] = { |
| 971 | TEGRA_PIN_GPIO_X4_AUD_PX4, |
| 972 | }; |
| 973 | |
| 974 | static const unsigned gpio_x5_aud_px5_pins[] = { |
| 975 | TEGRA_PIN_GPIO_X5_AUD_PX5, |
| 976 | }; |
| 977 | |
| 978 | static const unsigned gpio_x6_aud_px6_pins[] = { |
| 979 | TEGRA_PIN_GPIO_X6_AUD_PX6, |
| 980 | }; |
| 981 | |
| 982 | static const unsigned gpio_x7_aud_px7_pins[] = { |
| 983 | TEGRA_PIN_GPIO_X7_AUD_PX7, |
| 984 | }; |
| 985 | |
| 986 | static const unsigned ulpi_clk_py0_pins[] = { |
| 987 | TEGRA_PIN_ULPI_CLK_PY0, |
| 988 | }; |
| 989 | |
| 990 | static const unsigned ulpi_dir_py1_pins[] = { |
| 991 | TEGRA_PIN_ULPI_DIR_PY1, |
| 992 | }; |
| 993 | |
| 994 | static const unsigned ulpi_nxt_py2_pins[] = { |
| 995 | TEGRA_PIN_ULPI_NXT_PY2, |
| 996 | }; |
| 997 | |
| 998 | static const unsigned ulpi_stp_py3_pins[] = { |
| 999 | TEGRA_PIN_ULPI_STP_PY3, |
| 1000 | }; |
| 1001 | |
| 1002 | static const unsigned sdmmc1_dat3_py4_pins[] = { |
| 1003 | TEGRA_PIN_SDMMC1_DAT3_PY4, |
| 1004 | }; |
| 1005 | |
| 1006 | static const unsigned sdmmc1_dat2_py5_pins[] = { |
| 1007 | TEGRA_PIN_SDMMC1_DAT2_PY5, |
| 1008 | }; |
| 1009 | |
| 1010 | static const unsigned sdmmc1_dat1_py6_pins[] = { |
| 1011 | TEGRA_PIN_SDMMC1_DAT1_PY6, |
| 1012 | }; |
| 1013 | |
| 1014 | static const unsigned sdmmc1_dat0_py7_pins[] = { |
| 1015 | TEGRA_PIN_SDMMC1_DAT0_PY7, |
| 1016 | }; |
| 1017 | |
| 1018 | static const unsigned sdmmc1_clk_pz0_pins[] = { |
| 1019 | TEGRA_PIN_SDMMC1_CLK_PZ0, |
| 1020 | }; |
| 1021 | |
| 1022 | static const unsigned sdmmc1_cmd_pz1_pins[] = { |
| 1023 | TEGRA_PIN_SDMMC1_CMD_PZ1, |
| 1024 | }; |
| 1025 | |
| 1026 | static const unsigned pwr_i2c_scl_pz6_pins[] = { |
| 1027 | TEGRA_PIN_PWR_I2C_SCL_PZ6, |
| 1028 | }; |
| 1029 | |
| 1030 | static const unsigned pwr_i2c_sda_pz7_pins[] = { |
| 1031 | TEGRA_PIN_PWR_I2C_SDA_PZ7, |
| 1032 | }; |
| 1033 | |
| 1034 | static const unsigned sdmmc4_dat0_paa0_pins[] = { |
| 1035 | TEGRA_PIN_SDMMC4_DAT0_PAA0, |
| 1036 | }; |
| 1037 | |
| 1038 | static const unsigned sdmmc4_dat1_paa1_pins[] = { |
| 1039 | TEGRA_PIN_SDMMC4_DAT1_PAA1, |
| 1040 | }; |
| 1041 | |
| 1042 | static const unsigned sdmmc4_dat2_paa2_pins[] = { |
| 1043 | TEGRA_PIN_SDMMC4_DAT2_PAA2, |
| 1044 | }; |
| 1045 | |
| 1046 | static const unsigned sdmmc4_dat3_paa3_pins[] = { |
| 1047 | TEGRA_PIN_SDMMC4_DAT3_PAA3, |
| 1048 | }; |
| 1049 | |
| 1050 | static const unsigned sdmmc4_dat4_paa4_pins[] = { |
| 1051 | TEGRA_PIN_SDMMC4_DAT4_PAA4, |
| 1052 | }; |
| 1053 | |
| 1054 | static const unsigned sdmmc4_dat5_paa5_pins[] = { |
| 1055 | TEGRA_PIN_SDMMC4_DAT5_PAA5, |
| 1056 | }; |
| 1057 | |
| 1058 | static const unsigned sdmmc4_dat6_paa6_pins[] = { |
| 1059 | TEGRA_PIN_SDMMC4_DAT6_PAA6, |
| 1060 | }; |
| 1061 | |
| 1062 | static const unsigned sdmmc4_dat7_paa7_pins[] = { |
| 1063 | TEGRA_PIN_SDMMC4_DAT7_PAA7, |
| 1064 | }; |
| 1065 | |
| 1066 | static const unsigned pbb0_pins[] = { |
| 1067 | TEGRA_PIN_PBB0, |
| 1068 | }; |
| 1069 | |
| 1070 | static const unsigned cam_i2c_scl_pbb1_pins[] = { |
| 1071 | TEGRA_PIN_CAM_I2C_SCL_PBB1, |
| 1072 | }; |
| 1073 | |
| 1074 | static const unsigned cam_i2c_sda_pbb2_pins[] = { |
| 1075 | TEGRA_PIN_CAM_I2C_SDA_PBB2, |
| 1076 | }; |
| 1077 | |
| 1078 | static const unsigned pbb3_pins[] = { |
| 1079 | TEGRA_PIN_PBB3, |
| 1080 | }; |
| 1081 | |
| 1082 | static const unsigned pbb4_pins[] = { |
| 1083 | TEGRA_PIN_PBB4, |
| 1084 | }; |
| 1085 | |
| 1086 | static const unsigned pbb5_pins[] = { |
| 1087 | TEGRA_PIN_PBB5, |
| 1088 | }; |
| 1089 | |
| 1090 | static const unsigned pbb6_pins[] = { |
| 1091 | TEGRA_PIN_PBB6, |
| 1092 | }; |
| 1093 | |
| 1094 | static const unsigned pbb7_pins[] = { |
| 1095 | TEGRA_PIN_PBB7, |
| 1096 | }; |
| 1097 | |
| 1098 | static const unsigned cam_mclk_pcc0_pins[] = { |
| 1099 | TEGRA_PIN_CAM_MCLK_PCC0, |
| 1100 | }; |
| 1101 | |
| 1102 | static const unsigned pcc1_pins[] = { |
| 1103 | TEGRA_PIN_PCC1, |
| 1104 | }; |
| 1105 | |
| 1106 | static const unsigned pcc2_pins[] = { |
| 1107 | TEGRA_PIN_PCC2, |
| 1108 | }; |
| 1109 | |
| 1110 | static const unsigned sdmmc4_clk_pcc4_pins[] = { |
| 1111 | TEGRA_PIN_SDMMC4_CLK_PCC4, |
| 1112 | }; |
| 1113 | |
| 1114 | static const unsigned clk2_req_pcc5_pins[] = { |
| 1115 | TEGRA_PIN_CLK2_REQ_PCC5, |
| 1116 | }; |
| 1117 | |
| 1118 | static const unsigned pex_l0_rst_n_pdd1_pins[] = { |
| 1119 | TEGRA_PIN_PEX_L0_RST_N_PDD1, |
| 1120 | }; |
| 1121 | |
| 1122 | static const unsigned pex_l0_clkreq_n_pdd2_pins[] = { |
| 1123 | TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, |
| 1124 | }; |
| 1125 | |
| 1126 | static const unsigned pex_wake_n_pdd3_pins[] = { |
| 1127 | TEGRA_PIN_PEX_WAKE_N_PDD3, |
| 1128 | }; |
| 1129 | |
| 1130 | static const unsigned pex_l1_rst_n_pdd5_pins[] = { |
| 1131 | TEGRA_PIN_PEX_L1_RST_N_PDD5, |
| 1132 | }; |
| 1133 | |
| 1134 | static const unsigned pex_l1_clkreq_n_pdd6_pins[] = { |
| 1135 | TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, |
| 1136 | }; |
| 1137 | |
| 1138 | static const unsigned clk3_out_pee0_pins[] = { |
| 1139 | TEGRA_PIN_CLK3_OUT_PEE0, |
| 1140 | }; |
| 1141 | |
| 1142 | static const unsigned clk3_req_pee1_pins[] = { |
| 1143 | TEGRA_PIN_CLK3_REQ_PEE1, |
| 1144 | }; |
| 1145 | |
| 1146 | static const unsigned dap_mclk1_req_pee2_pins[] = { |
| 1147 | TEGRA_PIN_DAP_MCLK1_REQ_PEE2, |
| 1148 | }; |
| 1149 | |
| 1150 | static const unsigned hdmi_cec_pee3_pins[] = { |
| 1151 | TEGRA_PIN_HDMI_CEC_PEE3, |
| 1152 | }; |
| 1153 | |
| 1154 | static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = { |
| 1155 | TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, |
| 1156 | }; |
| 1157 | |
| 1158 | static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = { |
| 1159 | TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, |
| 1160 | }; |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1161 | |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1162 | static const unsigned dp_hpd_pff0_pins[] = { |
| 1163 | TEGRA_PIN_DP_HPD_PFF0, |
| 1164 | }; |
| 1165 | |
| 1166 | static const unsigned usb_vbus_en2_pff1_pins[] = { |
| 1167 | TEGRA_PIN_USB_VBUS_EN2_PFF1, |
| 1168 | }; |
| 1169 | |
| 1170 | static const unsigned pff2_pins[] = { |
| 1171 | TEGRA_PIN_PFF2, |
| 1172 | }; |
| 1173 | |
| 1174 | static const unsigned core_pwr_req_pins[] = { |
| 1175 | TEGRA_PIN_CORE_PWR_REQ, |
| 1176 | }; |
| 1177 | |
| 1178 | static const unsigned cpu_pwr_req_pins[] = { |
| 1179 | TEGRA_PIN_CPU_PWR_REQ, |
| 1180 | }; |
| 1181 | |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1182 | static const unsigned pwr_int_n_pins[] = { |
| 1183 | TEGRA_PIN_PWR_INT_N, |
| 1184 | }; |
| 1185 | |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1186 | static const unsigned gmi_clk_lb_pins[] = { |
| 1187 | TEGRA_PIN_GMI_CLK_LB, |
| 1188 | }; |
| 1189 | |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1190 | static const unsigned reset_out_n_pins[] = { |
| 1191 | TEGRA_PIN_RESET_OUT_N, |
| 1192 | }; |
| 1193 | |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1194 | static const unsigned owr_pins[] = { |
| 1195 | TEGRA_PIN_OWR, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1196 | }; |
| 1197 | |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1198 | static const unsigned clk_32k_in_pins[] = { |
| 1199 | TEGRA_PIN_CLK_32K_IN, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1200 | }; |
| 1201 | |
| 1202 | static const unsigned jtag_rtck_pins[] = { |
| 1203 | TEGRA_PIN_JTAG_RTCK, |
| 1204 | }; |
| 1205 | |
| 1206 | static const unsigned drive_ao1_pins[] = { |
| 1207 | TEGRA_PIN_KB_ROW0_PR0, |
| 1208 | TEGRA_PIN_KB_ROW1_PR1, |
| 1209 | TEGRA_PIN_KB_ROW2_PR2, |
| 1210 | TEGRA_PIN_KB_ROW3_PR3, |
| 1211 | TEGRA_PIN_KB_ROW4_PR4, |
| 1212 | TEGRA_PIN_KB_ROW5_PR5, |
| 1213 | TEGRA_PIN_KB_ROW6_PR6, |
| 1214 | TEGRA_PIN_KB_ROW7_PR7, |
| 1215 | TEGRA_PIN_PWR_I2C_SCL_PZ6, |
| 1216 | TEGRA_PIN_PWR_I2C_SDA_PZ7, |
| 1217 | }; |
| 1218 | |
| 1219 | static const unsigned drive_ao2_pins[] = { |
| 1220 | TEGRA_PIN_CLK_32K_OUT_PA0, |
| 1221 | TEGRA_PIN_CLK_32K_IN, |
| 1222 | TEGRA_PIN_KB_COL0_PQ0, |
| 1223 | TEGRA_PIN_KB_COL1_PQ1, |
| 1224 | TEGRA_PIN_KB_COL2_PQ2, |
| 1225 | TEGRA_PIN_KB_COL3_PQ3, |
| 1226 | TEGRA_PIN_KB_COL4_PQ4, |
| 1227 | TEGRA_PIN_KB_COL5_PQ5, |
| 1228 | TEGRA_PIN_KB_COL6_PQ6, |
| 1229 | TEGRA_PIN_KB_COL7_PQ7, |
| 1230 | TEGRA_PIN_KB_ROW8_PS0, |
| 1231 | TEGRA_PIN_KB_ROW9_PS1, |
| 1232 | TEGRA_PIN_KB_ROW10_PS2, |
| 1233 | TEGRA_PIN_KB_ROW11_PS3, |
| 1234 | TEGRA_PIN_KB_ROW12_PS4, |
| 1235 | TEGRA_PIN_KB_ROW13_PS5, |
| 1236 | TEGRA_PIN_KB_ROW14_PS6, |
| 1237 | TEGRA_PIN_KB_ROW15_PS7, |
| 1238 | TEGRA_PIN_KB_ROW16_PT0, |
| 1239 | TEGRA_PIN_KB_ROW17_PT1, |
| 1240 | TEGRA_PIN_SDMMC3_CD_N_PV2, |
| 1241 | TEGRA_PIN_CORE_PWR_REQ, |
| 1242 | TEGRA_PIN_CPU_PWR_REQ, |
| 1243 | TEGRA_PIN_PWR_INT_N, |
| 1244 | }; |
| 1245 | |
| 1246 | static const unsigned drive_at1_pins[] = { |
| 1247 | TEGRA_PIN_PH0, |
| 1248 | TEGRA_PIN_PH1, |
| 1249 | TEGRA_PIN_PH2, |
| 1250 | TEGRA_PIN_PH3, |
| 1251 | }; |
| 1252 | |
| 1253 | static const unsigned drive_at2_pins[] = { |
| 1254 | TEGRA_PIN_PG0, |
| 1255 | TEGRA_PIN_PG1, |
| 1256 | TEGRA_PIN_PG2, |
| 1257 | TEGRA_PIN_PG3, |
| 1258 | TEGRA_PIN_PG4, |
| 1259 | TEGRA_PIN_PG5, |
| 1260 | TEGRA_PIN_PG6, |
| 1261 | TEGRA_PIN_PG7, |
| 1262 | TEGRA_PIN_PI0, |
| 1263 | TEGRA_PIN_PI1, |
| 1264 | TEGRA_PIN_PI3, |
| 1265 | TEGRA_PIN_PI4, |
| 1266 | TEGRA_PIN_PI7, |
| 1267 | TEGRA_PIN_PK0, |
| 1268 | TEGRA_PIN_PK2, |
| 1269 | }; |
| 1270 | |
| 1271 | static const unsigned drive_at3_pins[] = { |
| 1272 | TEGRA_PIN_PC7, |
| 1273 | TEGRA_PIN_PJ0, |
| 1274 | }; |
| 1275 | |
| 1276 | static const unsigned drive_at4_pins[] = { |
| 1277 | TEGRA_PIN_PB0, |
| 1278 | TEGRA_PIN_PB1, |
| 1279 | TEGRA_PIN_PJ0, |
| 1280 | TEGRA_PIN_PJ7, |
| 1281 | TEGRA_PIN_PK7, |
| 1282 | }; |
| 1283 | |
| 1284 | static const unsigned drive_at5_pins[] = { |
| 1285 | TEGRA_PIN_GEN2_I2C_SCL_PT5, |
| 1286 | TEGRA_PIN_GEN2_I2C_SDA_PT6, |
| 1287 | }; |
| 1288 | |
| 1289 | static const unsigned drive_cdev1_pins[] = { |
| 1290 | TEGRA_PIN_DAP_MCLK1_PW4, |
| 1291 | TEGRA_PIN_DAP_MCLK1_REQ_PEE2, |
| 1292 | }; |
| 1293 | |
| 1294 | static const unsigned drive_cdev2_pins[] = { |
| 1295 | TEGRA_PIN_CLK2_OUT_PW5, |
| 1296 | TEGRA_PIN_CLK2_REQ_PCC5, |
| 1297 | }; |
| 1298 | |
| 1299 | static const unsigned drive_dap1_pins[] = { |
| 1300 | TEGRA_PIN_DAP1_FS_PN0, |
| 1301 | TEGRA_PIN_DAP1_DIN_PN1, |
| 1302 | TEGRA_PIN_DAP1_DOUT_PN2, |
| 1303 | TEGRA_PIN_DAP1_SCLK_PN3, |
| 1304 | }; |
| 1305 | |
| 1306 | static const unsigned drive_dap2_pins[] = { |
| 1307 | TEGRA_PIN_DAP2_FS_PA2, |
| 1308 | TEGRA_PIN_DAP2_SCLK_PA3, |
| 1309 | TEGRA_PIN_DAP2_DIN_PA4, |
| 1310 | TEGRA_PIN_DAP2_DOUT_PA5, |
| 1311 | }; |
| 1312 | |
| 1313 | static const unsigned drive_dap3_pins[] = { |
| 1314 | TEGRA_PIN_DAP3_FS_PP0, |
| 1315 | TEGRA_PIN_DAP3_DIN_PP1, |
| 1316 | TEGRA_PIN_DAP3_DOUT_PP2, |
| 1317 | TEGRA_PIN_DAP3_SCLK_PP3, |
| 1318 | }; |
| 1319 | |
| 1320 | static const unsigned drive_dap4_pins[] = { |
| 1321 | TEGRA_PIN_DAP4_FS_PP4, |
| 1322 | TEGRA_PIN_DAP4_DIN_PP5, |
| 1323 | TEGRA_PIN_DAP4_DOUT_PP6, |
| 1324 | TEGRA_PIN_DAP4_SCLK_PP7, |
| 1325 | }; |
| 1326 | |
| 1327 | static const unsigned drive_dbg_pins[] = { |
| 1328 | TEGRA_PIN_GEN1_I2C_SCL_PC4, |
| 1329 | TEGRA_PIN_GEN1_I2C_SDA_PC5, |
| 1330 | TEGRA_PIN_PU0, |
| 1331 | TEGRA_PIN_PU1, |
| 1332 | TEGRA_PIN_PU2, |
| 1333 | TEGRA_PIN_PU3, |
| 1334 | TEGRA_PIN_PU4, |
| 1335 | TEGRA_PIN_PU5, |
| 1336 | TEGRA_PIN_PU6, |
| 1337 | }; |
| 1338 | |
| 1339 | static const unsigned drive_sdio3_pins[] = { |
| 1340 | TEGRA_PIN_SDMMC3_CLK_PA6, |
| 1341 | TEGRA_PIN_SDMMC3_CMD_PA7, |
| 1342 | TEGRA_PIN_SDMMC3_DAT3_PB4, |
| 1343 | TEGRA_PIN_SDMMC3_DAT2_PB5, |
| 1344 | TEGRA_PIN_SDMMC3_DAT1_PB6, |
| 1345 | TEGRA_PIN_SDMMC3_DAT0_PB7, |
| 1346 | TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, |
| 1347 | TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, |
| 1348 | }; |
| 1349 | |
| 1350 | static const unsigned drive_spi_pins[] = { |
| 1351 | TEGRA_PIN_DVFS_PWM_PX0, |
| 1352 | TEGRA_PIN_GPIO_X1_AUD_PX1, |
| 1353 | TEGRA_PIN_DVFS_CLK_PX2, |
| 1354 | TEGRA_PIN_GPIO_X3_AUD_PX3, |
| 1355 | TEGRA_PIN_GPIO_X4_AUD_PX4, |
| 1356 | TEGRA_PIN_GPIO_X5_AUD_PX5, |
| 1357 | TEGRA_PIN_GPIO_X6_AUD_PX6, |
| 1358 | TEGRA_PIN_GPIO_X7_AUD_PX7, |
| 1359 | TEGRA_PIN_GPIO_W2_AUD_PW2, |
| 1360 | TEGRA_PIN_GPIO_W3_AUD_PW3, |
| 1361 | }; |
| 1362 | |
| 1363 | static const unsigned drive_uaa_pins[] = { |
| 1364 | TEGRA_PIN_ULPI_DATA0_PO1, |
| 1365 | TEGRA_PIN_ULPI_DATA1_PO2, |
| 1366 | TEGRA_PIN_ULPI_DATA2_PO3, |
| 1367 | TEGRA_PIN_ULPI_DATA3_PO4, |
| 1368 | }; |
| 1369 | |
| 1370 | static const unsigned drive_uab_pins[] = { |
| 1371 | TEGRA_PIN_ULPI_DATA7_PO0, |
| 1372 | TEGRA_PIN_ULPI_DATA4_PO5, |
| 1373 | TEGRA_PIN_ULPI_DATA5_PO6, |
| 1374 | TEGRA_PIN_ULPI_DATA6_PO7, |
| 1375 | TEGRA_PIN_PV0, |
| 1376 | TEGRA_PIN_PV1, |
| 1377 | }; |
| 1378 | |
| 1379 | static const unsigned drive_uart2_pins[] = { |
| 1380 | TEGRA_PIN_UART2_TXD_PC2, |
| 1381 | TEGRA_PIN_UART2_RXD_PC3, |
| 1382 | TEGRA_PIN_UART2_CTS_N_PJ5, |
| 1383 | TEGRA_PIN_UART2_RTS_N_PJ6, |
| 1384 | }; |
| 1385 | |
| 1386 | static const unsigned drive_uart3_pins[] = { |
| 1387 | TEGRA_PIN_UART3_CTS_N_PA1, |
| 1388 | TEGRA_PIN_UART3_RTS_N_PC0, |
| 1389 | TEGRA_PIN_UART3_TXD_PW6, |
| 1390 | TEGRA_PIN_UART3_RXD_PW7, |
| 1391 | }; |
| 1392 | |
| 1393 | static const unsigned drive_sdio1_pins[] = { |
| 1394 | TEGRA_PIN_SDMMC1_DAT3_PY4, |
| 1395 | TEGRA_PIN_SDMMC1_DAT2_PY5, |
| 1396 | TEGRA_PIN_SDMMC1_DAT1_PY6, |
| 1397 | TEGRA_PIN_SDMMC1_DAT0_PY7, |
| 1398 | TEGRA_PIN_SDMMC1_CLK_PZ0, |
| 1399 | TEGRA_PIN_SDMMC1_CMD_PZ1, |
| 1400 | }; |
| 1401 | |
| 1402 | static const unsigned drive_ddc_pins[] = { |
| 1403 | TEGRA_PIN_DDC_SCL_PV4, |
| 1404 | TEGRA_PIN_DDC_SDA_PV5, |
| 1405 | }; |
| 1406 | |
| 1407 | static const unsigned drive_gma_pins[] = { |
| 1408 | TEGRA_PIN_SDMMC4_CLK_PCC4, |
| 1409 | TEGRA_PIN_SDMMC4_CMD_PT7, |
| 1410 | TEGRA_PIN_SDMMC4_DAT0_PAA0, |
| 1411 | TEGRA_PIN_SDMMC4_DAT1_PAA1, |
| 1412 | TEGRA_PIN_SDMMC4_DAT2_PAA2, |
| 1413 | TEGRA_PIN_SDMMC4_DAT3_PAA3, |
| 1414 | TEGRA_PIN_SDMMC4_DAT4_PAA4, |
| 1415 | TEGRA_PIN_SDMMC4_DAT5_PAA5, |
| 1416 | TEGRA_PIN_SDMMC4_DAT6_PAA6, |
| 1417 | TEGRA_PIN_SDMMC4_DAT7_PAA7, |
| 1418 | }; |
| 1419 | |
| 1420 | static const unsigned drive_gme_pins[] = { |
| 1421 | TEGRA_PIN_PBB0, |
| 1422 | TEGRA_PIN_CAM_I2C_SCL_PBB1, |
| 1423 | TEGRA_PIN_CAM_I2C_SDA_PBB2, |
| 1424 | TEGRA_PIN_PBB3, |
| 1425 | TEGRA_PIN_PCC2, |
| 1426 | }; |
| 1427 | |
| 1428 | static const unsigned drive_gmf_pins[] = { |
| 1429 | TEGRA_PIN_PBB4, |
| 1430 | TEGRA_PIN_PBB5, |
| 1431 | TEGRA_PIN_PBB6, |
| 1432 | TEGRA_PIN_PBB7, |
| 1433 | }; |
| 1434 | |
| 1435 | static const unsigned drive_gmg_pins[] = { |
| 1436 | TEGRA_PIN_CAM_MCLK_PCC0, |
| 1437 | }; |
| 1438 | |
| 1439 | static const unsigned drive_gmh_pins[] = { |
| 1440 | TEGRA_PIN_PCC1, |
| 1441 | }; |
| 1442 | |
| 1443 | static const unsigned drive_owr_pins[] = { |
| 1444 | TEGRA_PIN_SDMMC3_CD_N_PV2, |
| 1445 | TEGRA_PIN_OWR, |
| 1446 | }; |
| 1447 | |
| 1448 | static const unsigned drive_uda_pins[] = { |
| 1449 | TEGRA_PIN_ULPI_CLK_PY0, |
| 1450 | TEGRA_PIN_ULPI_DIR_PY1, |
| 1451 | TEGRA_PIN_ULPI_NXT_PY2, |
| 1452 | TEGRA_PIN_ULPI_STP_PY3, |
| 1453 | }; |
| 1454 | |
| 1455 | static const unsigned drive_gpv_pins[] = { |
| 1456 | TEGRA_PIN_PEX_L0_RST_N_PDD1, |
| 1457 | TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, |
| 1458 | TEGRA_PIN_PEX_WAKE_N_PDD3, |
| 1459 | TEGRA_PIN_PEX_L1_RST_N_PDD5, |
| 1460 | TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, |
| 1461 | TEGRA_PIN_USB_VBUS_EN2_PFF1, |
| 1462 | TEGRA_PIN_PFF2, |
| 1463 | }; |
| 1464 | |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1465 | static const unsigned drive_dev3_pins[] = { |
| 1466 | TEGRA_PIN_CLK3_OUT_PEE0, |
| 1467 | TEGRA_PIN_CLK3_REQ_PEE1, |
| 1468 | }; |
| 1469 | |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1470 | static const unsigned drive_cec_pins[] = { |
| 1471 | TEGRA_PIN_HDMI_CEC_PEE3, |
| 1472 | }; |
| 1473 | |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1474 | static const unsigned drive_at6_pins[] = { |
| 1475 | TEGRA_PIN_PK1, |
| 1476 | TEGRA_PIN_PK3, |
| 1477 | TEGRA_PIN_PK4, |
| 1478 | TEGRA_PIN_PI2, |
| 1479 | TEGRA_PIN_PI5, |
| 1480 | TEGRA_PIN_PI6, |
| 1481 | TEGRA_PIN_PH4, |
| 1482 | TEGRA_PIN_PH5, |
| 1483 | TEGRA_PIN_PH6, |
| 1484 | TEGRA_PIN_PH7, |
| 1485 | }; |
| 1486 | |
| 1487 | static const unsigned drive_dap5_pins[] = { |
| 1488 | TEGRA_PIN_SPDIF_IN_PK6, |
| 1489 | TEGRA_PIN_SPDIF_OUT_PK5, |
| 1490 | TEGRA_PIN_DP_HPD_PFF0, |
| 1491 | }; |
| 1492 | |
| 1493 | static const unsigned drive_usb_vbus_en_pins[] = { |
| 1494 | TEGRA_PIN_USB_VBUS_EN0_PN4, |
| 1495 | TEGRA_PIN_USB_VBUS_EN1_PN5, |
| 1496 | }; |
| 1497 | |
| 1498 | static const unsigned drive_ao3_pins[] = { |
| 1499 | TEGRA_PIN_RESET_OUT_N, |
| 1500 | }; |
| 1501 | |
| 1502 | static const unsigned drive_ao0_pins[] = { |
| 1503 | TEGRA_PIN_JTAG_RTCK, |
| 1504 | }; |
| 1505 | |
| 1506 | static const unsigned drive_hv0_pins[] = { |
| 1507 | TEGRA_PIN_HDMI_INT_PN7, |
| 1508 | }; |
| 1509 | |
| 1510 | static const unsigned drive_sdio4_pins[] = { |
| 1511 | TEGRA_PIN_SDMMC1_WP_N_PV3, |
| 1512 | }; |
| 1513 | |
| 1514 | static const unsigned drive_ao4_pins[] = { |
| 1515 | TEGRA_PIN_JTAG_RTCK, |
| 1516 | }; |
| 1517 | |
Sean Paul | 3ccc11f | 2014-09-09 15:58:45 -0400 | [diff] [blame] | 1518 | static const unsigned mipi_pad_ctrl_dsi_b_pins[] = { |
| 1519 | TEGRA_PIN_DSI_B_CLK_P, |
| 1520 | TEGRA_PIN_DSI_B_CLK_N, |
| 1521 | TEGRA_PIN_DSI_B_D0_P, |
| 1522 | TEGRA_PIN_DSI_B_D0_N, |
| 1523 | TEGRA_PIN_DSI_B_D1_P, |
| 1524 | TEGRA_PIN_DSI_B_D1_N, |
| 1525 | TEGRA_PIN_DSI_B_D2_P, |
| 1526 | TEGRA_PIN_DSI_B_D2_N, |
| 1527 | TEGRA_PIN_DSI_B_D3_P, |
| 1528 | TEGRA_PIN_DSI_B_D3_N, |
| 1529 | }; |
| 1530 | |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1531 | enum tegra_mux { |
| 1532 | TEGRA_MUX_BLINK, |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1533 | TEGRA_MUX_CCLA, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1534 | TEGRA_MUX_CEC, |
| 1535 | TEGRA_MUX_CLDVFS, |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1536 | TEGRA_MUX_CLK, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1537 | TEGRA_MUX_CLK12, |
| 1538 | TEGRA_MUX_CPU, |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1539 | TEGRA_MUX_CSI, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1540 | TEGRA_MUX_DAP, |
| 1541 | TEGRA_MUX_DAP1, |
| 1542 | TEGRA_MUX_DAP2, |
| 1543 | TEGRA_MUX_DEV3, |
| 1544 | TEGRA_MUX_DISPLAYA, |
| 1545 | TEGRA_MUX_DISPLAYA_ALT, |
| 1546 | TEGRA_MUX_DISPLAYB, |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1547 | TEGRA_MUX_DP, |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1548 | TEGRA_MUX_DSI_B, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1549 | TEGRA_MUX_DTV, |
| 1550 | TEGRA_MUX_EXTPERIPH1, |
| 1551 | TEGRA_MUX_EXTPERIPH2, |
| 1552 | TEGRA_MUX_EXTPERIPH3, |
| 1553 | TEGRA_MUX_GMI, |
| 1554 | TEGRA_MUX_GMI_ALT, |
| 1555 | TEGRA_MUX_HDA, |
| 1556 | TEGRA_MUX_HSI, |
| 1557 | TEGRA_MUX_I2C1, |
| 1558 | TEGRA_MUX_I2C2, |
| 1559 | TEGRA_MUX_I2C3, |
| 1560 | TEGRA_MUX_I2C4, |
| 1561 | TEGRA_MUX_I2CPWR, |
| 1562 | TEGRA_MUX_I2S0, |
| 1563 | TEGRA_MUX_I2S1, |
| 1564 | TEGRA_MUX_I2S2, |
| 1565 | TEGRA_MUX_I2S3, |
| 1566 | TEGRA_MUX_I2S4, |
| 1567 | TEGRA_MUX_IRDA, |
| 1568 | TEGRA_MUX_KBC, |
| 1569 | TEGRA_MUX_OWR, |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1570 | TEGRA_MUX_PE, |
| 1571 | TEGRA_MUX_PE0, |
| 1572 | TEGRA_MUX_PE1, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1573 | TEGRA_MUX_PMI, |
| 1574 | TEGRA_MUX_PWM0, |
| 1575 | TEGRA_MUX_PWM1, |
| 1576 | TEGRA_MUX_PWM2, |
| 1577 | TEGRA_MUX_PWM3, |
| 1578 | TEGRA_MUX_PWRON, |
| 1579 | TEGRA_MUX_RESET_OUT_N, |
| 1580 | TEGRA_MUX_RSVD1, |
| 1581 | TEGRA_MUX_RSVD2, |
| 1582 | TEGRA_MUX_RSVD3, |
| 1583 | TEGRA_MUX_RSVD4, |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1584 | TEGRA_MUX_RTCK, |
| 1585 | TEGRA_MUX_SATA, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1586 | TEGRA_MUX_SDMMC1, |
| 1587 | TEGRA_MUX_SDMMC2, |
| 1588 | TEGRA_MUX_SDMMC3, |
| 1589 | TEGRA_MUX_SDMMC4, |
| 1590 | TEGRA_MUX_SOC, |
| 1591 | TEGRA_MUX_SPDIF, |
| 1592 | TEGRA_MUX_SPI1, |
| 1593 | TEGRA_MUX_SPI2, |
| 1594 | TEGRA_MUX_SPI3, |
| 1595 | TEGRA_MUX_SPI4, |
| 1596 | TEGRA_MUX_SPI5, |
| 1597 | TEGRA_MUX_SPI6, |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1598 | TEGRA_MUX_SYS, |
| 1599 | TEGRA_MUX_TMDS, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1600 | TEGRA_MUX_TRACE, |
| 1601 | TEGRA_MUX_UARTA, |
| 1602 | TEGRA_MUX_UARTB, |
| 1603 | TEGRA_MUX_UARTC, |
| 1604 | TEGRA_MUX_UARTD, |
| 1605 | TEGRA_MUX_ULPI, |
| 1606 | TEGRA_MUX_USB, |
| 1607 | TEGRA_MUX_VGP1, |
| 1608 | TEGRA_MUX_VGP2, |
| 1609 | TEGRA_MUX_VGP3, |
| 1610 | TEGRA_MUX_VGP4, |
| 1611 | TEGRA_MUX_VGP5, |
| 1612 | TEGRA_MUX_VGP6, |
| 1613 | TEGRA_MUX_VI, |
| 1614 | TEGRA_MUX_VI_ALT1, |
| 1615 | TEGRA_MUX_VI_ALT3, |
| 1616 | TEGRA_MUX_VIMCLK2, |
| 1617 | TEGRA_MUX_VIMCLK2_ALT, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1618 | }; |
| 1619 | |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1620 | #define FUNCTION(fname) \ |
| 1621 | { \ |
| 1622 | .name = #fname, \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1623 | } |
| 1624 | |
Stephen Warren | ce43625 | 2014-03-07 12:22:16 -0700 | [diff] [blame] | 1625 | static struct tegra_function tegra124_functions[] = { |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1626 | FUNCTION(blink), |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1627 | FUNCTION(ccla), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1628 | FUNCTION(cec), |
| 1629 | FUNCTION(cldvfs), |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1630 | FUNCTION(clk), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1631 | FUNCTION(clk12), |
| 1632 | FUNCTION(cpu), |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1633 | FUNCTION(csi), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1634 | FUNCTION(dap), |
| 1635 | FUNCTION(dap1), |
| 1636 | FUNCTION(dap2), |
| 1637 | FUNCTION(dev3), |
| 1638 | FUNCTION(displaya), |
| 1639 | FUNCTION(displaya_alt), |
| 1640 | FUNCTION(displayb), |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1641 | FUNCTION(dp), |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1642 | FUNCTION(dsi_b), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1643 | FUNCTION(dtv), |
| 1644 | FUNCTION(extperiph1), |
| 1645 | FUNCTION(extperiph2), |
| 1646 | FUNCTION(extperiph3), |
| 1647 | FUNCTION(gmi), |
| 1648 | FUNCTION(gmi_alt), |
| 1649 | FUNCTION(hda), |
| 1650 | FUNCTION(hsi), |
| 1651 | FUNCTION(i2c1), |
| 1652 | FUNCTION(i2c2), |
| 1653 | FUNCTION(i2c3), |
| 1654 | FUNCTION(i2c4), |
| 1655 | FUNCTION(i2cpwr), |
| 1656 | FUNCTION(i2s0), |
| 1657 | FUNCTION(i2s1), |
| 1658 | FUNCTION(i2s2), |
| 1659 | FUNCTION(i2s3), |
| 1660 | FUNCTION(i2s4), |
| 1661 | FUNCTION(irda), |
| 1662 | FUNCTION(kbc), |
| 1663 | FUNCTION(owr), |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1664 | FUNCTION(pe), |
| 1665 | FUNCTION(pe0), |
| 1666 | FUNCTION(pe1), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1667 | FUNCTION(pmi), |
| 1668 | FUNCTION(pwm0), |
| 1669 | FUNCTION(pwm1), |
| 1670 | FUNCTION(pwm2), |
| 1671 | FUNCTION(pwm3), |
| 1672 | FUNCTION(pwron), |
| 1673 | FUNCTION(reset_out_n), |
| 1674 | FUNCTION(rsvd1), |
| 1675 | FUNCTION(rsvd2), |
| 1676 | FUNCTION(rsvd3), |
| 1677 | FUNCTION(rsvd4), |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1678 | FUNCTION(rtck), |
| 1679 | FUNCTION(sata), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1680 | FUNCTION(sdmmc1), |
| 1681 | FUNCTION(sdmmc2), |
| 1682 | FUNCTION(sdmmc3), |
| 1683 | FUNCTION(sdmmc4), |
| 1684 | FUNCTION(soc), |
| 1685 | FUNCTION(spdif), |
| 1686 | FUNCTION(spi1), |
| 1687 | FUNCTION(spi2), |
| 1688 | FUNCTION(spi3), |
| 1689 | FUNCTION(spi4), |
| 1690 | FUNCTION(spi5), |
| 1691 | FUNCTION(spi6), |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1692 | FUNCTION(sys), |
| 1693 | FUNCTION(tmds), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1694 | FUNCTION(trace), |
| 1695 | FUNCTION(uarta), |
| 1696 | FUNCTION(uartb), |
| 1697 | FUNCTION(uartc), |
| 1698 | FUNCTION(uartd), |
| 1699 | FUNCTION(ulpi), |
| 1700 | FUNCTION(usb), |
| 1701 | FUNCTION(vgp1), |
| 1702 | FUNCTION(vgp2), |
| 1703 | FUNCTION(vgp3), |
| 1704 | FUNCTION(vgp4), |
| 1705 | FUNCTION(vgp5), |
| 1706 | FUNCTION(vgp6), |
| 1707 | FUNCTION(vi), |
| 1708 | FUNCTION(vi_alt1), |
| 1709 | FUNCTION(vi_alt3), |
| 1710 | FUNCTION(vimclk2), |
| 1711 | FUNCTION(vimclk2_alt), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1712 | }; |
| 1713 | |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1714 | #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ |
| 1715 | #define PINGROUP_REG_A 0x3000 /* bank 1 */ |
Sean Paul | 3ccc11f | 2014-09-09 15:58:45 -0400 | [diff] [blame] | 1716 | #define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1717 | |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1718 | #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1719 | #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1720 | #define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A) |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1721 | |
| 1722 | #define PINGROUP_BIT_Y(b) (b) |
| 1723 | #define PINGROUP_BIT_N(b) (-1) |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1724 | |
Stephen Warren | 6240d69 | 2014-04-14 15:33:40 -0600 | [diff] [blame] | 1725 | #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1726 | { \ |
| 1727 | .name = #pg_name, \ |
| 1728 | .pins = pg_name##_pins, \ |
| 1729 | .npins = ARRAY_SIZE(pg_name##_pins), \ |
| 1730 | .funcs = { \ |
Stephen Warren | 93cfb2d | 2014-03-07 12:22:17 -0700 | [diff] [blame] | 1731 | TEGRA_MUX_##f0, \ |
| 1732 | TEGRA_MUX_##f1, \ |
| 1733 | TEGRA_MUX_##f2, \ |
| 1734 | TEGRA_MUX_##f3, \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1735 | }, \ |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1736 | .mux_reg = PINGROUP_REG(r), \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1737 | .mux_bank = 1, \ |
| 1738 | .mux_bit = 0, \ |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1739 | .pupd_reg = PINGROUP_REG(r), \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1740 | .pupd_bank = 1, \ |
| 1741 | .pupd_bit = 2, \ |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1742 | .tri_reg = PINGROUP_REG(r), \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1743 | .tri_bank = 1, \ |
| 1744 | .tri_bit = 4, \ |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1745 | .einput_bit = 5, \ |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1746 | .odrain_bit = PINGROUP_BIT_##od(6), \ |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1747 | .lock_bit = 7, \ |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1748 | .ioreset_bit = PINGROUP_BIT_##ior(8), \ |
| 1749 | .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1750 | .drv_reg = -1, \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1751 | } |
| 1752 | |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 1753 | #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \ |
| 1754 | drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \ |
| 1755 | slwf_b, slwf_w, drvtype) \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1756 | { \ |
| 1757 | .name = "drive_" #pg_name, \ |
| 1758 | .pins = drive_##pg_name##_pins, \ |
| 1759 | .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ |
| 1760 | .mux_reg = -1, \ |
| 1761 | .pupd_reg = -1, \ |
| 1762 | .tri_reg = -1, \ |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1763 | .einput_bit = -1, \ |
| 1764 | .odrain_bit = -1, \ |
| 1765 | .lock_bit = -1, \ |
| 1766 | .ioreset_bit = -1, \ |
| 1767 | .rcv_sel_bit = -1, \ |
| 1768 | .drv_reg = DRV_PINGROUP_REG(r), \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1769 | .drv_bank = 0, \ |
| 1770 | .hsm_bit = hsm_b, \ |
| 1771 | .schmitt_bit = schmitt_b, \ |
| 1772 | .lpmd_bit = lpmd_b, \ |
| 1773 | .drvdn_bit = drvdn_b, \ |
| 1774 | .drvdn_width = drvdn_w, \ |
| 1775 | .drvup_bit = drvup_b, \ |
| 1776 | .drvup_width = drvup_w, \ |
| 1777 | .slwr_bit = slwr_b, \ |
| 1778 | .slwr_width = slwr_w, \ |
| 1779 | .slwf_bit = slwf_b, \ |
| 1780 | .slwf_width = slwf_w, \ |
Stephen Warren | e53b797 | 2014-04-15 11:00:50 -0600 | [diff] [blame] | 1781 | .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1782 | } |
| 1783 | |
Sean Paul | 3ccc11f | 2014-09-09 15:58:45 -0400 | [diff] [blame] | 1784 | #define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \ |
| 1785 | { \ |
| 1786 | .name = "mipi_pad_ctrl_" #pg_name, \ |
| 1787 | .pins = mipi_pad_ctrl_##pg_name##_pins, \ |
| 1788 | .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \ |
| 1789 | .funcs = { \ |
| 1790 | TEGRA_MUX_ ## f0, \ |
| 1791 | TEGRA_MUX_ ## f1, \ |
| 1792 | TEGRA_MUX_RSVD3, \ |
| 1793 | TEGRA_MUX_RSVD4, \ |
| 1794 | }, \ |
| 1795 | .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \ |
| 1796 | .mux_bank = 2, \ |
| 1797 | .mux_bit = b, \ |
| 1798 | .pupd_reg = -1, \ |
| 1799 | .tri_reg = -1, \ |
| 1800 | .einput_bit = -1, \ |
| 1801 | .odrain_bit = -1, \ |
| 1802 | .lock_bit = -1, \ |
| 1803 | .ioreset_bit = -1, \ |
| 1804 | .rcv_sel_bit = -1, \ |
| 1805 | .drv_reg = -1, \ |
| 1806 | } |
| 1807 | |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 1808 | static const struct tegra_pingroup tegra124_groups[] = { |
Stephen Warren | 6240d69 | 2014-04-14 15:33:40 -0600 | [diff] [blame] | 1809 | /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */ |
| 1810 | PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N), |
| 1811 | PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N), |
| 1812 | PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N), |
| 1813 | PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N), |
| 1814 | PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N), |
| 1815 | PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N), |
| 1816 | PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N), |
| 1817 | PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N), |
| 1818 | PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N), |
| 1819 | PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N), |
| 1820 | PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N), |
| 1821 | PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N), |
| 1822 | PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N), |
| 1823 | PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N), |
| 1824 | PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, 0x3038, N, N, N), |
| 1825 | PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, 0x303c, N, N, N), |
| 1826 | PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N), |
| 1827 | PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N), |
| 1828 | PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N), |
| 1829 | PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N), |
| 1830 | PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N), |
| 1831 | PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N), |
| 1832 | PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N), |
| 1833 | PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N), |
| 1834 | PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N), |
| 1835 | PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N), |
| 1836 | PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y), |
| 1837 | PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y), |
| 1838 | PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y), |
| 1839 | PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N), |
| 1840 | PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N), |
| 1841 | PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N, N), |
| 1842 | PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N, N), |
| 1843 | PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, 0x3174, N, N, N), |
| 1844 | PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, 0x3178, N, N, N), |
| 1845 | PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, 0x317c, N, N, N), |
| 1846 | PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, 0x3180, N, N, N), |
| 1847 | PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N, N), |
| 1848 | PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N, N), |
| 1849 | PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N, N), |
| 1850 | PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, 0x3190, N, N, N), |
| 1851 | PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, 0x3194, N, N, N), |
| 1852 | PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, 0x3198, N, N, N), |
| 1853 | PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, 0x319c, N, N, N), |
| 1854 | PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N), |
| 1855 | PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N), |
| 1856 | PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, 0x31a8, N, N, N), |
| 1857 | PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, 0x31ac, N, N, N), |
| 1858 | PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, 0x31b0, N, N, N), |
| 1859 | PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, 0x31b4, N, N, N), |
| 1860 | PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N), |
| 1861 | PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N), |
| 1862 | PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, 0x31c0, N, N, N), |
| 1863 | PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, 0x31c4, N, N, N), |
| 1864 | PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, 0x31c8, N, N, N), |
| 1865 | PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, 0x31cc, N, N, N), |
| 1866 | PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, 0x31d0, N, N, N), |
| 1867 | PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, 0x31d4, N, N, N), |
| 1868 | PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, 0x31d8, N, N, N), |
| 1869 | PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, 0x31dc, N, N, N), |
| 1870 | PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, 0x31e0, N, N, N), |
| 1871 | PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, 0x31e4, N, N, N), |
| 1872 | PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, 0x31e8, N, N, N), |
| 1873 | PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, 0x31ec, N, N, N), |
| 1874 | PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, 0x31f0, N, N, N), |
| 1875 | PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, 0x31f4, N, N, N), |
| 1876 | PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, 0x31f8, N, N, N), |
| 1877 | PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, 0x31fc, N, N, N), |
| 1878 | PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, 0x3200, N, N, N), |
| 1879 | PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, 0x3204, N, N, N), |
| 1880 | PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, 0x3208, N, N, N), |
| 1881 | PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, 0x320c, N, N, N), |
| 1882 | PINGROUP(ph0, PWM0, TRACE, GMI, DTV, 0x3210, N, N, N), |
| 1883 | PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, 0x3214, N, N, N), |
| 1884 | PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, 0x3218, N, N, N), |
| 1885 | PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, 0x321c, N, N, N), |
| 1886 | PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, 0x3220, N, N, N), |
| 1887 | PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, 0x3224, N, N, N), |
| 1888 | PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, 0x3228, N, N, N), |
| 1889 | PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, 0x322c, N, N, N), |
| 1890 | PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, 0x3230, N, N, N), |
| 1891 | PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, 0x3234, N, N, N), |
| 1892 | PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, 0x3238, N, N, N), |
| 1893 | PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, 0x323c, N, N, N), |
| 1894 | PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, 0x3240, N, N, N), |
| 1895 | PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, 0x3244, N, N, N), |
| 1896 | PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, 0x3248, N, N, N), |
| 1897 | PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, 0x324c, N, N, N), |
| 1898 | PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N), |
| 1899 | PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N), |
| 1900 | PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N), |
| 1901 | PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N), |
| 1902 | PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N), |
| 1903 | PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N), |
| 1904 | PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N), |
| 1905 | PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N), |
| 1906 | PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N), |
| 1907 | PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, 0x3274, N, Y, N), |
| 1908 | PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N), |
| 1909 | PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N), |
| 1910 | PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, 0x3284, N, N, N), |
| 1911 | PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, 0x3288, N, N, N), |
| 1912 | PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, 0x328c, N, N, N), |
| 1913 | PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, 0x3290, Y, N, N), |
| 1914 | PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, 0x3294, Y, N, N), |
| 1915 | PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, 0x3298, N, N, N), |
| 1916 | PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, 0x329c, N, N, N), |
| 1917 | PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, 0x32a0, N, N, N), |
| 1918 | PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, 0x32a4, N, N, N), |
| 1919 | PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, 0x32a8, N, N, N), |
| 1920 | PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, 0x32ac, N, N, N), |
| 1921 | PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N), |
| 1922 | PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N), |
| 1923 | PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N), |
| 1924 | PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N), |
| 1925 | PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N), |
| 1926 | PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N), |
| 1927 | PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, 0x32c8, N, N, N), |
| 1928 | PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32cc, N, N, N), |
| 1929 | PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32d0, N, N, N), |
| 1930 | PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N), |
| 1931 | PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N), |
| 1932 | PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N), |
| 1933 | PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N), |
| 1934 | PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N), |
| 1935 | PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, 0x32e8, N, N, N), |
| 1936 | PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, 0x32ec, N, N, N), |
| 1937 | PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, 0x32f0, N, N, N), |
| 1938 | PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, 0x32f4, N, N, N), |
| 1939 | PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, 0x32f8, N, N, N), |
| 1940 | PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, 0x32fc, N, N, N), |
| 1941 | PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, 0x3300, N, N, N), |
| 1942 | PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N), |
| 1943 | PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N), |
| 1944 | PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N), |
| 1945 | PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, 0x3310, N, N, N), |
| 1946 | PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, 0x3314, N, N, N), |
| 1947 | PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, 0x3318, N, N, N), |
| 1948 | PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N), |
| 1949 | PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N), |
| 1950 | PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N), |
| 1951 | PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N), |
| 1952 | PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N), |
| 1953 | PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y), |
| 1954 | PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N), |
| 1955 | PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N), |
| 1956 | PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, 0x3340, N, N, N), |
| 1957 | PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N), |
| 1958 | PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, 0x3348, N, N, N), |
| 1959 | PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N), |
| 1960 | PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, 0x3350, N, N, N), |
| 1961 | PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, 0x3354, N, N, N), |
| 1962 | PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, 0x3358, N, N, N), |
| 1963 | PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, 0x335c, N, N, N), |
| 1964 | PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, 0x3360, N, N, N), |
| 1965 | PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, 0x3364, N, N, N), |
| 1966 | PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, 0x3368, N, N, N), |
| 1967 | PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, 0x336c, N, N, N), |
| 1968 | PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, 0x3370, N, N, N), |
| 1969 | PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, 0x3374, N, N, N), |
| 1970 | PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, 0x3378, N, N, N), |
| 1971 | PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, 0x337c, N, N, N), |
| 1972 | PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, 0x3380, N, N, N), |
| 1973 | PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N), |
| 1974 | PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N), |
| 1975 | PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N), |
| 1976 | PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N), |
| 1977 | PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N), |
| 1978 | PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N), |
| 1979 | PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N), |
| 1980 | PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, 0x33bc, N, N, N), |
| 1981 | PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, 0x33c0, N, N, N), |
| 1982 | PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, 0x33c4, N, N, N), |
| 1983 | PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, 0x33cc, N, N, N), |
| 1984 | PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, 0x33d0, N, N, N), |
| 1985 | PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N, N), |
| 1986 | PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N), |
| 1987 | PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N), |
| 1988 | PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N), |
| 1989 | PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N), |
| 1990 | PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N), |
| 1991 | PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N), |
| 1992 | PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N), |
| 1993 | PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N), |
| 1994 | PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, 0x3404, N, N, N), |
| 1995 | PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N), |
| 1996 | PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, 0x340c, N, N, N), |
| 1997 | PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, 0x3410, N, N, N), |
| 1998 | PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, 0x3414, Y, N, N), |
| 1999 | PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, 0x3418, Y, N, N), |
| 2000 | PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 2001 | |
| 2002 | /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */ |
Stephen Warren | 6240d69 | 2014-04-14 15:33:40 -0600 | [diff] [blame] | 2003 | DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2004 | DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2005 | DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), |
| 2006 | DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), |
| 2007 | DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), |
| 2008 | DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), |
| 2009 | DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), |
| 2010 | DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2011 | DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2012 | DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2013 | DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2014 | DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2015 | DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2016 | DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2017 | DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), |
| 2018 | DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2019 | DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2020 | DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2021 | DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2022 | DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2023 | DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), |
| 2024 | DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2025 | DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y), |
| 2026 | DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), |
| 2027 | DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), |
| 2028 | DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), |
| 2029 | DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), |
| 2030 | DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2031 | DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2032 | DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2033 | DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2034 | DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2035 | DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), |
| 2036 | DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2037 | DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2038 | DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), |
| 2039 | DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2040 | DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), |
| 2041 | DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), |
| 2042 | DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), |
Sean Paul | 3ccc11f | 2014-09-09 15:58:45 -0400 | [diff] [blame] | 2043 | |
Stephen Warren | 8d4684b | 2015-02-24 14:00:48 -0700 | [diff] [blame] | 2044 | /* pg_name, r, b, f0, f1 */ |
| 2045 | MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B), |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 2046 | }; |
| 2047 | |
| 2048 | static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { |
| 2049 | .ngpios = NUM_GPIOS, |
| 2050 | .pins = tegra124_pins, |
| 2051 | .npins = ARRAY_SIZE(tegra124_pins), |
| 2052 | .functions = tegra124_functions, |
| 2053 | .nfunctions = ARRAY_SIZE(tegra124_functions), |
| 2054 | .groups = tegra124_groups, |
| 2055 | .ngroups = ARRAY_SIZE(tegra124_groups), |
Stephen Warren | ea62306 | 2015-02-24 14:00:49 -0700 | [diff] [blame^] | 2056 | .hsm_in_mux = false, |
| 2057 | .schmitt_in_mux = false, |
| 2058 | .drvtype_in_mux = false, |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 2059 | }; |
| 2060 | |
| 2061 | static int tegra124_pinctrl_probe(struct platform_device *pdev) |
| 2062 | { |
| 2063 | return tegra_pinctrl_probe(pdev, &tegra124_pinctrl); |
| 2064 | } |
| 2065 | |
Kiran Padwal | 5dfe10b | 2014-08-11 16:47:50 +0530 | [diff] [blame] | 2066 | static const struct of_device_id tegra124_pinctrl_of_match[] = { |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 2067 | { .compatible = "nvidia,tegra124-pinmux", }, |
| 2068 | { }, |
| 2069 | }; |
| 2070 | MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match); |
| 2071 | |
| 2072 | static struct platform_driver tegra124_pinctrl_driver = { |
| 2073 | .driver = { |
| 2074 | .name = "tegra124-pinctrl", |
Ashwini Ghuge | 1a16bee | 2013-12-10 12:40:56 +0530 | [diff] [blame] | 2075 | .of_match_table = tegra124_pinctrl_of_match, |
| 2076 | }, |
| 2077 | .probe = tegra124_pinctrl_probe, |
| 2078 | .remove = tegra_pinctrl_remove, |
| 2079 | }; |
| 2080 | module_platform_driver(tegra124_pinctrl_driver); |
| 2081 | |
| 2082 | MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>"); |
| 2083 | MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver"); |
| 2084 | MODULE_LICENSE("GPL v2"); |