blob: e6328b008a8cf268dc1cf0af3e24d44f9ef7d917 [file] [log] [blame]
Ben Skeggs2a259a32012-05-08 10:24:27 +10001#ifndef __NOUVEAU_ABI16_H__
2#define __NOUVEAU_ABI16_H__
3
4#define ABI16_IOCTL_ARGS \
5 struct drm_device *dev, void *data, struct drm_file *file_priv
6int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
7int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
8int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
9int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
10int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
11int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
12int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
13
14struct drm_nouveau_channel_alloc {
15 uint32_t fb_ctxdma_handle;
16 uint32_t tt_ctxdma_handle;
17
18 int channel;
19 uint32_t pushbuf_domains;
20
21 /* Notifier memory */
22 uint32_t notifier_handle;
23
24 /* DRM-enforced subchannel assignments */
25 struct {
26 uint32_t handle;
27 uint32_t grclass;
28 } subchan[8];
29 uint32_t nr_subchan;
30};
31
32struct drm_nouveau_channel_free {
33 int channel;
34};
35
36struct drm_nouveau_grobj_alloc {
37 int channel;
38 uint32_t handle;
39 int class;
40};
41
42struct drm_nouveau_notifierobj_alloc {
43 uint32_t channel;
44 uint32_t handle;
45 uint32_t size;
46 uint32_t offset;
47};
48
49struct drm_nouveau_gpuobj_free {
50 int channel;
51 uint32_t handle;
52};
53
54#define NOUVEAU_GETPARAM_PCI_VENDOR 3
55#define NOUVEAU_GETPARAM_PCI_DEVICE 4
56#define NOUVEAU_GETPARAM_BUS_TYPE 5
57#define NOUVEAU_GETPARAM_FB_SIZE 8
58#define NOUVEAU_GETPARAM_AGP_SIZE 9
59#define NOUVEAU_GETPARAM_CHIPSET_ID 11
60#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
61#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
62#define NOUVEAU_GETPARAM_PTIMER_TIME 14
63#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
64#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
65struct drm_nouveau_getparam {
66 uint64_t param;
67 uint64_t value;
68};
69
70struct drm_nouveau_setparam {
71 uint64_t param;
72 uint64_t value;
73};
74
75#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
76#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
77#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
78#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
79#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
80#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
81#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
82
83#endif