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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
Santosh Shilimkar44169072009-05-28 14:16:04 -07007 * Copyright (C) 2007-2009 Texas Instruments
Tony Lindgren646e3ed2008-10-06 15:49:36 +03008 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
Tony Lindgren1dbae812005-11-10 14:26:51 +000012 *
Santosh Shilimkar44169072009-05-28 14:16:04 -070013 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
Tony Lindgren1dbae812005-11-10 14:26:51 +000015 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
Tony Lindgren1dbae812005-11-10 14:26:51 +000019#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +010022#include <linux/io.h>
Paul Walmsley2f135ea2009-06-19 19:08:25 -060023#include <linux/clk.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000024
Tony Lindgren120db2c2006-04-02 17:46:27 +010025#include <asm/tlb.h>
Tony Lindgren120db2c2006-04-02 17:46:27 +010026#include <asm/mach/map.h>
27
Tony Lindgren45c3eb72012-11-30 08:41:50 -080028#include <linux/omap-dma.h>
Tony Lindgren646e3ed2008-10-06 15:49:36 +030029
Tony Lindgrendc843282012-10-03 11:23:43 -070030#include "omap_hwmod.h"
Tony Lindgrendbc04162012-08-31 10:59:07 -070031#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -080032#include "iomap.h"
33#include "voltage.h"
34#include "powerdomain.h"
35#include "clockdomain.h"
36#include "common.h"
Vaibhav Hiremathe30384a2012-05-29 15:26:41 +053037#include "clock.h"
Paul Walmsleye80a9722010-01-26 20:13:12 -070038#include "clock2xxx.h"
Paul Walmsley657ebfa2010-02-22 22:09:20 -070039#include "clock3xxx.h"
Tony Lindgren1d5aef42012-10-03 16:36:40 -070040#include "omap-pm.h"
Paul Walmsley3e6ece12012-10-17 00:46:45 +000041#include "sdrc.h"
Paul Walmsleyb6a42262012-10-29 20:50:21 -060042#include "control.h"
Tony Lindgren3d82cbb2012-10-15 12:50:46 -070043#include "serial.h"
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070044#include "sram.h"
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -060045#include "cm2xxx.h"
46#include "cm3xxx.h"
Tero Kristo7632a022014-10-27 08:39:23 -070047#include "cm33xx.h"
Tero Kristoab6c9bb2014-10-27 08:39:25 -070048#include "cm44xx.h"
Paul Walmsleyd9a16f92012-10-29 20:57:39 -060049#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
Paul Walmsley63a293e2012-11-21 16:15:16 -070053#include "prm2xxx.h"
54#include "prm3xxx.h"
Tero Kristod9bbe842014-10-27 08:39:24 -070055#include "prm33xx.h"
Paul Walmsley63a293e2012-11-21 16:15:16 -070056#include "prm44xx.h"
Tero Kristo69a1e7a2014-02-24 18:51:05 +020057#include "opp2xxx.h"
Tony Lindgren1dbae812005-11-10 14:26:51 +000058
Tony Lindgren1dbae812005-11-10 14:26:51 +000059/*
Tero Kristocfa96672013-10-22 11:53:02 +030060 * omap_clk_soc_init: points to a function that does the SoC-specific
Rajendra Nayakff931c82013-03-21 16:34:52 +053061 * clock initializations
62 */
Tero Kristocfa96672013-10-22 11:53:02 +030063static int (*omap_clk_soc_init)(void);
Rajendra Nayakff931c82013-03-21 16:34:52 +053064
65/*
Tony Lindgren1dbae812005-11-10 14:26:51 +000066 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
68 */
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030069
Tony Lindgrene48f8142012-03-06 11:49:22 -080070#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030071static struct map_desc omap24xx_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000072 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
Kyungmin Park09f21ed2008-02-20 15:30:06 -080078 {
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030079 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
Syed Mohammed Khasim72d0f1c2006-12-06 17:14:05 -080082 .type = MT_DEVICE
83 },
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030084};
85
Tony Lindgren59b479e2011-01-27 16:39:40 -080086#ifdef CONFIG_SOC_OMAP2420
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030087static struct map_desc omap242x_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000088 {
Paul Walmsley7adb9982010-01-08 15:23:05 -070089 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
Tony Lindgrenc40fae952006-12-07 13:58:10 -080092 .type = MT_DEVICE
93 },
94 {
Paul Walmsley7adb9982010-01-08 15:23:05 -070095 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
Tony Lindgrenc40fae952006-12-07 13:58:10 -080098 .type = MT_DEVICE
99 },
100 {
Paul Walmsley7adb9982010-01-08 15:23:05 -0700101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
Tony Lindgren1dbae812005-11-10 14:26:51 +0000104 .type = MT_DEVICE
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300105 },
Tony Lindgren1dbae812005-11-10 14:26:51 +0000106};
107
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300108#endif
109
Tony Lindgren59b479e2011-01-27 16:39:40 -0800110#ifdef CONFIG_SOC_OMAP2430
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300111static struct map_desc omap243x_io_desc[] __initdata = {
112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136};
137#endif
138#endif
139
Tony Lindgrena8eb7ca2010-02-12 12:26:48 -0800140#ifdef CONFIG_ARCH_OMAP3
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300141static struct map_desc omap34xx_io_desc[] __initdata = {
142 {
143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
152 .type = MT_DEVICE
153 },
154 {
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
184};
185#endif
Hemant Pedanekar01001712011-02-16 08:31:39 -0800186
Kevin Hilman33959552012-05-10 11:10:07 -0700187#ifdef CONFIG_SOC_TI81XX
Hemant Pedanekara9203602011-12-13 10:46:44 -0800188static struct map_desc omapti81xx_io_desc[] __initdata = {
Hemant Pedanekar01001712011-02-16 08:31:39 -0800189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800194 }
195};
196#endif
197
Afzal Mohammedaddb1542013-05-27 20:06:13 +0530198#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800199static struct map_desc omapam33xx_io_desc[] __initdata = {
Hemant Pedanekar01001712011-02-16 08:31:39 -0800200 {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
204 .type = MT_DEVICE
205 },
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800206 {
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
210 .type = MT_DEVICE
211 }
Hemant Pedanekar01001712011-02-16 08:31:39 -0800212};
213#endif
214
Santosh Shilimkar44169072009-05-28 14:16:04 -0700215#ifdef CONFIG_ARCH_OMAP4
216static struct map_desc omap44xx_io_desc[] __initdata = {
217 {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
229 {
Santosh Shilimkar44169072009-05-28 14:16:04 -0700230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
Santosh Shilimkar44169072009-05-28 14:16:04 -0700235};
236#endif
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300237
Nishanth Menonea827ad2015-06-22 10:12:14 -0500238#ifdef CONFIG_SOC_OMAP5
R Sricharan05e152c2012-06-05 16:21:32 +0530239static struct map_desc omap54xx_io_desc[] __initdata = {
240 {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258 {
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264};
265#endif
266
Nishanth Menonea827ad2015-06-22 10:12:14 -0500267#ifdef CONFIG_SOC_DRA7XX
268static struct map_desc dra7xx_io_desc[] __initdata = {
269 {
270 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
272 .length = L4_CFG_MPU_DRA7XX_SIZE,
273 .type = MT_DEVICE,
274 },
275 {
276 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
278 .length = L3_MAIN_SN_DRA7XX_SIZE,
279 .type = MT_DEVICE,
280 },
281 {
282 .virtual = L4_PER1_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
284 .length = L4_PER1_DRA7XX_SIZE,
285 .type = MT_DEVICE,
286 },
287 {
288 .virtual = L4_PER2_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
290 .length = L4_PER2_DRA7XX_SIZE,
291 .type = MT_DEVICE,
292 },
293 {
294 .virtual = L4_PER3_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
296 .length = L4_PER3_DRA7XX_SIZE,
297 .type = MT_DEVICE,
298 },
299 {
300 .virtual = L4_CFG_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
302 .length = L4_CFG_DRA7XX_SIZE,
303 .type = MT_DEVICE,
304 },
305 {
306 .virtual = L4_WKUP_DRA7XX_VIRT,
307 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
308 .length = L4_WKUP_DRA7XX_SIZE,
309 .type = MT_DEVICE,
310 },
311};
312#endif
313
Tony Lindgren59b479e2011-01-27 16:39:40 -0800314#ifdef CONFIG_SOC_OMAP2420
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600315void __init omap242x_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800316{
317 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
318 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800319}
320#endif
321
Tony Lindgren59b479e2011-01-27 16:39:40 -0800322#ifdef CONFIG_SOC_OMAP2430
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600323void __init omap243x_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800324{
325 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
326 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800327}
328#endif
329
Tony Lindgrena8eb7ca2010-02-12 12:26:48 -0800330#ifdef CONFIG_ARCH_OMAP3
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600331void __init omap3_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800332{
333 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800334}
335#endif
336
Kevin Hilman33959552012-05-10 11:10:07 -0700337#ifdef CONFIG_SOC_TI81XX
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600338void __init ti81xx_map_io(void)
Hemant Pedanekar01001712011-02-16 08:31:39 -0800339{
Hemant Pedanekara9203602011-12-13 10:46:44 -0800340 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
Hemant Pedanekar01001712011-02-16 08:31:39 -0800341}
342#endif
343
Afzal Mohammedaddb1542013-05-27 20:06:13 +0530344#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600345void __init am33xx_map_io(void)
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800346{
347 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800348}
349#endif
350
351#ifdef CONFIG_ARCH_OMAP4
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600352void __init omap4_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800353{
354 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
Russell Kingf7469292015-06-06 00:13:40 +0100355 omap_barriers_init();
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800356}
357#endif
358
Nishanth Menonea827ad2015-06-22 10:12:14 -0500359#ifdef CONFIG_SOC_OMAP5
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600360void __init omap5_map_io(void)
R Sricharan05e152c2012-06-05 16:21:32 +0530361{
362 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
Russell Kingf7469292015-06-06 00:13:40 +0100363 omap_barriers_init();
R Sricharan05e152c2012-06-05 16:21:32 +0530364}
365#endif
Nishanth Menonea827ad2015-06-22 10:12:14 -0500366
367#ifdef CONFIG_SOC_DRA7XX
368void __init dra7xx_map_io(void)
369{
370 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
371}
372#endif
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600373/*
374 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
375 *
376 * Sets the CORE DPLL3 M2 divider to the same value that it's at
377 * currently. This has the effect of setting the SDRC SDRAM AC timing
378 * registers to the values currently defined by the kernel. Currently
379 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
380 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
381 * or passes along the return value of clk_set_rate().
382 */
383static int __init _omap2_init_reprogram_sdrc(void)
384{
385 struct clk *dpll3_m2_ck;
386 int v = -EINVAL;
387 long rate;
388
389 if (!cpu_is_omap34xx())
390 return 0;
391
392 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
Aaro Koskinene281f7e2010-11-30 14:17:58 +0000393 if (IS_ERR(dpll3_m2_ck))
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600394 return -EINVAL;
395
396 rate = clk_get_rate(dpll3_m2_ck);
397 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
398 v = clk_set_rate(dpll3_m2_ck, rate);
399 if (v)
400 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
401
402 clk_put(dpll3_m2_ck);
403
404 return v;
405}
406
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700407static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
408{
409 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
410}
411
Tony Lindgren7b250af2011-10-04 18:26:28 -0700412static void __init omap_hwmod_init_postsetup(void)
Tony Lindgren120db2c2006-04-02 17:46:27 +0100413{
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700414 u8 postsetup_state;
415
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700416 /* Set the default postsetup state for all hwmods */
Rafael J. Wysockibf7c5442014-12-13 00:42:49 +0100417#ifdef CONFIG_PM
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700418 postsetup_state = _HWMOD_STATE_IDLE;
419#else
420 postsetup_state = _HWMOD_STATE_ENABLED;
421#endif
422 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
Benoit Cousson55d2cb02010-05-12 17:54:36 +0200423
Kevin Hilman53da4ce2010-12-09 09:13:48 -0600424 omap_pm_if_early_init();
Paul Walmsley48057342010-12-21 15:25:10 -0700425}
426
Arnd Bergmann069d0a72013-07-05 16:20:17 +0200427static void __init __maybe_unused omap_common_late_init(void)
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200428{
429 omap_mux_late_init();
430 omap2_common_pm_late_init();
Ruslan Bilovol6770b212013-02-14 13:55:24 +0200431 omap_soc_device_init();
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200432}
433
Paul Walmsley16110792012-01-25 12:57:46 -0700434#ifdef CONFIG_SOC_OMAP2420
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700435void __init omap2420_init_early(void)
436{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600437 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
438 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
439 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200440 omap2_control_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530441 omap2xxx_check_revision();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200442 omap2_prcm_base_init();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700443 omap2xxx_voltagedomains_init();
444 omap242x_powerdomains_init();
445 omap242x_clockdomains_init();
446 omap2420_hwmod_init();
447 omap_hwmod_init_postsetup();
Tero Kristo6a194a62014-03-04 10:53:54 +0200448 omap_clk_soc_init = omap2420_dt_clk_init;
449 rate_table = omap2420_rate_table;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700450}
Shawn Guobbd707a2012-04-26 16:06:50 +0800451
452void __init omap2420_init_late(void)
453{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200454 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800455 omap2_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530456 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800457}
Paul Walmsley16110792012-01-25 12:57:46 -0700458#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700459
Paul Walmsley16110792012-01-25 12:57:46 -0700460#ifdef CONFIG_SOC_OMAP2430
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700461void __init omap2430_init_early(void)
462{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600463 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
464 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
465 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200466 omap2_control_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530467 omap2xxx_check_revision();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200468 omap2_prcm_base_init();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700469 omap2xxx_voltagedomains_init();
470 omap243x_powerdomains_init();
471 omap243x_clockdomains_init();
472 omap2430_hwmod_init();
473 omap_hwmod_init_postsetup();
Tero Kristo6a194a62014-03-04 10:53:54 +0200474 omap_clk_soc_init = omap2430_dt_clk_init;
475 rate_table = omap2430_rate_table;
Tony Lindgren7b250af2011-10-04 18:26:28 -0700476}
Shawn Guobbd707a2012-04-26 16:06:50 +0800477
478void __init omap2430_init_late(void)
479{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200480 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800481 omap2_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530482 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800483}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530484#endif
Tony Lindgren7b250af2011-10-04 18:26:28 -0700485
486/*
487 * Currently only board-omap3beagle.c should call this because of the
488 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
489 */
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530490#ifdef CONFIG_ARCH_OMAP3
Tony Lindgren7b250af2011-10-04 18:26:28 -0700491void __init omap3_init_early(void)
492{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600493 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
494 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
495 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200496 /* XXX: remove these once OMAP3 is DT only */
497 if (!of_have_populated_dt()) {
498 omap2_set_globals_control(
Tero Kristoefde2342015-02-20 10:08:52 +0200499 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200500 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
501 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
502 NULL);
503 }
504 omap2_control_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530505 omap3xxx_check_revision();
506 omap3xxx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200507 omap2_prcm_base_init();
Tero Kristo425dc8b2014-11-21 15:51:37 +0200508 /* XXX: remove these once OMAP3 is DT only */
509 if (!of_have_populated_dt()) {
510 omap3xxx_prm_init(NULL);
511 omap3xxx_cm_init(NULL);
512 }
Tony Lindgren7b250af2011-10-04 18:26:28 -0700513 omap3xxx_voltagedomains_init();
514 omap3xxx_powerdomains_init();
515 omap3xxx_clockdomains_init();
516 omap3xxx_hwmod_init();
517 omap_hwmod_init_postsetup();
Tero Kristoeded36f2014-12-16 18:20:55 +0200518 if (!of_have_populated_dt()) {
Tero Kristo2208bf12014-11-13 19:17:34 +0200519 omap3_control_legacy_iomap_init();
Tero Kristoeded36f2014-12-16 18:20:55 +0200520 if (soc_is_am35xx())
521 omap_clk_soc_init = am35xx_clk_legacy_init;
522 else if (cpu_is_omap3630())
523 omap_clk_soc_init = omap36xx_clk_legacy_init;
524 else if (omap_rev() == OMAP3430_REV_ES1_0)
525 omap_clk_soc_init = omap3430es1_clk_legacy_init;
526 else
527 omap_clk_soc_init = omap3430_clk_legacy_init;
528 }
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700529}
530
531void __init omap3430_init_early(void)
532{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700533 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300534 if (of_have_populated_dt())
535 omap_clk_soc_init = omap3430_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700536}
537
538void __init omap35xx_init_early(void)
539{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700540 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300541 if (of_have_populated_dt())
542 omap_clk_soc_init = omap3430_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700543}
544
545void __init omap3630_init_early(void)
546{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700547 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300548 if (of_have_populated_dt())
549 omap_clk_soc_init = omap3630_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700550}
551
552void __init am35xx_init_early(void)
553{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700554 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300555 if (of_have_populated_dt())
556 omap_clk_soc_init = am35xx_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700557}
558
Shawn Guobbd707a2012-04-26 16:06:50 +0800559void __init omap3_init_late(void)
560{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200561 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800562 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530563 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800564}
565
566void __init omap3430_init_late(void)
567{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200568 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800569 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530570 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800571}
572
573void __init omap35xx_init_late(void)
574{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200575 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800576 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530577 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800578}
579
580void __init omap3630_init_late(void)
581{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200582 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800583 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530584 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800585}
586
587void __init am35xx_init_late(void)
588{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200589 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800590 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530591 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800592}
593
594void __init ti81xx_init_late(void)
595{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200596 omap_common_late_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530597 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800598}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530599#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700600
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800601#ifdef CONFIG_SOC_TI81XX
602void __init ti814x_init_early(void)
603{
604 omap2_set_globals_tap(TI814X_CLASS,
605 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200606 omap2_control_base_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800607 omap3xxx_check_revision();
608 ti81xx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200609 omap2_prcm_base_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800610 omap3xxx_voltagedomains_init();
611 omap3xxx_powerdomains_init();
Tony Lindgren185fde62015-07-16 01:55:57 -0700612 ti814x_clockdomains_init();
Tony Lindgren0f3ccb22015-07-16 01:55:58 -0700613 dm814x_hwmod_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800614 omap_hwmod_init_postsetup();
Tony Lindgrend8936562015-12-03 12:02:32 -0800615 omap_clk_soc_init = dm814x_dt_clk_init;
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800616}
617
618void __init ti816x_init_early(void)
619{
620 omap2_set_globals_tap(TI816X_CLASS,
621 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200622 omap2_control_base_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800623 omap3xxx_check_revision();
624 ti81xx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200625 omap2_prcm_base_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800626 omap3xxx_voltagedomains_init();
627 omap3xxx_powerdomains_init();
Tony Lindgren185fde62015-07-16 01:55:57 -0700628 ti816x_clockdomains_init();
Tony Lindgren0f3ccb22015-07-16 01:55:58 -0700629 dm816x_hwmod_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800630 omap_hwmod_init_postsetup();
631 if (of_have_populated_dt())
Tony Lindgren9cf705d2015-07-16 01:55:57 -0700632 omap_clk_soc_init = dm816x_dt_clk_init;
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800633}
634#endif
635
Afzal Mohammed08f30982012-05-11 00:38:49 +0530636#ifdef CONFIG_SOC_AM33XX
637void __init am33xx_init_early(void)
638{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600639 omap2_set_globals_tap(AM335X_CLASS,
640 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200641 omap2_control_base_init();
Afzal Mohammed08f30982012-05-11 00:38:49 +0530642 omap3xxx_check_revision();
Vaibhav Hiremath7bcad172013-05-17 15:43:41 +0530643 am33xx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200644 omap2_prcm_base_init();
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -0600645 am33xx_powerdomains_init();
Vaibhav Hiremath9c80f3a2012-06-18 00:47:27 -0600646 am33xx_clockdomains_init();
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600647 am33xx_hwmod_init();
648 omap_hwmod_init_postsetup();
Tero Kristo149c09d2013-07-19 11:37:17 +0300649 omap_clk_soc_init = am33xx_dt_clk_init;
Afzal Mohammed08f30982012-05-11 00:38:49 +0530650}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500651
652void __init am33xx_init_late(void)
653{
654 omap_common_late_init();
655}
Afzal Mohammed08f30982012-05-11 00:38:49 +0530656#endif
657
Afzal Mohammedc5107022013-05-27 20:06:23 +0530658#ifdef CONFIG_SOC_AM43XX
659void __init am43xx_init_early(void)
660{
661 omap2_set_globals_tap(AM335X_CLASS,
662 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200663 omap2_control_base_init();
Afzal Mohammedc5107022013-05-27 20:06:23 +0530664 omap3xxx_check_revision();
Afzal Mohammed7a2e0512014-02-07 15:51:25 +0530665 am33xx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200666 omap2_prcm_base_init();
Ambresh K8835cf62013-10-12 15:46:37 +0530667 am43xx_powerdomains_init();
668 am43xx_clockdomains_init();
669 am43xx_hwmod_init();
670 omap_hwmod_init_postsetup();
Sekhar Norid941f862014-04-22 13:58:03 +0530671 omap_l2_cache_init();
Tero Kristod22031e2013-11-21 16:49:59 +0200672 omap_clk_soc_init = am43xx_dt_clk_init;
Afzal Mohammedc5107022013-05-27 20:06:23 +0530673}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500674
675void __init am43xx_init_late(void)
676{
677 omap_common_late_init();
Dave Gerlach08224a72015-09-15 14:47:34 -0500678 omap2_clk_enable_autoidle_all();
Nishanth Menon765e7a02013-10-16 10:39:02 -0500679}
Afzal Mohammedc5107022013-05-27 20:06:23 +0530680#endif
681
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530682#ifdef CONFIG_ARCH_OMAP4
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700683void __init omap4430_init_early(void)
684{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600685 omap2_set_globals_tap(OMAP443X_CLASS,
686 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600687 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
Tero Kristoca125b52015-02-12 11:47:04 +0200688 omap2_control_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530689 omap4xxx_check_revision();
690 omap4xxx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200691 omap2_prcm_base_init();
Nishanth Menonde70af42014-01-20 14:06:37 -0600692 omap4_pm_init_early();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700693 omap44xx_voltagedomains_init();
694 omap44xx_powerdomains_init();
695 omap44xx_clockdomains_init();
696 omap44xx_hwmod_init();
697 omap_hwmod_init_postsetup();
Sekhar Norib39b14e2014-04-22 13:58:01 +0530698 omap_l2_cache_init();
Tero Kristoc8c88d82013-07-18 16:04:00 +0300699 omap_clk_soc_init = omap4xxx_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700700}
Shawn Guobbd707a2012-04-26 16:06:50 +0800701
702void __init omap4430_init_late(void)
703{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200704 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800705 omap4_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530706 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800707}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530708#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700709
R Sricharan05e152c2012-06-05 16:21:32 +0530710#ifdef CONFIG_SOC_OMAP5
711void __init omap5_init_early(void)
712{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600713 omap2_set_globals_tap(OMAP54XX_CLASS,
714 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600715 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
Tero Kristoca125b52015-02-12 11:47:04 +0200716 omap2_control_base_init();
Santosh Shilimkar628ed472014-05-20 16:19:23 -0500717 omap4_pm_init_early();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200718 omap2_prcm_base_init();
R Sricharan05e152c2012-06-05 16:21:32 +0530719 omap5xxx_check_revision();
Santosh Shilimkare4020aa2013-05-29 12:38:12 -0400720 omap54xx_voltagedomains_init();
721 omap54xx_powerdomains_init();
722 omap54xx_clockdomains_init();
723 omap54xx_hwmod_init();
724 omap_hwmod_init_postsetup();
Tero Kristocfa96672013-10-22 11:53:02 +0300725 omap_clk_soc_init = omap5xxx_dt_clk_init;
R Sricharan05e152c2012-06-05 16:21:32 +0530726}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500727
728void __init omap5_init_late(void)
729{
730 omap_common_late_init();
Santosh Shilimkar628ed472014-05-20 16:19:23 -0500731 omap4_pm_init();
732 omap2_clk_enable_autoidle_all();
Nishanth Menon765e7a02013-10-16 10:39:02 -0500733}
R Sricharan05e152c2012-06-05 16:21:32 +0530734#endif
735
R Sricharana3a93842013-07-03 11:52:04 +0530736#ifdef CONFIG_SOC_DRA7XX
737void __init dra7xx_init_early(void)
738{
Nishanth Menonec490f62016-04-01 17:53:06 -0500739 omap2_set_globals_tap(DRA7XX_CLASS,
740 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
R Sricharana3a93842013-07-03 11:52:04 +0530741 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
Tero Kristoca125b52015-02-12 11:47:04 +0200742 omap2_control_base_init();
Rajendra Nayak6af16a12014-08-22 09:02:34 -0500743 omap4_pm_init_early();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200744 omap2_prcm_base_init();
Nishanth Menon733d20e2014-05-19 10:27:11 -0500745 dra7xxx_check_revision();
Ambresh K7de516a2013-08-23 04:05:08 -0600746 dra7xx_powerdomains_init();
747 dra7xx_clockdomains_init();
748 dra7xx_hwmod_init();
749 omap_hwmod_init_postsetup();
Tero Kristof1cf4982013-08-29 11:35:43 +0300750 omap_clk_soc_init = dra7xx_dt_clk_init;
R Sricharana3a93842013-07-03 11:52:04 +0530751}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500752
753void __init dra7xx_init_late(void)
754{
755 omap_common_late_init();
Rajendra Nayak6af16a12014-08-22 09:02:34 -0500756 omap4_pm_init();
757 omap2_clk_enable_autoidle_all();
Nishanth Menon765e7a02013-10-16 10:39:02 -0500758}
R Sricharana3a93842013-07-03 11:52:04 +0530759#endif
760
761
Tony Lindgrena4ca9db2011-08-22 23:57:23 -0700762void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
Paul Walmsley48057342010-12-21 15:25:10 -0700763 struct omap_sdrc_params *sdrc_cs1)
764{
Tony Lindgrena66cb342011-10-04 13:52:57 -0700765 omap_sram_init();
766
Hemant Pedanekar01001712011-02-16 08:31:39 -0800767 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
Kevin Hilmanaa4b1f62010-03-10 17:16:31 +0000768 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
769 _omap2_init_reprogram_sdrc();
770 }
Tony Lindgren1dbae812005-11-10 14:26:51 +0000771}
Tero Kristocfa96672013-10-22 11:53:02 +0300772
773int __init omap_clk_init(void)
774{
775 int ret = 0;
776
777 if (!omap_clk_soc_init)
778 return 0;
779
Tero Kristo8111e012014-07-02 11:47:39 +0300780 ti_clk_init_features();
781
Tero Kristoe9e63082015-04-27 21:55:42 +0300782 omap2_clk_setup_ll_ops();
783
Tero Kristoeded36f2014-12-16 18:20:55 +0200784 if (of_have_populated_dt()) {
Tero Kristofe874142014-03-12 18:33:45 +0200785 ret = omap_control_init();
786 if (ret)
787 return ret;
788
Tero Kristo3a1a3882014-11-18 14:59:36 +0200789 ret = omap_prcm_init();
Tero Kristoeded36f2014-12-16 18:20:55 +0200790 if (ret)
791 return ret;
Tero Kristoc08ee142014-09-12 15:01:57 +0300792
Tero Kristoeded36f2014-12-16 18:20:55 +0200793 of_clk_init(NULL);
Tero Kristoc08ee142014-09-12 15:01:57 +0300794
Tero Kristoeded36f2014-12-16 18:20:55 +0200795 ti_dt_clk_init_retry_clks();
Tero Kristoc08ee142014-09-12 15:01:57 +0300796
Tero Kristoeded36f2014-12-16 18:20:55 +0200797 ti_dt_clockdomains_setup();
798 }
Tero Kristoc08ee142014-09-12 15:01:57 +0300799
800 ret = omap_clk_soc_init();
Tero Kristocfa96672013-10-22 11:53:02 +0300801
802 return ret;
803}