Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright (c) 2007-2008 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 23 | * IN THE SOFTWARE. |
| 24 | */ |
| 25 | #ifndef __INTEL_DRV_H__ |
| 26 | #define __INTEL_DRV_H__ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Damien Lespiau | 178f736 | 2013-08-06 20:32:18 +0100 | [diff] [blame] | 29 | #include <linux/hdmi.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/i915_drm.h> |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/drm_crtc.h> |
| 33 | #include <drm/drm_crtc_helper.h> |
| 34 | #include <drm/drm_fb_helper.h> |
Linus Torvalds | 612a9aa | 2012-10-03 23:29:23 -0700 | [diff] [blame] | 35 | #include <drm/drm_dp_helper.h> |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 36 | |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 37 | /** |
| 38 | * _wait_for - magic (register) wait macro |
| 39 | * |
| 40 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
| 41 | * contexts. Note that it's important that we check the condition again after |
| 42 | * having timed out, since the timeout could be due to preemption or similar and |
| 43 | * we've never had a chance to check the condition before the timeout. |
| 44 | */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 45 | #define _wait_for(COND, MS, W) ({ \ |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 46 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 47 | int ret__ = 0; \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 48 | while (!(COND)) { \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 49 | if (time_after(jiffies, timeout__)) { \ |
Daniel Vetter | 1d5bfac | 2013-03-28 00:03:25 +0100 | [diff] [blame] | 50 | if (!(COND)) \ |
| 51 | ret__ = -ETIMEDOUT; \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 52 | break; \ |
| 53 | } \ |
Ben Widawsky | 0cc2764 | 2012-09-01 22:59:48 -0700 | [diff] [blame] | 54 | if (W && drm_can_sleep()) { \ |
| 55 | msleep(W); \ |
| 56 | } else { \ |
| 57 | cpu_relax(); \ |
| 58 | } \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 59 | } \ |
| 60 | ret__; \ |
| 61 | }) |
| 62 | |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 63 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
| 64 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
Daniel Vetter | 6effa33 | 2013-03-28 11:31:04 +0100 | [diff] [blame] | 65 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
| 66 | DIV_ROUND_UP((US), 1000), 0) |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 67 | |
Jani Nikula | 49938ac | 2014-01-10 17:10:20 +0200 | [diff] [blame] | 68 | #define KHz(x) (1000 * (x)) |
| 69 | #define MHz(x) KHz(1000 * (x)) |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 70 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 71 | /* |
| 72 | * Display related stuff |
| 73 | */ |
| 74 | |
| 75 | /* store information about an Ixxx DVO */ |
| 76 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
| 77 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
| 78 | #define MAX_OUTPUTS 6 |
| 79 | /* maximum connectors per crtcs in the mode set */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 80 | |
| 81 | #define INTEL_I2C_BUS_DVO 1 |
| 82 | #define INTEL_I2C_BUS_SDVO 2 |
| 83 | |
| 84 | /* these are outputs from the chip - integrated only |
| 85 | external chips are via DVO or SDVO output */ |
| 86 | #define INTEL_OUTPUT_UNUSED 0 |
| 87 | #define INTEL_OUTPUT_ANALOG 1 |
| 88 | #define INTEL_OUTPUT_DVO 2 |
| 89 | #define INTEL_OUTPUT_SDVO 3 |
| 90 | #define INTEL_OUTPUT_LVDS 4 |
| 91 | #define INTEL_OUTPUT_TVOUT 5 |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 92 | #define INTEL_OUTPUT_HDMI 6 |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 93 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 94 | #define INTEL_OUTPUT_EDP 8 |
Jani Nikula | 72ffa33 | 2013-08-27 15:12:17 +0300 | [diff] [blame] | 95 | #define INTEL_OUTPUT_DSI 9 |
| 96 | #define INTEL_OUTPUT_UNKNOWN 10 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 97 | |
| 98 | #define INTEL_DVO_CHIP_NONE 0 |
| 99 | #define INTEL_DVO_CHIP_LVDS 1 |
| 100 | #define INTEL_DVO_CHIP_TMDS 2 |
| 101 | #define INTEL_DVO_CHIP_TVOUT 4 |
| 102 | |
Jani Nikula | 72ffa33 | 2013-08-27 15:12:17 +0300 | [diff] [blame] | 103 | #define INTEL_DSI_COMMAND_MODE 0 |
| 104 | #define INTEL_DSI_VIDEO_MODE 1 |
| 105 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 106 | struct intel_framebuffer { |
| 107 | struct drm_framebuffer base; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 108 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 109 | }; |
| 110 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 111 | struct intel_fbdev { |
| 112 | struct drm_fb_helper helper; |
| 113 | struct intel_framebuffer ifb; |
| 114 | struct list_head fbdev_list; |
| 115 | struct drm_display_mode *our_mode; |
| 116 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 117 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 118 | struct intel_encoder { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 119 | struct drm_encoder base; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 120 | /* |
| 121 | * The new crtc this encoder will be driven from. Only differs from |
| 122 | * base->crtc while a modeset is in progress. |
| 123 | */ |
| 124 | struct intel_crtc *new_crtc; |
| 125 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 126 | int type; |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 127 | /* |
| 128 | * Intel hw has only one MUX where encoders could be clone, hence a |
| 129 | * simple flag is enough to compute the possible_clones mask. |
| 130 | */ |
| 131 | bool cloneable; |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 132 | bool connectors_active; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 133 | void (*hot_plug)(struct intel_encoder *); |
Daniel Vetter | 7ae8923 | 2013-03-27 00:44:52 +0100 | [diff] [blame] | 134 | bool (*compute_config)(struct intel_encoder *, |
| 135 | struct intel_crtc_config *); |
Daniel Vetter | dafd226 | 2012-11-26 17:22:07 +0100 | [diff] [blame] | 136 | void (*pre_pll_enable)(struct intel_encoder *); |
Daniel Vetter | bf49ec8c | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 137 | void (*pre_enable)(struct intel_encoder *); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 138 | void (*enable)(struct intel_encoder *); |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 139 | void (*mode_set)(struct intel_encoder *intel_encoder); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 140 | void (*disable)(struct intel_encoder *); |
Daniel Vetter | bf49ec8c | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 141 | void (*post_disable)(struct intel_encoder *); |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 142 | /* Read out the current hw state of this connector, returning true if |
| 143 | * the encoder is active. If the encoder is enabled it also set the pipe |
| 144 | * it is connected to in the pipe parameter. */ |
| 145 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 146 | /* Reconstructs the equivalent mode flags for the current hardware |
Daniel Vetter | fdafa9e | 2013-06-12 11:47:24 +0200 | [diff] [blame] | 147 | * state. This must be called _after_ display->get_pipe_config has |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 148 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
| 149 | * be set correctly before calling this function. */ |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 150 | void (*get_config)(struct intel_encoder *, |
| 151 | struct intel_crtc_config *pipe_config); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 152 | int crtc_mask; |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 153 | enum hpd_pin hpd_pin; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 154 | }; |
| 155 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 156 | struct intel_panel { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 157 | struct drm_display_mode *fixed_mode; |
Vandana Kannan | ec9ed19 | 2013-12-10 13:37:36 +0530 | [diff] [blame] | 158 | struct drm_display_mode *downclock_mode; |
Jani Nikula | 4d89152 | 2012-10-26 12:03:59 +0300 | [diff] [blame] | 159 | int fitting_mode; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 160 | |
| 161 | /* backlight */ |
| 162 | struct { |
Jani Nikula | c91c9f3 | 2013-11-08 16:48:55 +0200 | [diff] [blame] | 163 | bool present; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 164 | u32 level; |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 165 | u32 max; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 166 | bool enabled; |
Jani Nikula | 636baeb | 2013-11-08 16:49:02 +0200 | [diff] [blame] | 167 | bool combination_mode; /* gen 2/4 only */ |
| 168 | bool active_low_pwm; |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 169 | struct backlight_device *device; |
| 170 | } backlight; |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 171 | }; |
| 172 | |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 173 | struct intel_connector { |
| 174 | struct drm_connector base; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 175 | /* |
| 176 | * The fixed encoder this connector is connected to. |
| 177 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 178 | struct intel_encoder *encoder; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 179 | |
| 180 | /* |
| 181 | * The new encoder this connector will be driven. Only differs from |
| 182 | * encoder while a modeset is in progress. |
| 183 | */ |
| 184 | struct intel_encoder *new_encoder; |
| 185 | |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 186 | /* Reads out the current hw, returning true if the connector is enabled |
| 187 | * and active (i.e. dpms ON state). */ |
| 188 | bool (*get_hw_state)(struct intel_connector *); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 189 | |
| 190 | /* Panel info for eDP and LVDS */ |
| 191 | struct intel_panel panel; |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 192 | |
| 193 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
| 194 | struct edid *edid; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 195 | |
| 196 | /* since POLL and HPD connectors may use the same HPD line keep the native |
| 197 | state of connector->polled in case hotplug storm detection changes it */ |
| 198 | u8 polled; |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 199 | }; |
| 200 | |
Ville Syrjälä | 80ad920 | 2013-04-19 14:36:51 +0300 | [diff] [blame] | 201 | typedef struct dpll { |
| 202 | /* given values */ |
| 203 | int n; |
| 204 | int m1, m2; |
| 205 | int p1, p2; |
| 206 | /* derived values */ |
| 207 | int dot; |
| 208 | int vco; |
| 209 | int m; |
| 210 | int p; |
| 211 | } intel_clock_t; |
| 212 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 213 | struct intel_crtc_config { |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 214 | /** |
| 215 | * quirks - bitfield with hw state readout quirks |
| 216 | * |
| 217 | * For various reasons the hw state readout code might not be able to |
| 218 | * completely faithfully read out the current state. These cases are |
| 219 | * tracked with quirk flags so that fastboot and state checker can act |
| 220 | * accordingly. |
| 221 | */ |
| 222 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
| 223 | unsigned long quirks; |
| 224 | |
Ville Syrjälä | 5113bc9 | 2013-09-04 18:25:29 +0300 | [diff] [blame] | 225 | /* User requested mode, only valid as a starting point to |
| 226 | * compute adjusted_mode, except in the case of (S)DVO where |
| 227 | * it's also for the output timings of the (S)DVO chip. |
| 228 | * adjusted_mode will then correspond to the S(DVO) chip's |
| 229 | * preferred input timings. */ |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 230 | struct drm_display_mode requested_mode; |
Ville Syrjälä | 3c52f4e | 2013-09-06 23:28:59 +0300 | [diff] [blame] | 231 | /* Actual pipe timings ie. what we program into the pipe timing |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 232 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 233 | struct drm_display_mode adjusted_mode; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 234 | |
| 235 | /* Pipe source size (ie. panel fitter input size) |
| 236 | * All planes will be positioned inside this space, |
| 237 | * and get clipped at the edges. */ |
| 238 | int pipe_src_w, pipe_src_h; |
| 239 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 240 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
| 241 | * between pch encoders and cpu encoders. */ |
| 242 | bool has_pch_encoder; |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 243 | |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 244 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
| 245 | * pipe on Haswell (where we have a special eDP transcoder). */ |
| 246 | enum transcoder cpu_transcoder; |
| 247 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 248 | /* |
| 249 | * Use reduced/limited/broadcast rbg range, compressing from the full |
| 250 | * range fed into the crtcs. |
| 251 | */ |
| 252 | bool limited_color_range; |
| 253 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 254 | /* DP has a bunch of special case unfortunately, so mark the pipe |
| 255 | * accordingly. */ |
| 256 | bool has_dp_encoder; |
Daniel Vetter | d8b3224 | 2013-04-25 17:54:44 +0200 | [diff] [blame] | 257 | |
| 258 | /* |
| 259 | * Enable dithering, used when the selected pipe bpp doesn't match the |
| 260 | * plane bpp. |
| 261 | */ |
Daniel Vetter | 965e0c4 | 2013-03-27 00:44:57 +0100 | [diff] [blame] | 262 | bool dither; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 263 | |
| 264 | /* Controls for the clock computation, to override various stages. */ |
| 265 | bool clock_set; |
| 266 | |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 267 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
| 268 | * work correctly, we need to track this at runtime.*/ |
| 269 | bool sdvo_tv_clock; |
| 270 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 271 | /* |
| 272 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
| 273 | * required. This is set in the 2nd loop of calling encoder's |
| 274 | * ->compute_config if the first pick doesn't work out. |
| 275 | */ |
| 276 | bool bw_constrained; |
| 277 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 278 | /* Settings for the intel dpll used on pretty much everything but |
| 279 | * haswell. */ |
Ville Syrjälä | 80ad920 | 2013-04-19 14:36:51 +0300 | [diff] [blame] | 280 | struct dpll dpll; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 281 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 282 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
| 283 | enum intel_dpll_id shared_dpll; |
| 284 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 285 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
| 286 | struct intel_dpll_hw_state dpll_hw_state; |
| 287 | |
Daniel Vetter | 965e0c4 | 2013-03-27 00:44:57 +0100 | [diff] [blame] | 288 | int pipe_bpp; |
Daniel Vetter | 6cf86a5 | 2013-04-02 23:38:10 +0200 | [diff] [blame] | 289 | struct intel_link_m_n dp_m_n; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 290 | |
| 291 | /* |
| 292 | * Frequence the dpll for the port should run at. Differs from the |
Ville Syrjälä | 3c52f4e | 2013-09-06 23:28:59 +0300 | [diff] [blame] | 293 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
| 294 | * already multiplied by pixel_multiplier. |
Daniel Vetter | df92b1e | 2013-03-28 10:41:58 +0100 | [diff] [blame] | 295 | */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 296 | int port_clock; |
| 297 | |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 298 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
| 299 | unsigned pixel_multiplier; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 300 | |
| 301 | /* Panel fitter controls for gen2-gen4 + VLV */ |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 302 | struct { |
| 303 | u32 control; |
| 304 | u32 pgm_ratios; |
Daniel Vetter | 68fc874 | 2013-04-25 22:52:16 +0200 | [diff] [blame] | 305 | u32 lvds_border_bits; |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 306 | } gmch_pfit; |
| 307 | |
| 308 | /* Panel fitter placement and size for Ironlake+ */ |
| 309 | struct { |
| 310 | u32 pos; |
| 311 | u32 size; |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 312 | bool enabled; |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 313 | } pch_pfit; |
Daniel Vetter | 33d29b1 | 2013-02-13 18:04:45 +0100 | [diff] [blame] | 314 | |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 315 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
Daniel Vetter | 33d29b1 | 2013-02-13 18:04:45 +0100 | [diff] [blame] | 316 | int fdi_lanes; |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 317 | struct intel_link_m_n fdi_m_n; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 318 | |
| 319 | bool ips_enabled; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 320 | |
| 321 | bool double_wide; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 322 | }; |
| 323 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 324 | struct intel_pipe_wm { |
| 325 | struct intel_wm_level wm[5]; |
| 326 | uint32_t linetime; |
| 327 | bool fbc_wm_enabled; |
| 328 | }; |
| 329 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 330 | struct intel_crtc { |
| 331 | struct drm_crtc base; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 332 | enum pipe pipe; |
| 333 | enum plane plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 334 | u8 lut_r[256], lut_g[256], lut_b[256]; |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 335 | /* |
| 336 | * Whether the crtc and the connected output pipeline is active. Implies |
| 337 | * that crtc->enabled is set, i.e. the current mode configuration has |
| 338 | * some outputs connected to this crtc. |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 339 | */ |
| 340 | bool active; |
Imre Deak | 6efdf35 | 2013-10-16 17:25:52 +0300 | [diff] [blame] | 341 | unsigned long enabled_power_domains; |
Wang Xingchao | 7b9f35a | 2013-01-22 23:25:25 +0800 | [diff] [blame] | 342 | bool eld_vld; |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 343 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 344 | bool lowfreq_avail; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 345 | struct intel_overlay *overlay; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 346 | struct intel_unpin_work *unpin_work; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 347 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 348 | atomic_t unpin_work_count; |
| 349 | |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 350 | /* Display surface base address adjustement for pageflips. Note that on |
| 351 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
| 352 | * handled in the hw itself (with the TILEOFF register). */ |
| 353 | unsigned long dspaddr_offset; |
| 354 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 355 | struct drm_i915_gem_object *cursor_bo; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 356 | uint32_t cursor_addr; |
| 357 | int16_t cursor_x, cursor_y; |
| 358 | int16_t cursor_width, cursor_height; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 359 | bool cursor_visible; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 360 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 361 | struct intel_crtc_config config; |
Ville Syrjälä | 50741ab | 2014-01-10 11:28:07 +0200 | [diff] [blame] | 362 | struct intel_crtc_config *new_config; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 363 | bool new_enabled; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 364 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 365 | uint32_t ddi_pll_sel; |
Ville Syrjälä | 10d8373 | 2013-01-29 18:13:34 +0200 | [diff] [blame] | 366 | |
| 367 | /* reset counter value when the last flip was submitted */ |
| 368 | unsigned int reset_counter; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 369 | |
| 370 | /* Access to these should be protected by dev_priv->irq_lock. */ |
| 371 | bool cpu_fifo_underrun_disabled; |
| 372 | bool pch_fifo_underrun_disabled; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 373 | |
| 374 | /* per-pipe watermark state */ |
| 375 | struct { |
| 376 | /* watermarks currently being used */ |
| 377 | struct intel_pipe_wm active; |
| 378 | } wm; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 379 | }; |
| 380 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 381 | struct intel_plane_wm_parameters { |
| 382 | uint32_t horiz_pixels; |
| 383 | uint8_t bytes_per_pixel; |
| 384 | bool enabled; |
| 385 | bool scaled; |
| 386 | }; |
| 387 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 388 | struct intel_plane { |
| 389 | struct drm_plane base; |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 390 | int plane; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 391 | enum pipe pipe; |
| 392 | struct drm_i915_gem_object *obj; |
Damien Lespiau | 2d354c3 | 2012-10-22 18:19:27 +0100 | [diff] [blame] | 393 | bool can_scale; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 394 | int max_downscale; |
| 395 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
Jesse Barnes | 5e1bac2 | 2013-03-26 09:25:43 -0700 | [diff] [blame] | 396 | int crtc_x, crtc_y; |
| 397 | unsigned int crtc_w, crtc_h; |
| 398 | uint32_t src_x, src_y; |
| 399 | uint32_t src_w, src_h; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 400 | |
| 401 | /* Since we need to change the watermarks before/after |
| 402 | * enabling/disabling the planes, we need to store the parameters here |
| 403 | * as the other pieces of the struct may not reflect the values we want |
| 404 | * for the watermark calculations. Currently only Haswell uses this. |
| 405 | */ |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 406 | struct intel_plane_wm_parameters wm; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 407 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 408 | void (*update_plane)(struct drm_plane *plane, |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 409 | struct drm_crtc *crtc, |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 410 | struct drm_framebuffer *fb, |
| 411 | struct drm_i915_gem_object *obj, |
| 412 | int crtc_x, int crtc_y, |
| 413 | unsigned int crtc_w, unsigned int crtc_h, |
| 414 | uint32_t x, uint32_t y, |
| 415 | uint32_t src_w, uint32_t src_h); |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 416 | void (*disable_plane)(struct drm_plane *plane, |
| 417 | struct drm_crtc *crtc); |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 418 | int (*update_colorkey)(struct drm_plane *plane, |
| 419 | struct drm_intel_sprite_colorkey *key); |
| 420 | void (*get_colorkey)(struct drm_plane *plane, |
| 421 | struct drm_intel_sprite_colorkey *key); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 422 | }; |
| 423 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 424 | struct intel_watermark_params { |
| 425 | unsigned long fifo_size; |
| 426 | unsigned long max_wm; |
| 427 | unsigned long default_wm; |
| 428 | unsigned long guard_size; |
| 429 | unsigned long cacheline_size; |
| 430 | }; |
| 431 | |
| 432 | struct cxsr_latency { |
| 433 | int is_desktop; |
| 434 | int is_ddr3; |
| 435 | unsigned long fsb_freq; |
| 436 | unsigned long mem_freq; |
| 437 | unsigned long display_sr; |
| 438 | unsigned long display_hpll_disable; |
| 439 | unsigned long cursor_sr; |
| 440 | unsigned long cursor_hpll_disable; |
| 441 | }; |
| 442 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 443 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 444 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 445 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 446 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 447 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 448 | |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 449 | struct intel_hdmi { |
Paulo Zanoni | b242b7f | 2013-02-18 19:00:26 -0300 | [diff] [blame] | 450 | u32 hdmi_reg; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 451 | int ddc_bus; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 452 | uint32_t color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 453 | bool color_range_auto; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 454 | bool has_hdmi_sink; |
| 455 | bool has_audio; |
| 456 | enum hdmi_force_audio force_audio; |
Ville Syrjälä | abedc07 | 2013-01-17 16:31:31 +0200 | [diff] [blame] | 457 | bool rgb_quant_range_selectable; |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 458 | void (*write_infoframe)(struct drm_encoder *encoder, |
Damien Lespiau | 178f736 | 2013-08-06 20:32:18 +0100 | [diff] [blame] | 459 | enum hdmi_infoframe_type type, |
Ville Syrjälä | fff6386 | 2013-12-10 15:19:08 +0200 | [diff] [blame] | 460 | const void *frame, ssize_t len); |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 461 | void (*set_infoframes)(struct drm_encoder *encoder, |
| 462 | struct drm_display_mode *adjusted_mode); |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 463 | }; |
| 464 | |
Adam Jackson | b091cd9 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 465 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 466 | |
| 467 | struct intel_dp { |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 468 | uint32_t output_reg; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 469 | uint32_t aux_ch_ctl_reg; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 470 | uint32_t DP; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 471 | bool has_audio; |
| 472 | enum hdmi_force_audio force_audio; |
| 473 | uint32_t color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 474 | bool color_range_auto; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 475 | uint8_t link_bw; |
| 476 | uint8_t lane_count; |
| 477 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 478 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
Adam Jackson | b091cd9 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 479 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 480 | struct i2c_adapter adapter; |
| 481 | struct i2c_algo_dp_aux_data algo; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 482 | uint8_t train_set[4]; |
| 483 | int panel_power_up_delay; |
| 484 | int panel_power_down_delay; |
| 485 | int panel_power_cycle_delay; |
| 486 | int backlight_on_delay; |
| 487 | int backlight_off_delay; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 488 | struct delayed_work panel_vdd_work; |
| 489 | bool want_panel_vdd; |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 490 | unsigned long last_power_cycle; |
| 491 | unsigned long last_power_on; |
| 492 | unsigned long last_backlight_off; |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 493 | bool psr_setup_done; |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 494 | bool use_tps3; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 495 | struct intel_connector *attached_connector; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 496 | }; |
| 497 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 498 | struct intel_digital_port { |
| 499 | struct intel_encoder base; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 500 | enum port port; |
Stéphane Marchesin | bcf53de | 2013-07-12 13:54:41 -0700 | [diff] [blame] | 501 | u32 saved_port_bits; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 502 | struct intel_dp dp; |
| 503 | struct intel_hdmi hdmi; |
| 504 | }; |
| 505 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 506 | static inline int |
| 507 | vlv_dport_to_channel(struct intel_digital_port *dport) |
| 508 | { |
| 509 | switch (dport->port) { |
| 510 | case PORT_B: |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 511 | return DPIO_CH0; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 512 | case PORT_C: |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 513 | return DPIO_CH1; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 514 | default: |
| 515 | BUG(); |
| 516 | } |
| 517 | } |
| 518 | |
Chris Wilson | f875c15 | 2010-09-09 15:44:14 +0100 | [diff] [blame] | 519 | static inline struct drm_crtc * |
| 520 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| 521 | { |
| 522 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 523 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
| 524 | } |
| 525 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 526 | static inline struct drm_crtc * |
| 527 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
| 528 | { |
| 529 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 530 | return dev_priv->plane_to_crtc_mapping[plane]; |
| 531 | } |
| 532 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 533 | struct intel_unpin_work { |
| 534 | struct work_struct work; |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 535 | struct drm_crtc *crtc; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 536 | struct drm_i915_gem_object *old_fb_obj; |
| 537 | struct drm_i915_gem_object *pending_flip_obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 538 | struct drm_pending_vblank_event *event; |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 539 | atomic_t pending; |
| 540 | #define INTEL_FLIP_INACTIVE 0 |
| 541 | #define INTEL_FLIP_PENDING 1 |
| 542 | #define INTEL_FLIP_COMPLETE 2 |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 543 | bool enable_stall_check; |
| 544 | }; |
| 545 | |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 546 | struct intel_set_config { |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 547 | struct drm_encoder **save_connector_encoders; |
| 548 | struct drm_crtc **save_encoder_crtcs; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 549 | bool *save_crtc_enabled; |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 550 | |
| 551 | bool fb_changed; |
| 552 | bool mode_changed; |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 553 | }; |
| 554 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 555 | struct intel_load_detect_pipe { |
| 556 | struct drm_framebuffer *release_fb; |
| 557 | bool load_detect_temp; |
| 558 | int dpms_mode; |
| 559 | }; |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 560 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 561 | static inline struct intel_encoder * |
| 562 | intel_attached_encoder(struct drm_connector *connector) |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 563 | { |
| 564 | return to_intel_connector(connector)->encoder; |
| 565 | } |
| 566 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 567 | static inline struct intel_digital_port * |
| 568 | enc_to_dig_port(struct drm_encoder *encoder) |
| 569 | { |
| 570 | return container_of(encoder, struct intel_digital_port, base.base); |
| 571 | } |
| 572 | |
Imre Deak | 9ff8c9b | 2013-05-08 13:14:02 +0300 | [diff] [blame] | 573 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| 574 | { |
| 575 | return &enc_to_dig_port(encoder)->dp; |
| 576 | } |
| 577 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 578 | static inline struct intel_digital_port * |
| 579 | dp_to_dig_port(struct intel_dp *intel_dp) |
| 580 | { |
| 581 | return container_of(intel_dp, struct intel_digital_port, dp); |
| 582 | } |
| 583 | |
| 584 | static inline struct intel_digital_port * |
| 585 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
| 586 | { |
| 587 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 588 | } |
| 589 | |
Damien Lespiau | b0ea7d3 | 2012-12-13 16:09:00 +0000 | [diff] [blame] | 590 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 591 | /* i915_irq.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 592 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| 593 | enum pipe pipe, bool enable); |
| 594 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
| 595 | enum transcoder pch_transcoder, |
| 596 | bool enable); |
| 597 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 598 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 599 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 600 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 601 | void hsw_pc8_disable_interrupts(struct drm_device *dev); |
| 602 | void hsw_pc8_restore_interrupts(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 603 | |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 604 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 605 | /* intel_crt.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 606 | void intel_crt_init(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 607 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 608 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 609 | /* intel_ddi.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 610 | void intel_prepare_ddi(struct drm_device *dev); |
| 611 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
| 612 | void intel_ddi_init(struct drm_device *dev, enum port port); |
| 613 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
| 614 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
| 615 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
| 616 | void intel_ddi_pll_init(struct drm_device *dev); |
| 617 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
| 618 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| 619 | enum transcoder cpu_transcoder); |
| 620 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| 621 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
| 622 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
Paulo Zanoni | 566b734 | 2013-11-25 15:27:08 -0200 | [diff] [blame] | 623 | bool intel_ddi_pll_select(struct intel_crtc *crtc); |
| 624 | void intel_ddi_pll_enable(struct intel_crtc *crtc); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 625 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
| 626 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
| 627 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
| 628 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| 629 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
| 630 | void intel_ddi_get_config(struct intel_encoder *encoder, |
| 631 | struct intel_crtc_config *pipe_config); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 632 | |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 633 | |
| 634 | /* intel_display.c */ |
Damien Lespiau | ba0fbca | 2014-01-08 14:18:23 +0000 | [diff] [blame] | 635 | const char *intel_output_name(int output); |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 636 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 637 | int intel_pch_rawclk(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 638 | void intel_mark_busy(struct drm_device *dev); |
| 639 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
| 640 | struct intel_ring_buffer *ring); |
| 641 | void intel_mark_idle(struct drm_device *dev); |
| 642 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
| 643 | void intel_crtc_update_dpms(struct drm_crtc *crtc); |
| 644 | void intel_encoder_destroy(struct drm_encoder *encoder); |
| 645 | void intel_connector_dpms(struct drm_connector *, int mode); |
| 646 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
| 647 | void intel_modeset_check_state(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 648 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 649 | struct intel_digital_port *port); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 650 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 651 | struct intel_encoder *encoder); |
| 652 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
| 653 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 654 | struct drm_crtc *crtc); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 655 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 656 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 657 | struct drm_file *file_priv); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 658 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 659 | enum pipe pipe); |
| 660 | void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
| 661 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
| 662 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 663 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
| 664 | struct intel_digital_port *dport); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 665 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
| 666 | struct drm_display_mode *mode, |
| 667 | struct intel_load_detect_pipe *old); |
| 668 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
| 669 | struct intel_load_detect_pipe *old); |
| 670 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
| 671 | struct drm_i915_gem_object *obj, |
| 672 | struct intel_ring_buffer *pipelined); |
| 673 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
| 674 | int intel_framebuffer_init(struct drm_device *dev, |
| 675 | struct intel_framebuffer *ifb, |
| 676 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 677 | struct drm_i915_gem_object *obj); |
| 678 | void intel_framebuffer_fini(struct intel_framebuffer *fb); |
| 679 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
| 680 | void intel_finish_page_flip(struct drm_device *dev, int pipe); |
| 681 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 682 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
| 683 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 684 | struct intel_shared_dpll *pll, |
| 685 | bool state); |
| 686 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
| 687 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
| 688 | void assert_pll(struct drm_i915_private *dev_priv, |
| 689 | enum pipe pipe, bool state); |
| 690 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
| 691 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
| 692 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 693 | enum pipe pipe, bool state); |
| 694 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
| 695 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 696 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 697 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
| 698 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 699 | void intel_write_eld(struct drm_encoder *encoder, |
| 700 | struct drm_display_mode *mode); |
| 701 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
| 702 | unsigned int tiling_mode, |
| 703 | unsigned int bpp, |
| 704 | unsigned int pitch); |
| 705 | void intel_display_handle_reset(struct drm_device *dev); |
| 706 | void hsw_enable_pc8_work(struct work_struct *__work); |
| 707 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv); |
| 708 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv); |
| 709 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 710 | struct intel_crtc_config *pipe_config); |
| 711 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
| 712 | void |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 713 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
| 714 | int dotclock); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 715 | bool intel_crtc_active(struct drm_crtc *crtc); |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 716 | void hsw_enable_ips(struct intel_crtc *crtc); |
| 717 | void hsw_disable_ips(struct intel_crtc *crtc); |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 718 | void intel_display_set_init_power(struct drm_device *dev, bool enable); |
Jesse Barnes | 586f49d | 2013-11-04 16:06:59 -0800 | [diff] [blame] | 719 | int valleyview_get_vco(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 720 | |
| 721 | /* intel_dp.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 722 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
| 723 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 724 | struct intel_connector *intel_connector); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 725 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| 726 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
| 727 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
| 728 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| 729 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| 730 | void intel_dp_check_link_status(struct intel_dp *intel_dp); |
| 731 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
| 732 | struct intel_crtc_config *pipe_config); |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 733 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 734 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
| 735 | void intel_edp_backlight_off(struct intel_dp *intel_dp); |
| 736 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
| 737 | void intel_edp_panel_off(struct intel_dp *intel_dp); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 738 | void intel_edp_psr_enable(struct intel_dp *intel_dp); |
| 739 | void intel_edp_psr_disable(struct intel_dp *intel_dp); |
| 740 | void intel_edp_psr_update(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 741 | |
| 742 | |
| 743 | /* intel_dsi.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 744 | bool intel_dsi_init(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 745 | |
| 746 | |
| 747 | /* intel_dvo.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 748 | void intel_dvo_init(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 749 | |
| 750 | |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 751 | /* legacy fbdev emulation in intel_fbdev.c */ |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 752 | #ifdef CONFIG_DRM_I915_FBDEV |
| 753 | extern int intel_fbdev_init(struct drm_device *dev); |
| 754 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
| 755 | extern void intel_fbdev_fini(struct drm_device *dev); |
| 756 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 757 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
| 758 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 759 | #else |
| 760 | static inline int intel_fbdev_init(struct drm_device *dev) |
| 761 | { |
| 762 | return 0; |
| 763 | } |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 764 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 765 | static inline void intel_fbdev_initial_config(struct drm_device *dev) |
| 766 | { |
| 767 | } |
| 768 | |
| 769 | static inline void intel_fbdev_fini(struct drm_device *dev) |
| 770 | { |
| 771 | } |
| 772 | |
| 773 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state) |
| 774 | { |
| 775 | } |
| 776 | |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 777 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 778 | { |
| 779 | } |
| 780 | #endif |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 781 | |
| 782 | /* intel_hdmi.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 783 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
| 784 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| 785 | struct intel_connector *intel_connector); |
| 786 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| 787 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
| 788 | struct intel_crtc_config *pipe_config); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 789 | |
| 790 | |
| 791 | /* intel_lvds.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 792 | void intel_lvds_init(struct drm_device *dev); |
| 793 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 794 | |
| 795 | |
| 796 | /* intel_modes.c */ |
| 797 | int intel_connector_update_modes(struct drm_connector *connector, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 798 | struct edid *edid); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 799 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 800 | void intel_attach_force_audio_property(struct drm_connector *connector); |
| 801 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 802 | |
| 803 | |
| 804 | /* intel_overlay.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 805 | void intel_setup_overlay(struct drm_device *dev); |
| 806 | void intel_cleanup_overlay(struct drm_device *dev); |
| 807 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
| 808 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
| 809 | struct drm_file *file_priv); |
| 810 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
| 811 | struct drm_file *file_priv); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 812 | |
| 813 | |
| 814 | /* intel_panel.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 815 | int intel_panel_init(struct intel_panel *panel, |
| 816 | struct drm_display_mode *fixed_mode); |
| 817 | void intel_panel_fini(struct intel_panel *panel); |
| 818 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
| 819 | struct drm_display_mode *adjusted_mode); |
| 820 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
| 821 | struct intel_crtc_config *pipe_config, |
| 822 | int fitting_mode); |
| 823 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
| 824 | struct intel_crtc_config *pipe_config, |
| 825 | int fitting_mode); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 826 | void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
| 827 | u32 max); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 828 | int intel_panel_setup_backlight(struct drm_connector *connector); |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 829 | void intel_panel_enable_backlight(struct intel_connector *connector); |
| 830 | void intel_panel_disable_backlight(struct intel_connector *connector); |
Jani Nikula | db31af1 | 2013-11-08 16:48:53 +0200 | [diff] [blame] | 831 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 832 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 833 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
Vandana Kannan | ec9ed19 | 2013-12-10 13:37:36 +0530 | [diff] [blame] | 834 | extern struct drm_display_mode *intel_find_panel_downclock( |
| 835 | struct drm_device *dev, |
| 836 | struct drm_display_mode *fixed_mode, |
| 837 | struct drm_connector *connector); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 838 | |
| 839 | /* intel_pm.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 840 | void intel_init_clock_gating(struct drm_device *dev); |
| 841 | void intel_suspend_hw(struct drm_device *dev); |
| 842 | void intel_update_watermarks(struct drm_crtc *crtc); |
| 843 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
| 844 | struct drm_crtc *crtc, |
| 845 | uint32_t sprite_width, int pixel_size, |
| 846 | bool enabled, bool scaled); |
| 847 | void intel_init_pm(struct drm_device *dev); |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 848 | void intel_pm_setup(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 849 | bool intel_fbc_enabled(struct drm_device *dev); |
| 850 | void intel_update_fbc(struct drm_device *dev); |
| 851 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| 852 | void intel_gpu_ips_teardown(void); |
Imre Deak | ddb642f | 2013-10-28 17:20:35 +0200 | [diff] [blame] | 853 | int intel_power_domains_init(struct drm_device *dev); |
| 854 | void intel_power_domains_remove(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 855 | bool intel_display_power_enabled(struct drm_device *dev, |
| 856 | enum intel_display_power_domain domain); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 857 | bool intel_display_power_enabled_sw(struct drm_device *dev, |
| 858 | enum intel_display_power_domain domain); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 859 | void intel_display_power_get(struct drm_device *dev, |
| 860 | enum intel_display_power_domain domain); |
| 861 | void intel_display_power_put(struct drm_device *dev, |
| 862 | enum intel_display_power_domain domain); |
Imre Deak | ddb642f | 2013-10-28 17:20:35 +0200 | [diff] [blame] | 863 | void intel_power_domains_init_hw(struct drm_device *dev); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 864 | void intel_set_power_well(struct drm_device *dev, bool enable); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 865 | void intel_enable_gt_powersave(struct drm_device *dev); |
| 866 | void intel_disable_gt_powersave(struct drm_device *dev); |
| 867 | void ironlake_teardown_rc6(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 868 | void gen6_update_ring_freq(struct drm_device *dev); |
Daniel Vetter | 076e29f | 2013-10-08 19:39:29 +0200 | [diff] [blame] | 869 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
| 870 | void gen6_rps_boost(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 871 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
| 872 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 873 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
| 874 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
| 875 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv); |
| 876 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 877 | void ilk_wm_get_hw_state(struct drm_device *dev); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 878 | |
| 879 | |
| 880 | /* intel_sdvo.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 881 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 882 | |
| 883 | |
| 884 | /* intel_sprite.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 885 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 886 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 887 | enum plane plane); |
| 888 | void intel_plane_restore(struct drm_plane *plane); |
| 889 | void intel_plane_disable(struct drm_plane *plane); |
| 890 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| 891 | struct drm_file *file_priv); |
| 892 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
| 893 | struct drm_file *file_priv); |
Paulo Zanoni | 5f1aae6 | 2013-09-24 13:52:53 -0300 | [diff] [blame] | 894 | |
| 895 | |
| 896 | /* intel_tv.c */ |
Paulo Zanoni | 8744042 | 2013-09-24 15:48:31 -0300 | [diff] [blame] | 897 | void intel_tv_init(struct drm_device *dev); |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 898 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 899 | #endif /* __INTEL_DRV_H__ */ |